Driver circuit and image display system

Abstract

To reduce possibility for abnormal display by wrong data for display control when displaying display data to a display panel on the basis of the data for display control.SOLUTION: FF circuits 23A, 23B for output hold data for display control used for controlling displaying display data to a display panel and output it at a prescribed timing. FF circuits 24A to 24D for determination hold determination data of preset logic. A determination circuit 25 outputs a determination result signal 103 showing that no abnormality has occurred when each logic of the determination data is preset and input latch data 101 is at H level. A mask control circuit comprising the FF circuits 26, 27, a NOR circuit 28 and a clock gate circuit 29 controls data for display control so that it is outputted to the display control circuit 12 when the determination result signal 103 shows that no abnormality is occurring.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a driver circuit (driver IC) for driving a liquid crystal display device such as an LCD (Liquid Crystal Display). [Background technology]

[0002] In recent years, various information processing devices such as personal computers and mobile phones have been using liquid crystal display devices such as LCDs as display devices. In order to display data on such liquid crystal display devices, a driver circuit (driver IC) is used to drive the liquid crystal display device (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-145492 [Patent Document 2] Patent No. 6712326 Summary of the Invention [Problem to be solved by the invention]

[0004] In a driver IC for driving such a liquid crystal display device, display control is performed by writing display data for each line based on display control data such as a source load pulse signal and an abnormality detection signal.

[0005] However, if external noise such as ESD (Electro Static Discharge) noise changes or destroys the display control data written in register circuits such as flip-flop circuits inside the driver IC, it may affect the displayed image and prevent normal image display. Therefore, there is a demand for driver ICs with improved EMS (Electro Magnetic Susceptibility) characteristics.

[0006] Therefore, in order to prevent such abnormalities in image display, a method has been proposed in which an external device that transmits display data to the driver IC reads and verifies the data stored inside the driver IC, and if it has changed from the data that was supposed to have been written, it determines that an abnormality has occurred and takes measures such as rewriting the display data to the driver IC (see, for example, Patent Document 2).

[0007] However, with a countermeasure method that involves detecting an abnormality in an external device and then re-displaying the image, there is a possibility that the abnormal display will already be occurring on the display panel when the abnormality is detected in the external device, making it difficult to completely prevent the abnormal display from occurring on the display panel.

[0008] Therefore, an object of the present invention is to provide a driver circuit and an image display system that can reduce the possibility of abnormal display being caused by the output of incorrect display control data when display data is displayed on a display panel based on display control data. [Means for solving the problem]

[0009] In order to solve the above problem, a driver circuit of the present invention is a driver circuit that displays received display data on a display panel, a first register circuit that holds display control data used for controlling the display of the display data on a display panel and outputs the display control data at a predetermined timing; a plurality of second register circuits for holding predetermined logic decision data; a determination circuit that outputs a determination result indicating that no abnormality has occurred when the logic of the determination data held in the plurality of second register circuits is a preset logic and the display control data held in the first register circuit is active; and a mask control circuit that controls the display control data held in the first register circuit to be output to a circuit that controls the display of the display panel when the judgment result output from the judgment circuit indicates that no abnormality has occurred. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing the overall configuration of an image display system according to a first embodiment of the present invention. [Figure 2] 1 is a block diagram showing a configuration of a driver IC 10 according to a first embodiment of the present invention. [Figure 3] 10 is a diagram for explaining how erroneous output data is output using an output FF circuit 23 (33) that outputs a source load pulse signal or an abnormality detection signal. FIG. [Figure 4] 4 is a timing chart of the output FF circuit 23 (33) shown in FIG. 3. [Figure 5] 3 is a diagram showing a detailed configuration of the noise detection circuit 40 according to the first embodiment of the present invention shown in FIG. 2. FIG. [Figure 6] 6 is a timing chart for explaining the operation of the noise detection circuit 40 in the first embodiment shown in FIG. 5. [Figure 7] FIG. 10 is a diagram showing a detailed configuration of a noise detection circuit 40A according to a second embodiment of the present invention. [Figure 8] 8 is a diagram for explaining the decision logic of the decision circuit 62 in FIG. 7. FIG. [Figure 9] 8 is a timing chart for explaining the operation of the noise detection circuit 40A according to the second embodiment shown in FIG. 7. [Figure 10] FIG. 10 is a diagram illustrating a circuit configuration in which a plurality of noise detection circuits operate in cooperation with each other. DETAILED DESCRIPTION OF THE INVENTION

[0011] Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[0012] [First embodiment] FIG. 1 is a block diagram showing an outline of the overall configuration of an image display system according to a first embodiment of the present invention.

[0013] The image display system of this embodiment is configured to display an image on a display panel 100, and includes a source driver 10, a gate driver 30, and a timing controller 20. The source driver 10 and the gate driver 30 may be built into the timing controller 20.

[0014] The display panel 100 is, for example, an active matrix liquid crystal display device, and includes display pixels 90 arranged in a matrix, each having a pixel transistor such as a thin film transistor. The display panel 100 includes scan lines connecting the display pixels 90 in the row direction and signal lines connecting the display pixels 90 in the column direction. The gate driver 30 sequentially selects each scan line, and applies a predetermined signal voltage to each signal line using the source driver 10. This writes a signal voltage corresponding to display data to the selected display pixels 90, thereby controlling the orientation of liquid crystal in each display pixel 90 and displaying a desired image. Note that the display panel 100 may be another type of display panel, such as an organic EL (Electro-Luminescence) panel.

[0015] Here, the operation timings of the source driver 10 and the gate driver 30 are controlled by a timing controller 20. The timing controller 20 supplies control signals to the source driver 10 and the gate driver 30, respectively, based on an externally supplied video signal, for displaying a predetermined image on the display panel 100, thereby applying a predetermined voltage to the pixel electrodes of the display pixels 90 at a predetermined timing, thereby controlling the display panel 100 to display an image based on the video signal. In other words, the timing controller 20 functions as a control circuit that transmits display data to the source driver 10.

[0016] Here, the source driver 10 is configured by a driver IC (driver circuit) that receives display data from the timing controller 20 and displays an image on the display panel 100 based on the received display data. Therefore, in the following description of this embodiment, the source driver 10 will be described as a driver IC 10.

[0017] The configuration of the driver IC 10 of this embodiment is shown in the block diagram of Fig. 2. The driver IC 10 of this embodiment includes a logic block 11 and a display control circuit 12 therein.

[0018] The logic block 11 is made up of flip-flop circuits (hereinafter abbreviated as FF circuits) 21, 31 for holding data, combinational circuits 22, 23 for processing data, output FF circuits 23, 33, and so on.

[0019] The logic block 11 has the above-described circuit configuration, and generates and outputs display control data such as a source load pulse signal and an abnormality detection signal. The display control circuit 12 then writes display data line by line based on the display control data, thereby controlling the display of a display panel 100 such as a liquid crystal display device.

[0020] Generally, in a FF circuit, external noise such as ESD noise may be superimposed on input data, resulting in the output of erroneous output data.

[0021] For example, a situation in which erroneous output data is output using the output FF circuit 23 (33) that outputs a source load pulse signal or an abnormality detection signal as shown in FIG. 3 will be described.

[0022] Fig. 4 shows a timing chart of the output FF circuit 23 (33) shown in Fig. 3. As shown in Fig. 4, the output FF circuit 23 (33) operates to hold the logic of input data in synchronization with the rising edge of the clock signal and output it as output data. At times T1 and T3 in Fig. 4, it can be seen that a normal pulse signal is output as output data based on the pulse signal input as input data.

[0023] 4, it can be seen that a pulse signal is output at a timing when it should not be output due to some kind of noise being superimposed on the input data. If such an abnormal signal is output due to noise, the display control circuit 12 cannot operate normally, and the image displayed on the display panel 100 may display abnormal content.

[0024] For example, if the source load pulse signal or the abnormality detection signal is output at a timing different from the normal timing, the display panel 100 will produce an abnormal display.

[0025] Therefore, in the driver IC 10 of this embodiment, noise detection circuits 40 and 50 are configured by providing judgment FF circuits 24 and 34 near the output FF circuits 23 and 33, respectively, as shown in FIG.

[0026] Next, Fig. 5 shows a detailed configuration of the noise detection circuit 40 according to the first embodiment of the present invention shown in Fig. 2. Note that explanations of the circuit configuration of the noise detection circuit 50 provided in the circuit for generating the abnormality detection signal and the circuit configuration of the noise detection circuit provided in the circuit for generating other display control signals will be omitted as they have the same circuit configuration as the noise detection circuit 40.

[0027] As shown in FIG. 5, the noise detection circuit 40 includes output FF circuits 23A and 23B, determination FF circuits 24A to 24D, a determination circuit 25, FF circuits 26 and 27, a NOR circuit 28, and a clock gate circuit 29.

[0028] The output FF circuits 23A and 23B are register circuits that hold display control data such as a source load pulse signal used for control to display display data on a display panel, and output the data at a predetermined timing.

[0029] Specifically, the output FF circuit 23A holds the input data generated by the combinational circuit 22 and outputs it as input latch data 101, and the output FF circuit 23B outputs this input latch data 101 as a source load pulse signal.

[0030] The judgment FF circuits 24A to 24D are a plurality of second register circuits that hold judgment data of preset logic. Specifically, the judgment FF circuits 24A and 24C each have an input connected to VDD, and therefore output a high-level (hereinafter abbreviated as H level) signal to the judgment circuit 25 when a reset signal is input. The judgment FF circuits 24B and 24D each have an input connected to GND, and therefore output a low-level (hereinafter abbreviated as L level) signal to the judgment circuit 25 when a reset signal is input.

[0031] The judgment circuit 25 outputs a judgment result signal 103 indicating that no abnormality has occurred when the logic of the judgment data held in the four judgment FF circuits 24A to 24D is a preset logic, and the input latch data 101 held in the output FF circuit 23A is at an active H level.

[0032] Here, the decision circuit 25 receives, as the comparison data 102, 5-bit data with logic levels of H level, H level, L level, H level, L level.

[0033] The judgment circuit 25 compares this 5-bit comparison data 102 with the logic of the input latch data 101 and the logic of the judgment data held in the four judgment FF circuits 24A to 24D, and outputs a high-level judgment result signal 103 if all bits match, and outputs a low-level judgment result signal 103 if any one bit does not match.

[0034] The FF circuits 26 and 27 operate in synchronization with the falling edge of the clock signal CLK. The FF circuit 26 receives the determination result signal 103 as an input, and the FF circuit 27 receives the output of the FF circuit 26 as an input. The NOR circuit 28 then outputs the negation result of the logical OR operation between the output of the FF circuit 26 and the output of the FF circuit 27 as a mask signal 104.

[0035] The FF circuits 26 and 27, the NOR circuit 28, and the clock gate circuit 29 constitute a mask control circuit that controls whether or not to output the clock signal CLK as the gate clock signal GCLK to the output FF circuit 23B based on the judgment result signal 103.

[0036] This mask control circuit controls the input latch data 101, which is display control data held in the output FF circuit 23A, to be output to the display control circuit 12 that controls the display of the display panel 100, when the judgment result signal 103 output from the judgment circuit 25 indicates that no abnormality has occurred.

[0037] Specifically, the judgment result signal 103 output from the judgment circuit 25 is transferred sequentially to the FF circuit 26 and the FF circuit 27. Then, the output of the FF circuit 26 and the output of the FF circuit 27 are input to the NOR circuit 28, where a logical operation is performed to generate the mask signal 104.

[0038] The clock gate circuit 29 masks the clock signal CLK when the mask signal 104 is at H level, and outputs the clock signal CLK to the output FF circuit 23B as a gated clock signal GCLK when the mask signal 104 is at L level.

[0039] With the mask control circuit configured as described above, when the determination result signal 103 goes high, the mask signal 104 goes low for a period of two clocks of the clock signal CLK, and two clocks of the gate clock signal GCLK are supplied to the output FF circuit 23B, which then outputs a source load pulse signal based on the logic of the input latch data 101 as output data.

[0040] In this way, when the judgment result signal 103 output from the judgment circuit 25 is at H level indicating that no abnormality has occurred, the mask control circuit controls the input latch data 101 held in the output FF circuit 23A to be output to the display control circuit 12 that controls the display of the display panel 100 by supplying the clock signal CLK to the output FF circuit 23B for outputting the input latch data 101, which is display control data held in the output FF circuit 23A.

[0041] When the logic of at least one bit of the judgment data held in the judgment FF circuits 24A to 24D changes due to external noise such as ESD noise, the judgment data no longer matches the comparison data 102 in the judgment circuit 25, and the judgment result signal 103 goes low indicating that an abnormality has occurred. As a result, the mask signal 104 goes high, and the clock signal CLK is masked, thereby masking the output data.

[0042] The 4-bit determination data held in the four determination FF circuits 24A to 24D is data that includes at least one of both H level logic and L level logic. Specifically, the 4-bit determination data is a 4-bit logic of H level, L level, H level, L level.

[0043] In this way, by using two types of judgment FF circuits, judgment FF circuits 24A and 24C which are expected to be at H level when normal, and judgment FF circuits 24B and 24D which are expected to be at L level when normal, the configuration is capable of detecting both negative noise on the power supply side and positive noise on the GND side.

[0044] Furthermore, by arranging the four determination FF circuits 24A to 24D in the vicinity of the output FF circuits 23A and 23B, the accuracy of noise detection is improved, and the risk of erroneous display is reduced.

[0045] Next, the operation of the noise detection circuit 40 in the first embodiment shown in FIG. 5 will be described with reference to the timing chart of FIG.

[0046] 6, when the input data goes high, the input latch data 101 also goes high in synchronization with the rising edge of the clock signal CLK. The combination of the input latch data 101 and the outputs (1010) of the judgment FF circuits 24A to 24D becomes "11010," which matches the logic "11010" of the comparison data 102. Therefore, the judgment circuit 25 changes the judgment result signal 103 from low to high at time T1.

[0047] Then, as a result of the determination result signal 103 going high, the mask signal 104 goes low at time T2 and remains low for a period of two clocks (until time T3). As a result of the mask signal 104 going low, the clock gate circuit 29 releases the mask state of the clock signal CLK. That is, the clock gate circuit 29 outputs two clocks of the clock signal CLK as the gated clock signal GCLK to the output FF circuit 23B. As a result, the output FF circuit 23B outputs the input latch data 101 as output data. This output data is output from the output FF circuit 23B as a source load pulse signal.

[0048] Next, a case will be described where noise occurs at time T4, causing the input latch data 101 to change from L level to H level, and the outputs of the determining FF circuits 24A to 24D to change from "1010" to "0010".

[0049] In this case, even if the input latch data 101 is at H level, the combination of the input latch data 101 and the outputs (0010) of the judgment FF circuits 24A to 24D becomes "10010", which does not match the logic "11010" of the comparison data 102.

[0050] Therefore, the determination result signal 103 output from the determination circuit 25 remains at L level, and the mask signal 104 is also maintained at H level. As a result, the clock gate circuit 29 keeps the clock signal CLK in the masked state, and no output data (source load pulse signal) is output from the output FF circuit 23B.

[0051] In the noise detection circuit 40 of this embodiment, if any one of the outputs of the four judgment FF circuits 24A to 24D changes due to noise, a source load pulse signal will not be output from the output FF circuit 23B even if the input latch data 101 becomes H level.

[0052] Therefore, according to the image display system of this embodiment, when display data is displayed on the display panel 100 based on display control data such as a source load pulse signal, it is possible to reduce the possibility of an abnormal display being produced due to the output of incorrect display control data.

[0053] [Second embodiment] Next, an image display system according to a second embodiment of the present invention will be described.

[0054] In the image display system of this embodiment, the noise detection circuit 40 is replaced with a noise detection circuit 40A as shown in Fig. 7. In the image display system of this embodiment, the noise detection circuit 50 also has a circuit configuration as shown in Fig. 7, but a description thereof will be omitted. In the image display system of this embodiment, only the circuit configurations of the noise detection circuits 40 and 50 differ from the circuit configuration in the first embodiment, and other circuit configurations are the same, so a description thereof will be omitted.

[0055] The noise detection circuit 40A in this embodiment is configured such that, compared to the noise detection circuit 40 in the first embodiment shown in FIG. 5, judgment FF circuits 24E and 24F are added, a selector 61 is added, the judgment circuit 25 is replaced with a judgment circuit 62, and the NOR circuit 28 is replaced with a NAND circuit 63.

[0056] The determination FF circuits 24A to 24C are a plurality of second register circuits that hold determination data of a preset logic. The determination FF circuits 24D to 24F are a plurality of third register circuits that hold determination data of a preset logic different from the determination data held in the determination FF circuits 24A to 24C. Specifically, the determination FF circuits 24A, 24C, and 24E each have an input connected to VDD, and therefore output an H-level signal to the selector 61 when a reset signal is input. The determination FF circuits 24B, 24D, and 24F each have an input connected to GND, and therefore output an L-level signal to the selector 61 when a reset signal is input.

[0057] That is, the judgment FF circuits 24A to 24C hold the judgment data "101", and the judgment FF circuits 24D to 24F hold the judgment data "010".

[0058] The selector 61 is a selection circuit that selects one of the judgment data held in the judgment FF circuits 24A to 24C or the judgment FF circuits 24D to 24F according to the logic of a control signal 105 that controls the timing at which the logic of the source load pulse signal switches, and outputs the selected judgment data to the judgment circuit 62 as judgment data 106.

[0059] In this embodiment, it is assumed that the timing at which the input latch data 101 becomes H level is determined, and the circuit is configured so that the control signal 105 also becomes H level at the timing at which the input latch data 101 becomes H level.

[0060] When the control signal 105 is at H level, the selector 61 selects the decision data "010" from the decision FF circuits 24D to 24F and outputs it to the decision circuit 62 as decision data 106. When the control signal 105 is at L level, the selector 61 selects the decision data "101" from the decision FF circuits 24A to 24C and outputs it to the decision circuit 62 as decision data 106.

[0061] The judgment circuit 62 outputs a judgment result signal 103 indicating that no abnormality has occurred when the combination of the logic of the judgment data 106 selected by the selector 61 and the logic of the input latch data 101 held in the output FF circuit 23A matches any of the preset combinations.

[0062] Specifically, the decision circuit 62 makes a decision based on the combination of the logic of the input latch data 101 and the logic of the decision data 106 using decision logic as shown in FIG. 8, and outputs the decision result as a decision result signal 103.

[0063] The decision logic of this decision circuit 62 will be described with reference to Fig. 8. As shown in Fig. 8, the decision circuit 62 outputs an H-level decision result signal 103 when the input latch data 101 is at H level (logic "1") and the logic of the 3-bit decision data 106 is "010".

[0064] Also, as shown in FIG. 8, the decision circuit 62 outputs a decision result signal 103 at an H level when the input latch data 101 is at an L level (logic "0") and the logic of the 3-bit decision data 106 is "101."

[0065] If the combination of the logic of the input latch data 101 and the logic of the decision data 106 is other than the above, the decision circuit 62 outputs the decision result signal 103 at an L level.

[0066] In a normal state where no noise is occurring, at the timing when the input latch data 101 becomes H level, the decision data of the decision FF circuits 24D to 24F is selected by the selector 61 and output as the decision data 106. At the timing when the input latch data 101 becomes H level, the decision data of the decision FF circuits 24A to 24C is selected by the selector 61 and output as the decision data 106.

[0067] That is, in a normal state where no noise is occurring, the combination of the input latch data 10 and the judgment data 106 input to the judgment circuit 62 will be either "1010" or "0101." Therefore, in a normal state where no noise is occurring, the judgment circuit 62 outputs an H-level judgment result signal 103.

[0068] If the combination of the input latch data 10 and the judgment data 106 is neither "1010" nor "0101", it is determined that an abnormality has occurred and the judgment result signal 103 is set to L level.

[0069] The FF circuit 26 receives the determination result signal 103 as an input, and the FF circuit 27 receives the output of the FF circuit 26 as an input. The NAND circuit 63 then outputs the negation result of the logical AND operation between the output of the FF circuit 26 and the output of the FF circuit 27 as a mask signal 104.

[0070] In this embodiment, the FF circuits 26 and 27, the NAND circuit 63, and the clock gate circuit 29 constitute a mask control circuit that controls whether or not to output the clock signal CLK to the output FF circuit 23B as the gate clock signal GCLK based on the judgment result signal 103.

[0071] Next, the operation of the noise detection circuit 40A in the second embodiment shown in FIG. 7 will be described with reference to the timing chart shown in FIG.

[0072] When the input data is at L level and the input latch data 101 is also at L level, the control signal 105 is also at L level. Therefore, the selector 61 selects the judgment data from the judgment FF circuits 24A to 24C and outputs it to the judgment circuit 62 as judgment data 106. As a result, the judgment circuit 62 outputs an H-level judgment result signal 103, the mask signal 104 becomes L level, and the clock signal CLK passes through the clock gate circuit 29 and is supplied to the output FF circuit 23B as a gated clock signal GCLK.

[0073] 9, when the input data becomes H level, the input latch data 101 also becomes H level in synchronization with the rising edge of the clock signal CLK. Then, since the control signal 105 also becomes H level, the selector 61 selects the judgment data from the judgment FF circuits 24D to 24F and outputs it to the judgment circuit 62 as judgment data 106. As a result, the judgment circuit 62 outputs an H level judgment result signal 103, the mask signal 104 becomes L level, and the clock signal CLK passes through the clock gate circuit 29 and is supplied to the output FF circuit 23B as the gated clock signal GCLK.

[0074] 9 will be described. Because noise occurs at time T2, the input latch data 101 goes to H level even though the input data should be at L level. Since time T2 is not the timing when the input data should be at H level, the control signal 105 remains at L level. Therefore, the selector 61 selects the decision data from the decision FF circuits 24A to 24C and outputs it to the decision circuit 62 as decision data 106.

[0075] Then, the input latch data 101 at H level is input to the decision circuit 62, and data "101" is input as the decision data 106. As a result, the logic input to the decision circuit 62 becomes "1101", and the decision circuit 62 outputs a decision result signal 103 at L level. Therefore, at time T3, the mask signal 104 becomes H level, the clock signal CLK is masked in the clock gate circuit 29, and the gate clock signal GCLK is no longer supplied to the output FF circuit 23B. As a result, the input latch data 101 that has been generated as an abnormal signal due to the occurrence of noise is not output as output data.

[0076] In this way, the image display system of this embodiment also makes it possible to reduce the possibility of abnormal display being caused by the output of incorrect display control data when display data is displayed on the display panel 100 based on display control data such as a source load pulse signal.

[0077] [Cooperative operation of multiple noise detection circuits] In the second embodiment, the generation of noise is detected by a single noise detection circuit 40A to prevent an erroneous source load pulse signal from being output. However, if noise occurs anywhere in the driver IC 10, it is highly likely that one of the circuits in the driver IC 10 is malfunctioning.

[0078] Therefore, when the occurrence of noise is detected in any of the multiple noise detection circuits, not only the display control data output from the location where that noise detection circuit is installed but also the display control data output from the locations where other noise detection circuits are installed may be stopped.

[0079] FIG. 10 shows a circuit configuration in which multiple noise detection circuits operate in cooperation with each other in this way.

[0080] In FIG. 10, a noise detection circuit 40A is provided for the circuit for outputting the source load pulse signal, and a noise detection circuit 50A is provided for the circuit for outputting the abnormality detection signal.

[0081] The noise detection circuit 50A has a circuit configuration similar to that of the noise detection circuit 40A, and includes output FF circuits 33A and 33B, a clock gate circuit 39, FF circuits 36 and 37, a determination circuit 64, and a NAND circuit 65. The output FF circuit 33A holds input data as input latch data 111.

[0082] 10 further includes an OR circuit 70 that receives output signals from the NAND circuits 63, 63. The OR circuit 70 performs a logical OR operation on the output signals from the NAND circuits 63, 63, and outputs the operation result as a mask signal 104. The mask signal 104 output from the OR circuit 70 is input to the clock gate circuits 29, 39 in the noise detection circuits 40A, 50A, respectively.

[0083] 10, there are provided a plurality of output FF circuits 23A, 33A that hold input data, and a plurality of decision circuits 62, 64. Two decision circuits 62, 64 are provided for each of the two output FF circuits 23A, 33A.

[0084] When a determination result signal indicating the occurrence of an abnormality is output from either one of the two determination circuits 62, 64, the mask control circuits provided in the noise detection circuits 40A, 50A perform control so that all of the display control data held in the two output FF circuits 23A, 33A is not output to the display control circuit 12 that controls the display of the display panel 100. In other words, with the circuit configuration described above, even if the occurrence of noise is detected in either one of the noise detection circuits 40A, 50A, erroneous output of both the source load pulse signal and the abnormality detection signal is prevented. [Explanation of symbols]

[0085] 10 Driver IC (source driver) 11 Logic Blocks 12 Display control circuit 21 FF circuit 22 Combinational Circuits 23, 23A, 23B output FF circuit 24, 24A~24F FF circuit for judgment 25 Judgment circuit 26, 27 FF circuit 28 NOR circuit 29 Clock Gate Circuit 30 Gate Driver 33, 33A, 33B output FF circuit 36, 37 FF circuit 39 Clock Gate Circuit 40, 40A noise detection circuit 50, 50A noise detection circuit 61 Selector 62 Judgment circuit 63 NAND circuit 64 Judgment circuit 65 NAND circuit 70 OR Circuit 90 display pixels 100 Display Panel 101 Input latch data 102 Comparative Data 103 Judgment result signal 104 Mask Signal 105 Control Signal 106 Judgment Data 111 Input latch data

Claims

1. A driver circuit for displaying received display data on a display panel, a first register circuit that holds display control data used for controlling display of the display data on a display panel and outputs the display control data at a predetermined timing; a plurality of second register circuits for holding predetermined logic determination data; a determination circuit that outputs a determination result indicating that no abnormality has occurred when the logic of the determination data held in the plurality of second register circuits is a preset logic and the display control data held in the first register circuit is active; a mask control circuit that controls the display control data held in the first register circuit to be output to a circuit that controls display of the display panel when the determination result output from the determination circuit indicates that no abnormality has occurred; A driver circuit comprising:

2. When the determination result output from the determination circuit indicates that no abnormality has occurred, the mask control circuit controls so that a clock signal is supplied to an output flip-flop circuit for outputting the display control data held in the first register circuit, thereby outputting the display control data held in the first register circuit to a circuit that controls display of the display panel.

2. The driver circuit of claim 1.

3. The determination data is data including at least one of both high-level logic and low-level logic.

2. The driver circuit of claim 1.

4. the plurality of second register circuits are arranged in the vicinity of the first register circuit; 2. The driver circuit of claim 1.

5. A driver circuit for displaying received display data on a display panel, a first register circuit that holds display control data used for controlling display of the display data on a display panel and outputs the display control data at a predetermined timing; a plurality of second register circuits for holding predetermined logic determination data; a plurality of third register circuits that hold judgment data of a preset logic different from the judgment data held in the plurality of second register circuits; a selection circuit that selects one of the determination data held in the plurality of second register circuits or the plurality of third register circuits in accordance with a logic of a control signal that controls a timing at which the logic of the display control data is switched; a determination circuit that outputs a determination result indicating that no abnormality has occurred when a combination of the logic of the determination data selected by the selection circuit and the logic of the display control data held in the first register circuit matches any of preset combinations; a mask control circuit that controls the display control data held in the first register circuit to be output to a circuit that controls display of the display panel when the determination result output from the determination circuit indicates that no abnormality has occurred; A driver circuit comprising:

6. a plurality of the first register circuits and a plurality of the determination circuits are provided; the plurality of determination circuits are arranged for each of the plurality of first register circuits, the mask control circuit controls the plurality of first register circuits so that none of the display control data held in the plurality of first register circuits is output to a circuit that controls display of the display panel when a determination result indicating that an abnormality has occurred is output from any one of the plurality of determination circuits.

6. A driver circuit according to claim 5.

7. A driver circuit according to any one of claims 1 to 6; a control circuit for transmitting the display data to the driver circuit; An image display system comprising:

Images