Display system

Abstract

To provide a display system which is high in display quality and achieves high definition.SOLUTION: The display system comprises a first layer and a display part. The display part is positioned on a region overlapping the first layer. The first layer includes a semiconductor substrate made of silicon, and on the semiconductor substrate, a plurality of first transistors and a plurality of second transistors including silicon in a channel formation region are formed. The first layer includes a first circuit and a second circuit. The first circuit has a driving circuit driving the display part. The second circuit has a storage device, a GPU, and an EL correction circuit. The display part includes pixels. The pixel has a light-emitting device including an organic EL and is electrically connected to the driving circuit. The storage device has a function of holding image data. The GPU has a function of decoding image data read from the storage device. The EL correction circuit has a function of correcting light generated by the light-emitting device.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display system and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] There is a demand for display devices that can be used for XR (a collective term for VR, AR, etc.), such as VR (virtual reality) and AR (augmented reality). Specifically, for example, to enhance the sense of realism and immersion, such display devices are desired to have high definition and excellent color reproducibility.

[0004] Examples of display devices that can be applied to the display include liquid crystal display devices, and light-emitting devices equipped with light-emitting devices such as organic electroluminescence (EL) devices and light-emitting diodes (LEDs: Light Emitting Diodes). Patent Document 1 discloses a high-pixel, high-definition display device equipped with a light-emitting device that includes an organic EL device. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 220278 Summary of the Invention [Problem to be solved by the invention]

[0006] As mentioned above, XR devices require display devices with high display quality. Furthermore, because XR display devices must be installed in eyeglass-type or goggle-type housings, the size of the display device must be reduced to approximately 2 inches or 1 inch diagonal or less.

[0007] Display devices also require peripheral circuits such as driver circuits, memory devices that pre-store images to be displayed, digital-to-analog converters (DACs), and decoders that restore encoded images. Furthermore, to improve display quality, it is preferable to provide a circuit that corrects image data. Therefore, providing these peripheral circuits increases the size of the display device's housing, which can place a strain on the wearer. Furthermore, increasing the number of peripheral circuits increases the number of signal accesses between pixels and peripheral circuits within the display device, which can increase access time and power consumption.

[0008] An object of one embodiment of the present invention is to provide a display device with a reduced circuit area.An object of one embodiment of the present invention is to provide a display device with reduced power consumption.An object of one embodiment of the present invention is to provide a display device with high display quality.An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide a system including any of the above-described semiconductor devices.

[0009] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0010] (1) One embodiment of the present invention is a display system including a first layer and a display unit. The display unit is located in a region overlapping the first layer. The first layer includes a semiconductor substrate made of silicon and includes a plurality of first transistors and a plurality of second transistors, each of which includes silicon in a channel formation region. The first layer includes a first circuit and a second circuit. The first circuit includes a source driver circuit and a gate driver circuit, each of which includes the first transistor. The second circuit includes a memory device, a CPU, a GPU, an EL correction circuit, a timing controller, and a high-frequency circuit. The display unit includes pixels, each of which includes a light-emitting device including an organic EL. The pixels are electrically connected to the source driver circuit and the gate driver circuit. The memory device has a function of holding image data, the CPU has a function of sending control signals to one or more selected from the memory device, the GPU, the EL correction circuit, the timing controller, and the high-frequency circuit, the GPU has a function of decoding image data read from the memory device, the source driver circuit has a function of sending the decoded image data to pixels, the EL correction circuit has a function of correcting the brightness of light emitted by the light-emitting device, and the timing controller has a function of increasing or decreasing the frame rate at which images are displayed on the display unit, and the high-frequency circuit has a function of converting an electrical signal generated by any one of the CPU, GPU, and memory device into an RF signal and sending it to the outside, and a function of converting an RF signal obtained from the outside into an electrical signal and sending it to any one of the CPU, GPU, and memory device.

[0011] (2) Another embodiment of the present invention is a display system including a first layer and a display unit. The display unit is located in a region overlapping the first layer. The first layer includes a semiconductor substrate made of silicon and includes a plurality of first transistors and a plurality of second transistors, each of which includes silicon in a channel formation region. The first layer includes a first circuit and a second circuit. The first circuit includes a source driver circuit and a gate driver circuit, each of which includes the first transistor. The second circuit includes a memory device, a GPU, an EL correction circuit, and a timing controller, each of which includes the second transistor. The display unit includes pixels, each of which includes a light-emitting device including an organic EL. The pixels are electrically connected to the source driver circuit and the gate driver circuit. The memory device has a function of storing image data, the GPU has a function of decoding image data read from the memory device, the source driver circuit has a function of transmitting the decoded image data to the pixels, the EL correction circuit has a function of correcting the brightness of the light emitted by the light-emitting device, and the timing controller has a function of increasing or decreasing the frame rate at which images are displayed on the display unit.

[0012] (3) Another embodiment of the present invention is a display system including a first layer, a second layer, and a display unit. The display unit is located in a region overlapping the first layer, and the second layer is located in a region overlapping the first layer. The first layer includes a semiconductor substrate made of silicon and includes a plurality of first transistors and a plurality of second transistors, each of which includes silicon in a channel formation region. The second layer includes a plurality of third transistors, each of which includes a metal oxide in a channel formation region. The first layer includes a first circuit and a second circuit. The first circuit includes a source driver circuit and a gate driver circuit, each of which includes the first transistor. The second circuit includes a memory device, a GPU, an EL correction circuit, and a timing controller, each of which includes the second transistor. The third transistor functions as a transistor included in the memory device included in the first layer. The display unit includes pixels, and the pixels include light-emitting devices including organic EL. The pixels are electrically connected to the source driver circuit and the gate driver circuit. The memory device has a function of storing image data, the GPU has a function of decoding image data read from the memory device, the source driver circuit has a function of transmitting the decoded image data to the pixels, the EL correction circuit has a function of correcting the brightness of the light emitted by the light-emitting device, and the timing controller has a function of increasing or decreasing the frame rate at which images are displayed on the display unit.

[0013] (4) Alternatively, in one embodiment of the present invention, in the above-mentioned (3), the second layer may include memory cells.

[0014] (5) Alternatively, in one embodiment of the present invention, in any one of the above (2) to (4), the second circuit may include a CPU including the second transistor. Preferably, the CPU has a function of transmitting a control signal to one or more selected from a storage device, a GPU, an EL correction circuit, and a timing controller.

[0015] (6) Alternatively, in one aspect of the present invention, in any one of (1) to (5) above, the GPU may have a function of performing calculations of an artificial neural network and correcting an image displayed on the display unit based on the results of the calculations.

[0016] (7) Another embodiment of the present invention is an electronic device including the display system according to any one of (1) to (6) above and a housing.

[0017] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices or may include semiconductor devices.

[0018] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0019] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0020] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0021] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0022] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0023] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0024] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification and the like, a "resistance element" is intended to include a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can sometimes be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," and "region having a resistance value" can sometimes be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0025] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, a gate capacitance of a transistor, etc. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with terms such as "capacitance." Conversely, the term "capacitance" can sometimes be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can sometimes be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," etc. The value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0026] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0027] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Furthermore, when operating in the saturation region, the multi-gate structure can provide a voltage-current characteristic with a flat slope, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing a voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0028] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0029] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration or device structure. A terminal, a wiring, etc. can also be referred to as a node.

[0030] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0031] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0032] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive or negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0033] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0034] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0035] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0036] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0037] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0038] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0039] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0040] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals for passing a current in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0041] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0042] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0043] In this specification, etc., a device fabricated using a metal mask or FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In this specification, etc., a device fabricated without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure.

[0044] In this specification, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (e.g., a color filter) to form a full-color display device.

[0045] Light-emitting devices can be broadly divided into single-structure and tandem-structure devices. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, two or more light-emitting layers may be selected so that the light emitted from each of the two or more light-emitting layers has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration in which the entire light-emitting device emits white light can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0046] A tandem-structured device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light, light from the light-emitting layers of the multiple light-emitting units may be combined to obtain white light. The configuration for obtaining white light is the same as that of the single-structured device. In a tandem-structured device, it is preferable to provide an intermediate layer such as a charge-generating layer between the multiple light-emitting units.

[0047] Furthermore, when comparing the above-mentioned white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If you want to keep power consumption low, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, so it is preferable because it can reduce manufacturing costs or increase manufacturing yields.

[0048] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0049] According to one embodiment of the present invention, a display device with a reduced circuit area can be provided. Alternatively, according to one embodiment of the present invention, a display device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a display device with high display quality can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a system including any of the above-described semiconductor devices can be provided.

[0050] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0051] [Figure 1] FIG. 1A is a diagram showing an example of the configuration of a display device, and FIG. 1B is a diagram showing an example of the configuration of a display system. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a display system. [Figure 3] FIG. 3A is a diagram showing an example of the configuration of a display device, and FIG. 3B is a diagram showing an example of the configuration of a display system. [Figure 4] FIG. 4 is a block diagram showing an example of the configuration of a display system. [Figure 5] 5A to 5G are circuit diagrams showing examples of the configuration of a memory cell. [Figure 6] FIG. 6 is a block diagram showing an example of the configuration of a display system. [Figure 7] 7A and 7B are cross-sectional schematic diagrams showing configuration examples of a display system. [Figure 8] FIG. 8 is a block diagram showing an example of the configuration of a display system. [Figure 9] 9A and 9B are diagrams showing an example of the configuration of a display system. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a display system. [Figure 11] 11A and 11B are diagrams showing an example of the configuration of a display system. [Figure 12] FIG. 12 is a diagram illustrating an example of the configuration of a display system. [Figure 13] FIG. 13 is a block diagram showing an example of the configuration of a display system. [Figure 14] 14A and 14B are cross-sectional schematic diagrams showing configuration examples of a display device or a display system. [Figure 15] 15A to 15C are diagrams showing configuration examples of a light-emitting device. [Figure 16] FIG. 16 is a cross-sectional view showing a configuration example of a display device or a display system. [Figure 17] 17A and 17B are cross-sectional views showing examples of the structure of a transistor. [Figure 18] 18A and 18B are cross-sectional views showing examples of the structure of a transistor. [Figure 19] FIG. 19 is a cross-sectional view showing a configuration example of a display device or a display system. [Figure 20] FIG. 20 is a cross-sectional view showing a configuration example of a display device or a display system. [Figure 21] FIG. 21A is a diagram illustrating the classification of IGZO crystal structures, FIG. 21B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 21C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 22] 22A to 22F are diagrams showing configuration examples of electronic devices. [Figure 23] 23A and 23B are diagrams showing configuration examples of a display module. [Figure 24] 24A and 24B are diagrams showing configuration examples of electronic devices. [Figure 25] 25A to 25C are diagrams showing configuration examples of electronic devices. [Figure 26] 26A to 26D are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0052] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0053] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0054] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0055] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0056] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0057] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0058] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0059] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0060] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0061] (Embodiment 1) In this embodiment, a display device and a display system according to one embodiment of the present invention will be described.

[0062] <Example of display device configuration> 1A is a schematic diagram illustrating a display device according to one embodiment of the present invention. The display device 100 illustrated in FIG. 1A includes a display unit DSP and a circuit unit SIC. The display device 100 has a configuration in which the circuit unit SIC is formed on a substrate, and the display unit DSP is further formed on the circuit unit SIC.

[0063] The display unit DSP has an area for displaying an image in the display device 100, and has a function of displaying an image based on a data signal transmitted from the circuit unit SIC. The display unit DSP may have pixels arranged in a regular pattern. For example, the pixels arranged in the display unit DSP may be arranged in a matrix. The arrangement of the pixels in the display unit DSP may be a stripe array, a mosaic array, or a delta array. Therefore, in this embodiment, the display unit DSP may be referred to as a pixel array. The screen ratio (aspect ratio) of the display unit DSP is not particularly limited. For example, the display unit DSP can support various screen ratios, such as 1:1 (square), 4:3, 16:9, and 16:10.

[0064] The circuit unit SIC has a peripheral circuit DRV including a source driver circuit, a gate driver circuit, a digital-to-analog conversion circuit, and a level shifter in the display device 100. In other words, the peripheral circuit DRV functions as a drive circuit for displaying an image on the display unit DSP.

[0065] The circuit section SIC can be constructed by, for example, providing transistors, capacitors, and the like on a substrate. The substrate can be a semiconductor substrate (e.g., a single-crystal substrate) made of silicon, germanium, or the like. Other than semiconductor substrates, examples include silicon-on-insulator (SOI) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, and base films. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is synthetic resins such as acrylic. Other examples include polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, etc. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, paper, etc. If the manufacturing process of the display device 100 includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate.

[0066] In this embodiment, the substrate included in the circuit unit SIC will be described as a semiconductor substrate made of silicon or the like.

[0067] By using a semiconductor substrate made of silicon as the substrate included in the circuit unit SIC, the transistors included in the peripheral circuit DRV can be formed on the semiconductor substrate. In this case, the transistors are transistors containing silicon in the channel formation region (hereinafter referred to as Si transistors). Si transistors have high field-effect mobility and can therefore pass large on-currents. This makes it possible to increase the driving speed of the peripheral circuit DRV and widen the signal range.

[0068] Furthermore, when a material containing single crystal silicon is used for the circuit section SIC, the size of the circuit section SIC can be 0.1 inches to 5 inches diagonally, preferably 0.5 inches to 3 inches diagonally, and more preferably 1 inch to 2 inches diagonally. Since the display section DSP is provided above the circuit section SIC, the size of the display section DSP can be determined according to the size of the circuit section SIC. Furthermore, the amount of light emitted from the display section DSP depends on the size of the display section DSP. For example, if the size of the circuit section SIC is 1 inch diagonally, it is preferable because about four times the amount of light can be extracted from the display section DSP compared to a size of 0.5 inches diagonally.

[0069] <Display system configuration example> Next, a display system according to one embodiment of the present invention will be described.

[0070] 1B is a schematic diagram illustrating a display system according to one embodiment of the present invention. The display system 200 illustrated in FIG. 1B differs from the display device 100 illustrated in FIG. 1A in that a functional circuit MFNC is provided in the circuit unit SIC of the display device 100 illustrated in FIG. 1A. Therefore, the description of the display device 100 illustrated in FIG. 1A should be referred to for the description of the display unit DSP and the peripheral circuit DRV in the display system 200 illustrated in FIG. 1B.

[0071] In this specification, a display system refers to a configuration in which a functional circuit is provided in a display device. Since a display system is a configuration in which an image is displayed, the display system can also be referred to as a display device.

[0072] The functional circuit MFNC may be provided with, for example, a memory device in which image data to be displayed on the display unit DSP is stored, a decoder for restoring encoded image data, a GPU (Graphics Processing Unit) for processing image data, a power supply circuit, a correction circuit, a CPU (Central Processing Unit), etc.

[0073] As a specific configuration example, a block diagram of a display system 200 is shown in FIG.

[0074] In FIG. 2, thick wires (for example, wire GL, wire SL, and wire BSL) are depicted as multiple wires or bus wires.

[0075] In the display system 200 of FIG. 2 , the display unit DSP has, as an example, a plurality of pixels PX arranged in a matrix. The pixels PX may be pixels to which at least one of a liquid crystal display device, a light-emitting device including an organic EL, and a light-emitting device including a light-emitting diode such as a micro LED is applied, for example. Note that in this embodiment, a light-emitting device including an organic EL is described as being applied to the pixels PX of the display unit DSP. Furthermore, each of the plurality of pixels PX may be a pixel that emits different colors rather than the same color. For example, the plurality of pixels PX may be a pixel that emits three colors, red, green, and blue. For this reason, in this specification and the like, a pixel may sometimes be described as a subpixel.

[0076] 2, the peripheral circuit DRV included in the circuit unit SIC has a source driver circuit 11, a digital-to-analog conversion circuit 12, a gate driver circuit 13, and a level shifter 14, for example.

[0077] In addition, in the display system 200 of Figure 2, the functional circuit MFNC included in the circuit unit SIC has, as an example, a memory device 21, a GPU (AI accelerator) 22, an EL correction circuit 23, a timing controller 24, a CPU (NoffCPU (registered trademark)) 25, a sensor controller 26, and a power supply circuit 27.

[0078] Furthermore, the display system 200 in FIG. 2 is configured such that, as an example, bus wiring BSL is electrically connected to each of the circuits included in the peripheral circuit DRV and the circuits included in the functional circuit MFNC.

[0079] For example, the source driver circuit 11 has a function of transmitting image data to the pixels PX included in the display unit DSP, and therefore the source driver circuit 11 is electrically connected to the pixels PX via wiring SL.

[0080] The digital-analog conversion circuit 12 has a function of converting image data that has been digitally processed by, for example, a GPU (described later) or an EL correction circuit (described later), into analog data. The image data converted into analog data is transmitted to the display unit DSP via the source driver circuit 11. Note that the digital-analog conversion circuit 12 may be included in the source driver circuit 11, or the image data may be transmitted in the order of the source driver circuit 11, the digital-analog conversion circuit 12, and the display unit DSP.

[0081] For example, the gate driver circuit 13 has a function of selecting pixels PX to which image data is to be sent in the display unit DSP. Therefore, the gate driver circuit 13 is electrically connected to the pixels PX via wiring GL.

[0082] The level shifter 14 has a function of converting signals input to the source driver circuit 11, the digital-to-analog conversion circuit 12, the gate driver circuit 13, etc., to appropriate levels, for example.

[0083] For example, the storage device 21 has a function of storing image data to be displayed on the display unit DSP. The storage device 21 can be configured to store image data as digital data or analog data.

[0084] Furthermore, when image data is stored in the storage device 21, it is preferable to use a nonvolatile memory as the storage device 21. In this case, for example, a NAND type memory or the like can be used as the storage device 21.

[0085] Furthermore, when temporary data generated by the GPU 22, the EL correction circuit 23, the CPU 25, etc. is stored in the storage device 21, it is preferable to use a volatile memory as the storage device 21. In this case, for example, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), etc. can be used as the storage device 21.

[0086] For example, the GPU 22 has a function of performing processing to render image data read from the storage device 21 on the display unit DSP. In particular, the GPU 22 is configured to perform parallel pipeline processing, so that it can process image data to be displayed on the display unit DSP at high speed. The GPU 22 can also function as a decoder for decoding encoded images.

[0087] The functional circuit MFNC may also include multiple circuits capable of improving the display quality of the display unit DSP. For example, such circuits may include a correction circuit (color adjustment, dimming) that detects color unevenness in an image displayed on the display unit DSP and corrects the color unevenness to create an optimal image. If a liquid crystal display device is used in the pixels of the display unit DSP, the functional circuit MFNC may also include a gamma correction circuit. If a light-emitting device using an organic EL element is used in the pixels of the display unit DSP, the functional circuit MFNC may also include an EL correction circuit that corrects variations in the luminance of the EL element. In the present embodiment, the pixels PX of the display unit DSP are described as being light-emitting devices including an organic EL element, and therefore the functional circuit MFNC includes an EL correction circuit 23, for example. The organic EL included in the display unit DSP can have a structure in which red (R), green (G), and blue (B) are provided independently (SBS, Side By Side structure), or a structure in which a tandem structure (a structure in which multiple colors such as R, G, and B are connected in series via an intermediate layer (charge generating layer)) is combined with a colored layer (for example, a color filter). By using a tandem structure, a light-emitting device capable of emitting light with high brightness can be obtained. The brightness of the light emitted from the display unit DSP can be, for example, 500 cd / m 2 or more, preferably 1000 cd / m 2 More than 10000cd / m 2 or less, more preferably 2000 cd / m 2 More than 5000cd / m 2 It can be as follows:

[0088] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through the display device (or the voltage applied to the display device) provided in the pixel may be monitored and acquired, and the image displayed on the display DSP may be acquired by an image sensor or the like, and the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (for example, an artificial neural network), and the output result may be used to determine whether or not to correct the image.

[0089] Furthermore, AI calculations can be applied not only to image correction but also to image data upconversion processing, which allows low-resolution image data to be upconverted to match the resolution of the display DSP, enabling high-quality images to be displayed on the display DSP.

[0090] The above-described artificial intelligence calculations can be performed using the GPU 22 included in the functional circuit MFNC. That is, various correction calculations can be performed using the GPU 22. Examples of the various correction calculations include color shading correction and up-conversion. As shown in FIG. 2, the GPU 22 may be configured to include a circuit 22a that corrects color shading and a circuit 22b that performs up-conversion.

[0091] In this specification, a GPU that performs computations for artificial intelligence is referred to as an AI accelerator. That is, in this specification, the GPU provided in the functional circuit MFNC may be described as an AI accelerator.

[0092] For example, the timing controller 24 has a function of increasing or decreasing the frame rate at which an image is displayed on the display unit DSP. For example, when a still image is displayed on the display unit DSP, the display system 200 can be driven by the timing controller 24 at a lower frame rate. Also, for example, when a moving image is displayed on the display unit DSP, the display system 200 can be driven by the timing controller 24 at an increased frame rate. In other words, by providing the timing controller 24 in the display system 200, the frame rate can be changed depending on whether the image is a still image or a moving image. In particular, when a still image is displayed on the display unit DSP, the frame rate can be lowered, thereby reducing the power consumption of the display system 200.

[0093] The CPU 25 has the function of performing general-purpose processing such as executing an operating system, controlling data, performing various calculations, and executing programs. In the display system 200, the CPU 25 has the role of issuing commands such as writing or reading image data to or from the storage device 21, correcting image data, and issuing commands to a sensor (described later). Furthermore, the CPU 25 may have the function of transmitting control signals to one or more selected from the storage device 21, the GPU 22, the EL correction circuit 23, the timing controller 24, the high-frequency circuit, and circuits included in the functional circuit MFNC.

[0094] The CPU 25 may also have a circuit (hereinafter referred to as a backup circuit) that temporarily backs up data. It is preferable that the backup circuit be able to retain the data even if, for example, the supply of power supply voltage is stopped. For example, when a still image is displayed on the display unit DSP, the CPU 25 can suspend its function until an image different from the current still image is displayed. Therefore, by temporarily saving data being processed by the CPU 25 to the backup circuit and then stopping the supply of power supply voltage to the CPU 25, the dynamic power consumption of the CPU 25 can be reduced. In this specification, a CPU having a backup circuit is referred to as an Noff CPU.

[0095] The sensor controller 26 has a function of controlling the sensor, for example. In addition, in Fig. 2, a wiring SNCL is illustrated as a wiring for electrically connecting to the sensor.

[0096] The sensor can be, for example, a touch sensor that can be provided above or below the display unit DSP or inside the display unit DSP.

[0097] Furthermore, the sensor can be, for example, an illuminance sensor. In particular, by acquiring the intensity of external light illuminating the display unit DSP using the illuminance sensor, it is possible to change the brightness (luminance) of the image displayed on the display unit DSP in accordance with the external light. For example, when the external light is bright, the luminance of the image displayed on the display unit DSP can be increased to improve the visibility of the image. Conversely, when the external light is dark, the luminance of the image displayed on the display unit DSP can be decreased to reduce power consumption.

[0098] For example, the power supply circuit 27 has a function of generating voltages to be supplied to circuits included in the peripheral circuit DRV, circuits included in the functional circuit MFNC, pixels included in the display unit DSP, etc. The power supply circuit 27 may also have a function of selecting the circuit to which to supply voltage. For example, the power supply circuit 27 can reduce the power consumption of the entire display system 200 by stopping the voltage supply to the CPU 25, GPU 22, etc. while a still image is being displayed on the display unit DSP.

[0099] <Display Device and Display System Variation 1> 1B, the transistors included in the peripheral circuit DRV and the functional circuit MFNC are transistors formed on a semiconductor substrate. In this embodiment, an example is shown in which the transistors are formed on a semiconductor substrate made of silicon and the peripheral circuit DRV and the functional circuit MFNC include Si transistors. However, in a display device or a display system according to one embodiment of the present invention, transistors having characteristics different from those of Si transistors can be applied to FIGS. 1A and 1B.

[0100] For example, a display device according to one embodiment of the present invention may have a structure (display device 100A) in which a layer OSC is formed between a circuit portion SIC and a display portion DSP as shown in Fig. 3A. Furthermore, a display system according to one embodiment of the present invention may have a structure (display system 200A) in which a layer OSC is formed between a circuit portion SIC and a display portion DSP as shown in Fig. 3A as shown in Fig. 3B.

[0101] The layer OSC may include, for example, an OS transistor. A channel formation region of the OS transistor includes the metal oxide described in Embodiment 4. The metal oxide may be one or more materials selected from the group consisting of indium, an element M (one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like), and zinc. In particular, when a metal oxide of indium, gallium, or zinc is contained in a semiconductor layer of an OS transistor, the band gap of the semiconductor layer can be increased. Therefore, the off-state current of the OS transistor can be reduced.

[0102] Since OS transistors can be formed not only on semiconductor substrates but also on insulating substrates, conductive substrates, and even conductive films, insulating films, and semiconductor films, they can be easily provided on semiconductor substrates (circuit portions SIC) on which Si transistors are formed.

[0103] The layer OSC may include not only OS transistors but also circuit elements such as capacitors, etc. The layer OSC may include a circuit therein.

[0104] By providing the layer OSC on the circuit portion SIC, the OS transistor included in the layer OSC can be used in the circuit formed in the circuit portion SIC, and the low off-state current characteristics of the OS transistor can be utilized in the circuit.

[0105] The OS transistor included in the layer OSC can be used as, for example, a switch for power gating. Specifically, the switch can be provided in a circuit included in the peripheral circuit DRV and the functional circuit MFNC. When the circuit is temporarily stopped, the switch can be turned off to stop the supply of power voltage to the circuit from the power supply circuit 27 or the like.

[0106] The OS transistor included in the layer OSC can be used, for example, as a write transistor included in a memory cell of the storage device 21. By using an OS transistor as a write transistor included in a memory cell, the leakage current (off current) between the source and drain of the write transistor can be reduced, allowing data written in the memory cell to be retained for a long period of time. This allows the interval between refresh operations of the data retained in the memory cell to be lengthened, thereby reducing the power consumption of the display system 200.

[0107] The layer OSC may also be provided with a storage device that temporarily stores data handled by circuits included in the peripheral circuit DRV and circuits included in the functional circuit MFNC. For example, as shown in the block diagram of a display system 200A in Figure 4, the layer OSC may also be provided with a storage device MDV. The storage device MDV shown in Figure 4 illustrates an example in which a plurality of memory cells MC are arranged in a matrix. The functional circuit MFNC of the display system 200A in Figure 4 is also provided with, as an example, a memory control circuit 31 that performs operations such as writing, reading, and erasing data in the memory cells MC.

[0108] The memory control circuit 31 includes, for example, a word line driver circuit, a bit line driver circuit, etc. for the memory cells MC included in the memory device MDV. Therefore, the memory cells MC included in the layer OSC and the memory control circuit 31 are electrically connected by wiring ML.

[0109] <<Memory cell configuration example 1>> Next, an example of a circuit configuration of a memory cell that can be applied to the memory cell MC will be described. For example, a memory cell of a storage circuit called DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) (registered trademark) or NOSRAM (Dynamic Oxide Semiconductor Random Access Memory) (registered trademark) can be applied to the memory cell MC.

[0110] 5A shows an example of the circuit configuration of a DOSRAM memory cell. Memory cell MC1 has a transistor M1 and a capacitance CA. Transistor M1 has a front gate (sometimes simply called a gate) and a back gate.

[0111] A first terminal of the transistor M1 is electrically connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is electrically connected to a wiring BIL, a gate of the transistor M1 is electrically connected to a wiring WOL, a back gate of the transistor M1 is electrically connected to a wiring BGL, and a second terminal of the capacitor CA is electrically connected to a wiring CVL.

[0112] The transistor M1 functions as a write transistor in the memory cell MC1. As described above, the transistor M1 is an OS transistor, for example.

[0113] 4. The wiring BIL, wiring WOL, wiring CAL, and wiring BGL correspond to the wiring ML in the display system 200A of FIG.

[0114] For example, the wiring BIL functions as a bit line, and the wiring WOL functions as a word line. For example, the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. Note that, when writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CVL.

[0115] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying a given potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0116] 5A, the back gate of the transistor M1 is electrically connected to the wiring BGL, but the memory cell MC1 may have a configuration in which the gate and back gate of the transistor M1 are electrically connected to each other in order to increase the on-state current of the transistor M1. Also, in the memory cell MC1 of FIG. 5A, the transistor M1 does not necessarily have to have a back gate.

[0117] Data is written and read by applying a high-level potential to the wiring WOL to turn on the transistor M1 and establish electrical continuity between the wiring BIL and the first terminal of the capacitor CA.

[0118] Specifically, data is written by applying a potential corresponding to the data to be written to the wiring BIL and writing the potential to the first terminal of the capacitor CA via the transistor M1. After the data is written, a low-level potential is applied to the wiring WOL to turn off the transistor M1, thereby holding the potential in the memory cell MC1.

[0119] To read data, the wiring BIL is first precharged to an appropriate potential, for example, a potential intermediate between a low-level potential and a high-level potential, and then the wiring BIL is set to an electrically floating state. After that, a high-level potential is applied to the wiring WOL, turning on the transistor M1 and changing the potential of the wiring BIL. The change in the potential of the wiring BIL is determined by the potential written to the first terminal of the capacitor CA, so the data stored in the memory cell MC1 can be read from the changed potential of the wiring BIL.

[0120] Furthermore, the above-described memory cell MC1 is not limited to the circuit configuration shown in FIG. 5A, and the circuit configuration of the memory cell MC1 may be changed as appropriate.

[0121] 5B shows an example of the circuit configuration of a NOSRAM memory cell. Memory cell MC2 includes transistors M2 and M3, and a capacitor C. Transistor M2 has a front gate (sometimes simply referred to as a gate) and a back gate.

[0122] The transistor M2 functions as a write transistor in the memory cell MC2. As described above, the write transistor is an OS transistor, for example.

[0123] Furthermore, the transistor M3 functions as a read transistor in the memory cell MC2. As described above, the read transistor is an OS transistor. In this operation example, the transistor M3 operates in the saturation region unless otherwise specified. That is, the gate voltage, source voltage, and drain voltage of the transistor M3 are appropriately biased to voltages within the range in which the transistor M3 operates in the saturation region.

[0124] At least one of the transistors M2 and M3 may be a Si transistor. That is, the Si transistor included in the memory cell MC2 may be formed in the circuit section SIC, and the remaining transistors included in the memory cell MC2 may be formed in the layer OSC as OS transistors.

[0125] The first terminal of the transistor M2 is electrically connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is electrically connected to the wiring WBL, the gate of the transistor M2 is electrically connected to the wiring WOL, and the back gate of the transistor M2 is electrically connected to the wiring BGL. The second terminal of the capacitor CB is electrically connected to the wiring CAL. The first terminal of the transistor M3 is electrically connected to the wiring RBL, the second terminal of the transistor M3 is electrically connected to the wiring SOL, and the gate of the transistor M3 is electrically connected to the first terminal of the capacitor CB.

[0126] 4. The wiring RBL, wiring WBL, wiring WOL, wiring CAL, wiring BGL, and wiring SOL correspond to the wiring ML in the display system 200A of FIG.

[0127] The line WBL functions as a write bit line, the line RBL functions as a read bit line, and the line WOL functions as a word line. The line CAL functions as a line for applying a predetermined potential to the second terminal of the capacitor CB. During data retention, it is preferable to apply a low-level potential (sometimes called a reference potential) to the line CAL, and during data writing and reading, it is preferable to apply a high-level potential to the line CAL.

[0128] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. The threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL. Note that, similar to the transistor M1 in FIG. 5A, the transistor M2 may have a structure in which the gate and back gate of the transistor M2 are electrically connected, or may have a structure in which a back gate is not provided.

[0129] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0130] Data is read by applying a predetermined potential to the wiring SOL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL electrically connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0131] Furthermore, the above-described memory cell MC2 is not limited to the circuit configuration shown in FIG. 5B, and the circuit configuration of the memory cell MC2 may be modified as appropriate. For example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in FIG. 5C. The memory cell MC2A is configured such that the wiring WBL and the wiring RBL of the memory cell MC2 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell MC2A is configured to operate as a single wiring BIL, using the write bit line and the read bit line.

[0132] <<Memory cell configuration example 2>> In addition, examples of memory cells of storage circuits other than DOSRAM and NOSRAM that can be applied to the memory cells MC of the layer OSC include MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive Random Access Memory), phase change memory (sometimes referred to as PCM, PRAM, etc.), and ferroelectric memory. The circuit configurations of these are described below.

[0133] The memory cell MC3 shown in FIG. 5D is an example of a STT-MRAM (Spin Transfer Torque-Magnetoresistive Random Access Memory).

[0134] The memory cell MC3 includes a transistor M10 and an MTJ (magnetic tunnel junction) element ME.

[0135] The transistor M10 can be, for example, an OS transistor, similar to the transistors M1 and M2.

[0136] The MTJ element ME has a layer FL having a free layer, a layer TIS having a tunnel insulator, and a layer RL having a fixed layer, with the layer FL and the layer RL overlapping with each other via the layer TIS.

[0137] A first terminal of the transistor M10 is electrically connected to a layer RL of the MTJ element ME, a second terminal of the transistor M10 is electrically connected to a wiring SL, and a gate of the transistor M10 is electrically connected to a wiring WL. A layer FL of the MTJ element ME is electrically connected to a wiring BL.

[0138] 4. The wiring BL, wiring WL, and wiring SL correspond to the wiring ML in the display system 200A of FIG.

[0139] The wiring BL functions as, for example, a write bit line or a read bit line for the memory cell MC3.

[0140] The wiring WL functions as a word line for the memory cell MC3, for example.

[0141] For example, the wiring SL functions as a wiring that applies a constant voltage. The constant voltage can be, for example, a low-level potential.

[0142] Although not shown in the drawings, not only STT-MRAM but also SOT-MRAM (Spin Orbit Torque-Magnetoresistive Random Access Memory) can be applied to the memory cells MC of the layer OSC.

[0143] The memory cell MC4 shown in FIG. 5E is an example of a ReRAM (Resistive Random Access Memory).

[0144] The memory cell MC4 includes a transistor M10 and a resistance change element RM.

[0145] The transistor M10 can be, for example, an OS transistor, similar to the transistors M1 and M2.

[0146] As shown in Fig. 5E, the memory cell MC4 has a configuration in which the MTJ element ME of the memory cell MC3 of Fig. 5D is replaced with a resistance change element RM. Note that in the memory cell MC of Fig. 5E, a first terminal of the resistance change element RM is electrically connected to a first terminal of the transistor M10, and a second terminal of the resistance change element RM is electrically connected to the wiring BL.

[0147] 4. The wiring BL, wiring WL, and wiring SL correspond to the wiring ML in the display system 200A of FIG.

[0148] The wiring BL functions as, for example, a write bit line or a read bit line for the memory cell MC4.

[0149] The wiring WL functions as a word line for the memory cell MC4, for example.

[0150] The wiring SL functions as, for example, a wiring that applies a constant voltage, which may be, for example, a reference potential.

[0151] The memory cell MC5 shown in FIG. 5F is an example of a storage circuit having a phase change memory.

[0152] The memory cell MC5 includes a transistor M10 and a phase change memory cell PCM1.

[0153] The transistor M10 can be, for example, an OS transistor, similar to the transistors M1 and M2.

[0154] The phase change memory PCM1 has, for example, an electrode TE, a phase change layer CHL, and an electrode BE, and the electrode TE, the phase change layer CHL, and the electrode BE are electrically connected in this order.

[0155] Furthermore, for example, chalcogenide glass can be applied to the phase change layer CHL. Note that in the present embodiment, the phase change layer CHL will be described as being made of chalcogenide glass.

[0156] It is preferable that the electrode TE and the electrode BE have different contact areas with the phase-change layer CHL. For example, in FIG. 5F, the contact area between the electrode TE and the phase-change layer CHL is illustrated as being larger than the contact area between the electrode BE and the phase-change layer CHL. By reducing the contact area between the electrode BE and the phase-change layer CHL, heat can be applied locally to the phase-change layer CHL, making it easier for a phase change to occur in the phase-change layer CHL near the electrode BE than in the phase-change layer CHL near the electrode TE.

[0157] 5F, the memory cell MC5 has a configuration in which the MTJ element ME of the memory cell MC3 in FIG. 5D is replaced with a phase-change memory PCM1. In the memory cell MC in FIG. 5F, the electrode BE of the phase-change memory PCM1 is electrically connected to the first terminal of the transistor M10, and the electrode TE of the phase-change memory PCM1 is electrically connected to the wiring BL.

[0158] 4. The wiring BL, wiring WL, and wiring SL correspond to the wiring ML in the display system 200A of FIG.

[0159] The wiring BL functions as, for example, a write bit line or a read bit line for the memory cell MC5.

[0160] The wiring WL functions as a word line for the memory cell MC5, for example.

[0161] For example, the wiring SL functions as a wiring that applies a constant voltage. The constant voltage can be, for example, a low-level potential.

[0162] The memory cell MC6 shown in FIG. 5G is an example of an FeRAM (Ferroelectric Random Access Memory).

[0163] The memory cell MC6 includes a transistor M11 and a ferroelectric capacitor FEA.

[0164] The transistor M11 can be, for example, an OS transistor, similar to the transistors M1 and M2.

[0165] A first terminal of the transistor M11 is electrically connected to the wiring BL, a second terminal of the transistor M11 is electrically connected to a first terminal of the ferroelectric capacitor FEA, and a gate of the transistor M11 is electrically connected to the wiring WL, and a second terminal of the ferroelectric capacitor FEA is electrically connected to the wiring FCA.

[0166] 4. The wiring BL, wiring WL, and wiring FCA correspond to the wiring ML in the display system 200A of FIG.

[0167] The wiring BL functions as, for example, a wiring that transmits data to be written to the memory cell MC6.

[0168] The wiring WL functions as, for example, a wiring for selecting a memory cell MC6 to which data is to be written.

[0169] For example, when writing data to the memory cell MC6, the wiring FCA functions as a wiring that applies a variable potential to the extent that polarization occurs in the material that may have ferroelectricity and is included in the ferroelectric capacitor FEA.

[0170] Here, a material that can have ferroelectricity and is contained in the ferroelectric capacitor FEA will be described.

[0171] A preferable example of a material that can have ferroelectricity is hafnium oxide. When hafnium oxide is used as the dielectric contained in the ferroelectric capacitor FEA, the film thickness of the hafnium oxide is preferably 10 nm or less, more preferably 5 nm or less, and even more preferably 2 nm or less.

[0172] Alternatively, materials that can have ferroelectricity include, in addition to hafnium oxide, zirconium oxide and hafnium zirconium oxide (HfZrO XExamples of materials that can have ferroelectricity include metal oxides such as J1 (wherein J1 is one or more elements selected from the group consisting of zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr)). The atomic ratio of hafnium atoms to element J1 can be set appropriately, and may be, for example, 1:1 or close to 1:1. Examples of materials that can have ferroelectricity include materials in which element J2 (wherein J2 is one or more elements selected from the group consisting of hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr)) is added to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0173] Furthermore, materials that can have ferroelectricity include aluminum scandium nitride (Al 1-a Sc a N b(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1.) Examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum (Al), gallium (Ga), indium (In), etc., and element M2 is one or more elements selected from boron (B), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), neodymium (Nd), europium (Eu), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Ferroelectric materials include the above-mentioned metal nitrides to which element M3 is added. The element M3 is one or more elements selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), and cadmium (Cd). The ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set. Because the above-mentioned metal nitrides contain at least a Group 13 element and nitrogen, a Group 15 element, these metal nitrides are sometimes referred to as Group III-V ferroelectrics or Group III nitride ferroelectrics.

[0174] Furthermore, materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0175] Furthermore, the material capable of exhibiting ferroelectricity can be, for example, a mixture or compound of multiple materials selected from the materials listed above. Alternatively, the material capable of exhibiting ferroelectricity can be a layered structure of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification, a material that exhibits ferroelectricity is not only referred to as a ferroelectric, but also as a material capable of exhibiting ferroelectricity or a material that imparts ferroelectricity. Furthermore, the term "ferroelectric" is intended to include not only materials that exhibit ferroelectricity but also materials capable of exhibiting ferroelectricity.

[0176] Among these, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferred as a material capable of exhibiting ferroelectricity, since it can retain ferroelectricity even when processed into a thin film of a few nanometers. Here, the film thickness of the ferroelectric material can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). For example, a film thickness of 8 nm to 12 nm is preferred. By forming a ferroelectric layer that can be thinned, the ferroelectric layer can be sandwiched between a pair of electrodes of a capacitive element, and the capacitive element can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device. Note that, in this specification and the like, a layer of a material capable of exhibiting ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification and the like.

[0177] In addition, HfZrO is a material that can have ferroelectric properties. XWhen using a ferroelectric material, it is preferable to form the film using atomic layer deposition (ALD), particularly thermal ALD. Furthermore, when using thermal ALD to form a film of a material that can have ferroelectricity, it is preferable to use a material that does not contain hydrocarbons (also called hydrocarbon, HC) as a precursor. If the material that can have ferroelectricity contains either or both of hydrogen and carbon, this may inhibit the crystallization of the material that can have ferroelectricity. Therefore, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the material that can have ferroelectricity. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Furthermore, as a material that can have ferroelectricity, a material containing hafnium oxide and zirconium oxide (HfZrO x ) is used, at least one of HfCl4 and ZrCl4 may be used as a precursor.

[0178] When a film is formed using a material that can have ferroelectricity, impurities in the film, in this case at least one of hydrogen, hydrocarbon, and carbon, are thoroughly removed, thereby forming a film having high-purity intrinsic ferroelectricity. The film having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later have very high compatibility in manufacturing processes. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0179] In addition, HfZrO is a material that can have ferroelectric properties. X When used, it is preferable to use a thermal ALD method to alternately form films of hafnium oxide and zirconium oxide in a 1:1 ratio.

[0180] Furthermore, when a film of a material that may have ferroelectricity is formed using a thermal ALD method, the oxidizing agent may be H2O or O3. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0181] Furthermore, the crystal structure of the material capable of exhibiting ferroelectricity is not particularly limited. For example, the crystal structure of the material capable of exhibiting ferroelectricity may be one or more selected from the group consisting of cubic, tetragonal, orthorhombic, and monoclinic. In particular, the material capable of exhibiting ferroelectricity preferably has an orthorhombic crystal structure, since ferroelectricity is exhibited. Alternatively, the material capable of exhibiting ferroelectricity may have a composite structure having an amorphous structure and a crystalline structure.

[0182] Note that, in the memory cell MC6 of FIG. 5G, FeRAM using a ferroelectric capacitor FEA has been described as an example, but the memory cell MC applicable to the layer OSC may be a memory cell using an FTJ (Ferroelectric Tunnel Junction or Ferroelectric Transportation Junction) element and / or an FeFET (Ferroelectric FET) (not shown).

[0183] By configuring the display device as described above, that is, by providing the peripheral circuit DRV below the display unit DSP, the wiring between the display unit DSP and the peripheral circuit DRV can be made shorter than before, thereby reducing the time required to transmit image data, etc. Also, since the wiring length can be made shorter than before, the power consumption of the display device can be reduced.

[0184] Furthermore, by providing a layer OSC between the display unit DSP and the circuit unit SIC, the influence of heat generated in the circuit unit SIC on the display unit DSP can be alleviated. In particular, when the display elements included in the display unit DSP have low heat resistance, the life of the display elements included in the display unit DSP can be extended by using the configurations shown in Figures 3A, 3B, 4, etc. Furthermore, by providing a cooling mechanism below the circuit unit SIC, the influence of heat generated in the circuit unit SIC can be reduced (not shown). Examples of such cooling mechanisms include a heat sink using a material with high thermal conductivity, a water-cooled heat sink using cooling water, and a fan.

[0185] <Modification 2 of the display device and display system> 4 shows an example in which the memory device MDV is provided in the layer OSC between the circuit unit SIC and the display unit DSP, but the layer OSC may be provided with circuits, devices, etc. other than the memory device. For example, part of the circuits included in the peripheral circuit DRV and / or the functional circuit MFNC may be formed in the layer OSC.

[0186] The display system 200B in Fig. 6 shows an example in which a part of the peripheral circuit DRV is formed on the layer OSC in the display system 200A in Fig. 4. Note that in Fig. 6, there is a portion where the wiring SL and the wiring GL intersect, but the two wirings are not directly connected to each other.

[0187] The display system 200B of Fig. 6 shows an example in which a part of the peripheral circuit DRV in the display system 200A of Fig. 4 is formed as a circuit DRVa in the circuit section SIC, and the rest of the peripheral circuit DRV in the display system 200A of Fig. 4 is formed as a circuit DRVb in the layer OSC. Specifically, the display system 200B is configured such that the circuit DRVa has a source driver circuit 11 and a digital-to-analog conversion circuit 12, and the circuit DRVb has a gate driver circuit 13 and a level shifter 14.

[0188] OS transistors have higher electrical resistance than Si transistors. Therefore, by using OS transistors as the transistors formed in the layer OSC, circuits included in the layer OSC (e.g., the gate driver circuit 13, the level shifter 14, etc.) can have high resistance to voltage. Therefore, by forming these circuits in the layer OSC, the electrical load on these circuits can be reduced.

[0189] <Display Device and Display System Modification Example 3> The display system 200 shown in FIG. 1B has a configuration in which the circuit portion SIC includes a peripheral circuit DRV and a functional circuit MFNC. However, a display system according to one embodiment of the present invention may have a configuration in which the circuit portion SIC is provided with a functional circuit MFNC, and the display portion DSP may be driven by a circuit external to the display system 200.

[0190] For example, a display system according to one embodiment of the present invention may have the configuration shown in FIG. 7A. A display system 200C includes a display unit DSP and a circuit unit SIC, and the circuit unit SIC includes a functional circuit MFNC. The display unit DSP is electrically connected to a circuit unit CHP, which includes a peripheral circuit DRV. The circuit unit CHP may be, for example, an external driver IC.

[0191] Further, methods for mounting the circuit unit CHP on the display system 200C include, for example, a COG (Chip On Glass) method and a COF (Chip On Film) method.

[0192] In the display system 200C, the transistors included in the display unit DSP and the circuit unit SIC may be, for example, Si transistors. Alternatively, OS transistors may be used instead of Si transistors.

[0193] Furthermore, the display system 200C may have a configuration in which the circuit unit CHP and the display unit DSP are electrically connected, as shown in FIG. 7B, but in which the circuit unit CHP and the circuit unit SIC are electrically connected.

[0194] Moreover, an example of a specific configuration of the display system 200C shown in Fig. 7A or 7B is shown in Fig. 8. Note that in Fig. 8, the bus wiring BSL of the functional circuit MFNC included in the display system 200C and the bus wiring of the circuit unit CHP are electrically connected.

[0195] As described above, in the display system 200 of FIG. 1B, the peripheral circuit DRV that drives the display unit DSP may be provided outside the display system 200 as a driver IC or the like, rather than being provided in the circuit unit SIC.

[0196] As described in this embodiment, by configuring a display device or display system, that is, by providing a peripheral circuit DRV and a functional circuit MFNC below the display unit DSP, it is possible to reduce the transmission time of image data, reduce power consumption, and also provide a correction circuit, a GPU, and the like without increasing the circuit area. This improves the display quality of the display unit DSP. Furthermore, because the circuit area does not increase, it is less subject to restrictions such as the size of the housing of the electronic device, which will be described in later embodiments.

[0197] In conventional display devices (e.g., display devices using Si transistors), the pixel array and peripheral circuits are configured on the same plane. However, by using OS transistors as transistors in a display device, it becomes possible to miniaturize the pixel circuits and peripheral circuits. This allows the area of ​​the pixel circuits and the peripheral areas of the pixel circuits (sometimes called frame) to be reduced. For example, while conventional display devices for XR (e.g., display devices using Si transistors) generally have a resolution of 3000 ppi or less, by using OS transistors in a display device for XR, a resolution of 5000 ppi or more can be achieved.

[0198] We also consider the brightness of light-emitting devices, including organic EL devices, when they are used in the pixels of a display device. When a constant current source is configured using a Si transistor, the Si transistor has a low withstand voltage, so in reality, a luminance of 1000 cd / m is required for a 3000 ppi display device. 2 On the other hand, when a constant current source is configured using an OS transistor, the OS transistor has a high withstand voltage, so for example, in a display device with a resolution of 5000 ppi or more and 7000 ppi or less, the brightness can only be output at approximately 10000 cd / m 2 It can output the brightness of the front and rear.

[0199] 1B, when the semiconductor substrate of the circuit section SIC is made of silicon, the system (interface, converter, driver, memory, CPU, GPU) can be built within a technology node of 6 nm to 7 nm, thereby reducing the area of ​​the circuits that make up the display system 200.

[0200] As described above, the details of display systems using Si transistors or OSLSIs are summarized in the table below. Note that in this specification and elsewhere, OSLSI refers to an integrated circuit in which an OS transistor is formed above a Si transistor formed on a semiconductor substrate.

[0201] [Table 1]

[0202] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0203] (Embodiment 2) In this embodiment, a configuration of a display system including a radio frequency (RF) circuit will be described.

[0204] Fig. 9A is a schematic diagram illustrating a display system according to one embodiment of the present invention. A display system 200D shown in Fig. 9A is configured by providing a high-frequency circuit 41 in a functional circuit MFNC included in the circuit unit SIC of the display system 200 shown in Fig. 1B. Fig. 9A also illustrates a device EXDV that wirelessly communicates with the high-frequency circuit 41.

[0205] In addition, in the present embodiment, the display system 200D and the device EXDV are described separately, but the display system according to an embodiment of the present invention may also include an external device that performs wireless communication with the display system. In other words, the display system according to an embodiment of the present invention may include the device EXDV.

[0206] The high frequency circuit 41 includes, for example, an antenna, a duplexer, a low noise amplifier, a power amplifier, a local oscillator, a down-conversion mixer, an up-conversion mixer, a band-pass filter, an analog-to-digital conversion circuit, and the like.

[0207] In particular, the high-frequency circuit 41 has a duplexer, which electrically separates the RF signal path for transmission from the RF signal path for reception. This allows the antenna provided in the high-frequency circuit 41 to be a single antenna that serves as both a transmission antenna and a reception antenna. This further reduces the circuit area of ​​the display system 200D.

[0208] In this embodiment, the high-frequency circuit 41 has a function of converting an electrical signal generated by any one of the circuits included in the first layer (e.g., a CPU, a GPU, a storage device, etc.) into an RF signal and transmitting it to the outside of the display system 200D. The high-frequency circuit 41 also has a function of converting an RF signal obtained from the outside into an electrical signal and transmitting it to any one of the circuits included in the first layer (e.g., a CPU, a GPU, a storage device, etc.).

[0209] It should be noted that various electronic devices can be applied as the device EXDV. For example, when the device EXDV exists outside the housing provided in the display system 200D, the device EXDV can be, for example, an electronic device such as a speaker (including earphones, headphones, etc.), a mobile information terminal such as a smartphone, a wearable information terminal, a tablet information terminal, a desktop information terminal, a server, or a device equipped with IoT (Internet of Things).

[0210] 10, the display system 200D may be a display unit of an electronic device HMD that is a head-mounted display, and the device EXDV may be a device EXDV1 that is a server existing on a cloud computing CLD. Alternatively, the device EXDV may be a device EXDV2 that is a mobile information terminal (e.g., a smartphone). Alternatively, the device EXDV may be a device EXDV3 that is a wearable information terminal.

[0211] By providing a high-frequency circuit 41 in the functional circuit MFNC of the display system 200D, wireless communication with electronic devices such as a server, a mobile information terminal, and a wearable information terminal can be performed, as shown in Fig. 10. This allows image data transmitted from the device EXDV1, device EXDV2, etc. to be received by the high-frequency circuit 41 of the display system 200D of the electronic device HMD, and the image data can be displayed on the display unit DSP of the display system 200D.

[0212] 11A, a user wearing the electronic device HMD (or a person not wearing the electronic device HMD) may use a finger FG to transmit an RF signal for operating the display system 200D from device EXDV2 or EXDV3 to the display system 200D, using device EXDV2 or EXDV3 as an input interface. At this time, the display unit of device EXDV2 or EXDV3 may be in a non-display state, and the display unit DSP of the display system 200D of the electronic device HMD may display an image that was originally intended to be displayed on device EXDV2 or EXDV3 on the display unit of device EXDV2 or EXDV3 by AR. Specifically, as an example, as shown in FIG. 11A, the display unit of device EXDV2 or device EXDV3, which is actually operated with finger FG, may be hidden, and the display unit DSP of the display system 200D of the electronic device HMD may be caused to display a display image DPC in which an operation screen is displayed on device EXDV2 or device EXDV3.

[0213] 11B, for example, a user wearing the electronic device HMD may move his / her hand HND to transmit an RF signal for operating device EXDV2 or device EXDV3 from the electronic device HMD to device EXDV2 or device EXDV3. In this case, the electronic device HMD preferably includes an imaging device, an infrared sensor, or the like for recognizing the movement of the hand HND. Furthermore, the hand HND (including fingers FG, wrist, etc.) may be equipped with a sensor device for recognizing the movement, and the electronic device HMD may recognize the movement of the hand HND by receiving sensing information from the sensor device. This allows the user wearing the electronic device HMD to operate device EXDV2 or device EXDV3 even if the device EXDV2 or device EXDV3 is far from the user. Specifically, for example, as shown in FIG. 11B, the display unit DSP of the display system 200D of the electronic device HMD can display a display image DPC in which the view outside the electronic device HMD, an operation area OPA, and an icon ICN within the operation area OPA are combined. At this time, by performing a gesture such as touching the icon ICN with the hand HND (finger FG in FIG. 11B), it is possible to remotely operate the device EXDV2 or device EXDV3.

[0214] 11A or 11B, the image displayed on the display unit DSP of the display system 200D of the electronic device HMD may be an image originally displayed by the device EXDV2 or the device EXDV3, rather than a view of the outside world of the electronic device HMD. The image is preferably displayed in 4K2K, more preferably in 8K4K, and even more preferably in 16K8K.

[0215] Furthermore, communication between the display system 200D and the device EXDV may be performed via a wireless repeater. This allows the display system 200D to communicate not only with electronic devices located near the display system 200D, but also with electronic devices located far away. In this case, it is preferable to use the fifth generation (5G) communication standard in order to transmit large amounts of data, reduce delay times, and increase communication speeds. Note that 5G (fifth generation mobile communication systems) uses communication frequencies such as the 3.7 GHz band, 4.5 GHz band, and 28 GHz band.

[0216] Since semiconductor devices compatible with 5G are often fabricated using semiconductors that use one type of element, such as silicon, as their main component, the high-frequency circuit 41 included in the functional circuit MFNC can be fabricated on the semiconductor substrate of the circuit section SIC (particularly a semiconductor substrate made of silicon), as in the display system 200D of Figure 9A.

[0217] Furthermore, if device EXDV is not provided outside the housing provided in display system 200D but is provided in the same housing as display system 200D, device EXDV may be, for example, a part of the circuit included in functional circuit MFNC of display system 200 in Figure 1B.

[0218] Specifically, as shown in Fig. 9B, some of the circuits of functional circuit MFNC may be provided as functional circuit MFNCa on the circuit unit SIC side, and the remaining circuits of functional circuit MFNC may be provided as functional circuit MFNCb in device EXDV. Also, Fig. 9B shows an example in which functional circuit MFNCa is provided with a high-frequency circuit 41a, and functional circuit MFNCb is provided with a high-frequency circuit 41b, and the high-frequency circuits 41a and 41b perform wireless communication. Note that in Fig. 9B, functional circuits MFNCa and MFNCb are collectively referred to as functional circuit MFNC. In other words, wireless communication is performed within the functional circuit MFNC shown in Fig. 9B.

[0219] 9B, wireless communication can be performed inside the functional circuit MFNC. This eliminates the need to provide wiring for transmitting and receiving electrical signals between the functional circuits MFNCa and MFNCb, allowing the circuit area inside the housing to be reduced.

[0220] An example of an application of the configuration of Fig. 9B is a configuration of a head-mounted display and headphones attached thereto. Specifically, as shown in Fig. 12, display system 200D is applied to the display unit of electronic device HMD, which is a head-mounted display, and device EXDV is applied to headphone unit HP, and audio data is transmitted from high-frequency circuit 41a to high-frequency circuit 41b via wireless communication, so that the headphones having device EXDV can play the audio data in accordance with the image displayed on the display unit.

[0221] 13 shows an example of a specific configuration of the display system 200D shown in Fig. 9A or 9B. As shown in Fig. 13, the high-frequency circuit 41 is electrically connected to the bus wiring BSL, and can convert the RF signal RFS into an electrical signal and transmit it to a predetermined circuit such as the CPU 25, and can also convert an electrical signal from a predetermined circuit such as the CPU 25 into the RF signal RFS and transmit it to the device EXDV.

[0222] 9A, 9B, and 13 described in this embodiment have been described as an example in which the high-frequency circuit 41 is provided in the functional circuit MFNC of the circuit unit SIC of the display system 200 in FIG. 1, but one embodiment of the present invention is not limited thereto. For example, one embodiment of the present invention may have a configuration in which the high-frequency circuit 41 is provided in the functional circuit MFNC of the circuit unit SIC of the display system 200A in FIG. 3 (not shown).

[0223] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0224] (Embodiment 3) In this embodiment mode, a structure of the display device or the display system described in the above embodiment mode will be described.

[0225] 1A or the display system shown in FIG. 1B and FIG. 2. In the display system shown in FIG. 14A, the circuit unit SIC includes a transistor 170, and the display unit DSP includes a transistor 180, a light-emitting device 260R, a light-emitting device 260G, and a light-emitting device 260B. In this specification, the light-emitting device 260R, the light-emitting device 260G, and the light-emitting device 260B are collectively referred to as the light-emitting device 260. FIG. 14A also shows a cross-sectional view of the transistor 170 and the transistor 180 in the channel length direction.

[0226] The transistor 170 is provided on a substrate 101 and includes an element isolation layer 171, a conductor 175, an insulator 174, a semiconductor region 173 formed of part of the substrate 101, and low-resistance regions 172a and 172b functioning as a source region or a drain region. The transistor 170 can be applied to, for example, the source driver circuit 11 or the gate driver circuit 13 included in the peripheral circuit DRV described in the above embodiment. The transistor 170 can also be applied to, for example, the memory device 21, the GPU 22, and the like included in the functional circuit MFNC.

[0227] The substrate 101 is preferably a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).

[0228] For example, the transistor 170 has a top surface and side surfaces in the channel width direction of a semiconductor region 173 covered with a conductor 175 via an insulator 174. By forming the transistor 170 as a fin type in this manner, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 170. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 170.

[0229] The transistor 170 may be either a p-channel type or an n-channel type.

[0230] The region where the channel of the semiconductor region 173 is formed, the region nearby, the low-resistance region 172a that serves as the source region or the drain region, and the low-resistance region 172b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 170 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0231] The conductor 175 functioning as the gate electrode can be made of a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material.

[0232] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0233] The element isolation layer 171 is provided to isolate a plurality of transistors formed on the substrate 101. The element isolation layer 171 can be formed by, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, a mesa isolation method, or the like.

[0234] 14A is just an example, and the transistor 170 is not limited to this structure, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 170 may have a planar structure instead of a FIN structure.

[0235] In the transistor 170 shown in FIG. 14A, an insulator 116, an insulator 117, and an insulator 118 are stacked in this order.

[0236] The insulators 116 and 117 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0237] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0238] The insulator 117 may function as a planarizing film that flattens steps caused by the insulator 116 and the transistor 170 covered by the insulator 117. For example, the top surface of the insulator 117 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0239] The insulator 118 is preferably a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 101, the transistor 170, or the like to a region above the insulator 118.

[0240] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion to a circuit element provided above the insulator 118 may degrade the characteristics of the circuit element. Therefore, a film that suppresses hydrogen diffusion is preferably used between the circuit element and the transistor 170. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0241] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorbed hydrogen from the insulator 118 is calculated by TDS analysis as follows: when the surface temperature of the film is in the range of 50° C. to 500° C., the amount of desorbed hydrogen converted into hydrogen atoms is 10×10 per area of ​​the insulator 118. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0242] Note that the insulator 118 preferably has a lower dielectric constant than the insulator 117. For example, the relative dielectric constant of the insulator 118 is preferably less than 4, more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 118 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 117. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0243] Furthermore, insulators 116, 117, and 118, conductors 126 and the like are embedded, which connect to circuit elements (for example, transistor 180 included in the display unit DSP, light-emitting devices 260R to 260B, etc.) provided above insulator 118. Note that conductor 126 functions as a plug or wiring. Furthermore, for conductors that function as plugs or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0244] As the material for each plug and wiring (conductor 126, conductor 127 and conductor 128 described later, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0245] A wiring layer (not shown) may be provided above the insulator 118.

[0246] 14A, an insulator 221 is stacked above the insulator 118. The insulator 221 functions as a base film for the transistor 180.

[0247] Further, a conductor 211 functioning as a gate electrode of the transistor 180 or a wiring is formed over the insulator 221.

[0248] An insulator 222 functioning as a gate insulating film of the transistor 180 is formed over the insulator 221 and the conductor 211.

[0249] Furthermore, a conductor 127 and the like that connect to the transistor 180 and the circuit elements included in the circuit portion SIC are embedded in the insulator 221 and the insulator 222. Note that the conductor 127 functions as a plug or a wiring.

[0250] 14A, the semiconductor 231 is formed on the insulator 222. In addition, the semiconductor 231 is formed so as to include a region overlapping with the conductor 211.

[0251] As the semiconductor 231, for example, the metal oxide described in the fourth embodiment can be used. As the semiconductor 231, for example, a semiconductor material such as Si or Ge can be used. As the semiconductor 231, for example, a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe can be used. As the semiconductor 231, for example, a carbon nanotube or an organic semiconductor can be used.

[0252] Further, conductors 212 are formed on the insulator 222, the conductor 127, and the semiconductor 231. The conductors 212 are formed as a pair with the semiconductor 231 interposed therebetween. One of the pair of conductors 212 functions as one of the source or drain of the transistor 180, and the other of the pair of conductors 212 functions as the other of the source or drain of the transistor 180. Furthermore, in FIG. 14A , one of the pair of conductors 212 is formed so as to be electrically connected to the conductor 127.

[0253] Note that although Figure 14A shows an example in which the conductor 127 is electrically connected to one of the source and drain of the transistor 180, the conductor 127 may be electrically connected to the other of the source and drain of the transistor 180, or may be electrically connected to the gate of the transistor 180.

[0254] An insulator 223 and an insulator 224 are formed in this order on the insulator 222, the conductor 212, and the semiconductor 231.

[0255] Next, light-emitting device 260R, light-emitting device 260G, and light-emitting device 260B that can be provided on insulator 224 will be described. It is preferable that each light-emitting device emits a different color. In this embodiment, as an example, light-emitting device 260R emits red, light-emitting device 260G emits green, and light-emitting device 260B emits blue, and to easily distinguish between the light-emitting devices, the symbols R, G, and B are assigned within the light-emitting regions of each light-emitting device.

[0256] An insulator 251 is formed on the insulator 224 .

[0257] Furthermore, a conductor 128 and the like that connect to the transistor 180 and the circuit elements included in the circuit portion SIC are embedded in the insulator 224 and the insulator 251. Note that the conductor 128 functions as a plug or a wiring.

[0258] On the insulator 251 and the conductor 128, pixel electrodes 261 of the light emitting devices 260R, 260G, and 260B are formed.

[0259] Furthermore, an insulator 272 is provided to cover the end of the pixel electrode 261. The end of the insulator 272 is preferably tapered.

[0260] An EL layer 262R, an EL layer 262G, and an EL layer 262B are formed on the upper surface of the pixel electrode 261 and on a portion of the surface of the insulator 272. In addition, it is preferable that the ends of the EL layer 262R, the EL layer 262G, and the EL layer 262B are located on the insulator 272 during formation.

[0261] 14A, an EL layer 262R that emits red (R) light, an EL layer 262G that emits green (G) light, and an EL layer 262B that emits blue (B) light are independently provided on a plurality of pixel electrodes 261. In this specification, a structure in which different light-emitting layers for different colors are formed on a plurality of pixel electrodes 261 is referred to as an SBS (Side By Side) structure.

[0262] 14A has an SBS structure, the display device (display system) may have a structure in which a light-emitting layer that emits white light is formed in a continuous manner on a plurality of pixel electrodes 261, and red (R), green (G), and blue (B) colored layers (for example, color filters) are provided on the plurality of pixel electrodes 261. In particular, by forming the white light-emitting layer in a tandem structure described later, a white light-emitting device with high brightness and a long life can be obtained.

[0263] The EL layer 262R, the EL layer 262G, and the EL layer 262B may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0264] For example, as shown in FIG. 15A, the EL layer 262R, the EL layer 262G, and the EL layer 262B can be configured with multiple layers such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can have, for example, a layer containing a substance with high electron injection properties (electron injection layer) and a layer containing a substance with high electron transport properties (electron transport layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with high hole injection properties (hole injection layer) and a layer containing a substance with high hole transport properties (hole transport layer).

[0265] A structure having the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 15A is referred to as a single structure in this specification and the like.

[0266] As shown in FIG. 15B, a configuration in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0267] 15C, a configuration in which a plurality of light-emitting units (EL layer 262a, EL layer 262b) are connected in series via an intermediate layer (charge generating layer) 4440 is referred to as a tandem structure in this specification. Note that, although the configuration shown in FIG. 15C is referred to as a tandem structure in this specification, it is not limited thereto, and for example, the tandem structure may also be referred to as a stack structure. Note that by using a tandem structure, a light-emitting device capable of emitting light with high brightness can be obtained.

[0268] The light-emitting device 260 can emit light in red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 262. Furthermore, the color purity can be further improved by providing the light-emitting device 260 with a microcavity structure.

[0269] A light-emitting device that emits white light preferably has a structure in which the light-emitting layer contains two or more light-emitting materials. To obtain white light, it is sufficient to select two or more light-emitting materials whose respective emissions are complementary colors.

[0270] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0271] 14A, a gap is provided between two EL layers between light-emitting devices of different colors. In this manner, it is preferable that the EL layer 262R, the EL layer 262G, and the EL layer 262B are provided so as not to contact each other. This makes it possible to effectively prevent current from flowing through two adjacent EL layers, resulting in unintended light emission (also known as crosstalk). This allows for increased contrast, resulting in a display device with high display quality.

[0272] The EL layer 262R, the EL layer 262G, and the EL layer 262B can be separately fabricated by vacuum deposition using a shadow mask such as a metal mask. Alternatively, they may be separately fabricated by photolithography. By using photolithography, it is possible to realize a high-definition display device that is difficult to achieve using a metal mask.

[0273] A common electrode 263 is provided on the insulator 272, the EL layer 262R, the EL layer 262G, and the EL layer 262G. The common electrode 263 is provided as a continuous layer common to each light-emitting device.

[0274] In this case, the light-emitting device 260R, the light-emitting device 260G, and the light-emitting device 260B are configured such that an EL layer 262R, an EL layer 262G, and an EL layer 262B are provided between the pixel electrode 261 and the common electrode 263, respectively. The EL layer 262R contains a light-emitting organic compound that emits light having an intensity in at least the red wavelength range. The EL layer 262G of the light-emitting device 260G contains a light-emitting organic compound that emits light having an intensity in at least the green wavelength range. The EL layer 262B of the light-emitting device 260B contains a light-emitting organic compound that emits light having an intensity in at least the blue wavelength range.

[0275] 14A, a pixel electrode 261 is provided for each light-emitting device. Conversely, for example, by selecting a reflective conductive material for the pixel electrode 261 and a light-transmitting conductive material for the common electrode 263, a top-emission display device can be obtained.

[0276] Furthermore, a protective layer 271 is provided on the common electrode 263 to cover the light-emitting device 260R, the light-emitting device 260G, and the light-emitting device 260B. The protective layer 271 has a function of preventing impurities such as water from diffusing from above to each light-emitting device.

[0277] The protective layer 271 may have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide may be used for the protective layer 271. Note that the protective layer 271 may be formed by an ALD method, a CVD method, or a sputtering method. Note that, although the protective layer 271 includes an inorganic insulating film, this is not limiting. For example, the protective layer 271 may have a stacked structure including an inorganic insulating film and an organic insulating film.

[0278] As an example, the light emitting devices 260R, 260G, and 260B may be arranged in a matrix. However, the arrangement of the light emitting devices is not limited to this, and other arrangements such as a delta arrangement or a zigzag arrangement may also be used, or a pentile arrangement may also be used.

[0279] Furthermore, it is preferable to use EL elements such as OLEDs (Organic Light Emitting Diodes) or QLEDs (Quantum-dot Light Emitting Diodes) as light-emitting devices 260R, 260G, and 260B. Examples of light-emitting materials that EL elements have include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and materials that exhibit thermally activated delayed fluorescence (TADF materials).

[0280] The display device or display system of one embodiment of the present invention is not limited to the configuration shown in FIG. 14A . Although a display device or display system using light-emitting devices of three colors is described in FIG. 14A , the display device or display system of one embodiment of the present invention may be, for example, a display device or display system using a white light-emitting device and colored layers of each color. In this case, the white light-emitting device may have a single light-emitting layer structure shown in FIG. 15A or 15B , or a tandem light-emitting layer structure shown in FIG. 15C .

[0281] 14B, the light emitting device 260W has an EL layer 262W that emits white light between the pixel electrode and the common electrode 263.

[0282] The EL layer 262W may be configured by stacking two or more light-emitting layers selected so that the emitted light colors are complementary to each other. Alternatively, a stacked EL layer may be used in which a charge generating layer is sandwiched between light-emitting layers.

[0283] 14B shows three light-emitting devices 260W lined up. A colored layer 264R is provided on top of the left light-emitting device 260W. The colored layer 264R functions as a bandpass filter that transmits red light. Similarly, a colored layer 264G that transmits green light is provided on top of the center light-emitting device 260W, and a colored layer 264B that transmits blue light is provided on top of the right light-emitting device 260W. This allows the display device to display color images.

[0284] Here, the EL layer 262W and the common electrode 263 are separated between two adjacent light-emitting devices 260W. This effectively prevents unintended light emission due to current flowing through the EL layer 262W between the two adjacent light-emitting devices 260W. In particular, when a stacked EL element in which a charge-generating layer is provided between two light-emitting layers is used as the EL layer 262W, the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using such a configuration, a display device that combines high resolution and high contrast can be realized.

[0285] The EL layer 262W and the common electrode 263 are preferably separated by photolithography, which allows the distance between the light-emitting devices to be narrowed, thereby achieving a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0286] Fig. 16 is a cross-sectional view showing an example of the configuration of the display device shown in Fig. 3A or the display system shown in Fig. 4 and Fig. 6. The display system in Fig. 16 is configured such that the circuit unit SIC includes a transistor 170, the layer OSC includes a transistor 500, and the display unit DSP includes a transistor 180, a light-emitting device 260R, a light-emitting device 260G, and a light-emitting device 260B. Fig. 16 also shows cross-sectional views of the transistors 170, 180, and 500 in the channel length direction.

[0287] Furthermore, the description of FIG. 14A can be applied to the circuit section SIC and the display section DSP, so the following will describe the transistor 500 included in the layer OSC and its peripheral configuration.

[0288] An insulator 512 is formed above the insulator 118 of the circuit section SIC. The insulator 512 is preferably made of a material that has barrier properties against oxygen and hydrogen.

[0289] The insulator 512 may be made of the same material as the insulator 116, for example.

[0290] As shown in FIGS. 17A and 17B, an insulator 514 and an insulator 516 are formed on the insulator 512.

[0291] The insulator 514 is preferably a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 101 or a region where the transistor 170 is provided to a region where the transistor 500 is provided. Therefore, the insulator 514 can be, for example, silicon nitride formed by a CVD method.

[0292] The insulator 516 can be made of, for example, the same material as the insulator 116 .

[0293] Above the insulator 516 is the transistor 500 .

[0294] As shown in FIGS. 17A and 17B , the transistor 500 includes an insulator 516 on an insulator 514, a conductor 503 (conductors 503a and 503b) disposed so as to be embedded in the insulator 514 or the insulator 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, a conductor 542a on the oxide 530b, an insulator 571a on the conductor 542a, and a conductor 542b on the oxide 530b. 542b, insulator 571b on conductor 542b, insulator 552 on oxide 530b, insulator 550 on insulator 552, insulator 554 on insulator 550, conductor 560 (conductor 560a and conductor 560b) located on insulator 554 and overlapping with part of oxide 530b, and insulator 544 arranged on insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542 (conductor 542a and conductor 542b), and insulator 571 (insulator 571a and insulator 571b). 17A and 17B , insulator 552 contacts the upper surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side surface and upper surface of oxide 530b, the side surface of conductor 542, the side surface of insulator 571, the side surface of insulator 544, the side surface of insulator 580, and the lower surface of insulator 550. Furthermore, the upper surface of conductor 560 is disposed so as to be at approximately the same height as the upper surfaces of insulators 554, 550, 552, and 580. Furthermore, insulator 574 contacts at least a portion of the upper surface of conductor 560, 552, 550, 554, and 580.

[0295] Openings reaching the oxide 530b are provided in the insulator 580 and the insulator 544. The insulator 552, the insulator 550, the insulator 554, and the conductor 560 are disposed in the openings. In addition, the conductor 560, the insulator 552, the insulator 550, and the insulator 554 are provided between the insulator 571a and the conductor 542a and between the insulator 571b and the conductor 542b in the channel length direction of the transistor 500. The insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.

[0296] The oxide 530 preferably includes an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By providing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b.

[0297] Note that although the transistor 500 has a structure in which the oxide 530 has two layers, the oxide 530a and the oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a single layer of the oxide 530b or a stacked structure of three or more layers. Alternatively, each of the oxide 530a and the oxide 530b can have a stacked structure.

[0298] The conductor 560 functions as a first gate (also referred to as a top gate) electrode, and the conductor 503 functions as a second gate (also referred to as a back gate) electrode. The insulators 552, 550, and 554 function as a first gate insulator, and the insulators 522 and 524 function as a second gate insulator. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 542a functions as either a source or a drain, and the conductor 542b functions as the other. At least a part of a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0299] FIG. 18A shows an enlarged view of the vicinity of the channel formation region in FIG. 17A. When oxygen is supplied to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Therefore, as shown in FIG. 18A, the oxide 530b includes a region 530bc that functions as the channel formation region of the transistor 500, and regions 530ba and 530bb that are provided on either side of the region 530bc and function as source and drain regions. At least a portion of the region 530bc overlaps with the conductor 560. In other words, the region 530bc is located in the region between the conductor 542a and the conductor 542b. The region 530ba overlaps with the conductor 542a, and the region 530bb overlaps with the conductor 542b.

[0300] The region 530bc, which functions as a channel formation region, has a smaller oxygen vacancy (in this specification, oxygen vacancy in a metal oxide is referred to as V) than the regions 530ba and 530bb. O The region 530bc is a high-resistance region with a low carrier concentration due to its low oxygen vacancy or low impurity concentration. Therefore, the region 530bc can be said to be i-type (intrinsic) or substantially i-type.

[0301] A transistor using a metal oxide has impurities or oxygen vacancies (V O ) may cause fluctuations in electrical characteristics and reduce reliability. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V OIt is preferable that H is reduced as much as possible.

[0302] The regions 530ba and 530bb that function as source and drain regions have oxygen vacancies (V O ) or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, resulting in an increased carrier concentration and low resistance. That is, the regions 530ba and 530bb are n-type regions with a higher carrier concentration and lower resistance than the region 530bc.

[0303] Here, the carrier concentration of the region 530bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 530bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0304] A region having a carrier concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc may be formed between region 530bc and regions 530ba or 530bb. That is, this region functions as a junction region between region 530bc and regions 530ba or 530bb. The junction region may have a hydrogen concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc. The junction region may also have oxygen vacancies equal to or lower than those of regions 530ba and 530bb and equal to or higher than those of region 530bc.

[0305] 18A shows an example in which the regions 530ba, 530bb, and 530bc are formed in the oxide 530b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 530b but also in the oxide 530a.

[0306] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than gradually varying from region to region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in the region closer to the channel formation region.

[0307] In the transistor 500, the oxide 530 including the channel formation region (the oxide 530a and the oxide 530b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0308] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0309] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 530. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0310] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0311] In this way, by disposing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 530a into the oxide 530b.

[0312] Furthermore, since the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Because the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0313] The oxide 530b preferably has crystallinity, and in particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 530b.

[0314] CAAC-OS has a highly crystalline and dense structure, and is free of impurities and defects (e.g., oxygen vacancies (V O In particular, the CAAC-OS can be made to have a dense structure with higher crystallinity by heat-treating the formed metal oxide at a temperature (for example, 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0315] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0316] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy is converted into a defect where hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0317] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 500. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies across the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0318] Therefore, in the oxide semiconductor, the region 530bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 530ba and 530bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 530ba and 530bb.

[0319] Therefore, in this embodiment, in a state where the conductors 542a and 542b are provided on the oxide 530b, microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 530bc and V O The microwave treatment here refers to a treatment using a device with a power source that generates high-density plasma using microwaves, for example.

[0320] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 530bc. The V of the region 530bc can be activated by the action of the plasma, microwaves, etc. O H is split off, hydrogen H is removed from the region 530bc, and oxygen vacancy V Ocan be compensated with oxygen. That is, in the region 530bc, O H→H+V O This reaction occurs, and the hydrogen concentration in the region 530bc can be reduced. O H can be reduced to lower the carrier concentration.

[0321] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 542a and 542b and do not reach the regions 530ba and 530bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 571 and 580 that cover the oxide 530b and the conductor 542. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0322] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 552 or after forming the insulating film that becomes the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 552 or the insulator 550 in this manner, oxygen can be efficiently injected into the region 530bc. Furthermore, by arranging the insulator 552 so as to be in contact with the side surface of the conductor 542 and the surface of the region 530bc, injection of more oxygen than necessary into the region 530bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 542. Furthermore, oxidation of the side surface of the conductor 542 can be suppressed during formation of the insulating film that becomes the insulator 550.

[0323] The oxygen implanted into the region 530bc can be in various forms, such as oxygen atoms, oxygen molecules, or oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 530bc preferably takes one or more of the above forms, and oxygen radicals are particularly preferred. This can improve the film quality of the insulators 552 and 550, thereby improving the reliability of the transistor 500.

[0324] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 530bc. O By removing H, the region 530bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 530ba and 530bb, which function as source and drain regions, can be suppressed, thereby maintaining conductivity. This suppresses fluctuations in the electrical characteristics of the transistor 500 and reduces variations in the electrical characteristics of the transistor 500 within the substrate surface.

[0325] By adopting the above-described configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0326] 17B, ​​in a cross-sectional view of the transistor 500 in the channel width direction, a curved surface may be formed between the side surface of the oxide 530b and the top surface of the oxide 530b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0327] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 530b with the insulators 552, 550, and 554, and the conductor 560.

[0328] The oxide 530 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0329] The oxide 530b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 530b. This can reduce the extraction of oxygen from the oxide 530b even during heat treatment, making the transistor 500 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0330] Here, the conduction band minimum changes gradually at the junction between the oxides 530a and 530b. In other words, the conduction band minimum at the junction between the oxides 530a and 530b changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxides 530a and 530b.

[0331] Specifically, when the oxide 530a and the oxide 530b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-M-Zn oxide, the oxide 530a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0332] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. Oxide 530b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0333] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0334] 17A and other figures, providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530 can cause indium in the oxide 530 to be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. This results in an atomic ratio near the surface of the oxide 530 that is close to that of indium oxide or In-Zn oxide. The increased atomic ratio of indium near the surface of the oxide 530, particularly the oxide 530b, can improve the field-effect mobility of the transistor 500.

[0335] The oxide 530a and the oxide 530b have the above-described structure, which can reduce the defect state density at the interface between the oxide 530a and the oxide 530b. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can achieve a large on-state current and high frequency characteristics.

[0336] At least one of the insulators 512, 514, 544, 571, 574, 576, and 581 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 is preferably made of an insulating material that suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably made of an insulating material that suppresses diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., through which the above oxygen is less likely to permeate).

[0337] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0338] For the insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use an insulator that has the function of suppressing diffusion of oxygen and impurities such as water and hydrogen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has a high hydrogen barrier property, is preferably used for the insulators 512, 544, and 576. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high ability to capture and fix hydrogen, for the insulators 514, 571, 574, and 581. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Alternatively, impurities such as water and hydrogen can be prevented from diffusing toward the transistor 500 from an interlayer insulating film disposed outside the insulator 581. Alternatively, oxygen contained in the insulator 524 and the like can be prevented from diffusing toward the substrate through the insulators 512 and 514. Alternatively, oxygen contained in the insulator 580 and the like can be prevented from diffusing upward from the transistor 500 through the insulator 574. In this way, the transistor 500 is preferably surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of preventing the diffusion of impurities such as water and hydrogen and oxygen.

[0339] Here, it is preferable to use an oxide having an amorphous structure as the insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen present around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a highly reliable transistor 500 and semiconductor device can be manufactured with excellent characteristics.

[0340] Furthermore, the insulators 512, 514, 544, 571, 574, 576, and 581 preferably have an amorphous structure, but may have a polycrystalline structure in part. The insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0341] The insulators 512, 514, 544, 571, 574, 576, and 581 can be formed by, for example, a sputtering method. Sputtering does not require the use of molecules containing hydrogen in the film formation gas, and therefore can reduce the hydrogen concentrations of the insulators 512, 514, 544, 571, 574, 576, and 581. Note that the film formation method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like may also be used as appropriate.

[0342] It may also be desirable to reduce the resistivity of insulators 512, 544, and 576. For example, it may be desirable to reduce the resistivity of insulators 512, 544, and 576 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulators 512, 544, and 576 may be able to reduce charge-up of the conductors 503, 542, and 560 during treatment using plasma or the like in the manufacturing process of a semiconductor device. The resistivity of the insulators 512, 544, and 576 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0343] The insulators 516, 574, 580, and 581 preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 516, 580, and 581.

[0344] For example, the insulator 581 is preferably an insulator that functions as an interlayer film, a planarizing film, or the like.

[0345] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Here, the conductor 503 is preferably provided by being embedded in an opening formed in the insulator 516. In addition, a part of the conductor 503 may be embedded in the insulator 514.

[0346] The conductor 503 includes a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and sidewall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the top of the conductor 503b is approximately the same as the height of the top of the conductor 503a and the height of the top of the insulator 516.

[0347] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0348] By using a conductive material that can reduce hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 524 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 503a, it is possible to prevent the conductor 503b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 503a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 503a may be made of titanium nitride.

[0349] The conductor 503b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0350] The conductor 503 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the Vth of the transistor 500 and reduce its off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0351] Note that if the oxide 530 is highly pure and intrinsic, and impurities are removed from the oxide 530 as much as possible, it may be possible to make the transistor 500 normally off (to make the threshold voltage of the transistor 500 higher than 0 V) ​​without applying a potential to the conductor 503 and / or the conductor 560. In this case, it is preferable to connect the conductor 560 and the conductor 503 so that the same potential is applied to them.

[0352] The electrical resistivity of the conductor 503 is designed taking into consideration the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the range permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby reducing the diffusion of the impurities into the oxide 530.

[0353] Note that the conductor 503 is preferably larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in FIG. 17B , the conductor 503 preferably extends to an area outside the channel width direction ends of the oxides 530a and 530b. That is, outside the side surfaces of the oxide 530 in the channel width direction, the conductor 503 and the conductor 560 preferably overlap with each other via an insulator. With this structure, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560, which functions as the first gate electrode, and the electric field of the conductor 503, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0354] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0355] By configuring the transistor 500 as a normally-off transistor and adopting the above-described S-Channel structure, the channel formation region can be electrically surrounded. Therefore, the transistor 500 can also be considered to have a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By configuring the transistor 500 as an S-Channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulating film can be the entire bulk of the oxide 530. In other words, by configuring the transistor 500 as an S-Channel structure, a GAA structure, or an LGAA structure, the entire bulk can be used as a carrier path, making it a so-called bulk-flow type. The bulk-flow type transistor structure can increase the current density flowing through the transistor, which is expected to improve the on-state current or field-effect mobility of the transistor.

[0356] 17B, ​​the conductor 503 is extended to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 503. Furthermore, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0357] Note that although the conductor 503 in the transistor 500 has a stacked structure of the conductor 503a and the conductor 503b, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0358] Insulator 522 and insulator 524 function as gate insulators.

[0359] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.

[0360] The insulator 522 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 to the substrate and diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, the insulator 522 can suppress diffusion of impurities such as hydrogen into the transistor 500 and suppress generation of oxygen vacancies in the oxide 530. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0361] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 522 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0362] The insulator 522 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more highly integrated, thinning of the gate insulator can lead to problems such as leakage current. Using a high-k material as the gate insulator can reduce the gate potential during transistor operation while maintaining the physical film thickness. Alternatively, the insulator 522 may be made of a material with a high dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST).

[0363] The insulator 524 in contact with the oxide 530 can be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0364] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0365] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, OFurthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0366] The insulators 522 and 524 may each have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 524 may be formed in an island shape overlapping the oxide 530a. In this case, the insulator 544 is configured to contact the side surface of the insulator 524 and the top surface of the insulator 522.

[0367] The conductor 542a and the conductor 542b are provided in contact with the top surface of the oxide 530b. The conductor 542a and the conductor 542b function as a source electrode and a drain electrode of the transistor 500, respectively.

[0368] As the conductor 542 (conductor 542a and conductor 542b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0369] Note that hydrogen contained in the oxide 530b and the like may diffuse into the conductor 542a or the conductor 542b. In particular, by using a nitride containing tantalum for the conductors 542a and 542b, hydrogen contained in the oxide 530b and the like is likely to diffuse into the conductor 542a or the conductor 542b, and the diffused hydrogen may bond with nitrogen contained in the conductor 542a or the conductor 542b. In other words, hydrogen contained in the oxide 530b and the like may be absorbed by the conductor 542a or the conductor 542b.

[0370] Furthermore, it is preferable that no curved surface be formed between the side surface of the conductor 542 and the top surface of the conductor 542. The conductor 542 without such a curved surface can increase the cross-sectional area of ​​the conductor 542 in the cross section in the channel width direction. This can increase the conductivity of the conductor 542 and the on-state current of the transistor 500.

[0371] The insulator 571a is provided in contact with the top surface of the conductor 542a, and the insulator 571b is provided in contact with the top surface of the conductor 542b. The insulator 571 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 571 preferably has a function of suppressing oxygen diffusion. For example, the insulator 571 preferably has a function of suppressing oxygen diffusion more than the insulator 580. The insulator 571 may be, for example, a nitride containing silicon, such as silicon nitride. The insulator 571 preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 571 may be an insulator of a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 571 is preferable because hydrogen can be more effectively captured or fixed. This enables the manufacture of a highly reliable transistor 500 and a semiconductor device with favorable characteristics.

[0372] The insulator 544 is provided to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has a function of capturing and fixing hydrogen. In this case, the insulator 544 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 544 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0373] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be surrounded by an insulator having a barrier property against oxygen. That is, oxygen contained in the insulator 524 and the insulator 580 can be prevented from diffusing into the conductor 542. This can prevent the conductor 542 from being directly oxidized by the oxygen contained in the insulator 524 and the insulator 580, which increases the resistivity and reduces the on-state current.

[0374] The insulator 552 functions as part of the gate insulator. The insulator 552 is preferably a barrier insulating film against oxygen. Any of the insulators that can be used for the insulator 574 described above can be used as the insulator 552. The insulator 552 can be an insulator containing one or both of an oxide of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 contains at least oxygen and aluminum.

[0375] As shown in FIG. 17B, the insulator 552 is provided in contact with the top surface and side surfaces of the oxide 530b, the side surfaces of the oxide 530a, the side surfaces of the insulator 524, and the top surface of the insulator 522. That is, the regions of the oxide 530a, the oxide 530b, and the insulator 524 that overlap with the conductor 560 are covered with the insulator 552 in the cross section in the channel width direction. This allows the insulator 552, which has oxygen barrier properties, to block oxygen from being released from the oxides 530a and 530b during heat treatment or the like. This reduces the formation of oxygen vacancies (Vo) in the oxides 530a and 530b. This reduces the oxygen vacancies (Vo) and V formed in the region 530bc. O H can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved, and the reliability can be improved.

[0376] Conversely, even if the insulator 580, the insulator 550, or the like contains excessive amounts of oxygen, the oxygen can be prevented from being excessively supplied to the oxide 530a and the oxide 530b. Therefore, the region 530bc can prevent the regions 530ba and 530bb from being excessively oxidized, which would cause a decrease in the on-state current or the field-effect mobility of the transistor 500.

[0377] 17A , the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 571, the insulator 544, and the insulator 580. This reduces the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface. This reduces the on-state current or field-effect mobility of the transistor 500.

[0378] The insulator 552, together with the insulator 554, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 552 preferably has a small thickness. The thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 552 only needs to have at least a region with the above-described thickness. The thickness of the insulator 552 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 552 only needs to have at least a region with a thickness thinner than the insulator 550.

[0379] To form the insulator 552 into a thin film as described above, it is preferable to form the film by the ALD method. The ALD method includes a thermal ALD method in which the reaction between a precursor and a reactant is carried out using only thermal energy, and a PEALD (Plasma Enhanced ALD) method in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, allowing film formation at a lower temperature.

[0380] The ALD method utilizes the self-regulating property of atoms and can deposit atoms one layer at a time, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with few defects such as pinholes, film formation with excellent coverage, film formation at low temperatures, etc. Therefore, the insulator 552 can be formed with good coverage on the side surfaces of an opening formed in the insulator 580 or the like and with the thin film thickness described above.

[0381] Some precursors used in ALD contain carbon and other impurities. Therefore, films formed by ALD may contain more carbon and other impurities than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0382] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. The insulator 550 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 550 is an insulator containing at least oxygen and silicon.

[0383] Like the insulator 524, the insulator 550 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of the insulator 550 preferably has a lower limit of 1 nm or more, or 0.5 nm or more, and an upper limit of 15 nm or less, or 20 nm or less. Note that the above-mentioned lower and upper limits can be combined. In this case, the insulator 550 only needs to have a region with the above-mentioned thickness in at least a portion thereof.

[0384] 17A and 17B show a configuration in which the insulator 550 is a single layer, but the present invention is not limited to this and the insulator 550 may have a laminated structure of two or more layers. For example, as shown in Fig. 18B, the insulator 550 may have a two-layer laminated structure of an insulator 550a and an insulator 550b on the insulator 550a.

[0385] As shown in FIG. 18B , when the insulator 550 has a two-layer stacked structure, the lower insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper insulator 550b is preferably formed using an insulator that suppresses oxygen diffusion. This structure can suppress the oxygen contained in the insulator 550a from diffusing into the conductor 560. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 530. It can also suppress oxidation of the conductor 560 due to the oxygen contained in the insulator 550a. For example, the insulator 550a may be formed using a material that can be used for the insulator 550 described above, and the insulator 550b may be formed using an insulator containing one or both of aluminum and hafnium oxides. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b contains at least oxygen and hafnium. The thickness of the insulator 550b preferably has a lower limit of 0.5 nm or more, or 1.0 nm or more, and an upper limit of 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned thickness in at least a portion.

[0386] When silicon oxide, silicon oxynitride, or the like is used for the insulator 550a, the insulator 550b may be an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator as a layered structure of the insulators 550a and 550b, a layered structure that is thermally stable and has a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 550 to be increased.

[0387] The insulator 554 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 554. This can prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and the oxide 530b. The insulator 554 can be any of the insulators that can be used for the insulator 576. For example, silicon nitride formed by a PEALD method can be used as the insulator 554. In this case, the insulator 554 contains at least nitrogen and silicon.

[0388] The insulator 554 may further have a barrier property against oxygen, which can prevent oxygen contained in the insulator 550 from diffusing into the conductor 560.

[0389] The insulator 554, together with the insulator 552, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 554 preferably has a thin thickness. The lower limit of the thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and the upper limit is preferably 3.0 nm or less or 5.0 nm or less. The above-described lower and upper limits can be combined. In this case, the insulator 554 only needs to have at least a region with the above-described thickness. The insulator 554 is preferably thinner than the insulator 550. In this case, the insulator 554 only needs to have at least a region with a thinner thickness than the insulator 550.

[0390] The conductor 560 functions as a first gate electrode of the transistor 500. The conductor 560 preferably includes a conductor 560a and a conductor 560b disposed over the conductor 560a. For example, the conductor 560a is preferably disposed so as to surround the bottom and side surfaces of the conductor 560b. As shown in FIGS. 17A and 17B, the height of the top of the conductor 560 roughly coincides with the height of the top of the insulator 550. Note that although the conductor 560 is shown as having a two-layer structure of the conductor 560a and the conductor 560b in FIGS. 17A and 17B, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers other than the two-layer structure.

[0391] The conductor 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0392] Furthermore, since conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of conductor 560b caused by oxygen contained in insulator 550. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0393] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b can have a layered structure. Specifically, for example, the conductor 560b can have a layered structure of titanium or titanium nitride and the above conductive material.

[0394] Furthermore, in the transistor 500, the conductor 560 is formed in a self-aligned manner so as to fill an opening formed in the insulator 580 or the like. By forming the conductor 560 in this manner, the conductor 560 can be reliably placed in the region between the conductor 542a and the conductor 542b without alignment.

[0395] 17B, ​​in the channel width direction of the transistor 500, the height of the bottom surface of the conductor 560 in a region where the conductor 560 does not overlap with the oxide 530b is preferably lower than the height of the bottom surface of the oxide 530b when the bottom surface of the insulator 522 is used as the reference. When the conductor 560, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 530b via the insulator 550 or the like, the electric field of the conductor 560 can be easily applied to the entire channel formation region of the oxide 530b. Therefore, the on-state current of the transistor 500 can be increased, and the frequency characteristics can be improved. The difference between the height of the bottom surface of conductor 560 and the height of the bottom surface of oxide 530b in the region where oxide 530a and oxide 530b do not overlap with conductor 560, relative to the bottom surface of insulator 522, preferably has a lower limit of 0 nm or more, 3 nm or more, or 5 nm or more, and an upper limit of 20 nm or less, 50 nm or less, or 100 nm or less. Note that the above-mentioned lower and upper limits can be combined.

[0396] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are to be provided. The top surface of the insulator 580 may be planarized.

[0397] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 580 is preferably formed using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form a region containing oxygen that is released by heating.

[0398] The insulator 580 preferably has a low concentration of impurities such as water and hydrogen. For example, the insulator 580 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0399] The insulator 574 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580 and preferably has a function of capturing impurities such as hydrogen. The insulator 574 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 574 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 574 contains at least oxygen and aluminum. By providing the insulator 574, which is in contact with the insulator 580 and has a function of capturing impurities such as hydrogen, in the region between the insulators 512 and 581, the insulator 574 can capture impurities such as hydrogen contained in the insulator 580 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 574 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 500 and semiconductor device with excellent characteristics.

[0400] The insulator 576 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580. The insulator 576 is disposed over the insulator 574. The insulator 576 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 576 may be formed using silicon nitride deposited by a sputtering method. A high-density silicon nitride film can be formed by depositing the insulator 576 by a sputtering method. Alternatively, the insulator 576 may be formed by stacking a silicon nitride film deposited by a PEALD method or a CVD method on the silicon nitride film deposited by a sputtering method.

[0401] One of the first and second terminals of the transistor 500 is electrically connected to a conductor 540a that functions as a plug, and the other of the first and second terminals of the transistor 500 is electrically connected to a conductor 540b. Note that the conductors 540a, 540b, etc. may function as wiring for electrically connecting to the display unit DSP above or the circuit unit SIC below. Note that in this specification and the like, the conductors 540a and 540b will be collectively referred to as conductors 540.

[0402] For example, conductor 540a is provided in a region overlapping with conductor 542a. Specifically, in the region overlapping with conductor 542a, openings are formed in insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 17A , and conductor 540a is provided inside the openings. For example, conductor 540b is provided in a region overlapping with conductor 542b. Specifically, in the region overlapping with conductor 542b, openings are formed in insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 17A , and conductor 540b is provided inside the openings.

[0403] 17A, an insulator 541a may be provided as an insulator having barrier properties against impurities between the conductor 540a and a side surface of the opening in a region overlapping with the conductor 542a. Similarly, an insulator 541b may be provided as an insulator having barrier properties against impurities between the conductor 540b and a side surface of the opening in a region overlapping with the conductor 542b. Note that in this specification and the like, the insulators 541a and 541b are collectively referred to as the insulator 541.

[0404] The conductors 540a and 540b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 540a and 540b may have a layered structure.

[0405] Furthermore, when the conductor 540 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the insulators 574, 576, 581, 580, 544, and the first conductor disposed near the insulator 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 576 from being mixed into the oxide 530 through the conductors 540a and 540b.

[0406] The insulators 541a and 541b may be a barrier insulating film that can be used for the insulator 544, etc. For example, the insulators 541a and 541b may be made of an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 541a and 541b are provided in contact with the insulators 574, 576, and 571, and thus can prevent impurities such as water and hydrogen contained in the insulator 580 from entering the oxide 530 through the conductors 540a and 540b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b.

[0407] When insulators 541a and 541b are formed into a layered structure as shown in FIG. 17A, it is preferable that the first insulator in contact with the inner wall of an opening such as insulator 580 and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0408] For example, aluminum oxide formed by the ALD method can be used as the first insulator, and silicon nitride formed by the PEALD method can be used as the second insulator. With this structure, oxidation of the conductor 540 can be suppressed and hydrogen contamination of the conductor 540 can be reduced.

[0409] Although the transistor 500 has a structure in which the first insulator of the insulator 541 and the second conductor of the insulator 541 are stacked, the present invention is not limited to this. For example, the insulator 541 may be provided as a single layer or a stacked structure of three or more layers. Furthermore, the transistor 500 has a structure in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are stacked, but the present invention is not limited to this. For example, the conductor 540 may be provided as a single layer or a stacked structure of three or more layers.

[0410] Note that the structure of the transistor included in the semiconductor device of one embodiment of the present invention is not limited to the transistor 500 illustrated in Figures 16, 17A, and 17B. The structure of the transistor included in the semiconductor device of one embodiment of the present invention may be changed depending on the situation.

[0411] Although the transistor 180 included in the display portion DSP in this embodiment is a bottom-gate transistor, one embodiment of the present invention is not limited thereto. For example, the display device (display system) illustrated in FIG. 14A may have a structure similar to that of an OS transistor that can be used as a layer OSC, as in the display device (display system) illustrated in FIG. 19. The display device (display system) illustrated in FIG. 19 may also have a layer OSC, as in the display device (display system) illustrated in FIG. 20, similar to the display device (display system) illustrated in FIG. 16. That is, the display system of one embodiment of the present invention can have a structure including a plurality of stacked OS transistors.

[0412] As described above, by providing the circuit unit SIC and the display unit DSP above the circuit unit SIC, a display device or display system (herein referred to as the display device or display system as an ultra-high definition OLED system display) having functions such as image processing, image correction, frame rate variation, and artificial intelligence can be configured. Furthermore, by providing a layer OSC between the circuit units SIC and SIC, transistors other than those formed on the semiconductor substrate included in the circuit unit SIC can be provided, thereby broadening the design possibilities for the peripheral circuit DRV and the functional circuit MFNC included in the circuit unit SIC. Furthermore, by providing circuits in the layer OSC, an increase in the circuit area of ​​the ultra-high definition OLED system display can be prevented.

[0413] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0414] (Fourth embodiment) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0415] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0416] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 21A. Fig. 21A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0417] As shown in FIG. 21A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0418] The structure within the bold frame in Figure 21A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0419] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 21B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" (the vertical axis represents intensity in arbitrary units (au)). The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 21B may be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 21B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 21B is 500 nm.

[0420] As shown in Figure 21B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 21B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0421] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 21C. Figure 21C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 21C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0422] As shown in FIG. 21C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0423] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 21A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0424] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0425] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0426] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0427] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0428] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0429] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0430] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0431] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0432] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the formation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0433] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0434] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0435] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0436] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0437] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0438] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0439] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0440] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0441] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0442] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0443] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0444] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0445] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0446] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0447] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0448] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0449] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0450] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0451] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17atoms / cm 3 The following applies.

[0452] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0453] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0454] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0455] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0456] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0457] (Embodiment 5) In this embodiment, an example of a head-mounted display to which at least one of a display device and a display system is applied will be described as an example of an electronic device of one embodiment of the present invention.

[0458] 22A and 22B show the appearance of the head mounted display 8300.

[0459] The head mounted display 8300 includes a housing 8301, a display portion 8302, operation buttons 8303, and a band-shaped fixture 8304.

[0460] The operation button 8303 has a function of a power button, etc. In addition to the operation button 8303, other buttons may be provided.

[0461] 22C, a lens 8305 may be provided between the display unit 8302 and the user's eyes. The lens 8305 allows the user to view a magnified image of the display unit 8302, enhancing the sense of realism. In this case, as shown in FIG. 22C, a dial 8306 may be provided to change the position of the lens for diopter adjustment.

[0462] At least one of the display device and the display system of one embodiment of the present invention can be applied to the display portion 8302. At least one of the display device and the display system of one embodiment of the present invention has extremely high definition, so that even when an image is enlarged using the lens 8305 as in FIG. 22C , pixels are not visible to a user, and a more realistic image can be displayed.

[0463] 22A to 22C show an example in which one display portion 8302 is included. With such a configuration, the number of components can be reduced.

[0464] The display portion 8302 can display two images, one for the right eye and one for the left eye, side by side in two regions, left and right, respectively, thereby enabling display of a stereoscopic image using binocular parallax.

[0465] Alternatively, a single image that can be viewed with both eyes may be displayed across the entire area of ​​the display unit 8302. This allows a panoramic image to be displayed across both ends of the field of view, thereby enhancing the sense of reality.

[0466] Here, the head mounted display 8300 preferably has a mechanism for changing the curvature of the display portion 8302 to an appropriate value depending on the size of the user's head, the position of the user's eyes, etc. For example, the user may adjust the curvature of the display portion 8302 by operating a dial 8307 for adjusting the curvature of the display portion 8302. Alternatively, the housing 8301 may be provided with a sensor (for example, a camera, a contact sensor, a non-contact sensor, etc.) that detects the size of the user's head, the position of the user's eyes, etc., and the head mounted display 8300 may have a mechanism for adjusting the curvature of the display portion 8302 based on detection data from the sensor.

[0467] When the lens 8305 is used, it is preferable to provide a mechanism for adjusting the position and angle of the lens 8305 in synchronization with the curvature of the display portion 8302. Alternatively, the dial 8306 may have a function for adjusting the angle of the lens.

[0468] 22E and 22F show an example including a driver 8308 that controls the curvature of the display unit 8302. The driver 8308 is fixed to at least a part of the display unit 8302. The driver 8308 has a function of deforming the display unit 8302 by deforming or moving a part fixed to the display unit 8302.

[0469] 22E is a schematic diagram showing a case where a user 8310 with a relatively large head size is wearing housing 8301. At this time, the shape of display unit 8302 is adjusted by drive unit 8308 so that the curvature is relatively small (the radius of curvature is large).

[0470] On the other hand, Fig. 22F shows a case where a user 8311, whose head is smaller than that of the user 8310, is wearing the housing 8301. Furthermore, the distance between the eyes of the user 8311 is narrower than that of the user 8310. In this case, the shape of the display unit 8302 is adjusted by the driving unit 8308 so that the curvature of the display unit 8302 is large (the radius of curvature is small). In Fig. 22F, the position and shape of the display unit 8302 in Fig. 22E are indicated by dashed lines.

[0471] In this way, the head mounted display 8300 has a mechanism for adjusting the curvature of the display portion 8302, and can provide an optimal display to various users, regardless of age or gender.

[0472] Furthermore, by changing the curvature of the display portion 8302 depending on the content displayed on the display portion 8302, a high sense of realism can be given to the user. For example, a trembling motion can be expressed by vibrating the curvature of the display portion 8302. In this way, various effects can be produced according to the scene in the content, and a new experience can be provided to the user. Furthermore, by linking the display portion 8302 with a vibration module provided in the housing 8301, a more realistic display can be achieved.

[0473] Note that the head mounted display 8300 may have two display units 8302 as shown in FIG. 22D.

[0474] By having two display units 8302, the user can view one display unit per eye. This allows high-resolution images to be displayed even when performing 3D display using parallax. Furthermore, the display unit 8302 is curved in an arc shape roughly centered on the user's eye. This allows the distance from the user's eye to the display surface of the display unit to be constant, allowing the user to view more natural images. Furthermore, even if the brightness and chromaticity of light from the display unit change depending on the viewing angle, this effect can be substantially ignored because the user's eyes are positioned in the normal direction to the display surface of the display unit, allowing for the display of more realistic images.

[0475] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0476] (Embodiment 6) In this embodiment, a display module that can be manufactured using at least one of a display device and a display system according to one embodiment of the present invention will be described.

[0477] A display module 6000 shown in FIG. 23A has a display device 6006 connected by an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0478] For example, at least one of a display device and a display system manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0479] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately to match the size of the display device 6006.

[0480] The display device 6006 may have a function as a touch panel.

[0481] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0482] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.

[0483] FIG. 23B is a cross-sectional schematic diagram of a display module 6000 equipped with an optical touch sensor.

[0484] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. The display module 6000 also has a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) in an area surrounded by an upper cover 6001 and a lower cover 6002.

[0485] The display device 6006 is provided so as to overlap the printed circuit board 6010 and the battery 6011 with the frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to the light guide portions 6017a and 6017b.

[0486] Light 6018 emitted from light-emitting unit 6015 passes through light-guiding unit 6017a, passes through the upper part of display device 6006, and reaches light-receiving unit 6016 through light-guiding unit 6017b. When light 6018 is blocked by a detectable object such as a finger or a stylus, a touch operation can be detected.

[0487] A plurality of light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light-receiving units 6016 are provided at positions facing the light-emitting units 6015. This makes it possible to obtain information about the position where a touch operation is performed.

[0488] The light-emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light-receiving unit 6016 may be a photoelectric element that receives the light emitted by the light-emitting unit 6015 and converts it into an electrical signal. Preferably, a photodiode that can receive infrared light may be used.

[0489] The light guiding portions 6017a and 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, thereby preventing external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, using a resin that absorbs visible light and transmits infrared light can more effectively prevent the touch sensor from malfunctioning.

[0490] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0491] (Embodiment 7) In this embodiment, examples of electronic devices to which at least one of a display device and a display system according to one embodiment of the present invention can be applied will be described.

[0492] The electronic device 6500 shown in FIG. 24A is a portable information terminal that can be used as a smartphone.

[0493] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0494] At least one of the display device and the display system of one embodiment of the present invention can be applied to the display portion 6502.

[0495] FIG. 24B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0496] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0497] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0498] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to a terminal provided on a printed circuit board 6517.

[0499] For example, a flexible display panel can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, it is possible to mount a large-capacity battery 6518 while suppressing the thickness of the electronic device. In addition, by folding back a part of the display panel 6511 and arranging a connection part with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0500] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0501] (Embodiment 8) In this embodiment, an electronic device including at least one of a display device and a display system manufactured using one embodiment of the present invention will be described.

[0502] The electronic devices exemplified below include at least one of the display device and the display system according to one embodiment of the present invention in their display portions. Therefore, the electronic devices have high resolution. Furthermore, the electronic devices can have both high resolution and a large screen.

[0503] One embodiment of the present invention includes a display device and at least one of an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button.

[0504] The electronic device of one embodiment of the present invention may include a secondary battery, and it is preferable that the secondary battery can be charged using contactless power transmission.

[0505] Examples of secondary batteries include lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) that use a gel electrolyte, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0506] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0507] The display portion of the electronic device of one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0508] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0509] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a building such as a house or a building, or the interior or exterior of a car or the like.

[0510] FIG. 25A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0511] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. The camera 8000 also has a detachable lens 8006 attached thereto.

[0512] The camera 8000 may have the lens 8006 and the housing integrated together.

[0513] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0514] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as a strobe device and the like.

[0515] The finder 8100 includes a housing 8101 , a display unit 8102 , and a button 8103 .

[0516] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0517] The button 8103 has a function such as a power button.

[0518] At least one of the display device and the display system of one embodiment of the present invention can be applied to the display portion 8002 of the camera 8000 and the display portion 8102 of the finder 8100. Note that the camera 8000 may have a built-in finder.

[0519] 25B shows an external appearance of an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation buttons 5903, a crown 5904, a band 5905, and the like.

[0520] The wearable terminal can display high-quality images on the display portion 5902 by applying at least one of the display device and the display system described in the above embodiment.

[0521] 25C is a diagram showing the appearance of a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0522] Furthermore, the video images of the portable game machine 5200 can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0523] By applying at least one of the display device and the display system described in the above embodiment modes to the portable game console 5200, a high-quality image can be displayed in the display portion 5202. In addition, a low-power portable game console 5200 can be realized. Furthermore, the low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0524] FIG. 26A is a diagram showing the appearance of the head mounted display 8200.

[0525] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0526] A cable 8205 supplies power from a battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like, and can display received video information on a display portion 8204. The main body 8203 also includes a camera, and can use information on the movement of the user's eyeballs or eyelids as an input means.

[0527] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that come into contact with the user, capable of detecting a current that flows in accordance with the movement of the user's eyeballs. The wearing unit 8201 may also have a function of monitoring the user's pulse rate based on the current that flows through the electrodes. The wearing unit 8201 may also have various sensors, such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may also have a function of displaying the user's biological information on the display unit 8204 and a function of changing the image displayed on the display unit 8204 in accordance with the movement of the user's head.

[0528] At least one of the display device and the display system of one embodiment of the present invention can be applied to the display portion 8204.

[0529] 26B, 26C, and 26D are diagrams showing the appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0530] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to arrange the display portion 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing different images displayed in different regions of the display portion 8302 through the lens 8305, it is possible to perform 3D display using parallax. Note that the present invention is not limited to a configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided, with one display portion being provided for each eye of the user.

[0531] Note that at least one of the display device and the display system of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition, and therefore, even when an image is enlarged using a lens 8305 as in FIG. 26D , pixels are not visible to a user, and a more realistic image can be displayed.

[0532] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. [Explanation of symbols]

[0533] DSP: Display unit, OSC: Layer, SIC: Circuit unit, CHP: Circuit unit, DRV: Peripheral circuit, MFNC: Functional circuit, MFNCa: Functional circuit, MFNCb: Functional circuit, DRVa: Circuit, DRVb: Circuit, MDV: Memory device, PX: Pixel, MC: Memory cell, GL: Wiring, SL: Wiring, SNCL: Wiring, ML: Wiring, BSL: Bus wiring, MC1: Memory cell, MC2: Memory cell, MC2A: Memory cell, MC3: Memory cell, MC4: Memory cell, MC5: Memory cell, MC6: Memory cell, M1: Transistor, M2: Transistor, M3: Transistor, M1 0: transistor, M11: transistor, CA: capacitor, CB: capacitor, ME: MTJ element, FL: layer, TIS: layer, RL: layer, RM: resistive change element, PCM1: phase change memory, TE: electrode, CHL: phase change layer, BE: electrode, FEA: ferroelectric capacitor, WOL: wiring, BIL: wiring, CVL: wiring, BGL: wiring, CAL: wiring, RBL: wiring, WBL: wiring, SOL: wiring, WL: wiring, BL: wiring, FCA: wiring, HMD: electronic device, EXDV: device, EXDV1: device, EXDV2: device, EXDV3: device, RFS: RF signal, CLD: cloud computer Computing, HP: headphone part, FG: finger, HND: hand, DPC: display image, OPA: operation area, ICN: icon, 11: source driver circuit, 12: digital-to-analog conversion circuit, 13: gate driver circuit, 14: level shifter, 21: memory device, 22: GPU, 22a: circuit, 22b: circuit, 23: EL correction circuit, 24: timing controller, 25: CPU, 26: sensor controller, 27: power supply circuit, 31: memory control circuit, 41: high-frequency circuit, 41a: high-frequency circuit, 41b: high-frequency circuit, 100: display device, 100A: display device, 101: substrate, 116: insulator, 117: insulator, 118: insulator, 126: conductor, 127: conductor, 128: conductor, 170: transistor, 171: element isolation layer, 172a: low resistance region, 172b: low resistance region, 173: semiconductor region, 174: insulator, 175: conductor, 180: transistor, 200: display system, 200A: display system, 200B: display system, 200C: display system, 200D: display system, 211: conductor, 212: conductor, 221: insulator, 222: insulator, 223: insulator, 224: insulator, 231: semiconductor,251: insulator, 260R: light-emitting device, 260G: light-emitting device, 260B: light-emitting device, 260W: light-emitting device, 261: pixel electrode, 262R: EL layer, 262G: EL layer, 262B: EL layer, 262W: EL layer, 262a: EL layer, 262b: EL layer, 263: common electrode, 264R: colored layer, 264G: colored layer, 264B: colored layer, 271: protective layer, 272: insulator, 500: transistor, 503: conductor, 503a: conductor, 503b: conductor, 512: insulator, 514: insulator, 516: insulator, 522: insulator, 524: insulator, 5 30: oxide, 530a: oxide, 530b: oxide, 530ba: region, 530bb: region, 530bc: region, 540: conductor, 540a: conductor, 540b: conductor, 541: insulator, 541a: insulator, 541b: insulator, 542: conductor, 542a: conductor, 542b: conductor, 544: insulator, 550: insulator, 550a: insulator, 550b: insulator, 552: insulator, 554: insulator, 560: conductor, 560a: conductor, 560b: conductor, 571: insulator, 571a: insulator, 571b: insulator, 574: insulator, 576: insulator, 58 0: insulator, 581: insulator, 4411: light-emitting layer, 4412: light-emitting layer, 4413: light-emitting layer, 4420: layer, 4430: layer, 5200: portable game console, 5201: housing, 5202: display unit, 5203: button, 5900: information terminal, 5901: housing, 5902: display unit, 5903: operation button, 5904: crown, 5905: band, 6000: display module, 6001: upper cover, 6002: lower cover, 6005: FPC, 6006: display device, 6009: frame, 6010: printed circuit board, 6011: battery, 6015: light-emitting unit, 6017a : Light guide section, 6017b: Light guide section, 6018: Light, 6500: Electronic device, 6501: Housing, 6502: Display section, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective member, 6511: Display panel, 6512: Optical member, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 8000: Camera, 8001: Housing, 8002: Display section, 8003: Operation button, 8004: Shutter button, 8006: Lens,8100: viewfinder, 8101: housing, 8102: display unit, 8103: button, 8200: head mounted display, 8201: attachment unit, 8202: lens, 8203: main body, 8204: display unit, 8205: cable, 8206: battery, 8300: head mounted display, 8301: housing, 8302: display unit, 8303: operation buttons, 8304: fixture, 8305: lens, 8306: dial, 8307: dial, 8308: drive unit, 8310: user, 8311: user,

Claims

[Claim 1] A display device having a first layer, a second layer, and a display unit, the display unit is located in an area overlapping the first layer, the second layer is located in a region overlapping the first layer, the first layer has a semiconductor substrate made of silicon; the first layer includes a plurality of first transistors and a plurality of second transistors, each of which includes the silicon in a channel formation region; the second layer has a plurality of third transistors each including a metal oxide in a channel formation region; the first layer has a first circuit and a second circuit; the first circuit includes a source driver circuit and a gate driver circuit, each of which includes the first transistor; the second circuit includes a memory device, a GPU, an EL correction circuit, and a timing controller, each of which includes the second transistor; the third transistor functions as a transistor included in the memory device included in the first layer, the display unit has pixels, The pixel has a light-emitting device including an organic electroluminescent device, the pixels are electrically connected to the source driver circuit and the gate driver circuit; the storage device has a function of storing image data, the GPU has a function of decoding the image data read from the storage device, the source driver circuit has a function of transmitting the decoded image data to the pixels; the EL correction circuit has a function of correcting the luminance of light emitted by the light-emitting device; the timing controller has a function of increasing or decreasing a frame rate at which an image is displayed on the display unit; Display system.

Images