Display substrate and display device

Abstract

To provide a display substrate and a display device.SOLUTION: A display substrate has a good effect to solve a failure problem in a pixel circuit. The display substrate includes a base substrate, and a subpixel on the base substrate. The subpixel includes a pixel circuit, and the pixel circuit includes a data writing sub-circuit, a recording sub-circuit, and a driving sub-circuit. The recording sub-circuit includes a storage capacitor. A second capacitor electrode of the recording sub-circuit includes a first projection part and a second projection part that project along a first direction. This installation is useful in terms of increasing the capacitance value of the storage capacitor and improving the charging speed.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] This application is a divisional application of an invention patent application with application number 2025-024797, titled "Display substrate and display device."

[0002] The embodiments of the present disclosure relate to a display substrate and a display device. [Background technology]

[0003] Micro OLED displays are a combination of organic light-emitting diode (OLED) technology and CMOS technology, and are related to the mutual integration of the optoelectronics and microelectronics industries. This is promoting the development of next-generation micro display technology, as well as promoting the research and development of organic electronics on silicon and even molecular electronics on silicon.

[0004] Micro OLED displays have excellent display characteristics such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption, and are expected to be a promising display. Summary of the Invention [Means for solving the problem]

[0005] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate; and a plurality of sub-pixels on the base substrate, each sub-pixel comprising a pixel circuit, the pixel circuit comprising a data writing sub-circuit, a recording sub-circuit, and a driving sub-circuit, the data writing sub-circuit electrically connected to a first terminal of the recording sub-circuit and configured to transmit a data signal to the first terminal of the recording sub-circuit in response to a control signal, the driving sub-circuit comprising a control electrode, a first electrode, and a second electrode, the control electrode of the driving sub-circuit electrically connected to the first terminal of the recording sub-circuit, the first electrode of the driving sub-circuit configured to receive a first power supply voltage, the driving sub-circuit configured to drive a light-emitting element to emit light in response to a voltage of the first terminal of the recording sub-circuit, the recording sub-circuit comprising a storage capacitor comprising a first capacitor electrode and a second capacitor electrode, the plurality of sub-pixels comprising a first sub-pixel, the second capacitor electrode of the first sub-pixel comprising a first protrusion and a second protrusion, the first protrusion and the second protrusion protruding along a first direction.

[0006] In some examples, the plurality of sub-pixels further includes a second sub-pixel, a second capacitor electrode of the second sub-pixel includes a third protrusion, and the third protrusion extends along the first direction.

[0007] In some examples, the second capacitor electrode includes a first electrode portion and a second electrode portion spaced apart from each other in the first direction, and the first protrusion and the second protrusion are located on the first electrode portion of the second capacitor electrode.

[0008] In some examples, the plurality of subpixels further includes a second subpixel adjacent to the first subpixel in the first direction, and the first electrode portions of the second capacitor electrodes of the first subpixel and the second subpixel are integrally connected to each other.

[0009] In some examples, the pixel circuit further includes a resistor, a first terminal of the resistor electrically connected to the second electrode of the driving sub-circuit, and a second terminal of the resistor electrically connected to the light-emitting element, the resistor being insulated from the same layer as the control electrode of the driving sub-circuit, and the resistivity of the resistor being higher than the resistivity of the control electrode of the driving sub-circuit, and the materials of the resistor and the control electrode of the driving sub-circuit are both polycrystalline silicon materials.

[0010] In some examples, the first sub-pixel further includes a first connection electrode electrically connecting a first terminal of the resistor and a second electrode of the sub-circuit, the first connection electrode and the second capacitor electrode being spaced apart on the same layer, and the first electrode portion and the second electrode portion of the second capacitor electrode being located on either side of the first connection electrode, respectively.

[0011] In some examples, the storage capacitor further includes a third capacitor electrode, which is located on a side of the first capacitor electrode away from the second capacitor electrode in a direction perpendicular to the base substrate and is arranged to be electrically connected to the second capacitor electrode.

[0012] In some examples, the third capacitor electrode includes a first electrode protrusion that protrudes in the first direction and a second electrode protrusion that protrudes in a second direction that intersects with the first direction.

[0013] In some examples, a third capacitor electrode of the storage capacitor is in the first region of the base substrate and overlaps with the first capacitor electrode in a direction perpendicular to the base substrate.

[0014] In some examples, the third capacitor electrode includes an electrode region and a connection hole region, the electrode region and the first capacitor electrode overlap in a direction perpendicular to the base substrate, the second capacitor electrode is electrically connected to the third capacitor electrode through the connection hole region, and the doping concentration of the connection hole region is higher than the doping concentration of the electrode region.

[0015] In some examples, the first capacitor electrode includes a fourth protrusion and a fifth protrusion extending along a second direction, the fourth protrusion being a control electrode of the drive subcircuit, and the first direction intersects with the second direction.

[0016] In some examples, the pixel further includes a first power line extending along the first direction, the first power line configured to supply the first power voltage to the first subpixel, and the first power line and the second protrusion of the second capacitor electrode at least partially overlap in a direction perpendicular to the base substrate.

[0017] In some examples, the pixel further includes a second power supply line extending along the first direction, the second power supply line configured to supply a second power supply voltage different from the first power supply voltage to the first subpixel, and the second power supply line and the first protrusion of the second capacitor electrode at least partially overlap in a direction perpendicular to the base substrate.

[0018] In some examples, the data write sub-circuit includes a first data write transistor, the drive sub-circuit includes a drive transistor, the first data write transistor is a P-type metal-oxide semiconductor field effect transistor, and the drive transistor is an N-type metal-oxide semiconductor field effect transistor, and in a direction parallel to the plate surface of the base substrate, the P-type first data write transistor and the N-type drive transistor are located on both sides of the storage capacitor.

[0019] In some examples, the first capacitor electrode and the second capacitor electrode are respectively the first terminal and the second terminal of the recording sub-circuit, and the first sub-pixel further includes a second connection electrode, which is insulated from and installed in the same layer as the second capacitor electrode and electrically connects the first capacitor electrode to the data writing sub-circuit.

[0020] In some examples, the second connection electrode includes a first portion extending along the first direction and a second portion extending along the second direction, the first portion and the second portion being an integral structure, the first direction and the second direction being perpendicular to each other, the first portion being electrically connected to the data writing sub-circuit, and the second portion being electrically connected to the first capacitor electrode.

[0021] In some examples, the data writing sub-circuit, the second connecting electrode, and the driving sub-circuit are arranged in order along a second direction, and the first direction and the second direction are orthogonal to each other.

[0022] At least one embodiment of the present disclosure further provides a display device, which includes a display substrate according to any one of the above embodiments and the light-emitting element on the display substrate.

[0023] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below, and it is obvious that the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure. [Brief explanation of the drawings]

[0024] [Figure 1A] FIG. 1A is a schematic diagram 1 of a display substrate according to at least one embodiment of the present disclosure. [Figure 1B] FIG. 1B is a pixel circuit diagram 1 according to at least one embodiment of the present disclosure. [Figure 1C] FIG. 1C is a structural schematic diagram of a pixel circuit. [Figure 2A]FIG. 2A is a pixel circuit diagram 2 according to at least one embodiment of the present disclosure. [Figure 2B] FIG. 2B is a pixel circuit diagram 3 according to at least one embodiment of the present disclosure. [Figure 2C] FIG. 2C is a signal timing diagram of a pixel circuit in accordance with at least one embodiment of the present disclosure. [Figure 3A] FIG. 3A is a schematic diagram 2 of a display substrate according to at least one embodiment of the present disclosure. [Figure 3B] FIG. 3B is a schematic diagram of the display substrate taken along the cross-sectional line II' shown in FIG. 3A. [Figure 4A] FIG. 4A is a schematic diagram 3 of a display substrate according to at least one embodiment of the present disclosure. [Figure 4B] FIG. 4B is an enlarged schematic diagram of one sub-pixel of a display substrate according to at least one embodiment of the present disclosure. [Figure 5A] FIG. 5A shows a diagram of the fabrication steps of the display substrate shown in FIG. 4A. [Figure 5B] FIG. 5B shows a diagram of the fabrication steps of the display substrate shown in FIG. 4A. [Figure 5C] FIG. 5C shows a diagram of the fabrication steps of the display substrate shown in FIG. 4A. [Figure 5D] FIG. 5D shows a diagram of the fabrication steps of the display substrate shown in FIG. 4A. [Figure 5E] FIG. 5E shows a diagram of the fabrication steps of the display substrate shown in FIG. 4A. [Figure 6A] FIG. 6A is a schematic diagram of a first conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 6B] FIG. 6B is a schematic diagram of a first conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 6C] FIG. 6C shows a cross-sectional view taken along the cross-sectional line IV-IV' in FIG. 6B. [Figure 7A] FIG. 7A is a schematic diagram of a second conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 7B] FIG. 7B is a schematic diagram of a second conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 8A] FIG. 8A is a schematic diagram of a third conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 8B] FIG. 8A is a schematic diagram of a third conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 9A] FIG. 9A is a schematic diagram of a fourth conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 9B] FIG. 9B is a schematic diagram of a fourth conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 10A] FIG. 10A is a schematic diagram 4 of a display substrate according to at least one embodiment of the present disclosure. [Figure 10B] FIG. 10B is an enlarged schematic view of the area of ​​the display substrate shown by the dashed line in FIG. 10A. [Figure 10C] FIG. 10C is a cross-sectional view taken along the cross-sectional line VV' in FIG. 10B. [Figure 11A] FIG. 11A is a schematic diagram 5 of a display substrate according to at least one embodiment of the present disclosure. [Figure 11B] FIG. 11B is a schematic diagram 6 of a display substrate according to at least one embodiment of the present disclosure. [Figure 11C] FIG. 11C is a cross-sectional view of the display substrate shown in FIG. 11B taken along the cross-sectional line II-II'. [Figure 11D] FIG. 11D is a cross-sectional view of the display substrate shown in FIG. 11B taken along the cross-sectional line III-III'. [Figure 12] FIG. 12 is a schematic diagram of a display device in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0025] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Of course, the described embodiments are only some of the embodiments of the present disclosure, and are not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments that a person skilled in the art can obtain without inventive efforts fall within the scope of protection of the present disclosure.

[0026] Unless otherwise defined, technical or scientific terms used in this disclosure shall have their ordinary meaning as understood by those skilled in the art. As used in this disclosure, the terms "first," "second," and similar words do not denote order, number, or importance, but are used only to distinguish between different components. Similarly, similar words such as "one," "an," or "the" do not limit the quantity but mean that there is at least one. Similar words such as "comprise" or "comprises" mean that the element or component shown before the word includes the element or component listed after the word and its equivalents, but does not exclude other elements or components. Similar words such as "connect" or "coupled" are not limited to physical or mechanical connections, but may include direct or indirect electrical connections. Terms such as "top," "bottom," "left," and "right" are used only to indicate relative positions, and if the absolute position of the objects being described changes, the relative positions may change accordingly.

[0027] In the field of OLED (organic light-emitting diode) displays, the rapid development of high-resolution products places increasing demands on the structural design of display substrates, such as the arrangement of pixels and signal lines. For example, compared with a 4K-resolution OLED display, a large-sized 8K-resolution OLED display requires twice the number of subpixel units, thereby doubling the pixel density. On the one hand, the line width of the signal lines is correspondingly smaller, resulting in higher resistance of the signal lines themselves. On the other hand, there is more overlap between signal lines, resulting in higher parasitic capacitance of the signal lines. These factors result in higher resistive-capacitive loads on the signal lines. Consequently, phenomena such as signal delay (RC delay), voltage drop (IR drop), and voltage rise (IR rise) due to the resistive-capacitive load become more severe. These phenomena seriously impair the display quality of display products.

[0028] Micro OLED displays generally have a size smaller than 100 micrometers, such as smaller than 50 micrometers, and involve the combination of organic light-emitting diode (OLED) technology with CMOS technology, where the OLED array is fabricated on a silicon-based substrate that also contains CMOS circuitry.

[0029] Micro OLED is widely applied in the fields of AR and VR. With the continuous development of technology, higher resolution is required, which increases the requirements for the structural design of the display substrate, such as the arrangement of pixels and signal lines.

[0030] A display substrate according to at least one embodiment of the present disclosure can achieve a sub-pixel area of ​​5.45 μm×13.6 μm through optimized layout and wiring design processes, achieving high pixel resolution (PPI) and optimized pixel circuit array layout, while also providing a relatively good display effect.

[0031] FIG. 1A is a block diagram of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 1A, the display substrate 10 includes a plurality of sub-pixels 100 arranged in an array, a plurality of scan lines 11, and a plurality of data lines 12. Each sub-pixel 100 includes a light-emitting element and a pixel circuit for driving the light-emitting element. The scan lines 11 and the data lines 12 intersect with each other to define a plurality of pixel regions arranged in an array in the display area, with the pixel circuit of one sub-pixel 100 being installed in each pixel region. The pixel circuits may be, for example, conventional pixel circuits, such as 2T1C (i.e., two transistors and one capacitor) pixel circuits, or nTmC (n and m are positive integers) pixel circuits, such as 4T2C, 5T1C, and 7T1C. In different embodiments, the pixel circuits may further include a compensation sub-circuit, including an internal compensation sub-circuit or an external compensation sub-circuit, which may include a transistor, a capacitor, etc. For example, the pixel circuits may further include a reset circuit, a light-emitting control sub-circuit, a detection circuit, etc., as needed. For example, the display substrate may further include a gate driving sub-circuit 13 and a data driving sub-circuit 14 located in the non-display area. The gate driving sub-circuit 13 is connected to the pixel circuits via scan lines 11 to provide various scanning signals, and the data driving sub-circuit 14 is connected to the pixel circuits via data lines 12 to provide data signals. The positional relationship between the gate driving sub-circuit 13 and the data driving sub-circuit 14 on the display substrate, and the positional relationship between the scan lines 11 and the data lines 12 on the display substrate shown in Figure 1A are merely examples, and their actual positions can be designed as needed.

[0032] For example, the display substrate 10 may further include a control circuit (not shown). For example, the control circuit may be configured to control the data driving sub-circuit 14 to apply the data signals and to control the gate driving sub-circuit to apply the scan signals. An example of the control circuit is a timing control circuit (T-con). The control circuit may take various forms, for example, including a processor and a memory, the memory including executable code, and the processor executing the executable code to perform the detection method.

[0033] For example, a processor may be a central processing unit (CPU) or other form of processing device having data processing capabilities and / or instruction execution functionality, and may include, for example, a microprocessor, a programmable logic controller (PLC), etc.

[0034] For example, a storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. The computer-readable storage media may store one or more computer program instructions, enabling a processor to perform the functions desired by the program instructions. The computer-readable storage media may also store various application programs and various data.

[0035] The pixel circuit may include a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, and a recording sub-circuit as needed, and may further include a light emission control sub-circuit, a reset circuit, etc. as needed.

[0036] 1B shows a schematic diagram of a pixel circuit, which includes a data writing sub-circuit 111, a driving sub-circuit 112 and a recording sub-circuit 113.

[0037] The data writing sub-circuit 111 is electrically connected to a first terminal of the recording sub-circuit 113 and is configured to transmit a data signal Vd to the first terminal of the recording sub-circuit 113 in response to a control signal (first control signal SEL). A second terminal of the recording sub-circuit 113 is configured to receive, for example, a second power supply voltage VSS.

[0038] The driving sub-circuit 112 includes a control electrode (control terminal) 150, a first electrode (first terminal) 151, and a second electrode (second terminal) 152, where the control electrode 150 of the driving sub-circuit is electrically connected to the first terminal of the recording sub-circuit, the first electrode 151 of the driving sub-circuit 112 is configured to receive a first power supply voltage VDD, and the second electrode 152 of the driving sub-circuit 112 is electrically connected to a first node S and to a first electrode 121 of the light-emitting element 120. The driving sub-circuit 112 is configured to drive the light-emitting element 120 to emit light in response to the voltage of the first terminal of the recording sub-circuit. The second electrode 122 of the light-emitting element 120 is configured to receive, for example, a first common voltage Vcom1.

[0039] In at least some embodiments of the present disclosure, as shown in FIG. 1B , the pixel circuit further includes a bias sub-circuit 114. The bias sub-circuit 114 includes a control terminal, a first terminal, and a second terminal. The control terminal of the bias sub-circuit 114 is configured to receive a bias signal. The first terminal of the bias sub-circuit 114 is configured to receive, for example, a second power supply voltage VSS, and the second terminal of the bias sub-circuit 114 is electrically connected to the first node S. For example, the bias signal is a second common voltage Vcom2. For example, the bias signal Vcom2 is a constant voltage signal, for example, 0.8V-1V. The bias sub-circuit 114 is in a normally open state under the action of the bias signal and is configured to provide a constant current, thereby achieving a linear relationship between the voltage applied to the light-emitting element 120 and the data signal, contributing to precise control of the gray scale and thereby improving the display effect. This will be further described below with reference to specific circuits.

[0040] For example, when the data signal (voltage) Vd changes from high to low, the grayscale voltage of the first electrode 121 of the write light-emitting element 120 needs to change quickly, and the bias sub-circuit 114 can also allow the first electrode 121 of the light-emitting element 120 to release charge quickly, thereby achieving good dynamic contrast.

[0041] The transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. In the embodiments of the present disclosure, metal-oxide semiconductor field effect transistors are used as examples. The source and drain of the transistors used herein may be symmetrical in structure, so the source and drain do not need to be structurally distinct. In the embodiments of the present disclosure, to distinguish between the two poles of a transistor other than the gate, one pole is referred to as the first pole and the other pole as the second pole. Furthermore, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When a transistor is a P-type transistor, its on-voltage is a low-level voltage (e.g., 0 V, −5 V, −10 V, or other suitable voltage) and its off-voltage is a high-level voltage (e.g., 5 V, 10 V, or other suitable voltage). When a transistor is an N-type transistor, its on-voltage is a high-level voltage (e.g., 5 V, 10 V, or other suitable voltage) and its off-voltage is a low-level voltage (e.g., 0 V, −5 V, −10 V, or other suitable voltage).

[0042] The display substrate according to the embodiments of the present disclosure may be a rigid substrate such as a glass substrate or a silicon substrate, or may be formed of a flexible material having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetate cellulose (TAC), cycloolefin polymer (COP), cycloolefin copolymer (COC), etc. Although the embodiments of the present disclosure are all described using a silicon substrate as an example, i.e., the pixel structure is fabricated on a silicon substrate, the embodiments of the present disclosure are not limited thereto.

[0043] For example, the pixel circuit includes a complementary metal-oxide semiconductor circuit (CMOS circuit), i.e., the pixel circuit is fabricated on a single-crystal silicon-based substrate. Due to the mature CMOS integrated circuit technology, the silicon-based process can achieve high precision (for example, PPI can reach 6500 or even 10,000 or more).

[0044] For example, due to process variations in the display substrate, a short circuit may occur between the first electrode 121 and the second electrode 122 of the light-emitting element 120 in the sub-pixel, causing the voltage of the first electrode 121 of the light-emitting element 120 to be too high (e.g., the first common voltage Vcom1 is at a high potential) or too low (e.g., the first common voltage Vcom1 is at a low potential), which turns on the PN junction formed between the second electrode of the driving sub-circuit and the base substrate, resulting in a failure of the CMOS circuit and causing defects such as dark lines on the display substrate.

[0045] In some examples, for example, the data write sub-circuit includes a first data write transistor P1, and the driving sub-circuit includes a driving transistor N2. For example, the first data write transistor is a P-type metal-oxide semiconductor field effect transistor (PMOS), and the driving transistor N2 is an N-type metal-oxide semiconductor field effect transistor (NMOS), and the gate, first pole, and second pole of the driving transistor N2 are the control electrode 150, the first electrode 151, and the second electrode 152 of the driving sub-circuit 112, respectively. In this case, for example, if the first common voltage Vcom1 provided to the second electrode 122 of the light-emitting element 120 is at a low potential and the first electrode 121 and the second electrode 122 of the light-emitting element 120 are short-circuited, the potential of the second pole of the driving transistor directly connected to the first electrode 121 will be too low.

[0046] 1C shows a schematic diagram of a transistor failure in the pixel circuit, in which the N-type active region (e.g., second pole) of the driving transistor N2, the P-type silicon-based base, the N-type well region in which the first data write transistor P1 is located, and the P-type active region (e.g., first pole) of the first data write transistor P1 form two interconnected parasitic transistors Q1 and Q2, forming an NPNP structure. Because the potential of the second pole of the driving transistor N2 (i.e., the first node S) is too low, a forward bias is caused at the PN junction (emitter junction) between the second pole (N-type heavily doped region) of the driving transistor N2 and the P-type base, causing Q1 to conduct and providing enough current to make the parasitic transistor Q2 conduct, which in turn feeds back the current to the parasitic transistor Q1, forming a vicious cycle. Ultimately, most of the current is not controlled by the gate voltage of the transistor, but passes directly from VDD through the parasitic transistor to VSS, resulting in failure of the CMOS pixel circuit. When the circuit fails, the parasitic transistor Q2 will constantly draw current from the emitter, i.e., the data line, causing failure of a column of sub-pixels connected to the data line, resulting in defects such as dark lines appearing on the display substrate, and greatly impairing the display effect.

[0047] In at least some embodiments of the present disclosure, at least one sub-pixel further includes a resistor connected between the second electrode 152 of the driving sub-circuit 112 and the first electrode 121 of the light-emitting element 120 to increase or decrease the potential of the first node S, thereby reducing or avoiding circuit failure, improving circuit reliability, and improving the display effect.

[0048] 2A is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. As shown in FIG. 2A, the pixel circuit further includes a resistor 130, a first terminal 131 of which is electrically connected to a second electrode 152 of the driving sub-circuit 112, and a second terminal 132 of which is electrically connected to a first electrode 121 of the light-emitting element 120. That is, the second electrode 152 of the driving sub-circuit 112 is electrically connected to the first electrode 121 of the light-emitting element 120 by the resistor 130.

[0049] For example, the resistor 130 may be a constant resistor or a variable resistor, or may have an equivalent resistor formed from other devices (eg, transistors).

[0050] For example, the resistor 130 is insulated from the control electrode 150 of the drive subcircuit 112 in the same layer, and the resistivity of the resistor is higher than the resistivity of the control electrode of the drive subcircuit. That is, the conductivity of the control electrode of the drive subcircuit is higher than the conductivity of the resistor. For example, the resistivity of the resistor is 10 times or more the resistivity of the control electrode.

[0051] In the present disclosure, "formed in the same layer" refers to two (or more) structures formed by the same deposition process and patterned by the same patterning process, and the materials may be the same or different. For example, the precursor materials forming multiple structures formed in the same layer are the same, and the final formed materials may be the same or different. In the present disclosure, "integral structure" refers to two (or more) structures formed by the same deposition process and patterned by the same patterning process, and are interconnected, and the materials may be the same or different.

[0052] Such placement allows the control electrodes and resistors of the drive sub-circuits to be formed in the same patterning process, thereby saving processing.

[0053] For example, the material of the resistor and the control electrode of the drive sub-circuit are both polycrystalline silicon material, and the doping concentration of the resistor is lower than the doping concentration of the control electrode, so the resistor has a higher resistivity than the control electrode. For example, the resistor may be intrinsic polycrystalline silicon or lightly doped polycrystalline silicon, and the control electrode is heavily doped polycrystalline silicon.

[0054] In some other examples, the materials of the control electrode and the resistor may be different. For example, the materials of the control electrode and the resistor may each include a metal and a metal oxide corresponding to the metal. For example, the metal may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials combining these.

[0055] In at least one embodiment of the present disclosure, the data writing sub-circuit 111 may include a transmission gate circuit configured by connecting two complementary transistors in parallel, and the control signal includes two control signals of opposite phases. The data writing sub-circuit 111 uses a transmission gate structure circuit to help transmit the data signal to the first terminal of the recording sub-circuit 113 without loss.

[0056] For example, the data writing subcircuit includes a first control electrode, a second control electrode, a first terminal, and a second terminal, the first control electrode and the second control electrode of the data writing subcircuit are configured to receive a first control signal and a second control signal, respectively, the first terminal of the data writing subcircuit is configured to receive a data signal, and the second terminal of the data writing subcircuit is electrically connected to the first terminal of the recording subcircuit and is configured to transmit the data signal to the first terminal of the recording subcircuit in response to the first control signal and the second control signal.

[0057] However, in the description of the embodiments of the present disclosure, the first node S does not necessarily represent an actually existing component, but represents a junction that connects related circuits in a circuit diagram.

[0058] In the description of the embodiments of the present disclosure, the symbol Vd can refer to both a data signal terminal and a data signal level, the symbol SEL can refer to both a control signal and a control signal terminal, the symbols Vcom1 and Vcom2 can refer to a first common voltage and a second common voltage, or can refer to a first common voltage terminal and a second common voltage terminal, the symbol VDD can refer to both a first voltage terminal and a first power supply voltage, and the symbol VSS can refer to both a second voltage terminal and a second power supply voltage. The following embodiments are similar to this, and their descriptions will be omitted.

[0059] 2B shows a circuit diagram of a specific implementation of the pixel circuit shown in FIG. 2A. As shown in FIG. 2B, the data write sub-circuit 111 includes a first data write transistor P1 and a second data write transistor N1 connected in parallel. The first data write transistor P1 and the second data write transistor N1 are P-type metal-oxide semiconductor field effect transistors (PMOS) and N-type metal-oxide semiconductor field effect transistors (NMOS), respectively. The control signals include a first control signal SEL and a second control signal SEL_B that are opposite in phase to each other. The gate of the first data write transistor P1 serves as a first control electrode of the data write sub-circuit and is configured to receive the first control signal SEL, and the gate of the second data write transistor N1 serves as a second control electrode of the data write sub-circuit and is configured to receive the second control signal SEL_B. The first pole of the second data write transistor N1 and the first pole of the first data write transistor P1 are electrically connected and configured to receive a data signal Vd as a first terminal of the data write sub-circuit, and the second pole of the second data write transistor N1 and the second pole of the first data write transistor P1 are electrically connected and configured to receive a data signal Vd as a second terminal of the data write sub-circuit, and are electrically connected to the control electrode 150 of the driving sub-circuit 112.

[0060] For example, the first data write transistor P1 and the second data write transistor N1 have the same size and the same channel aspect ratio.

[0061] The data writing sub-circuit 111 utilizes the complementary electrical characteristics of transistors to have low on-state resistance whether the transmission level is high or low, thereby having the advantage of transmitting electrical signals perfectly, and transmitting the data signal Vd to the first terminal of the recording sub-circuit 113 without loss.

[0062] 2B, the driving sub-circuit 112 includes a driving transistor N2, for example, the driving transistor N2 is an NMOS, and the gate, first electrode, and second electrode of the driving transistor N2 are the control electrode, first electrode, and second electrode of the driving sub-circuit 112, respectively.

[0063] For example, the recording sub-circuit 113 includes a storage capacitor Cst, which includes a first capacitor electrode 141 (an example of a first capacitor electrode in the present disclosure) and a second capacitor electrode 142 (an example of a third capacitor electrode in the present disclosure), and the first capacitor electrode 141 and the second capacitor electrode 142 are respectively a first terminal and a second terminal of the recording sub-circuit 113.

[0064] For example, the resistor 130 includes a resistor R. For example, a PN junction is formed between the second electrode 152 of the driving sub-circuit 112 and the base substrate, and the resistance value of the resistor 130 is set so that the PN junction is turned off when the driving transistor N2 operates in a saturation region, that is, when the pixel circuit operates to drive the light emitting element 120 to emit light. In this case, even if a short circuit occurs between the two electrodes of the light emitting element 120, a voltage drop exists across the resistor 130, so that the potential of the second electrode 152 can be protected, thereby avoiding circuit failure.

[0065] For example, the resistance of resistor 130 is

number

number

[0066] For example, the light-emitting element 120 is specifically implemented as an organic light-emitting diode (OLED). For example, the light-emitting element 120 may be an OLED with a top-emitting structure, and may emit red light, green light, blue light, or white light. For example, the light-emitting element 120 is a micro OLED. The embodiments of the present disclosure do not limit the specific structure of the light-emitting element. For example, the first electrode 121 of the light-emitting element 120 is the anode of the OLED, and the second electrode 122 is the cathode of the OLED, i.e., the pixel circuit has a common cathode structure. However, the embodiments of the present disclosure are not limited thereto, and depending on the circuit structure, the pixel circuit may have a common anode structure.

[0067] For example, the bias sub-circuit 114 includes a bias transistor N3, and the gate, first pole, and second pole of the bias transistor N3 are the control terminal, first terminal, and second terminal of the bias sub-circuit 114, respectively.

[0068] Figure 2C shows a signal timing diagram of the pixel circuit shown in Figure 2B. The operation principle of the pixel circuit shown in Figure 2C will be described below with reference to the signal timing diagram shown in Figure 2B. For example, the second data write transistor, the drive transistor, and the bias transistor are all N-type transistors, and the first data write transistor is a P-type transistor, but the embodiments of the present disclosure are not limited thereto.

[0069] FIG. 2C shows waveform diagrams of each signal in two consecutive display periods T1 and T2, for example, the data signal Vd is a high gray-scale voltage in the display period T1 and a low gray-scale voltage in the display period T2.

[0070] 2C, the process of displaying an image for each frame includes a data writing step 1 and an emission step 2. The operation process of the pixel circuit includes a data writing step 1 in which the first control signal SEL and the second control signal SEL_B are both on signals, the first data writing transistor P1 and the second data writing transistor N1 are conductive, and the data signal Vd is transmitted to the gate of the driving transistor N2 via the first data writing transistor P1 and the second data writing transistor N1, and an emission step 2 in which the first control signal SEL and the second control signal SEL_B are both off signals, and the voltage across the storage capacitor Cst does not change due to the bootstrap phenomenon of the storage capacitor Cst, the driving transistor N2 operates in a saturated state, the current does not change, and the light emitting element 120 is driven to emit light. When the pixel circuit switches from display period T1 to display period T2, the data signal Vd changes from a high gray-scale voltage to a low gray-scale voltage, and the bias transistor N3 generates a stable drain current under the control of the second common voltage Vcom2, which can quickly discharge the charge stored in the OLED anode when the OLED display gray scale needs to change quickly. For example, since the discharge process occurs in data writing phase 1 of display period T2, the voltage of the OLED anode drops quickly in light-emitting phase 2 of display period T2, thereby achieving high dynamic contrast and improving the display effect.

[0071] As shown in FIG. 2B, for example, in the light emitting stage, when the light emitting element OLED writes gray scale data, the light emitting current is in the order of nanoamperes (e.g., several nanoamperes), but the bias transistor N3 is controlled by the bias signal, i.e., the second common voltage Vcom2, to operate in the saturation region, and the generated current is in the order of microamperes (e.g., 1 microampere). Therefore, most of the current flowing through the driving transistor N2 flows into the bias transistor N3, and both can be treated in the same way, that is,

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number

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[0072] For example, the bias transistor N3 is controlled by the bias signal Vcom2 to operate in the saturation region, and the voltage difference between the gate and source of the bias transistor N3 is

number

[0073] For example, when the first node S is directly electrically connected to the light emitting element 120, the voltage V0 is directly applied to the first electrode 121 of the light emitting element 120, such as the anode voltage of an OLED. When the first node S is electrically connected to the light emitting element 120 via a resistor 130, the current flowing through the light emitting element 120 is very small, so the voltage of the first node S may be approximately equal to the voltage of the first electrode 121 of the light emitting element 120. That is, the voltage of the first electrode 121 of the light emitting element 120 and the data signal (data voltage) Vd have a linear relationship, which can realize high-precision control of the gray scale and improve the display effect.

[0074] For example, the first control signal SEL and the second control signal SEL_B are differential complementary signals with the same amplitude and opposite phase, which contributes to improving the anti-interference performance of the circuit. For example, the first control signal SEL and the second control signal SEL_B can be output from the same gate driving circuit unit (e.g., GOA unit), thereby simplifying the circuit.

[0075] 1A, the display substrate 10 may further include a data driving circuit 13 and a scan driving circuit 14. The data driving circuit 13 is configured to transmit a data signal, such as the data signal Vd, as needed (e.g., an image signal input to the display device). The scan driving circuit 14 is configured to output various scan signals, including the first control signal SEL and the second control signal SEL_B, and is, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly fabricated on the display substrate.

[0076] For example, the display substrate may use a silicon substrate as the base substrate 101, and the pixel circuits, data driving circuit 13, and scan driving circuit 14 may all be integrated on the silicon substrate. In this case, since silicon-based circuits can achieve high precision, the data driving circuit 13 and scan driving circuit 14 do not necessarily need to be located in the non-display area, and may be formed, for example, in an area corresponding to the display area of ​​the display substrate.

[0077] For example, the display substrate 10 further includes a control circuit (not shown). For example, the control circuit is configured to control the data driving circuit 13 to apply the data signal Vd and to control the gate driving circuit 13 to apply various scanning signals. An example of the control circuit is a timing control circuit (T-con). The control circuit may take various forms, for example, including a processor and a memory, where the memory includes executable code, and the processor executes the executable code to perform the above detection method.

[0078] For example, the processor may be a central processing unit (CPU) or other form of processing device having data processing and / or instruction execution capabilities, and may include, for example, a microprocessor, a programmable logic controller (PLC), etc.

[0079] For example, the recording device may include one or more computer program products, which may include various forms of computer-readable recording media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be recorded on the computer-readable recording media, allowing the processor 121 to perform the functions desired by the program instructions. Various application programs and various data, such as electrical characteristic parameters obtained by the above-mentioned detection method, may also be recorded on the computer-readable recording media.

[0080] Hereinafter, a display substrate according to at least one embodiment of the present disclosure will be described exemplarily using the pixel circuit shown in FIG. 2B as an example, but the embodiments of the present disclosure are not limited thereto.

[0081] 3A is a schematic diagram of a display substrate 10 according to at least one embodiment of the present disclosure. For example, as shown in FIG. 3A, the display substrate 10 includes a base substrate 101, on which a plurality of subpixels 100 are located. The subpixels 100 are arranged as a subpixel array, with the row direction of the subpixel array being a first direction D1 and the column direction being a second direction D2, and the first direction D1 and the second direction D2 intersecting, for example, perpendicular to each other. FIG. 3A exemplarily illustrates two rows and six columns of subpixels, i.e., two pixel rows 20 and six pixel columns 30, with the regions of three pixel columns spaced apart from each other indicated by dashed-line frames.

[0082] For example, the base substrate 101 may be a rigid substrate, such as a glass substrate or a silicon substrate, or may be formed of a flexible material having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetate cellulose (TAC), cycloolefin polymer (COP), and cycloolefin copolymer (COC). Although the embodiments of the present disclosure will be described with reference to an example where the base substrate 101 is a silicon substrate, the embodiments of the present disclosure are not limited thereto.

[0083] For example, the base substrate 101 includes single crystal silicon or high-purity silicon. The pixel circuit is formed on the base substrate 10 by a CMOS semiconductor process, for example, by forming transistor active regions (including transistor channel regions, first electrodes, and second electrodes) in the base substrate 101 by a doping process, forming each insulating layer by a silicon oxidation process or a chemical vapor deposition process (CVD), and forming multiple conductive layers by a sputtering process to form a wiring structure, etc. The active region of each transistor is located inside the base substrate 101.

[0084] Figure 3B shows a cross-sectional view taken along line II' in Figure 3A. For clarity, Figure 3B omits wiring or electrode structures that have no direct connection relationship.

[0085] 3B, the display substrate 10 includes a base substrate 101, a first insulating layer 201, a polycrystalline silicon layer 102, a second insulating layer 202, a first conductive layer 301, a third insulating layer 203, a second conductive layer 302, a fourth insulating layer 204, a third conductive layer 303, a fifth insulating layer 205, and a fourth conductive layer 304, which are arranged on the base substrate 101 in this order. The structure of the display substrate 10 will be described below layer by layer, and will also be described with reference to FIG. 3B.

[0086] For clarity and convenience of explanation, Figure 4A shows the portion of the display substrate 10 located below the first conductive layer 301, i.e., the base substrate 101 and the first insulating layer 201 and polysilicon layer 102 thereon, including the transistors (P1, N1-N3), the storage capacitor Cst, and the resistor 130. Figure 4B is an enlarged schematic view of one sub-pixel 100 in Figure 4A, and for clarity, Figure 4A also shows the corresponding cross-sectional line I-I' in Figure 3A. Figures 5A-5E show the formation process of the substrate structure shown in Figure 4A.

[0087] As shown in FIG. 4B, for example, in a direction parallel to the substrate surface of the base substrate 101, the first data write transistor P1 and the driving transistor N2 are located on opposite sides of the storage capacitor Cst, for example, on opposite sides of the storage capacitor Cst in the second direction D2.

[0088] As shown in conjunction with FIG. 1C, this placement contributes to increasing the distance between the first data write transistor P1 and the drive transistor N2, thereby increasing the resistance of the parasitic circuit and further reducing the risk of circuit failure in the CMOS circuit.

[0089] For example, the material of the second capacitor electrode 142 of the storage capacitor 140 is a conductor or a semiconductor. For example, as shown in FIGS. 3B and 4B, the second capacitor electrode 142 of the storage capacitor 140 is a first region 401 of the base substrate 101. For example, the base substrate 101 is a P-type silicon-based substrate, and the material of the second capacitor electrode 142 is P-type single-crystal silicon. When a voltage is applied to the first capacitor electrode 141, the first region 401, which is a semiconductor located below the first capacitor electrode 141 in the base substrate 101, forms an inversion region and becomes a conductor, electrically connecting to the contact hole regions on both sides of the first region 401 (contact hole regions 145a and 145b shown in FIG. 4B). In this case, the first region 401 is not subjected to any additional processing, such as doping.

[0090] In another example, the first region 401 may be a conductive region, such as a heavily doped region, in the base substrate 101, so that the second capacitor electrode 142 can have a stable and high conductivity.

[0091] For example, the base substrate 101 further includes a second region 402, which is an N-type well region in the base substrate 101. As shown in Figure 4B, for example, the first data write transistor P1 and the resistor 130 are arranged in parallel in the second direction D2 in the second region 402. The resistor 130 made of polycrystalline silicon material is arranged in the N-type base, which helps reduce parasitic phenomena and improve circuit performance.

[0092] For example, in a direction parallel to the substrate surface of the base substrate 101, the resistor (R) 130 and the first data write transistor P1 are located on the same side of the second capacitor electrode 142. For example, in a direction parallel to the substrate surface of the base substrate 101, the drive transistor N2 and the bias transistor N3 are located on the same side of the second capacitor electrode 142.

[0093] 4B, the first data write transistor P1 and the second data write transistor P1 are arranged in parallel in the first direction D1 and are symmetrical about a symmetry axis along the second direction D2. For example, the gate 160 of the first data write transistor P1 and the gate 170 of the second data write transistor N1 are arranged in parallel in the first direction D1 and are symmetrical about a symmetry axis along the second direction D2.

[0094] For example, resistor 130 has a U-shaped structure, e.g., an asymmetric U-shaped structure, e.g., the lengths of the two branches of the U-shaped structure are not equal. For example, as shown in Figure 4B, the second terminal 132 of resistor 130 is closer to drive transistor N2.

[0095] The resistor 130 is configured in a U-shape to reduce the area occupied by the resistor, thereby increasing the space utilization rate of the layout and improving the resolution of the display substrate. For example, in the same space, the resistor with a U-shape structure can increase the length of the resistor, thereby achieving a desired resistance value.

[0096] The resistor 130 may also be designed as an asymmetric structure to rationally utilize the layout space. For example, as shown in FIG. 4B , a contact hole region 411a is disposed above the shorter branch of the U-shaped resistor, and the contact hole region 411a is parallel to the second terminal 132 of the resistor 130 in the first direction D1. For example, the contact hole region 411a is an N-type heavily doped region (N+). For example, the contact hole region 411a is used to bias the well region 401 in which the first data write transistor P1 is located, thereby avoiding threshold voltage changes due to parasitic phenomena such as base bias phenomenon and improving circuit stability. For example, as shown in FIG. 3B , applying a low voltage bias to the P-type base 101 and a high voltage bias to the N-type well region 402 reverse-biass the parasitic PN junction between the two, electrically isolating the devices and reducing parasitic phenomena between the devices, thereby improving circuit stability.

[0097] For example, the opening of the U-shaped structure faces the first capacitor electrode 141, and the first terminal 131 and the second terminal 132 of the resistor 130 are respectively located at two ends of the U-shaped structure. As shown in the figure, the first terminal 131 of the resistor 130 is provided with a contact hole region 133 for electrically connecting to the gate 150 of the driving transistor N2, and the second terminal 132 of the resistor 130 is provided with a contact hole region 134 for electrically connecting to the first electrode 121 of the light-emitting element 120.

[0098] For example, the material of the resistor 130 includes polycrystalline silicon material, the contact hole regions 133 and 134 are doped regions for reducing contact resistance, and the body region of the resistor 130 other than the contact hole regions is, for example, an intrinsic region or a lightly doped region, thereby obtaining a desired resistance value.

[0099] For example, the first capacitor electrode 141 of the storage capacitor 140 and the resistor 130 are insulated from each other in the same layer and both comprise polysilicon material, and the doping concentration of the first capacitor electrode 141 of the storage capacitor 140 is higher than the doping concentration of the body region of the resistor 130. For example, the body region of the resistor 130 is made of intrinsic polysilicon material.

[0100] For example, the gates 160, 170, 150, and 180 of each of the transistors P1, N1-N3 and the first capacitor electrode 141 of the storage capacitor 140 are located in the same layer and include polycrystalline silicon material. For example, as shown in FIG. 4B, the gate 150 and the first capacitor electrode 141 of the driving transistor N2 are connected to each other to form an integral structure.

[0101] FIG. 4B further shows the active regions P1a, N1a, N2a, and N3a of each transistor P1, N1-N3, respectively, and also shows the first pole 161 and second pole 162 of the first data write transistor P1, the first pole 171 and second pole 172 of the second data write transistor N1, the first pole 151 and second pole 152 of the drive transistor N2, and the first pole 181 and second pole 182 of the bias transistor N3.

[0102] 4B further shows a gate contact region 165, a first contact region 163, and a second pole contact region 164 of the first data write transistor P1, a gate contact region 175, a first contact region 173, and a second pole contact region 174 of the second data write transistor N1, a gate contact region 155, a first contact region 153, and a second pole contact region 154 of the drive transistor N2, and a gate contact region 185, a first contact region 183, and a second pole contact region 184 of the bias transistor N3. For example, each first pole contact region is a region for making electrical contact to a corresponding first pole, each second pole contact region is a region for making electrical contact to a corresponding second pole, and each gate contact region is a region for making electrical contact to a corresponding gate.

[0103] For example, the active region P1a of the first data write transistor P1 and the active region N1a of the second data write transistor N1 are arranged in parallel in the first direction D1 and are symmetrical with respect to a symmetry axis along the second direction D2.

[0104] As shown in FIG. 4B, the area of ​​the active area N2a of the driving transistor N2 is larger than the areas of the active areas of the other transistors, which can achieve a large aspect ratio, which contributes to improving the driving capability of the driving transistor N2 and thereby improving the display effect.

[0105] As shown in FIG. 4B, transistors with large active areas, such as the driving transistor N2 and the bias transistor N3, have enough space to provide at least two contact hole areas on their first and second poles, respectively, so that they can make sufficient contact with the structure to be connected and form a parallel connection structure, thereby reducing the contact resistance.

[0106] 4B further shows contact hole areas 144 in the first capacitor electrode 141 and contact hole areas 145a, 145b configured to be electrically connected to the second capacitor electrode 142. As shown in FIG. 4B, the first capacitor electrode 141 and the second capacitor electrode 142 each have at least two corresponding contact hole areas to reduce contact resistance.

[0107] 4A , the distribution of transistors (including, for example, the shape and size of each transistor), storage capacitors, and resistors in two subpixels 100 adjacent to each other in the first direction D1 is symmetrical about an axis of symmetry along the second direction D2, i.e., the corresponding structures in the two subpixels are symmetrical about an axis of symmetry along the second direction D2. The distribution of transistors in two subpixels 100 adjacent to each other in the second direction D2 is symmetrical about the axis of symmetry along the first direction D1.

[0108] This symmetrical arrangement can minimize process error uniformity, thereby improving the uniformity of the display substrate. Furthermore, this symmetrical arrangement allows several interconnected structures to be integrally formed on the same layer of the substrate, which allows for a more compact pixel arrangement than separate arrangements, improving space utilization and thereby improving the resolution of the display substrate.

[0109] 4A , the second regions 402 of two sub-pixels 100 adjacent to each other in the first direction D1 are integrally formed, and the second regions 402 of two sub-pixels 100 adjacent to each other in the second direction D2 are integrally formed, i.e., the first data write transistors N1 and resistors 130 of the four adjacent sub-pixels 100 are located in the same well region. Compared with individually providing independent well regions, this arrangement can make the pixel layout more compact while satisfying design rules, and contributes to improving the resolution of the display substrate.

[0110] For example, as shown in FIG. 4A, the active regions P1a of the first data writing transistors P1 of two subpixels adjacent to each other in the second direction D2 are connected to each other to form an integral structure, i.e., the active regions P1a of the two first data writing transistors P1 are located in the same doping region A1 (P well) of the same second region 402, and the first poles of the two first data transistors P1 are connected to each other to form an integral structure so as to receive the same data signal Vd.

[0111] For example, as shown in FIG. 4A, the active regions N1a of the second data write transistors N1 of two subpixels adjacent to each other in the second direction D2 are connected to each other to form an integral structure, that is, the active regions N1a of the two second data write transistors N1 are located in the same doping region A2 (N-well) of the base substrate 101, and the first poles of the two second data write transistors N1 are connected to each other to form an integral structure so as to receive the same data signal Vd.

[0112] For example, as shown in FIG. 4A, the gates of the first data write transistor P1 or the gates of the second data write transistor N2 of two sub-pixels 100 adjacent to each other in the first direction D1 are connected to each other to form an integral structure.

[0113] In each row of pixels, the gates of the first data write transistors P1 are all configured to receive the same first control signal SEL, and the gates of the second data write transistors N1 are all configured to receive the same second control signal SEL_B. The transistors of two adjacent subpixels in the first direction D1 are mirror-symmetrical, so that the first write transistors P1 and the second write transistors N1 of the two subpixels alternately lie adjacent to each other in the first direction D1. Therefore, the gates of two adjacent first data write transistors P1 are directly connected to form a single structure, forming a first control electrode group 191, and the gates of adjacent second data write transistors N1 are directly connected to form a single structure, forming a second control electrode group 192. This arrangement allows for a more compact pixel layout while satisfying design rules, contributing to improved resolution of the display substrate.

[0114] As shown in FIG. 4A, in two subpixels 100 adjacent to each other in the first direction D1, when the driving transistors N2 thereof are adjacent to each other, the active regions N2a of the two driving transistors N2 are connected to each other to form an integral structure, that is, the active regions N2a of the two driving transistors N2 are located in the same doping region B (N well) of the base substrate 101, and the first electrodes of the two driving transistors N2 are connected to each other to form an integral structure that receives the same first power supply voltage VDD, thereby forming the third control electrode group 193. When the bias transistors N3 are adjacent to each other, the gates of the two bias transistors N3 are connected to each other to form an integral structure so as to receive the same second common voltage Vcom2, and the active regions N3a of the two bias transistors N3 are connected to each other to form an integral structure, i.e., the active regions N3a of the two bias transistors N3 are located in the same doping region C (N well) of the base substrate 101, and the first poles of the two bias transistors N3 are connected to each other to form an integral structure so as to receive the same second power supply voltage VSS.

[0115] By arranging the pixels in this way, the pixel arrangement can be made more compact while still satisfying the design rules, which contributes to improving the resolution of the display substrate.

[0116] 5A-5D illustrate the formation process of the substrate structure shown in FIG. 4A. For clarity, the figures only show two rows and two columns of sub-pixels, i.e., four adjacent sub-pixels 100, which constitute one pixel unit group. In FIG. 4A, the pixel unit group 420 is schematically illustrated by a dashed-line frame. For example, the display substrate includes a plurality of pixel unit groups arranged along a first direction D1 and a second direction D2.

[0117] Hereinafter, a process for forming a display substrate according to an embodiment of the present disclosure will be described with reference to FIGS. 5A-5D as an example, but not by way of limitation.

[0118] For example, a silicon-based base substrate is provided, for example, the material of which is P-type single crystal silicon, and an N-type transistor (e.g., a driving transistor) can be directly fabricated on the P-type silicon base, i.e., the P-type base serves as the channel region of the N-type transistor, which is advantageous in realizing the high speed advantages of NMOS devices and improving the performance of the circuit.

[0119] As shown in FIG. 5A, for example, a P-type silicon base substrate is N-type doped to form an N-type well region, ie, a second region 402, which serves as the base of the first data write transistor P1 and the resistor .

[0120] For example, the second regions 402 of two adjacent sub-pixels in the first direction D1 may be connected to each other, and the second regions 402 of two adjacent sub-pixels in the second direction D2 may be connected to each other. For example, when the N-type doping is performed, the undoped regions of the base substrate 101 are shielded.

[0121] As shown in FIG. 4B and FIG. 5B, for example, a first insulating layer 201 is formed on the base substrate 101, and then a polycrystalline silicon layer 102 is formed on the first insulating layer 201.

[0122] The first insulating layer 201 includes the gate insulating layer of each transistor and also includes the dielectric layer 104 of the storage capacitor Cst. The polysilicon layer 102 includes the first capacitor electrode 141, the resistor 130, and the gates 150, 160, 170, and 180 of each transistor (P1, N1-N3).

[0123] The gate of the first data write transistor P1 is located in the second region 402, and the N-type well region serves as the channel region of the P-type transistor. The resistor 130 is also formed in the second region 402, i.e., the orthogonal projection of the resistor 130 on the base substrate is located within the second region. Forming the resistor 130 made of polysilicon material on the N-type base reduces parasitic phenomena and improves circuit performance. Each N-type transistor is formed directly on the P-type base outside the N-type well region.

[0124] 5B , the orthogonal projections of the first capacitor electrodes 141 of the four sub-pixels in each pixel unit group on the base substrate are located outside the second region 402 and surround the second region 402. For example, the second region 402 is rectangular, and the orthogonal projections of the first capacitor electrodes 141 of each sub-pixel on the base substrate surround one corner of the rectangle, for example, each first capacitor electrode 141 includes a recessed structure with an L-shaped outline, and one corner of the rectangle extends into the orthogonal projection of the recessed structure to match the L-shaped outline.

[0125] 5B, the patterns of the polysilicon layers in two subpixels adjacent in the first direction D1 are symmetrical about an axis of symmetry along the second direction D2, and the patterns of the polysilicon layers in two subpixels adjacent in the second direction D2 are symmetrical about the axis of symmetry along the first direction D1, i.e., the patterns of the polysilicon layers are symmetrical patterns. For example, as shown in FIG. 5B, the resistors of the subpixels adjacent in the first direction are symmetrical about an axis of symmetry along the second direction, and the resistors of the subpixels adjacent in the second direction are symmetrical about the axis of symmetry along the first direction. For example, the first capacitor electrodes of the subpixels adjacent in the first direction are symmetrical about the axis of symmetry along the second direction, and the first capacitor electrodes of the subpixels adjacent in the second direction are symmetrical about the axis of symmetry along the first direction.

[0126] For example, the gates of the first data write transistor P1 and the second data write transistor N1 of two subpixels adjacent to each other in the first direction D1 are symmetrical with respect to an axis of symmetry along the second direction D1, and the gates of the first data write transistor P1 or the second data write transistor N1 of two subpixels adjacent to each other in the first direction D1 are integrally formed.

[0127] For example, the gates of the first data write transistor P1 and the second data write transistor N1 of two sub-pixels adjacent in the second direction D2 are symmetrical with respect to the axis of symmetry along the first direction.

[0128] For example, the first insulating layer is formed on the base substrate by thermal oxidation, and the material of the first insulating layer is, for example, silicon nitride, silicon oxide, or silicon oxynitride.

[0129] For example, a polycrystalline silicon material layer is formed on the first insulating layer by a chemical vapor deposition process (PVD), and then a lithography process is performed on the polycrystalline silicon material layer to form the polycrystalline silicon layer 102 .

[0130] FIG. 5C shows a doping window region 103 (left) in the base substrate, and the doping window region (right) in the substrate structure shown in FIG. 5B. For example, the doping is heavy doping to form contact hole regions for electrical connection to the base substrate. For example, the doping window region includes the source and drain regions of each transistor. For example, the doping window region further includes each contact hole region in the base and the contact hole region in the resistor 130, such as contact hole regions 400a, 400b, 411a, 411b, 145a, 145b, 133, and 134 shown in FIG. 4B. For example, because the transistor gate is made of polycrystalline silicon material, the polycrystalline silicon gate also needs to be doped. When doping, a barrier layer needs to be formed to block the undoped regions, exposing only the corresponding doping window region and amorphous silicon region.

[0131] 5C only shows each doping window region, and in the actual doping process, corresponding barrier / mask layers are provided to expose the corresponding doping window regions and polysilicon regions for doping, and the material of the barrier / mask layers can be, for example, photoresist or oxide material.

[0132] 5D, a barrier layer 135 is formed corresponding to the resistor 130. In order to protect the resistance value of the resistor 130, it is necessary to shield the resistor 130 during the doping process to prevent the resistor 130 from being damaged by the doping. The barrier layer 135 shields the main body of the resistor 130, and only exposes the contact hole regions 133 and 134 at both ends of the resistor 130.

[0133] For example, the barrier layer 135 may be silicon nitride, silicon oxide, silicon oxynitride, or a photoresist material. After the doping process is complete, the barrier layer 135 may remain on the display substrate or may be removed.

[0134] In some other examples, the barrier layer 135 of the resistor 130 may be formed together with the barrier layer / mask layer of other regions when doping, and the embodiments of the present disclosure are not limited thereto.

[0135] For example, in the doping process, N-type doping and P-type doping are required, respectively, to form the source and drain regions of an N-type transistor and the source and drain regions of a P-type transistor. When performing the N-type doping process, a barrier layer must be formed to block the region that is not to be N-type doped, and when performing the P-type doping process, a barrier layer must be formed to block the region that is not to be P-type doped.

[0136] Figure 5E shows the N-type doped regions SN and P-type doped regions SP with different shading patterns (left) and the N-type doped regions SN and P-type doped regions SP (right) in the substrate shown in Figure 5D, which are also shown in Figure 4B and may be referenced thereto.

[0137] For example, performing an N-type doping process involves forming a barrier layer covering the P-type doping region SP and the N-type doping region SN except for the doping window region and the polysilicon region, leaving only the N-type doping region SN and the polysilicon region, i.e., the overlapping region between the SN region and the doping window region 103 and the polysilicon region shown in FIG. 5C, and then performing the N-type doping process. In contrast to FIG. 4B, the gates, first and second poles, and contact hole regions 411a, 411b, 145a, and 145b of transistors N1-N3 can be formed by the N-type doping process. The N-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, boron.

[0138] For example, performing a P-type doping process includes forming a barrier layer covering the N-type doping region SN and the P-type doping region SP except for the doping window region and the polysilicon region, leaving only the doping window region and the polysilicon region of the P-type doping region SP, i.e., the overlapping region of the SP region with the doping window region 103 and the polysilicon region shown in FIG. 5C, and then performing a P-type doping process. In contrast to FIG. 4B, the gate, first and second electrodes, and contact holes 400a, 400b, 133, and 134 of transistor P1 can be formed by the P-type doping process. The P-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, phosphorus.

[0139] During the doping process, for example, an ion implantation process is used, and the polysilicon pattern is used as a mask, so that ions are implanted into the silicon-based base exactly on both sides of the polysilicon, thereby forming the first and second electrodes of each transistor and achieving self-alignment. Furthermore, the resistivity of the polysilicon, which is originally high in resistance, is reduced by the doping process, allowing it to be used to form the gates of each transistor and the first capacitor electrodes. Therefore, using polysilicon material as the material for the resistors and gates has multiple beneficial effects and reduces process costs.

[0140] In this way, the structure of the display substrate including the transistors P1, N1-N3, the resistor 130, and the storage capacitor Cst shown in FIG. 4A is formed.

[0141] For example, corresponding transistors, resistors, and storage capacitors Cst in two adjacent subpixels in the first direction D1 are each symmetrical with respect to an axis of symmetry along the second direction D2, and corresponding transistors, resistors, and storage capacitors Cst in two adjacent subpixels in the second direction D2 are each symmetrical with respect to an axis of symmetry along the first direction D1.

[0142] In this embodiment, the storage capacitor Cst is a capacitor formed by the field effect, and after a voltage is applied to the first capacitor electrode 141, an inversion charge is generated in the region located below the first capacitor electrode 141 on the base substrate 101, making the lower electrode of the storage capacitor Cst, i.e., the second capacitor electrode 142, a conductor.

[0143] In some other embodiments, a conductive treatment (e.g., a doping treatment) may be performed in advance on the region of the base substrate 101 located below the first capacitor electrode 141 to form the second capacitor electrode 142. The embodiments of the present disclosure are not limited thereto.

[0144] The display substrate shown in Figure 3A is formed by sequentially forming the second insulating layer 202, the first conductive layer 301, the third insulating layer 203, the second conductive layer 302, the fourth insulating layer 204, the third conductive layer 303, the fifth insulating layer 205 and the fourth conductive layer 304 on the substrate shown in Figure 4A.

[0145] 6A and 6B respectively show the pattern of the first conductive layer 301 and the first conductive layer 301 when disposed on the substrate structure shown in FIG. 4A, and FIG. 6C shows a cross-sectional view taken along the cross-sectional line IV-IV' of FIG. 6B. FIG. 6B also shows vias in the second insulating layer 202, which correspond one-to-one to the contact areas in FIG. 4B and are used to electrically connect the contact hole areas to the pattern in the first conductive layer 301. For clarity, the figures only show two rows and six columns of sub-pixels, and the area of ​​one sub-pixel 100 is indicated by a dashed frame. FIG. 6B also shows the corresponding position of the cross-sectional line I-I' in FIG. 3A.

[0146] 6A, the patterns of the first conductive layers in two subpixels adjacent to each other in the first direction D1 are symmetrical about an axis of symmetry along the second direction D2, and the patterns of the first conductive layers in two subpixels adjacent to each other in the second direction D2 are symmetrical about the axis of symmetry along the first direction D1. Hereinafter, the patterns of the first conductive layers will be described by taking one subpixel as an example.

[0147] As shown in FIG. 6A, the first conductive layer 301 includes a connection electrode 313 (an example of a first connection electrode in this disclosure) for electrically connecting the first terminal 131 of the resistor 130 to the second electrode 152 of the driving subcircuit 112.

[0148] For example, as shown in FIG. 6B, the first terminal of the connection electrode 313 is electrically connected to the first terminal 131 of the resistor 130 by a via 225 in the second insulating layer 202, and the second terminal of the connection electrode 313 includes a first branch portion 331 and a second branch portion 332, and as shown in FIG. 3B, the first branch portion 331 is electrically connected to the first pole 151 of the driving transistor N2 by a via 226a in the second insulating layer 202, and the second branch portion 332 is electrically connected to the first pole 181 of the bias transistor N3 by a via 226b in the second insulating layer 202.

[0149] For example, as shown in FIG. 6B, in the second direction D2, the vias 225 and 226a are located on opposite sides of the first capacitor electrode 141, respectively, i.e., the orthogonal projection of the connection electrode 313 on the base substrate 101 passes through the orthogonal projection of the first capacitor electrode 141 on the base substrate 101 in the second direction D2.

[0150] For example, at least two vias 226a and 226b may be provided to reduce contact resistance.

[0151] For example, as shown in Figures 6A and 6B, the first conductive layer 301 further includes a connection electrode 314, which is electrically connected to the second terminal 132 of the resistor 130 by a via 229 in the second insulating layer 202, and the connection electrode 314 is used to electrically connect to the first electrode 121 of the light-emitting element 120.

[0152] For example, the connecting electrode 314 is L-shaped, one branch of which is electrically connected to the second terminal 132 of the resistor 130 , and the other branch of which is electrically connected to the first electrode 121 of the light emitting element 120 .

[0153] 6B and 6C, the first conductive layer 301 further includes a third capacitor electrode 315 (an example of a second capacitor electrode in the present disclosure) overlapping the first capacitor electrode 141 in a direction perpendicular to the base substrate. The third capacitor electrode 315 is located on the side of the first capacitor electrode 141 away from the second capacitor electrode 142 and is configured to be electrically connected to the second capacitor electrode 142. That is, in a direction perpendicular to the base substrate, the second capacitor electrode 142 and the third capacitor electrode 315 are located on both sides of the first capacitor electrode 141 and are electrically connected to each other, thereby forming a parallel-connected capacitor structure and increasing the capacitance value of the storage capacitor Cst.

[0154] 6B and 6C, the third capacitor electrode 315 includes a first portion 315a and a second portion 315b, and the first portion 315a and the second portion 315b are spaced apart from each other in the first direction D1. For example, the first portion 315a of the third capacitor electrode 315 is electrically connected to the contact hole region 145b by a via 228 in the second insulating layer 202 to be electrically connected to the second capacitor electrode 142, and the second portion 315b is electrically connected to the contact hole region 145a by a via 227 in the second insulating layer 202 to be electrically connected to the second capacitor electrode 142.

[0155] For example, the first portion 315a and the second portion 315b of the third capacitor electrode 315 are located on both sides of the connection electrode 313 in the first direction D1, and are spaced apart from the connection electrode 313, respectively.

[0156] For example, the third capacitor electrodes 315 of two adjacent subpixels in the first direction D1 are symmetrical with respect to an axis of symmetry along the second direction D2, and the third capacitor electrodes 315 of two adjacent subpixels in the second direction D2 are symmetrical with respect to an axis of symmetry along the first direction D1.

[0157] For example, as shown in FIG. 6B, the first portion 315a or the second portion 315b of the third capacitor electrode 135 of two subpixels adjacent to each other in the first direction D1 are integrally formed.

[0158] For example, as shown in FIG. 6B, for each pixel unit group 420, the first portions 315a of the third capacitor electrodes 315 of two sub-pixels adjacent to each other in the first direction D1 are connected to each other to form an integral structure.

[0159] For example, as shown in FIG. 6B , the second portion 315b of the third capacitor electrode 315 of the subpixel in each pixel unit group 420 is interconnected to the second portion 315b of the third capacitor electrode 315 of the subpixel adjacent to the subpixel in the pixel unit group adjacent to the pixel unit group 420, forming an integral structure.

[0160] For example, as shown in FIG. 6A, adjacent third capacitor electrodes 315 in two subpixels adjacent in the first direction D1 may be integrally formed so as to receive the same second power supply voltage VSS, and adjacent third capacitor electrodes 315 in two subpixels adjacent in the first direction D1 may be integrally formed so as to receive the same second power supply voltage VSS.

[0161] For example, to reduce contact resistance, at least two vias 227 and at least two vias 228 may be provided, for example, the at least two vias 227 are arranged along the second direction D2, and the at least two vias 228 are arranged along the second direction D2.

[0162] For example, the first conductive layer 301 further includes a connection electrode 317 (an example of a second connection electrode in the present disclosure), which is used to electrically connect the second terminal of the data writing sub-circuit to the first terminal of the recording sub-circuit, i.e., to electrically connect the second pole 161 of the first data writing transistor P1, the second pole 171 of the second data writing transistor N1, and the first capacitor electrode 141.

[0163] 6A and 6B, the connection electrode 317 has three ends, for example, a T-shaped structure. Referring to FIG. 3B, a first terminal of the connection electrode 317 is electrically connected to the second electrode of the first data write transistor P1 by a via 261a in the second insulating layer 202, a second terminal of the connection electrode 317 is electrically connected to the second electrode of the second data write transistor N1 by a via 261b in the second insulating layer 202, and a third terminal of the connection electrode 317 is electrically connected to the first capacitor electrode 141 by a via 261c in the second insulating layer 202.

[0164] 6B, in the second direction D2, the connecting electrode 314 at least partially overlaps with the third terminal of the connecting electrode 317. This arrangement makes the pixel arrangement more compact, thereby increasing the space utilization rate of the display substrate and improving the resolution of the display substrate.

[0165] 6A and 6B, the first conductive layer 301 further includes a first scan line connecting portion 311 and a second scan line connecting portion 312, the first scan line connecting portion 311 is used to electrically connect the gate of the first data write transistor P1 to a first scan line so as to receive a first control signal SEL, and the second scan line connecting portion 312 is used to electrically connect the gate of the second data write transistor N1 to a second scan line so as to receive a first control signal SEL_B.

[0166] For example, the first scanning line connection portion 311 is electrically connected to the gate of the first data writing transistor P1 by a via 221 in the second insulating layer 202, and the second scanning line connection portion 312 is electrically connected to the gate of the second data writing transistor N1 by a via 222 in the second insulating layer 202.

[0167] For example, as shown in FIG. 6A, sub-pixels adjacent to each other in the first direction D1 share the first scan line connection portion 311 or the second scan line connection portion 312.

[0168] For a detailed description of the first and second scan line connecting portions, please refer to the description of FIGS. 10A-10B below.

[0169] As shown in FIG. 6A, the first conductive layer 301 further includes a data line connection portion 245, which is used to electrically connect to a data line such that the first pole of the first data write transistor P1 and the first pole of the second data write transistor N1 receive a data signal Vd transmitted through the data line.

[0170] As shown in FIG. 6B, the data line connection portion 245 is electrically connected to the first pole 161 of the first data write transistor P1 by a via 223 in the second insulating layer 202, and is electrically connected to the first pole 171 of the second data write transistor N1 by a via 224 in the second insulating layer 202.

[0171] 6A, the data line connection portions 245 are spaced apart in the first direction D1, for example, at the boundaries of two subpixel rows, and for example, two adjacent subpixels in the second direction D2 share one data line connection portion 245.

[0172] For a detailed description of the data line connection portion, please refer to the description of the second data line connection portion in FIGS. 8A-8D below.

[0173] 6A and 6B, the first conductive layer 301 further includes a connection electrode 318, which is electrically connected to the first electrode of the driving transistor N2 by a via 230 in the second insulating layer 202.

[0174] 4A and 6B, the first conductive layer 301 further includes connecting electrodes 319a, 319b, and 319c, which are all set to bias the bases of the transistors, for example, connecting the N-type base to a first power supply voltage terminal to receive a first power supply voltage VDD (high voltage), or connecting the P-type base to a second power supply voltage terminal to receive a second power supply voltage VSS (low voltage), thereby avoiding parasitic phenomena such as base bias and improving circuit stability.

[0175] 4B , the connection electrodes 319a and 319b are electrically connected to contact hole regions 411a and 411b in the second region (N-well region) 402 of the base substrate 101 by vias 262a and 262b in the second insulating layer 202, respectively, and the connection electrodes 319a and 319b are connected to a first voltage terminal VDD to bias the N-type base of the first data write transistor P1. The connection electrode 319c is electrically connected to contact hole region 400a in the base substrate 101 by via 262c in the second insulating layer 202, and the connection electrode 319c is connected to a second voltage terminal VSS to bias the P-type base of the second data write transistor N1.

[0176] 6A-6B, the first conductive layer 301 further includes a bias voltage line 250 extending along the first direction D1 to provide a second common voltage Vcom2 and electrically connected to the gate of the bias transistor N3 by a via 263 in the second insulating layer 202.

[0177] 4B and 6A-6B, the first conductive layer 301 further includes a power line 260 extending along a first direction D1 for transmitting a second power supply voltage VSS. The power line 260 is electrically connected to a first electrode of the bias transistor N3 by a via 264a in the second insulating layer 202 to provide the second power supply voltage VSS, and is electrically connected to a contact hole region 400b in the base substrate 101 by a via 264b in the second insulating layer 202 to bias the P-type base of the second data write transistor N1.

[0178] 7A shows a schematic diagram of the second conductive layer 302, and FIG. 7B shows the second conductive layer 302 based on the first conductive layer 301. FIG. 7B also shows vias in the third insulating layer 203, which are used to connect the pattern in the first conductive layer 301 with the pattern in the second conductive layer 302. For clarity, the figure only shows four rows and six columns of subpixels, and dashed lines indicate the boundaries between two subpixel rows. FIG. 7B also shows the corresponding location of the cross-sectional line I-I' in FIG. 3A.

[0179] 7A, the patterns of the second conductive layers in two subpixels adjacent to each other in the first direction D1 are symmetrical about an axis of symmetry along the second direction D2, and the patterns of the second conductive layers in two subpixels adjacent to each other in the second direction D2 are symmetrical about the axis of symmetry along the first direction D1. Hereinafter, the patterns of the second conductive layers will be described by taking one subpixel as an example.

[0180] 7A, the second conductive layer 302 includes power lines 270a, 270b, 280a, and 280b extending along a first direction D1, where the power lines 270a and 270b are used to transmit the second power voltage VSS and the power lines 280a and 280b are used to transmit the first power voltage VDD. The power lines 270a, 280a, 270b, and 280b are alternately arranged in a second direction D2.

[0181] 3B, 7A, and 7B, the power supply line 270a is electrically connected to the power supply line 260 in the first conductive layer 301 by a plurality of vias 235 arranged in the third insulating layer 203 along the first direction D1, thereby forming a parallel connection structure and effectively reducing wiring resistance. For example, the power supply line 270b is electrically connected to the third capacitor electrode 315 by vias 236 arranged in the third insulating layer 203 along the second direction D2 to provide the second power supply voltage VSS. For example, the power supply line 270b is further electrically connected to the third capacitor electrode 315 (315b) by vias 267 arranged in the third insulating layer 203 along the second direction D2 to provide the second power supply voltage VSS.

[0182] For example, the width of power line 270b is greater than that of power line 270a in the second direction D2 because the first and second portions of third capacitor electrode 315 electrically connected to power line 270b both have large areas. By being arranged to have a large width, power line 270b contributes to forming multiple connection holes 236, 267 between power line 270b and third capacitor electrode 315, thereby effectively reducing contact resistance.

[0183] 7A and 7B, the power supply line 280a is electrically connected to the connection electrode 318 on the first conductive layer 301 by a via 237 in the third insulating layer 203 to provide a first power supply voltage VDD and is connected to the first electrode of the drive transistor N2. The power supply line 280b is electrically connected to the connection electrode 319a on the first conductive layer 301 by a via 238 in the third insulating layer 203 to bias a second region (N-well region) 402 in the base substrate 101 to a high voltage, and for example, the multiple vias 238 are arranged along the second direction D2.

[0184] For example, the width of the power line 280b is larger than that of the power line 280a in the second direction D2 because the connection electrode 319a electrically connected to the power line 280b has a relatively large size in the second direction D2. The power line 280b is arranged to have a relatively large width, which contributes to forming multiple connection holes 238 between the power line 280b and the connection electrode 319a, thereby increasing the contact area with the connection electrode 319a and effectively reducing the contact resistance.

[0185] For example, the second conductive layer 302 further includes a plurality of first scan lines 210 and a plurality of second scan lines 220 extending along a first direction D1. For example, the scan line 11 shown in FIG. 1A may be the first scan line 210 or the second scan line 220.

[0186] 6A and 6B, the first scanning line 210 is electrically connected to the first scanning line connection portion 311 by a via 231 in the third insulating layer 203, and the second scanning line 220 is electrically connected to the second scanning line connection portion 312 by a via 232 in the third insulating layer 203.

[0187] For a detailed description of the first and second scan lines, please refer to the description of FIGS. 10A-10B below.

[0188] 3B, 7A and 7B, the second conductive layer 302 further includes a connection electrode 323, which is electrically connected to the connection electrode 314 of the first conductive layer 301 by a via 239 in the third insulating layer 203, and is connected to the second terminal 132 of the resistor 130. The connection electrode 323 is electrically connected to the first electrode 121 of the light emitting element 120. For example, the number of the vias 239 is at least two.

[0189] For example, as shown in conjunction with Figures 7A and 7B, the second conductive layer 302 further includes a connection electrode 324, which is electrically connected to the connection electrode 319b in the first conductive layer 301 by a via 265 in the third insulating layer 203 so as to be electrically connected to the contact hole region 411b of the second region (N-well region) 402 in the base substrate 101.

[0190] For example, as shown in conjunction with Figures 7A and 7B, the second conductive layer 302 further includes a connection electrode 325, which is electrically connected to the connection electrode 319c in the first conductive layer 301 by a via 266 in the third insulating layer 203 so as to be electrically connected to the contact hole region 400a in the base substrate 101.

[0191] For example, the connecting electrodes 325 have a cross structure, and the connecting electrodes 324 and 325 are alternately distributed in the first direction D1 and located at the boundaries of two sub-pixel rows.

[0192] For example, as shown in Figure 7A, the second conductive layer 302 further includes a data line connection portion 244. As shown in Figure 7B, the data line connection portion 244 is electrically connected to a data line connection portion 245 in the first conductive layer 301 by a via 233.

[0193] For example, as shown in FIG. 7A, the data line connecting portions 244 are spaced apart in the first direction D1, and one connecting electrode 324 or one connecting electrode 325 is provided between every two adjacent data line connecting portions 244.

[0194] For example, the data line connection portion 244 is located at the boundary between two sub-pixel rows, and two sub-pixels adjacent to each other in the second direction D2 share one data line connection portion 244.

[0195] For example, as shown in Figures 7A and 7B, in the second direction D2, the data line connection portions 244 in the sub-pixels of each column are alternately located on both sides of the data line connection portion 245, and are electrically connected to the first terminal and the second terminal of the data line connection portion 245 by vias 233 and 234, respectively, thereby connecting the data line connection portion 245 to different data lines.

[0196] For a specific description of the data line connection portion, please refer to the description of the first data line connection portion in FIGS. 11A-11D below.

[0197] 8A shows a schematic diagram of the third conductive layer 303, and FIG. 8B shows the third conductive layer 303 based on the second conductive layer 302. FIG. 8B also shows vias in the fourth insulating layer 204, which are used to connect the patterns in the second conductive layer 302 and the patterns in the third conductive layer 303. For clarity, the figure only shows the conductive patterns corresponding to the sub-pixels of four rows and six columns, and FIG. 8A shows the boundaries of two rows of sub-pixels with dashed lines. FIG. 8B also shows the corresponding position of the cross-sectional line I-I' in FIG. 3A.

[0198] For example, the third conductive layer 303 includes a plurality of data lines extending along the second direction D2, which are used to connect to first terminals of data writing sub-circuits in the sub-pixels to provide data signals Vd. For example, as shown in FIG. 8A, the plurality of data lines includes a plurality of first data lines 241 and a plurality of second data lines 242 alternately arranged one after another in the first direction D1. For example, the data line 12 shown in FIG. 1A may be the first data line 241 or the second data line 242.

[0199] For example, the data lines are divided into multiple data line groups, and each data line group includes one first data line 241 and one second data line 242. For example, each subpixel column is connected to one data line group, i.e., one first data line 241 and one second data line 242, that is, one column of subpixels is driven by two data lines, which contributes to reducing the load on each data line, thereby improving the driving capability of the data lines, reducing signal delay, and improving the display effect.

[0200] 8B, the first data line 241 is electrically connected to the data line connection portion 244 located between the subpixels of the first row and the subpixels of the second row in the second conductive layer 302 shown in FIG. 7B by the via 403 in the fourth insulating layer 204, thereby providing data signals to the subpixels of the first and second rows, and the second data line 242 is electrically connected to the data line connection portion 244 located between the subpixels of the third row and the subpixels of the fourth row in the second conductive layer 302 shown in FIG. 7B by the via 404 in the fourth insulating layer 204, thereby providing data signals to the subpixels of the third and fourth rows.

[0201] For a detailed description of the first and second data lines, please refer to the description of Figures 11A-11D below. For ease of comparison, Figure 8B shows positions corresponding to cross-sectional lines II-II' and III-III' in Figure 11B.

[0202] For example, the third conductive layer 303 includes power lines 330 and 340 extending in the second direction D2. The power line 330 is used to transmit a first power voltage VDD, and the power line 340 is used to transmit a second power voltage VSS. As shown in FIG. 8A, the power lines 330 and 340 are alternately arranged in the first direction D1.

[0203] 8B, the power supply line 330 is electrically connected to the power supply lines 280a and 280b in the second conductive layer 302 by vias 405 and 406 in the fourth insulating layer 204, respectively, thereby forming a mesh-like power supply line structure for transmitting the first power supply voltage. Such a structure contributes to reducing the resistance in the power supply line, thereby reducing the voltage drop in the power supply line and contributing to uniformly transmitting the first power supply voltage VDD to each subpixel of the display substrate. The power supply line 330 is further electrically connected to the connection electrode 324 (see FIG. 7A) in the second conductive layer 302 by via 407 in the fourth insulating layer to bias the N-type base where the first data write transistor P1 and resistor 130 are located, and is electrically connected to the contact hole region 411b in the second region (N-well region) 402 in the base substrate 101.

[0204] 8B, the power supply line 340 is electrically connected to the power supply lines 270a and 270b in the second conductive layer 302 by vias 408 and 409 in the fourth insulating layer 204, respectively, thereby forming a mesh-like power supply line structure for transmitting the second power supply voltage. Such a structure contributes to reducing the resistance in the power supply line, thereby reducing the voltage rise in the power supply line, and contributing to uniformly transmitting the second power supply voltage VSS to each subpixel of the display substrate. The power supply line 340 is further electrically connected to the connection electrode 325 (see FIGS. 3B and 6A) in the second conductive layer 302 by vias 412 in the fourth insulating layer to bias the P-type bases on which the transistors N1-N3 are located, and is electrically connected to the contact hole region 400a in the base substrate 101.

[0205] As shown in FIG. 8A , the third conductive layer 303 further includes a connecting electrode 333 located between the first data line 241 and the second data line 242 in one data line group. As shown in FIG. 7B , the connecting electrode 333 is electrically connected to the power line 270b in the second conductive layer by a via 413 in the fourth insulating layer, where the number of vias 413 is at least two, so that the connecting electrode 333 can be in sufficient contact with the power line 270b and reduce contact resistance. The connection electrode 333 connected in parallel to the power line 270b reduces the resistance of the power line 270b, thereby reducing the voltage rise in the power line and contributing to uniformly transmitting the second power supply voltage VSS to each sub-pixel of the display substrate.

[0206] 3B, 8A and 8B, the third conductive layer 303 further includes a connection electrode 334, which is electrically connected to the connection electrode 323 of the second conductive layer 302 by a via 414 in the fourth insulating layer, and is connected to the second terminal 132 of the resistor 130. The connection electrode 334 is used to electrically connect to the first electrode 121 of the light emitting element 120. For example, the number of the vias 414 is at least two.

[0207] 8A and 8B, the third conductive layer 303 further includes a shielding electrode 341. For example, the shielding electrode 341 extends along the second direction D2 and is located between the first data line 241 and the second data line 242 in one data line group. For example, the first data line 241 and the second data line 242 are symmetrically disposed on both sides of the shielding electrode 341 of the second data line. The shielding electrode 341 is disposed between the two data lines and performs a shielding function to prevent signals on the two data lines from interfering with each other. For example, the shielding electrode 341 receives a constant voltage to improve shielding capability. In this embodiment, the shielding electrode 341 receives the second power supply voltage VSS.

[0208] For example, the display substrate includes a plurality of shielding electrodes 341 that are arranged in one-to-one correspondence with the plurality of data line groups, and each shielding electrode is located between the first data line and the second data line of the corresponding data line group.

[0209] 8A, the connecting electrode 333, the connecting electrode 334, and the shielding electrode 341 are arranged in the second direction D2 and are located between the first data line 241 and the second data line 242. The connecting electrode 333, the connecting electrode 334, and the shielding electrode 341 form a shielding wall, which performs a shielding function within the entire extension range of the first data line 241 and the second data line 242 to prevent signals from interfering with each other on the two data lines.

[0210] 8A , the connecting electrode 333 and the shielding electrode 341 are located on either side of the connecting electrode 334, and are spaced apart from the connecting electrode 334. One end of the connecting electrode 333 that is close to the connecting electrode 334 has a protrusion 333a that is L-shaped, with a first branch extending along a first direction D1 and connected to the main body of the connecting electrode 333, and a second branch extending along a second direction D2 that is close to the connecting electrode 334 and overlapping the gap between the connecting electrode 333 and the connecting electrode 334 in the first direction D1, thereby improving the shielding ability and preventing signal interference between the two data lines.

[0211] Similarly, one end of the shielding electrode 341 close to the connecting electrode 334 has an L-shaped protrusion 341a for further blocking the gap between the shielding electrode 341 and the connecting electrode 334 and improving the shielding ability.

[0212] In this way, the shielding wall achieves complete shielding in the second direction D2, and the first data line 241 and the second data line 242 do not have any areas directly facing each other in the first direction D1, thereby achieving excellent signal shielding function, so that the display data has good stability and the display effect is improved.

[0213] 9A shows a schematic diagram of the fourth conductive layer 304, and FIG. 9B shows the fourth conductive layer 304 based on the third conductive layer 303. FIG. 9B also shows a via in the fifth insulating layer 205, which is used to connect the pattern in the third conductive layer 303 with the pattern in the fourth conductive layer 304. For clarity, the figure only shows sub-pixels with four rows and six columns, and dashed lines indicate the boundaries of two rows of sub-pixels. FIG. 9B also shows the corresponding position of the cross-sectional line I-I' in FIG. 3A.

[0214] For example, the fourth conductive layer 304 includes power lines 350 and 360 extending along the second direction D2. The power line 350 is used to transmit a first power voltage VDD, and the power line 360 ​​is used to transmit a second power voltage VSS. As shown in FIG. 9A , the power lines 350 and 360 are alternately arranged in the first direction D1.

[0215] For example, the plurality of power lines 350 and the plurality of power lines 330 are arranged in one-to-one correspondence, the plurality of power lines 360 and the plurality of power lines 340 are arranged in one-to-one correspondence, and in the direction perpendicular to the base substrate 101, each power line 350 overlaps and is electrically connected (for example, connected in parallel) to the corresponding power line 330, and each power line 360 ​​overlaps and is electrically connected (for example, connected in parallel) to the corresponding power line 340. This reduces the resistance in the power lines and improves display uniformity.

[0216] 9B, the power line 350 is electrically connected to the corresponding power line 330 by a via 251 in the fifth insulating layer 205, and the power line 360 ​​is electrically connected to the corresponding power line 340 by a via 252 in the fifth insulating layer 205. For example, the number of the vias 251 and 252 is at least two.

[0217] 9A and 9B , the fourth conductive layer 304 further includes a connecting electrode 342, which is electrically connected to the connecting electrode 333 of the third conductive layer 303 by a via 253 in the fifth insulating layer, where the number of vias 253 is at least two, so that the connecting electrode 342 can be in sufficient contact with the connecting electrode 333 and reduce contact resistance. The provision of the connecting electrode 342 contributes to further reducing the resistance of the power supply line 270b, thereby reducing the voltage rise in the power supply line and contributing to uniformly transmitting the second power supply voltage VSS to each sub-pixel of the display substrate.

[0218] 3B, 9A and 9B, the fourth conductive layer 304 further includes a connection electrode 343, which is electrically connected to the connection electrode 334 of the third conductive layer 303 by a via 254 in the fifth insulating layer, and is connected to the second terminal 132 of the resistor 130. The connection electrode 343 is electrically connected to the first electrode 121 of the light emitting element 120. For example, the number of the vias 254 is at least two.

[0219] 9A and 9B , the fourth conductive layer 304 further includes a connection electrode 344, which is electrically connected to the shielding electrode 341 in the third conductive layer 303 by a via 255 in the fifth insulating layer. As shown in FIG. 9A , the fourth conductive layer 304 further includes a connection portion 345 that connects the connection electrode 344 to a power line 360 ​​that is directly adjacent to the connection electrode 344.

[0220] 9A, the connection electrodes 344 on both sides of the power line 360 ​​are symmetrically arranged with respect to the power line 360. The power line 360, the connection electrodes 344 on both sides thereof, and the corresponding connection portions 345 are interconnected to form an integrated structure. In this way, the power line 360 ​​can provide the second power supply voltage VSS to the shielding electrode 341, so as to improve the shielding ability of the shielding electrode.

[0221] For example, each via can be made conductive by further filling it with a conductive material (eg, tungsten).

[0222] FIG. 9B also shows the contact hole area 256 of the connection electrode 343 , which is used to electrically connect to the first electrode 121 of the light emitting device 120 .

[0223] Although the portion of the connection electrode 343 located at the contact hole region 256 along the cross-sectional line I-I' is not continuous with the portion of the connection electrode 343 corresponding to the via 254 (area F shown in FIG. 9B ), for ease of explanation, the cross-sectional view shown in FIG. 3B shows the contact hole region 256 and the via 254 in the continuous connection electrode 343, i.e., consistent with the actual situation. For example, as shown in FIG. 3B , the display substrate 10 further includes a sixth insulating layer 206, in which a via 257 is formed corresponding to the contact hole region 256 of the connection electrode 343, and the via 257 is filled with a conductive material (e.g., tungsten), and a polishing process (e.g., chemical mechanical polishing) is performed to form a flat surface to form the light-emitting element 120.

[0224] For example, the number of vias 257 is at least two.

[0225] For example, as shown in FIG. 3B, the number of contact hole areas for electrical connection in the connection electrodes 314, 323, 334, and 343 connected to the first electrode 121 of the light-emitting element 120 is at least two, which reduces the contact resistance between the connection electrodes and ultimately reduces the connection resistance between the resistor 130 and the first electrode 121 of the light-emitting element 120. This reduces the voltage drop in the transmission path through which the data signal is transmitted from the resistor 130 to the first electrode 121, alleviating problems such as color cast and display unevenness caused by anode potential loss (grayscale loss) due to the voltage drop, and improving the display effect.

[0226] 3B, the vias 257, 254, and 414 corresponding to the first electrodes 121 of the light-emitting elements 120 do not overlap with each other in the direction perpendicular to the base substrate 101. Stacking the vias in the direction perpendicular to the substrate can easily cause poor connections, disconnections, and unevenness at the points where the vias are located. Therefore, arranging them as described above improves the quality of the electrical connection of the first electrodes 121 of the light-emitting elements 120 and enhances the display effect.

[0227] 3B , the light-emitting element 120 includes a first electrode 121, a light-emitting layer 123, and a second electrode 122, which are sequentially disposed on the sixth insulating layer 206. For example, the first electrode 121 and the second electrode 122 are respectively an anode and a cathode of an OLED. For example, a plurality of first electrodes 121 are disposed at intervals on the same layer, and correspond one-to-one to a plurality of sub-pixels. For example, the second electrode 122 is a common electrode, and its entire surface is disposed within the display substrate 10.

[0228] For example, as shown in FIG. 3B, the display substrate further includes a first package layer 124, a color filter layer 125, and a cover plate 126, which are located on the side of the light emitting element 120 away from the base substrate 101.

[0229] For example, the first package layer 124 is configured to seal the light emitting element to prevent damage to the device due to intrusion of external moisture and oxygen into the light emitting element and pixel circuit. For example, the package layer 124 includes an organic thin film or a structure in which organic thin films and inorganic films are alternately stacked. For example, a water absorbing layer configured to absorb water vapor or sol remaining in the light emitting element during the previous manufacturing process may be further installed between the package layer 124 and the light emitting element. The cover plate 126 is, for example, a glass cover plate.

[0230] For example, as shown in FIG. 3B, the display substrate may further include a second package layer 127 located between the color filter layer 125 and the cover plate 126, which can protect the color filter layer 125.

[0231] For example, the light emitting element 120 may be configured to emit white light and, in combination with a color filter layer 124, provide a full color display.

[0232] In some other examples, the light emitting element 120 is configured to emit light of three primary colors, in which case the color filter layer 124 is not required. The embodiments of the present disclosure do not limit the manner in which the display substrate 10 achieves a full color display.

[0233] Table A below exemplarily shows thickness ranges and exemplary values ​​for the first to sixth insulating layers, Table B exemplarily shows thickness ranges and exemplary values ​​for the first to fourth conductive layers, Table C exemplarily shows sizes and exemplary values ​​for via VIA2 in the second insulating layer, via VIA3 in the third insulating layer, via VIA4 in the fourth insulating layer, via VIA5 in the fifth insulating layer, and via VIA6 in the sixth insulating layer, and Table D exemplarily shows exemplary values ​​for the channel width, length, and aspect ratio of each transistor (N1-N4, P1), but these do not limit the present disclosure.

[0234] [Table 1]

[0235] [Table 2]

[0236] [Table 3]

[0237] [Table 4]

[0238] For example, as shown in Table A, among the first to sixth insulating layers, the first insulating layer 201 has the smallest thickness and the second insulating layer 202 has the largest thickness. This is because the first insulating layer 201 includes the gate insulating layer of each transistor and also includes the dielectric layer 104 of the storage capacitor Cst. Setting the thickness of the first insulating layer 201 to a small value contributes to improving the gate controllability of the transistor and achieving a large storage capacitance. Furthermore, the second insulating layer 202 serves as a field oxide layer, and setting it to a large thickness contributes to electrical isolation between each transistor. For example, the thicknesses of the third insulating layer 203, the fourth insulating layer 204, the fifth insulating layer 205, and the sixth insulating layer 206 are the same or similar. For example, the thickness of the second insulating layer 202 is 1.5-2 times the thicknesses of the third insulating layer 203, the fourth insulating layer 204, the fifth insulating layer 205, and the sixth insulating layer 206.

[0239] For example, the planar shape of the vias may be rectangular (e.g., square) or circular, and the sizes in Table C indicate the average side length or hole diameter of the rectangle. For example, as shown in Table C, the sizes of the vias in each insulating layer are the same. For example, among the second to sixth insulating layers, the size of the vias in the sixth insulating layer 206 is the largest. This is because the sixth insulating layer 206 is closest to the light-emitting element, and in the driving process of the light-emitting element, current converges from the transistor in the lowest layer upward to the light-emitting element, so the size of the vias in the sixth insulating layer 206 is made the largest to transmit a large converged current.

[0240] For example, the distance between the first data write transistor P1 and the second data write transistor N1 is in the range of 0.4-0.45 micrometers, e.g., 0.42 micrometers, thereby contributing to improving pixel density. As shown in FIG. 4B , the distance D0 is the distance between the nearest sides of the gate 160 of the first data write transistor P1 and the gate 170 of the second data write transistor N1.

[0241] For example, as shown in FIG. 4B, resistor 130 has an equivalent length of 4.4 micrometers and an average width of 0.42 micrometers.

[0242] For example, as shown in FIG. 4B, the effective capacitance area of ​​the storage capacitor Cst is 20 square micrometers, i.e., the effective area of ​​the polysilicon layer 102 for forming the storage capacitor Cst is 20 square micrometers. For example, the area ratio of the storage capacitor Cst to each subpixel is 20%-35%, e.g., 27%. The display substrate according to the embodiment of the present disclosure can effectively increase the area ratio of the storage capacitor through a rational layout, thereby improving the capacitance value.

[0243] For example, the thickness of the polycrystalline silicon layer 102 is 200 nanometers.

[0244] At least one embodiment of the present disclosure further provides a pixel structure, the pixel structure including: a base substrate; a pixel row located on the base substrate; a first scan line; and a second scan line. The pixel row includes a plurality of sub-pixels located on the base substrate and arranged along a first direction, the first scan line and the second scan line extending along the first direction, each sub-pixel including a pixel circuit including a data writing sub-circuit, a recording sub-circuit, and a driving sub-circuit. The data writing sub-circuit includes a first control electrode, a second control electrode, a first terminal, and a second electrode, the first control electrode and the second control electrode of the data writing circuit are configured to receive a first control signal and a second control signal, respectively, the first terminal of the data writing sub-circuit is configured to receive a data signal, the second terminal of the data writing circuit is electrically connected to the first terminal of the recording sub-circuit and is configured to transmit the data signal to the first terminal of the recording sub-circuit in response to the first control signal and the second control signal, the driving sub-circuit includes a control terminal, a first terminal, and a second terminal, the control terminal of the driving sub-circuit is electrically connected to the first terminal of the recording sub-circuit. a first terminal of the driving subcircuit configured to receive a first power supply voltage and a second terminal of the driving subcircuit configured to be connected to a light-emitting element, the driving subcircuit configured to drive the light-emitting element to emit light in response to a voltage at the first terminal of the recording subcircuit; the first scan line electrically connected to a first control electrode of a data writing circuit of the plurality of subpixels to provide the first control signal; the second scan line electrically connected to a second control electrode of a data writing circuit of the plurality of subpixels to provide the second control signal; the first scan line and the second scan line have the same resistance and the same area of ​​orthogonal projection on the base substrate.

[0245] In some examples, for example, the first and second scan lines are portions of wiring within the display area that transmit corresponding control signals from the scan drive circuit to each subpixel, and therefore, when comparing resistance values ​​and areas, portions of the wiring located outside the display area are not taken into account.

[0246] In some other examples, for example, the first and second scan lines may refer to all portions of wiring that transmit corresponding control signals from a scan driving circuit to each subpixel, i.e., may include portions of the wiring located in the display area and the non-display area, such as the S portion shown in Figure 1A. For example, the first control signal SEL and the second control signal SEL_B can be output from the same gate driving circuit unit (e.g., GOA unit).

[0247] This configuration ensures that the resistance-capacitance (RC) loads of the first and second scan lines are the same. As shown in FIG. 1A , during the process of transmitting control signals from the scan driving circuit 14 to each subpixel, the proportion of the portions of the scan lines 11 (e.g., the first and second scan lines) outside the display area (shown in the dashed frame) is small. Therefore, setting the resistance-capacitance loads of the portions of the scan lines 11 within the display area to be the same can improve the synchronization of the first control signal SEL and the second control signal SEL_B. As shown in FIG. 2C , for example, when transitioning from data writing phase 1 to light-emitting phase 2, this configuration allows the rising edge of the first control signal SEL and the falling edge of the second control signal SEL_B to occur at the same time, thereby improving the anti-interference performance of the pixel circuit.

[0248] The present disclosure further provides a display substrate, including a plurality of pixel structures, wherein a plurality of pixel rows in the plurality of pixel structures are arranged along a second direction, and the first direction and the second direction intersect, whereby a plurality of sub-pixels in the plurality of pixel rows are arranged as a plurality of pixel columns.

[0249] The pixel structure according to the embodiments of the present disclosure may be applied to any one of the display substrates 10 according to the above embodiments. However, the pixel structure according to the embodiments of the present disclosure is not limited to silicon-based display substrates, and may also be applied to, for example, glass substrates or flexible substrates. In such cases, the light-emitting element may have, for example, a bottom-emitting or double-sided emitting structure.

[0250] FIG. 10A is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. For clarity, the diagram shows two rows and six columns of sub-pixels, i.e., only two of the above-described pixel structures. Compared with the display substrate shown in FIG. 3A, this display substrate omits the third and fourth conductive layers. Hereinafter, the placement of the first and second scan lines in the display substrate and pixel structure according to embodiments of the present disclosure will be described with reference to FIG. 10A as an example, but embodiments of the present disclosure are not limited thereto.

[0251] For example, as shown in FIG. 10A, each sub-pixel row is respectively connected to one first scan line 210 and one second scan line 220, but this is not a limitation of the present disclosure.

[0252] For example, the display substrate 10 further includes a plurality of first scan line connection parts 311 electrically connected to the first scan lines 210 and a plurality of second scan line connection parts 312 electrically connected to the second scan lines 220, and the first scan lines 210 are electrically connected to first control electrodes (i.e., gates of the first data writing transistors) of the data writing circuits of the sub-pixels in one row by the plurality of first scan line connection parts 311, and the second scan lines 220 are electrically connected to second control electrodes (i.e., gates of the second data writing transistors) of the data writing circuits of the sub-pixels in the same row by the plurality of second scan line connection parts 312.

[0253] For example, the first scan line 210 and the second scan line 220 are insulated from each other in the same layer and made of the same material.

[0254] For example, the plurality of first scan line connecting portions 311 and the plurality of second scan line connecting portions 312 are spaced apart in the same layer, made of the same material, and located in a different conductive layer from the first scan lines 210 and the second scan lines 220.

[0255] 10B shows an enlarged schematic view of the dashed frame region E in FIG. 10A. For clarity, the figure only shows the gates of the first data write transistor P1 and the second data write transistor N1, the first scan line 210, the second scan line 220, and the first scan line connecting portion 311 and the second scan line connecting portion 312. For ease of comparison, FIG. 7B also shows the corresponding location of region E. FIG. 10C shows a cross-sectional view along the cross-sectional line V-V' in FIG. 10B.

[0256] For example, the first scan line 210 and the second scan line 220 have the same length and width.

[0257] For example, the first scan line connecting portions 311 and the second scan line connecting portions 312 are alternately arranged in the first direction D1 and extend in a direction different from the first direction D1, the first scan line connecting portion 311 intersects with both the orthogonal projections of the first scan line 210 and the second scan line 220 on the base substrate, and the second scan line connecting portion 312 intersects with both the orthogonal projections of the first scan line 210 and the second scan line 220 on the base substrate. For example, the first scan line connecting portions 311 and the second scan line connecting portions 312 are both linear structures and extend along the second direction D2.

[0258] For example, the total area of ​​the orthogonal projection of the plurality of first scan line connection portions 311 on the base substrate is the same as the total area of ​​the orthogonal projection of the plurality of second scan line connection portions 312 on the base substrate. Therefore, the parasitic capacitances of the plurality of first scan line connection portions 311 and the plurality of second scan line connection portions 312 are the same.

[0259] By setting them in this way, the load due to the parasitic capacitance in the wiring (including the corresponding scanning lines and connecting parts) when the first control signal and the second control signal are transmitted from the first scanning line and the second scanning line to the data writing sub-circuit, respectively, is made the same, thereby further improving the synchronization of the first control signal and the second control signal.

[0260] For example, the sizes of the first data write transistor P1 and the second data write circuit N1 electrically connected to the first and second scan lines, respectively, are also the same, and therefore the loads imposed by the scan lines connected to them are also the same, which further improves the synchronization of the first and second control signals and thereby improves the anti-interference performance of the circuit.

[0261] For example, the first scanning line connecting portions 311 have the same length along the second direction D2 and the same line width. The second scanning line connecting portions 312 have the same length along the second direction D2 and the same line width.

[0262] For example, the first scan line 210 is electrically connected to the first scan line connection portion 311 by a via 231, and the second scan line 220 is connected to the second scan line connection portion 312 by a via 232, and the vias 231 and 232 are both located in the third insulating layer 203.

[0263] For example, as shown in FIG. 10B, a first control electrode group 191 consisting of first control electrodes of two subpixels adjacent in the first direction D1 is alternately arranged with a second control electrode group 192 of two adjacent subpixels, one by one, in the first direction D1.

[0264] 10B , the first scanning line connection portion 311 is electrically connected to the first control electrode group 191 or the first control electrode by a via 221, and the second scanning line connection portion 312 is electrically connected to the second control electrode group 192 or the second control electrode by a via 222. For example, the plurality of first scanning line connection portions 311 and the plurality of first control electrode groups 191 are electrically connected in one-to-one correspondence, and the plurality of second scanning line connection portions 312 and the plurality of second control electrode groups 192 are electrically connected in one-to-one correspondence.

[0265] For example, the first scanning line 210313 and the second scanning line 220 are located on the same side of the plurality of first control electrode groups 191 and the plurality of second control electrode groups 192, and the first scanning line 210 is closer to the plurality of first control electrode groups 191 and the second control electrode groups 192.

[0266] 10B , in the direction perpendicular to the base substrate, the first scan line 210 intersects with both the first scan line connection portion 311 and the second scan line connection portion 312, and the second scan line 220 intersects with both the first scan line connection portion 311 and the second scan line connection portion 312. The via 231 is located at the intersection of the first scan line 210 and the first scan line connection portion 311, and the via 232 is located at the intersection of the second scan line 220 and the second scan line connection portion 312.

[0267] For example, as shown in FIG. 10B, vias 231 and 232 are arranged alternately in the first direction D1 and staggered in the second direction, with via 231 being closer to the plurality of first control electrode groups 191 and second control electrode groups 192 than via 232.

[0268] 10B, one end of the second scan line connection portion 312 is electrically connected to the second scan line 220 through a via 232, and the other end is electrically connected to the second control electrode or second control electrode group to be connected through a via 222. The first scan line 210 passes between the via 232 and the via 222.

[0269] 10B , the first scan line connecting portion 311 includes a main body portion 321 and an extension portion 322, and the extension portion 322 is a portion of the main body portion 321 that extends away from the first scan line 20 along the second direction D2. The main body portion 321 is used to electrically connect the first scan line connecting portion 311 to the first control electrode or the first control electrode group, and is located between the first scan line 210 and the first control electrode or the first control electrode group connected thereto in the second direction D2, and the extension portion 322 is located on the side away from the first control electrode or the first control electrode group connected to the first scan line 210 in the second direction D2.

[0270] Here, the extension portion 322 is a virtual structure and therefore cannot actually perform the function of electrical connection. By installing the extension portion 322, the first scanning line connection portion 311 and the second scanning line connection portion 312 have the same length, the same area, and form the same capacitance load.

[0271] 10B, the via 221 is located in the middle of the first control electrode group 191, and the via 222 is located in the middle of the second control electrode group 192. The two first control electrodes in the first control electrode group 191 are axially symmetrical with respect to the first scanning line connection portion 311 connected to the first control electrode group and its extension, and the two second control electrodes in the second control electrode group 192 are axially symmetrical with respect to the second scanning line connection portion 312 connected to the second control electrode group and its extension.

[0272] As shown in FIG. 10A, the first scanning lines 210 connected to two adjacent pixel rows are symmetrical with respect to an axis of symmetry along the first direction D1, and the second scanning lines 220 connected to two adjacent pixel rows are symmetrical with respect to an axis of symmetry along the first direction D1.

[0273] The display substrate 10 includes a plurality of data lines extending along a second direction D2, which are connected to first terminals of data writing sub-circuits in the sub-pixels to provide data signals Vd.

[0274] FIG. 11A shows a schematic diagram of a display substrate according to some other embodiments of the present disclosure, and the diagram shows a schematic diagram of a data line of the display substrate according to at least one embodiment of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0275] 8A, the data lines are divided into a plurality of data line groups, each of which includes one first data line 241 and one second data line 242. The plurality of data line groups are electrically connected to a plurality of pixel columns in one-to-one correspondence to provide the data signal Vd. Each sub-pixel column is electrically connected to one first data line 241 and one second data line 242, respectively, i.e., the sub-pixels in one column are driven by two data lines.

[0276] 11A, each subpixel column is connected to two data lines, i.e., a first data line 241 and a second data line 242. For each column of subpixels, two subpixels located in adjacent n-th and n+1-th pixel rows form one pixel group 240 and share one data line, where n is an odd or even number greater than 0. For each column of subpixels, in the second direction D2, the N-th pixel group 240 is connected to the first data line 241, and the N+1-th pixel group 240 is connected to the second data line 242, where N is a natural number. That is, in the second direction D2, the pixel groups 240 are alternately connected to the first data line 241 and the second data line 242, with the odd-numbered pixel groups sharing one data line and the even-numbered pixel groups sharing the other data line.

[0277] By using two data lines to drive one sub-pixel column, the load on each data line can be reduced, thereby improving the driving capability of the data lines, reducing signal delay, and improving the display effect.

[0278] The display substrate according to the embodiment of the present disclosure has a symmetrical structure, so that the layout of the signal lines can be matched with the driving method of the data lines, thereby achieving the effect of design optimization.

[0279] 4A , for example, the first poles of two first data write transistors P1 in one pixel group 240 are connected to each other to form an integral structure (see region A1), and the first poles of two second data write transistors N1 are connected to each other to form an integral structure (see region A2). Therefore, in combination with the above-mentioned data line driving method, without providing connection vias for connecting to the data lines in the two transistors, respectively, the data lines can be electrically connected to the two first data write transistors P1 or the two second data write transistors N2 in the pixel group 240 by providing connection vias for connecting to the data lines in the first poles of the integral structure within a limited contact area. This not only saves processes, but also makes the layout design more compact and improves the resolution of the display substrate, even when limited by design rules.

[0280] FIG. 11B shows the connection structure of the data lines in two adjacent pixel groups 240. For clarity, only partial views where the first and second data lines are connected to the sub-pixels in each pixel group are selectively shown, and the partial views corresponding to the two pixel groups are connected to show the continuous relationship of the signal lines, with dashed lines indicating the boundary between the two pixel groups.

[0281] As shown in FIG. 11B, in the direction perpendicular to the base substrate, the first data line 241 overlaps the first data write transistor P1 and is electrically connected to the first poles of two adjacent first data write transistors P1 in one pixel row 240, and the second data line 242 overlaps the second data write transistor N1 and is electrically connected to the first poles of two adjacent second data write transistors N1 in one pixel group 240.

[0282] For example, as shown in FIG. 11B, in the direction perpendicular to the base substrate, the first data line 241 overlaps with the gate 160 of the first data write transistor P1, and the second data line 242 overlaps with the gate 170 of the second data write transistor N1. That is, both the first data line 241 and the second data line 242 pass through the pixel area, thereby improving space utilization without occupying additional pixel space.

[0283] 11C and 11D show cross-sectional views taken along lines II-II' and III-III' in FIG. 11B, respectively, which are aligned along the first direction D1. For clarity, the figures only show structures electrically connected to the data lines, and omit other structures. As shown in FIGS. 11C and 11D, the first data line 241 and the second data line 242 are located on the third conductive layer 303 and are electrically connected to corresponding first data line connection portions 244 on the second conductive layer 302 by vias 403 and 404 in the fourth insulating layer 204, respectively. In a direction perpendicular to the base substrate, the first data line connection portions 244 overlap the corresponding first data line 241 or second data line 242. The first data line connection portion 244 is electrically connected to the second data line connection portion 245 in the first conductive layer 301 by vias 233 and 234 in the third insulating layer 203, and the second data line connection portion 245 is electrically connected to the first pole 161 of the first data write transistor P1 and the first pole 171 of the second data write transistor N1 by vias 223 and 224 in the second insulating layer 202, respectively, thereby transmitting data signals to the transistors.

[0284] The first poles of two adjacent first data write transistors P1 and the first poles of two adjacent second data write transistors N1 in one pixel row are connected to form an integrated structure, and the second data line connection part 245 electrically connects the first pole of the first data write transistor P1 to the first pole of the second data write transistor N1 in one subpixel, so that the second data line connection part 245 electrically connects the first poles 161 of the two first data write transistors P1 to the first poles 171 of the two second data write transistors N1 in two subpixels adjacent to each other in the second direction D2 in one subpixel group, and is connected to the corresponding first data line 241 or second data line 242 by the corresponding first data line connection part 244. As can be seen, the first poles of the four transistors can be electrically connected to the data lines by only installing one via in the third insulating layer and one via in the fourth insulating layer, respectively, which greatly saves layout space and improves space utilization.

[0285] As shown in FIGS. 11B-11D, for example, the first data line 241 and the second data line 242 are symmetrically arranged on both sides of the second data line connecting portion 245.

[0286] 11C and 11D, the third conductive layer further includes a shielding electrode 341 located between the first data line 241 and the second data line 242, where the first data line 241 and the second data line 242 are symmetrically disposed on both sides of the second data line's shielding electrode 341. The shielding electrode 341 is disposed between the two data lines to perform a shielding function and prevent signals on the two data lines from interfering with each other. For example, the shielding electrode 341 is configured to receive a constant voltage, e.g., the shielding electrode 341 is configured to receive a second power supply voltage, to improve shielding capability.

[0287] For example, as shown in FIG. 4A, the first poles 161 of the first data writing transistors P1 of two adjacent subpixels 100 in the second direction D2 are connected to each other to form an integral structure, and the first poles 171 of the second data writing transistors N1 of two adjacent subpixels 100 in the second direction D2 are connected to each other to form an integral structure.

[0288] For example, the materials of the first to fourth conductive layers are metal materials such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials combining these metals. For example, the materials of the first to fourth conductive layers may be conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and aluminum zinc oxide (AZO).

[0289] For example, the materials of the first to sixth insulating layers are inorganic insulating layers, such as silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, silicon nitrides, silicon nitrogen oxides, or metal nitrogen oxides such as aluminum oxide and titanium nitride.

[0290] For example, the light emitting element 120 has a top emission structure, in which the first electrode 121 is reflective, while the second electrode 122 is transmissive or semi-transmissive. For example, the first electrode 121 is made of a high work function material, such as an ITO / Ag / ITO stacked structure, to serve as an anode, and the second electrode 122 is made of a low work function material, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material, to serve as a cathode.

[0291] At least one embodiment of the present disclosure further provides a display panel, any of which includes a display substrate 10. Note that the display substrate 10 according to at least one embodiment of the present disclosure may include a light emitting element 120, but may not include the light emitting element 120; that is, the light emitting element 120 can be formed in a panel factory after the display substrate 10 is completed. If the display substrate 10 itself does not include the light emitting element 120, the display panel according to the embodiment of the present disclosure further includes the light emitting element 120 in addition to the display substrate 10.

[0292] At least one embodiment of the present disclosure further provides a display device 40, which includes any one of the display substrates 10 or display panels described above, as shown in FIG. 12 , and the display device in this embodiment may be any product or component having a display function, such as a display, an OLED panel, an OLED television, electronic paper, a mobile phone, a tablet PC, a laptop, a digital photo frame, or a navigation system.

[0293] The above description is merely a specific embodiment of the present disclosure, but does not limit the scope of protection of the present disclosure, which should be governed by the claims.

Claims

1. A display substrate, a base substrate; and a plurality of sub-pixels on the base substrate, each sub-pixel including a pixel circuit, the pixel circuit including a data writing sub-circuit, a recording sub-circuit, and a driving sub-circuit; the data writing sub-circuit is electrically connected to a first terminal of the recording sub-circuit and configured to transmit a data signal to the first terminal of the recording sub-circuit in response to a control signal; the driving subcircuit includes a control electrode, a first electrode, and a second electrode, the control electrode of the driving subcircuit being electrically connected to a first terminal of the recording subcircuit, the first electrode of the driving subcircuit being configured to receive a first power supply voltage, and the driving subcircuit being configured to drive a light emitting element to emit light in response to a voltage at the first terminal of the recording subcircuit; the recording subcircuit includes a storage capacitor including a first capacitor electrode and a second capacitor electrode; the plurality of sub-pixels include a first sub-pixel, a second capacitor electrode of the first sub-pixel includes a first protrusion and a second protrusion, the first protrusion and the second protrusion protruding along a first direction.

2. The display substrate of claim 1 , wherein the plurality of sub-pixels further includes a second sub-pixel, a second capacitor electrode of the second sub-pixel includes a third protrusion, and the third protrusion extends along the first direction.

3. 2. The display substrate of claim 1, wherein the second capacitor electrode includes a first electrode portion and a second electrode portion spaced apart from each other in the first direction, and the first protrusion and the second protrusion are located on the first electrode portion of the second capacitor electrode.

4. the plurality of sub-pixels further includes a second sub-pixel adjacent to the first sub-pixel in the first direction, The display substrate of claim 3 , wherein the first electrode portions of the second capacitor electrodes of the first sub-pixel and the second sub-pixel are integrally connected to each other.

5. the pixel circuit further includes a resistor; a first terminal of the resistor electrically connected to a second electrode of the driving sub-circuit, and a second terminal of the resistor electrically connected to the light-emitting element; 4. The display substrate according to claim 3, wherein the resistor is insulated from the control electrode of the driving sub-circuit in the same layer, and the resistivity of the resistor is higher than the resistivity of the control electrode of the driving sub-circuit.

6. 6. The display substrate according to claim 5, wherein the materials of the resistor and the control electrode of the driving sub-circuit are both polycrystalline silicon materials.

7. The display substrate of claim 5 , wherein the first sub-pixel further includes a first connecting electrode, the first connecting electrode electrically connecting the first terminal of the resistor and the second electrode of the driving sub-circuit.

8. 8. The display substrate of claim 7, wherein the first connection electrode and the second capacitor electrode are spaced apart on the same layer, and the first electrode portion and the second electrode portion of the second capacitor electrode are located on both sides of the first connection electrode, respectively.

9. the storage capacitor further includes a third capacitor electrode; 2. The display substrate of claim 1, wherein in a direction perpendicular to the base substrate, the third capacitor electrode is located on a side of the first capacitor electrode away from the second capacitor electrode and is arranged so as to be electrically connected to the second capacitor electrode.

10. The display substrate of claim 9 , wherein the third capacitor electrode includes a first electrode protrusion protruding in the first direction and a second electrode protrusion protruding in a second direction intersecting the first direction.

11. The display substrate of claim 9 , wherein the third capacitor electrode of the storage capacitor is in the first region of the base substrate and overlaps with the first capacitor electrode in a direction perpendicular to the base substrate.

12. the third capacitor electrode includes an electrode region and a connection hole region, the electrode region and the first capacitor electrode overlap in a direction perpendicular to the base substrate, and the second capacitor electrode is electrically connected to the third capacitor electrode via the connection hole region; The display substrate of claim 9 , wherein the doping concentration of the contact hole region is higher than the doping concentration of the electrode region.

13. the first capacitor electrode includes a fourth protrusion and a fifth protrusion extending along a second direction; The display substrate of claim 1 , wherein the fourth protrusion is a control electrode of the driving sub-circuit, and the first direction intersects with the second direction.

14. further including a first power line extending along the first direction; 2. The display substrate of claim 1, wherein the first power supply line is configured to supply the first power supply voltage to the first sub-pixel, and the first power supply line and the second protrusion of the second capacitor electrode at least partially overlap in a direction perpendicular to the base substrate.

15. a second power line extending along the first direction; the second power supply line is configured to supply a second power supply voltage different from the first power supply voltage to the first sub-pixel; The display substrate according to claim 1 , wherein the second power line and the first protrusion of the second capacitor electrode at least partially overlap in a direction perpendicular to the base substrate.

16. the data write sub-circuit includes a first data write transistor, the drive sub-circuit includes a drive transistor, the first data write transistor is a P-type metal-oxide semiconductor field effect transistor, and the drive transistor is an N-type metal-oxide semiconductor field effect transistor; 2. The display substrate of claim 1, wherein the P-type first data write transistor and the N-type driving transistor are located on both sides of the storage capacitor in a direction parallel to a surface of the base substrate.

17. the first capacitor electrode and the second capacitor electrode are respectively a first terminal and a second terminal of the recording sub-circuit; 2. The display substrate according to claim 1, wherein the first sub-pixel further includes a second connection electrode, the second connection electrode being insulated from the second capacitor electrode and electrically connecting the first capacitor electrode to the data writing sub-circuit.

18. the second connection electrode includes a first portion extending along the first direction and a second portion extending along the second direction, the first portion and the second portion being integral with each other, and the first direction and the second direction being perpendicular to each other; 18. The display substrate of claim 17, wherein the first portion is electrically connected to the data writing sub-circuit, and the second portion is electrically connected to the first capacitor electrode.

19. The display substrate of claim 17 , wherein the data writing sub-circuit, the second connecting electrode, and the driving sub-circuit are arranged in order along a second direction, and the first direction and the second direction are perpendicular to each other.

20. A display device, A display device comprising: a display substrate according to any one of claims 1 to 19; and the light-emitting element located on the display substrate.

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