Display device

Abstract

To provide a display device capable of reducing parasitic capacitance generated between a circuit element and a light emitting element of an adjacent sub-pixel.SOLUTION: A display device comprises: first and second sub-pixels arranged adjacent to each other; a first light-emitting element arranged in the first sub-pixel; a second light-emitting element arranged in the second sub-pixel; a first driving transistor configured to supply a drive current to the first light-emitting element; a second driving transistor configured to supply a drive current to the second light-emitting element and disposed to at least partially overlap the first light-emitting element; and a first metal layer arranged between the second driving transistor and the first light-emitting element.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present specification relates to a display device. [Background technology]

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms, and various display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), quantum dot light emitting displays (QLEDs), and organic light emitting displays (OLEDs) are being used in recent years.

[0003] Discussion of the background art should not be considered prior art. Summary of the Invention [Problem to be solved by the invention]

[0004] A display device displays an image by having a plurality of sub-pixels between two substrates facing each other. A light-emitting element and a circuit element may be disposed in each of the plurality of sub-pixels. The light-emitting element and the circuit element may be disposed on different layers and may overlap in some areas. Parasitic capacitance may occur in the overlapping areas between the light-emitting element and the circuit element, which may increase or decrease the brightness of the sub-pixel, resulting in a failure to achieve the desired brightness.

[0005] In the present disclosure, when the area of ​​a sub-pixel is reduced to realize high resolution or high transmittance, a circuit element may overlap with a light emitting element of an adjacent sub-pixel, and a parasitic capacitance generated between a light emitting element and a circuit element of an adjacent sub-pixel may be reduced.

[0006] Another technical objective of the present specification is to provide a display device that can reduce greenhouse gas emissions that may be generated during the manufacturing process of a display device and can embody ESG (Environment / Social / Governance). [Means for solving the problem]

[0007] A display device according to one embodiment of the present specification includes a first sub-pixel and a second sub-pixel arranged adjacent to each other, a first light-emitting element provided in the first sub-pixel, a second light-emitting element provided in the second sub-pixel, a first driving transistor that supplies a driving current to the first light-emitting element, a second driving transistor that supplies a driving current to the second light-emitting element and is arranged so that at least a portion of the second driving transistor overlaps with the first light-emitting element, and a first metal layer arranged between the second driving transistor and the first light-emitting element.

[0008] A display device according to another embodiment of the present invention includes a display area including a transmissive area and a non-transmissive area, a first light emitting element and a second light emitting element arranged adjacent to each other in the non-transmissive area, a first circuit element arranged in the non-transmissive area for driving the first light emitting element, and a second circuit element arranged in the non-transmissive area for driving the second light emitting element, wherein the second circuit element at least partially overlaps with the first light emitting element.

[0009] The systems, methods, features, and advantages will become apparent to one of ordinary skill in the art from the accompanying figures and the following description.

[0010] The foregoing general description and the following detailed description are exemplary and are intended to aid in the understanding of the present specification.

[0011] The present specification can eliminate a first parasitic capacitance by disposing a first metal layer between a gate electrode of a driving transistor of a specific subpixel and an anode electrode of an adjacent subpixel, and can reduce a second parasitic capacitance by disposing a floating second metal layer between the first metal layer and the anode electrode of the adjacent subpixel.

[0012] In addition, the present invention may prevent significant fluctuations in the driving current supplied to the anode electrode of a specific subpixel even when an adjacent subpixel is driven, thereby preventing poor gradation due to parasitic capacitance.

[0013] In addition, the present invention can increase the capacitance of the capacitor by using a portion of the first metal layer as a capacitor electrode, and can improve the brightness of the sub-pixel as the capacitance of the capacitor increases.

[0014] Furthermore, the present invention can simultaneously form the first metal layer and the capacitor electrode, which eliminates the first parasitic capacitance, through a simple process, thereby optimizing the process and reducing production energy.

[0015] Additionally, the present invention can increase transparency by removing the insulating layer from within the transmissive regions.

[0016] This specification also reduces the product defect rate, thereby reducing manufacturing process costs, shortening manufacturing process time, and reducing production energy. This specification also reduces greenhouse gas emissions that may be generated during the manufacturing process, thereby achieving ESG (Environment / Social / Governance). [Brief explanation of the drawings]

[0017] The accompanying drawings are intended to aid in understanding the present specification and can be combined with each other. The objectives and features of the present specification will be more clearly understood from the accompanying drawings and the following description. [Figure 1] 1 is a perspective view schematically illustrating a display device according to an embodiment of the present specification; [Figure 2] 1 is a plan view schematically illustrating a display panel according to an embodiment of the present specification; [Figure 3]3 is a diagram schematically illustrating an embodiment of a pixel provided in region A of FIG. 2. FIG. [Figure 4] 4 is a circuit diagram showing an example of a circuit element of the sub-pixel shown in FIG. 3. FIG. [Figure 5] FIG. 2 is a diagram schematically illustrating an example in which pixel circuits are arranged in a circuit region. [Figure 6A] FIG. 10 is a diagram schematically illustrating an example in which a first metal layer is disposed in a circuit region. [Figure 6B] FIG. 10 is a diagram schematically illustrating an example in which a second metal layer is disposed in a circuit region. [Figure 7] FIG. 6C is a cross-sectional view showing an embodiment of II' in FIGS. 6A and 6B. [Figure 8] 10 is a cross-sectional view illustrating a parasitic capacitance that occurs between a pixel circuit and a light emitting element of an adjacent sub-pixel when a first metal layer and a second metal layer are not provided. FIG. [Figure 9] 10 is a circuit diagram illustrating a parasitic capacitance that occurs between a pixel circuit and a light emitting element of an adjacent sub-pixel when a first metal layer and a second metal layer are not provided. FIG. [Figure 10] 10 is a circuit diagram illustrating a parasitic capacitance that occurs between a pixel circuit and a light emitting element of an adjacent sub-pixel when a first metal layer and a second metal layer are provided. FIG. [Figure 11] FIG. 10 is a diagram schematically illustrating another example in which a first metal layer is disposed in a circuit region. [Figure 12] FIG. 10 is a diagram schematically illustrating an example in which a shield layer is disposed in a circuit region. [Figure 13] 3 is a diagram schematically illustrating another embodiment of a pixel provided in region A of FIG. 2. FIG. [Figure 14] 14 is a diagram schematically showing an example in which pixel circuits are arranged in the circuit region of FIG. 13. FIG. [Figure 15] 10A and 10B are diagrams illustrating an example in which the area of ​​a transmissive region is reduced by pixel circuit arrangement. [Figure 16A] 14 is a diagram schematically showing an example in which a first metal layer is arranged in the circuit region of FIG. 13. FIG. [Figure 16B] 14 is a diagram schematically showing an example in which a second metal layer is disposed in the circuit region of FIG. 13. FIG. [Figure 17] FIG. 16B is a cross-sectional view showing an embodiment of II-II' in FIGS. 16A and 16B. [Figure 18] 14 is a diagram schematically showing another example in which a first metal layer is disposed in the circuit region of FIG. 13. FIG. [Figure 19] 10 is a graph showing an increase rate of a driving current depending on a driving voltage of an adjacent sub-pixel when a first metal layer and a second metal layer are not provided. [Figure 20] 1 is a graph showing the increase rate of driving current depending on the driving voltage of adjacent subpixels when a first metal layer and a second metal layer are provided. In the above figures, the same reference numerals may refer to the same components unless otherwise specified. In the figures, the size of each component may be exaggerated for ease of understanding. DETAILED DESCRIPTION OF THE INVENTION

[0018] The advantages and features of the present specification and the methods for achieving them will be described in detail with the accompanying drawings.

[0019] The advantages and features of the present invention, and methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be implemented in various different forms. The present embodiments are merely provided to complete the disclosure of the present invention and to fully convey the scope of the specification to those skilled in the art.

[0020] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative only and are not intended to limit the scope of the present specification. The same reference numerals refer to the same components throughout this specification. In the description of this specification, if a specific description of related publicly known technology is deemed to unnecessarily obscure the gist of this specification, the detailed description will be omitted. When terms such as "comprise," "have," and "consist of" are used in this specification, other parts may be added unless "only" is used. When a component is expressed in the singular, the plural is also included unless otherwise explicitly stated.

[0021] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0022] When describing a location relationship, for example when describing the location of two parts using "above," "on top," "below," or "next to," one or more other parts may be located between the two parts, unless "immediately" or "directly" is used.

[0023] When describing a temporal relationship, for example, when a temporal precedence relationship is described using "after," "following," "after," or "before," it can also include cases where the relationship is not consecutive, unless "immediately" or "directly" is used.

[0024] Although terms such as "first," "second," "A," and "B" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may also be a second component within the technical spirit of this specification.

[0025] The term "at least one" should be understood to include all possible combinations of one or more related items. For example, "at least one of the first, second, and third items" can mean each of the first, second, and third items, as well as all possible combinations of two or more items among the first, second, and third items.

[0026] The features of the various embodiments of this specification may be partially or fully combined or combined with each other, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or in conjunction with each other.

[0027] Unless otherwise explained or defined, terms are used with the meaning commonly understood in the art.

[0028] In this specification, a transistor can be understood to be either an n-channel transistor (NMOS) or a p-channel transistor (PMOS). The transistor can be an oxide semiconductor transistor having an oxide semiconductor as an active layer, or a low-temperature polysilicon (LTPS) transistor having LTPS as an active layer.

[0029] Hereinafter, preferred examples of the display device according to the present specification will be described in detail with reference to the accompanying drawings. When assigning reference numerals to components in each drawing, identical components may be assigned the same numerals as far as possible even when they are displayed in different drawings. In addition, in the description of this specification, if a detailed description of related known configurations or functions is determined to obscure the gist of this specification, the detailed description may be omitted.

[0030] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0031] FIG. 1 is a perspective view schematically showing a display device according to an embodiment of the present specification, and FIG. 2 is a plan view schematically showing a display panel according to an embodiment of the present specification.

[0032] In the following description, the X axis indicates a direction parallel to the scan lines, the Y axis indicates a direction parallel to the data lines, and the Z axis indicates the height direction of the display device 100.

[0033] Although the display device 100 according to an embodiment of the present specification has been described as being implemented as an organic light emitting display (OLED), the embodiment of the present specification is not limited thereto. The display device 100 may also be implemented as a liquid crystal display (LCD), a quantum dot light emitting display (QLED), a micro LED display, or an electrophoresis display.

[0034] 1 and 2, a display device 100 according to an embodiment of the present disclosure includes a display panel 110, a source drive integrated circuit (hereinafter referred to as "IC") 210, a flexible film 220, a circuit board 230, and a timing control unit 240.

[0035] The display panel 110 includes a first substrate 111 and a second substrate 112 facing each other. The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film. The first substrate 111 and the second substrate 112 may be made of a transparent material. For example, the first substrate 111 or the second substrate 112 may include a flexible polymer film made of any one of polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile butadiene styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS).

[0036] The display panel 110 may be divided into a display area (DA) where pixels are formed to display an image and a non-display area (NDA) where no image is displayed. The non-display area (NDA) may be located adjacent to the display area (DA).

[0037] The display area (DA) may include a first signal line (SL1), a second signal line (SL2), and sub-pixels, and the non-display area (NDA) may include a pad area (PA) where pads are arranged, and at least one scan driver 205.

[0038] The first signal line (SL1) may extend in a first direction (e.g., the Y-axis direction) and may intersect with the second signal line (SL2) in the display area (DA). The second signal line (SL2) may extend in a second direction (e.g., the X-axis direction) in the display area (DA). Pixels are provided in the area where the first signal line (SL1) is provided or in the area where the first signal line (SL1) and the second signal line (SL2) intersect, and emit predetermined light to display an image. The first signal line (SL1) may include a gate line, and the second signal line (SL2) may include signal lines DL, VDDL, VSSL, and REFL, which will be described below.

[0039] A plurality of pads can be arranged in the pad area (PA). Since the size of the first substrate 111 is larger than the size of the second substrate 112, a portion of the first substrate 111 can be exposed and not covered by the second substrate 112. The exposed portion of the first substrate 111 that is not covered by the second substrate 112 can be provided with pads such as power supply pads and data pads.

[0040] The scan driver 205 is connected to the scan lines and supplies scan signals. The scan driver 205 may be formed in a gate driver in panel (GIP) manner in an outer non-display area (NDA) on one or both sides of the display area (DA) of the display panel 110. Alternatively, the scan driver 205 may be fabricated as a driver chip, mounted on a flexible film, and attached to the outer non-display area (NDA) on one or both sides of the display area (DA) of the display panel 110 using a tape automated bonding (TAB) manner.

[0041] The source drive IC 210 receives digital video data and a data control signal from the timing control unit 240. The source drive IC 210 converts the digital video data into an analog data voltage according to the data control signal and supplies it to the data line. When the source drive IC 210 is manufactured as a driving chip, it can be mounted on the flexible film 220 using a COF (chip on film) or COP (chip on plastic) method.

[0042] The flexible film 220 may have wiring formed thereon that connects the pads to the source drive ICs 210 and wiring that connects the pads to the wiring of the circuit board 230. The flexible film 220 is attached onto the pads using an anisotropic conducting film, thereby connecting the pads to the wiring of the flexible film 220.

[0043] The circuit board 230 may be attached to the flexible film 220. The circuit board 230 may have a plurality of circuits implemented as driving chips mounted thereon. For example, the timing control unit 240 may be mounted on the circuit board 230. The circuit board 230 may be a printed circuit board or a flexible printed circuit board.

[0044] The timing control unit 240 receives digital video data and timing signals from an external system board (not shown). Based on the timing signals, the timing control unit 240 generates scan control signals for controlling the operation timing of the scan driver and data control signals for controlling the source drive IC 210. The timing control unit 240 supplies the scan control signals to the scan driver 205 and the data control signals to the source drive IC 210.

[0045] FIG. 3 is a diagram schematically illustrating an example of a pixel provided in region A of FIG. 2, FIG. 4 is a circuit diagram illustrating an example of circuit elements of the subpixel shown in FIG. 3, and FIG. 5 is a diagram schematically illustrating an example of a pixel circuit arranged in a circuit region.

[0046] The display panel 110 according to an embodiment of the present disclosure may include a display area (DA) and a non-display area (NDA, FIG. 2). The display area (DA) may include pixels (P) to display an image.

[0047] 3 to 5, each pixel P includes a plurality of sub-pixels SP1, SP2, and SP3. The sub-pixels SP1, SP2, and SP3 are arranged in a matrix and emit predetermined light to display an image. The sub-pixels SP1, SP2, and SP3 include a plurality of row lines formed by the sub-pixels SP1, SP2, and SP3 arranged in a first direction (e.g., the X-axis direction) and a plurality of column lines formed by the sub-pixels SP1, SP2, and SP3 arranged in a second direction (e.g., the Y-axis direction).

[0048] Each of the sub-pixels (SP1, SP2, SP3) may be, but is not limited to, one of a first sub-pixel (SP1) emitting red light, a second sub-pixel (SP2) emitting green light, and a third sub-pixel (SP3) emitting blue light. The unit pixel (P) may include at least two sub-pixels (SP1, SP2, SP3). For example, as shown in FIG. 3, the unit pixel (P) may include a first sub-pixel (SP1), a second sub-pixel (SP2), and a third sub-pixel (SP3). The unit pixel (P) may further include a fourth sub-pixel emitting white light. The arrangement order and direction of the sub-pixels (SP1, SP2, SP3) may be variously changed.

[0049] Each of the sub-pixels (SP1, SP2, SP3) may include a light-emitting element and circuit elements. Specifically, as shown in FIG. 4, each of the sub-pixels (SP1, SP2, SP3) may include a circuit element having a 3T (Transistor) 1C (Capacitor) structure including a first switching transistor (SWT), a second switching transistor (SWT'), a driving transistor (DT), and a capacitor (Cst), and a light-emitting element (ED). Each of the sub-pixels (SP1, SP2, SP3) may further include a compensation circuit. In this case, the compensation circuit may have various structures such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, or 7T2C, and may include more or fewer transistors and capacitors.

[0050] Each of the transistors (DT, SWT, SWT') of the sub-pixels (SP1, SP2, SP3) includes a gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode are not fixed but can be changed depending on the direction of the voltage and current applied to the gate electrode. Therefore, one of the source electrode and the drain electrode can be referred to as a first electrode, and the other can be referred to as a second electrode. The transistors (DT, SWT, SWT') of the sub-pixels (SP1, SP2, SP3) can be made of at least one of polysilicon semiconductor, amorphous silicon semiconductor, and oxide semiconductor. The transistors (DT, SWT, SWT') can be P-type or N-type, or a mixture of P-type and N-type.

[0051] The first switching transistor (SWT) may serve to supply the data voltage (Vdata) supplied from the data line (DL) to the drive transistor (DT). Specifically, the first switching transistor (SWT) may charge the data voltage (Vdata) supplied from the data line (DL) to the capacitor (Cst). In this case, the first switching transistor (SWT) may have a gate electrode connected to the scan line (SCANL) and a first electrode connected to the data line (DL). In addition, the first switching transistor (SWT) may have a second electrode connected to one end of the capacitor (Cst), for example, the gate electrode of the drive transistor (DT).

[0052] The first switching transistor SWT can be turned on in response to a scan signal Scan applied via a scan line SCANL, and when the first switching transistor SWT is turned on, it can transfer a data voltage Vdata applied via a data line DL to one end of the capacitor Cst.

[0053] The second switching transistor (SWT') may serve to supply the reference voltage (Vref) supplied from the reference line (REFL) to the driving transistor (DT). Specifically, the second switching transistor (SWT') may have a gate electrode connected to the scan line (SCANL) and a first electrode connected to the reference line (REFL). In addition, the second switching transistor (SWT') may have a second electrode connected to a second electrode (e.g., a source electrode) of the driving transistor (DT) and the other end of the capacitor (Cst).

[0054] The second switching transistor (SWT') can be turned on in response to a scan signal (Scan) applied via a scan line (SCANL). When the second switching transistor (SWT') is turned on, it can transfer a reference voltage (Vref) applied via a reference line (REFL) to the other end of the capacitor (Cst). It can also apply the reference voltage (Vref) to the source electrode of the driving transistor (DT).

[0055] The capacitor Cst may serve to maintain the data voltage Vdata supplied to the drive transistor DT for one frame. Specifically, the capacitor Cst may have a first electrode connected to the gate electrode of the drive transistor DT and a second electrode connected to the source electrode of the drive transistor DT. The capacitor Cst may charge a drive voltage Vgs corresponding to the data voltage Vdata transmitted through the first switching transistor SWT and supply the charged drive voltage Vgs to the drive transistor DT.

[0056] The driving transistor (DT) may generate a driving current (Ids) from a first power supply (EVDD) supplied from a pixel power line (VDDL) and supply the driving current to an anode electrode of the light emitting element (ED). Specifically, the driving transistor (DT) may have a gate electrode connected to one end of the capacitor (Cst) and a first electrode connected to the pixel power line (VDDL). In addition, the driving transistor (DT) may have a second electrode (e.g., a source electrode) connected to the anode electrode of the light emitting element (ED).

[0057] The driving transistor (DT) can be turned on by the driving voltage (Vgs) charged in the capacitor (Cst). When the driving transistor (DT) is turned on, it can transfer the first power supply (EVDD) applied through the pixel power line (VDDL) to the anode electrode of the light emitting element (ED). The driving transistor (DT) can control the light emitting intensity of the light emitting element (ED) by controlling the driving current (Ids) according to the driving voltage (Vgs) charged in the capacitor (Cst).

[0058] The light emitting device (ED) may include an anode electrode connected to the driving transistor (DT), a cathode electrode supplied with a second power supply (EVSS) from a common power line (VSSL), and an emission layer between the anode and cathode electrodes. The anode electrode may be an independent electrode for each light emitting device, and the cathode electrode may be a common electrode shared by all light emitting devices. When a driving current (Ids) is supplied from the driving transistor (DT), electrons from the cathode electrode are injected into the emission layer, and holes from the anode electrode are injected into the emission layer. The electrons and holes are recombined in the emission layer, causing a fluorescent or phosphorescent material to emit light, thereby generating light with a brightness proportional to the current value of the driving current.

[0059] The light emitting element (ED) may have an anode electrode connected to the second electrode of the driving transistor (DT) and a cathode electrode connected to the common power line (VSSL). The light emitting element (ED) may emit light in response to the driving current (Ids) generated by the driving transistor (DT).

[0060] The plurality of sub-pixels (SP1, SP2, SP3) described above may include light-emitting areas (EA1, EA2, EA3) in which light-emitting elements (ED) are disposed and which emit light. To increase the aperture ratio, the display panel 110 may be arranged such that circuit elements (DT, SWT, SWT', Cst) and a plurality of signal lines (DL, VDDL, VSSL, REFL) overlap the light-emitting areas (EA1, EA2, EA3). As shown in FIG. 3 , the light-emitting areas (EA1, EA2, EA3) may overlap a signal line area (SLA) in which a plurality of signal lines (DL, VDDL, VSSL, REFL) are disposed and a circuit area (CA) in which circuit elements (DT, SWT, SWT', Cst) are disposed.

[0061] Here, the plurality of signal lines (DL, VDDL, VSSL, REFL) arranged in the signal line area (SLA) may include signal lines extending in the second direction (e.g., the Y-axis direction). As an example, the plurality of signal lines (DL, VDDL, VSSL, REFL) may include at least one of a plurality of data lines (DL), a reference line (REFL), a pixel power supply line (VDDL), and a common power supply line (VSSL) corresponding to each of the plurality of sub-pixels (SP1, SP2, SP3).

[0062] Each of the data lines (DL) may supply a data voltage to the sub-pixels (SP1, SP2, SP3). For example, the first data line (DL) may supply a first data voltage to the first driving transistor of the first sub-pixel (SP1), the second data line (DL) may supply a second data voltage to the second driving transistor of the second sub-pixel (SP2), and the third data line (DL) may supply a third data voltage to the third driving transistor of the third sub-pixel (SP3).

[0063] The reference line (REFL) can supply an initialization voltage (or a reference voltage) to the driving transistor (DT) of each of the sub-pixels (SP1, SP2, SP3) provided in the display area (DA).

[0064] The pixel power supply line (VDDL) can supply a first power supply to the driving transistor (DT) of each of the sub-pixels (SP1, SP2, SP3) provided in the display area (DA).

[0065] The common power supply line (VSSL) may supply a second power supply to the cathode electrodes of the sub-pixels (SP1, SP2, SP3) provided in the display area (DA). Here, the second power supply may be a common power supply commonly supplied to the sub-pixels (SP1, SP2, SP3).

[0066] A signal line area (SLA) can be formed by arranging the above-mentioned multiple signal lines (DL, VDDL, VSSL, REFL) on each of multiple column lines consisting of sub-pixels (SP1, SP2, SP3) arranged in the second direction (e.g., the Y-axis direction).

[0067] The circuit area (CA) may be disposed on one side of the signal line area (SLA) without overlapping with the signal line area (SLA). For example, in a display panel 110 according to an embodiment of the present specification, the circuit elements (DT, SWT, SWT', Cst) may be disposed together on one side of the signal line area (SLA). The circuit area (CA) may be disposed in an area on one side of the sub-pixels (SP1, SP2, SP3).

[0068] Specifically, the circuit element (CE) may include a first switching transistor (SWT), a second switching transistor (SWT'), a driving transistor (DT), and a capacitor (Cst), and may be provided for each of the sub-pixels (SP1, SP2, SP3). For example, the circuit element may include a first circuit element (CE1) connected to the first sub-pixel (SP1) to drive the first sub-pixel (SP1), a second circuit element (CE2) connected to the second sub-pixel (SP2) to drive the second sub-pixel (SP2), and a third circuit element (CE3) connected to the third sub-pixel (SP3) to drive the third sub-pixel (SP3).

[0069] The plurality of sub-pixels (SP1, SP2, SP3) may be arranged in a line along a second direction (e.g., the Y-axis direction) as shown in Figures 3 and 5. The circuit elements (CE1, CE2, CE3) for each of the plurality of sub-pixels (SP1, SP2, SP3) may be arranged in the second direction (e.g., the Y-axis direction) along one side edge region of each of the plurality of sub-pixels (SP1, SP2, SP3). Here, at least some of the circuit elements (CE1, CE2, CE3) may partially overlap with the adjacent sub-pixels (SP1, SP2, SP3) rather than with the corresponding sub-pixels (SP1, SP2, SP3).

[0070] For example, as shown in FIG. 5, the second sub-pixel (SP2) may include a second circuit element (CE2) including a second driving transistor (DT2) and a second capacitor (Cst2). The second driving transistor (DT2) of the second sub-pixel (SP2) may at least partially overlap with the adjacent first sub-pixel (SP1). The second driving transistor (DT2) of the second sub-pixel (SP2) may at least partially overlap with the first light-emitting element of the adjacent first sub-pixel (SP1). Furthermore, the second capacitor (Cst2) of the second sub-pixel (SP2) may at least partially overlap with the second light-emitting element of the corresponding second sub-pixel (SP2).

[0071] In a display panel 110 according to an embodiment of the present specification, the signal line area (SLA) and the circuit area (CA) are arranged so as not to overlap each other, thereby minimizing or reducing the area of ​​the area in which the multiple signal lines (DL, VDDL, VSSL, REFL) and circuit elements (CE1, CE2, CE3) are formed. When the circuit elements (CE1, CE2, CE3) are arranged between the multiple signal lines (DL, VDDL, VSSL, REFL) corresponding to one column line, the circuit elements (CE1, CE2, CE3) require space above, below, left, and right to ensure a minimum separation distance from the multiple signal lines (DL, VDDL, VSSL, REFL). This may increase the area of ​​the area in which the multiple signal lines (DL, VDDL, VSSL, REFL) and circuit elements (CE1, CE2, CE3) are formed.

[0072] The display panel 110 according to one embodiment of the present specification can minimize the space required to separate the circuit elements (CE1, CE2, CE3) from multiple signal lines (DL, VDDL, VSSL, REFL) by concentrating and arranging the circuit elements (CE1, CE2, CE3) on one side of the signal line area (SLA) corresponding to one column line.

[0073] Furthermore, the display panel 110 according to an embodiment of the present specification may arrange circuit elements (CE1, CE2, CE3) corresponding to each of the plurality of sub-pixels (SP1, SP2, SP3) in a second direction (e.g., the Y-axis direction) along one side edge regions of each of the plurality of sub-pixels (SP1, SP2, SP3). Here, some regions of the circuit elements (CE1, CE2, CE3) may be arranged to overlap the corresponding sub-pixels (SP1, SP2, SP3). Meanwhile, other regions of the circuit elements (CE1, CE2, CE3) may not be arranged to overlap the corresponding sub-pixels (SP1, SP2, SP3) but may extend to the adjacent sub-pixels (SP1, SP2, SP3) and overlap the adjacent sub-pixels (SP1, SP2, SP3).

[0074] As the resolution of the display panel 110 increases, the area of ​​each of the sub-pixels (SP1, SP2, SP3) decreases. However, each of the sub-pixels (SP1, SP2, SP3) must have a minimum area required to accommodate circuit elements (CE1, CE2, CE3) in one side region. This limits how much the area of ​​each of the sub-pixels (SP1, SP2, SP3) can be reduced, which can result in a limit to the resolution.

[0075] In the display panel 110 according to an embodiment of the present specification, the circuit elements (CE1, CE2, CE3) are not necessarily arranged within the area where the corresponding sub-pixels (SP1, SP2, SP3) are arranged, but may be arranged to partially overlap the area where the adjacent sub-pixels (SP1, SP2, SP3) are arranged. The display panel 110 according to an embodiment of the present specification can minimize the circuit area (CA) by efficiently arranging the circuit elements (CE1, CE2, CE3). As a result, the display panel 110 according to an embodiment of the present specification can increase the resolution while reducing the area of ​​each of the sub-pixels (SP1, SP2, SP3).

[0076] In the display panel 110 according to an embodiment of the present specification, some of the circuit elements (CE1, CE2, CE3) are not disposed in the regions where the corresponding sub-pixels (SP1, SP2, SP3) are formed, and some of the regions may overlap with the regions where the sub-pixels (SP1, SP2, SP3) are formed. The first to third sub-pixels (SP1, SP2, SP3) may have different areas. The first to third sub-pixels (SP1, SP2, SP3) may have different lifetimes depending on the material of the light-emitting layer that emits light. In this case, the light-emitting areas of the first to third sub-pixels (SP1, SP2, SP3) may be designed to be the same or different so that the first to third sub-pixels (SP1, SP2, SP3) have the same or substantially similar lifetimes.

[0077] At least one of the first to third sub-pixels (SP1, SP2, SP3) may have a relatively large area or a relatively small area compared to the other sub-pixels. The circuit elements (CE1, CE2, CE3) corresponding to the sub-pixels (SP1, SP2, SP3) having a relatively small area may be formed to at least partially overlap with the adjacent sub-pixels (SP1, SP2, SP3) if there is a surplus space between the adjacent sub-pixels (SP1, SP2, SP3).

[0078] For example, as shown in FIG. 5, the second subpixel (SP2) and the third subpixel (SP3) may have smaller areas than the first subpixel (SP1). Here, the first subpixel (SP1) may be a blue subpixel, and the second subpixel (SP2) and the third subpixel (SP3) may be red and green subpixels, respectively. For example, the red and green subpixels may have smaller areas than the blue subpixel. The second circuit element (CE2) corresponding to the second subpixel (SP2) may partially overlap the second subpixel (SP2), but may extend to the adjacent first subpixel (SP1) because the area of ​​the second subpixel (SP2) is small and the other portion does not overlap the second subpixel (SP2). For example, the second capacitor (Cst2) of the second circuit element (CE2) overlaps with the second sub-pixel (SP2), while the second driving transistor (DT2) of the second circuit element (CE2) can overlap with the first sub-pixel (SP1).

[0079] In this case, the second driving transistor (DT2) of the second circuit element (CE2) overlaps with the light emitting element of the first sub-pixel (SP1), and parasitic capacitance may occur between the light emitting element of the first sub-pixel (SP1) and the second driving transistor (DT2) of the second circuit element (CE2). The gate voltage of the second driving transistor (DT2) of the second circuit element (CE2) may increase due to the parasitic capacitance generated when the adjacent first sub-pixel (SP1) is driven, which may increase the luminance of the light emitting element of the second sub-pixel (SP2) connected to the second driving transistor (DT2). Gray scale defects may occur in the second sub-pixel (SP2).

[0080] In the display panel 110 according to one embodiment of the present specification, when a circuit element (CE) overlaps with an adjacent subpixel (SP1, SP2, SP3) rather than with the corresponding subpixel (SP1, SP2, SP3), a metal layer can be disposed between the circuit element (CE) and the light-emitting element of the adjacent subpixel (SP1, SP2, SP3) to reduce parasitic capacitance.

[0081] Hereinafter, with reference to FIGS. 6A to 10, a structure for reducing the parasitic capacitance generated when the circuit element (CE) overlaps with the adjacent sub-pixels (SP1, SP2, SP3) will be described in more detail.

[0082] Fig. 6A is a diagram illustrating an example in which a first metal layer is disposed in a circuit region, Fig. 6B is a diagram illustrating an example in which a second metal layer is disposed in a circuit region, Fig. 7 is a cross-sectional view showing an embodiment of I-I' in Fig. 6A and Fig. 6B, Fig. 8 is a cross-sectional view illustrating a parasitic capacitance generated between a pixel circuit and a light-emitting element of an adjacent sub-pixel when the first metal layer and the second metal layer are not provided, Fig. 9 is a circuit diagram illustrating a parasitic capacitance generated between a pixel circuit and a light-emitting element of an adjacent sub-pixel when the first metal layer and the second metal layer are not provided, and Fig. 10 is a circuit diagram illustrating a parasitic capacitance generated between a pixel circuit and a light-emitting element of an adjacent sub-pixel when the first metal layer and / or the second metal layer is provided.

[0083] 6A to 10, for convenience of explanation, a portion of the second circuit element (CE2) connected to the second sub-pixel (SP2) overlaps with the first sub-pixel (SP1), but this is not necessarily limited to this. The following description can be applied to all cases where a portion of a pixel circuit connected to one sub-pixel overlaps with another adjacent sub-pixel.

[0084] 5, 6A, 6B, and 7, the second sub-pixel SP2 may include a second circuit element CE2 including a second driving transistor DT2 and a second capacitor Cst2. The second driving transistor DT2 of the second sub-pixel SP2 may at least partially overlap with the first light-emitting element ED1 of the adjacent first sub-pixel SP1.

[0085] Specifically, a light-shielding layer (LS) may be provided on the first substrate 111. The light-shielding layer (LS) is provided in a region where the driving transistor (DT) is formed and can block external light from entering the active layer (ACT) of the driving transistor (DT). The light-shielding layer (LS) is provided in a region where the second driving transistor (DT2) is formed and can block external light from entering the active layer (ACT). The light-shielding layer (LS) may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0086] A buffer layer (BF) may be provided on the light-shielding layer (LS). The buffer layer (BF) protects the driving transistor (DT) from impurities such as hydrogen and moisture that may penetrate through the first substrate 111, which is susceptible to moisture permeation, and may have a single layer or multi-layer structure including an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or aluminum oxide (Al2O3).

[0087] A drive transistor (DT) can be disposed on the buffer layer (BF). The drive transistor (DT) can include an active layer (ACT) disposed on the buffer layer (BF), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE).

[0088] A gate insulating film (GI) may be provided between the active layer (ACT) and the gate electrode (GE). The gate insulating film (GI) may be patterned only in the region where the gate electrode (GE) is provided, as shown in FIG. 7, but is not limited to this. In another embodiment, the gate insulating film (GI) may be formed to cover the active layer (ACT).

[0089] An interlayer insulating layer (ILD) may be disposed between the gate electrode (GE) and the source electrode (SE) and drain electrode (DE). The source electrode (SE) and drain electrode (DE) of the second driving transistor (DT2) may be connected to the source region and drain region of the active layer (ACT), respectively, through first contact holes (CH1) penetrating the interlayer insulating layer (ILD).

[0090] In addition, one of the source electrode (SE) and drain electrode (DE) of the driving transistor (DT) may be connected to the light-shielding layer (LS) through a contact hole penetrating the interlayer insulating layer (ILD) and the buffer layer (BF). The light-shielding layer (LS) may be electrically connected to one of the source electrode (SE) and drain electrode (DE) of the driving transistor (DT2) and function as a floating gate. If the light-shielding layer (LS) is floating without being connected to other electrodes, the floating light-shielding layer (LS) may cause fluctuations in the threshold voltage of the driving transistor (DT). The display panel 110 according to an embodiment of the present specification can minimize or reduce fluctuations in the threshold voltage of the driving transistor (DT) by electrically connecting the light-shielding layer (LS) to one of the source electrode (SE) and drain electrode (DE) of the driving transistor (DT).

[0091] The active layer (ACT) can be formed of a silicon-based semiconductor material or an oxide-based semiconductor material, and the gate electrode (GE), source electrode (SE), and drain electrode (DE) can be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0092] The gate insulating film (GI) and interlayer insulating layer (ILD) may have a single layer or multi-layer structure including inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), and aluminum oxide (Al2O3).

[0093] A first insulating layer (PAS1) may be formed on the driving transistor (DT), and a second insulating layer (PAS2) may be formed on the first insulating layer (PAS1). The first insulating layer (PAS1) and the second insulating layer (PAS2) may have a single layer or multi-layer structure including an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or aluminum oxide (Al2O3).

[0094] A first metal layer (M1) may be provided between the first insulating layer (PAS1) and the second insulating layer (PAS2). The first metal layer (M1) may be disposed on the drive transistor (DT) and may be provided in a planar manner to cover the gate electrode (GE) of the drive transistor (DT). The first metal layer (M1) may be electrically connected to one of the source electrode (SE) and drain electrode (DE) of the drive transistor (DT). For example, the first metal layer (M1) may be electrically connected to the source electrode (SE) of the drive transistor (DT) through a second contact hole (CH2) penetrating the first insulating layer (PAS1).

[0095] A planarization layer (PLN) for flattening the steps caused by the drive transistors (DT) can be provided on the second insulating layer (PAS2). Such a planarization layer (PLN) can be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0096] A second metal layer (M2) may be provided between the second insulating layer (PAS2) and the planarization layer (PLN). The second metal layer (M2) may be disposed on the first metal layer (M1) and may be provided to planarly cover a portion of the first metal layer (M1). The second metal layer (M2) may be provided to cover a region where the first metal layer (M1) overlaps with the first sub-pixel (SP1). The second metal layer (M2) may be in a floating state, not electrically connected to any layer.

[0097] The first metal layer (M1) and the second metal layer (M2) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and ITO, or an alloy thereof, but are not limited thereto. For example, the first metal layer (M1) or the second metal layer (M2) may be made of an alloy of molybdenum (Mo) and titanium (Ti), or may be made of a laminated structure of an alloy of molybdenum (Mo) and titanium (Ti) and ITO.

[0098] A light emitting element (ED) including a first electrode 120, a light emitting layer 130, and a second electrode 140, and a bank (BN) may be provided on the planarization layer (PLN).

[0099] The first electrode 120 may be provided on the planarization layer (PLN) for each subpixel (SP1, SP2, SP3). The first electrode 120 may include one first electrode 121 disposed in the first subpixel (SP1) and another first electrode 122 disposed in the second subpixel (SP2). Although not shown, the first electrode 120 may include another first electrode disposed in the third subpixel (SP3). The first electrodes 121 and 122 provided for each subpixel (SP1, SP2, SP3) may be spaced apart from each other and electrically insulated.

[0100] The first electrode 120 may be electrically connected to the driving transistor (DT). For example, the first electrode 122 of the second sub-pixel (SP2) may be connected to the first metal layer (M1) through a third contact hole (CH3) that penetrates the planarization layer (PLN) and the second insulating layer (PAS2) as shown in FIG. 7. The first metal layer (M1) may be connected to one of the source electrode (SE) and the drain electrode (DE) of the driving transistor (DT) through a second contact hole (CH2) that penetrates the first insulating layer (PAS1). As a result, the first electrode 122 of the second sub-pixel (SP2) may be electrically connected to one of the source electrode (SE) and the drain electrode (DE) of the driving transistor (DT) through the first metal layer (M1).

[0101] The first electrode 120 may be formed of a metal material with high reflectivity, such as a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, a laminated structure of Ag alloy and ITO (ITO / Ag alloy / ITO), an MoTi alloy, or a laminated structure of MoTi alloy and ITO (ITO / MoTi alloy / ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), copper (Cu), etc. The MoTi alloy may be an alloy of molybdenum (Mo) and titanium (Ti). The first electrode 120 may be an anode electrode of a light emitting device (ED).

[0102] The bank (BN) may be provided on the planarization layer (PLN). The bank (BN) may also be provided between the first electrodes 121 and 122. The bank (BN) may be formed to cover the ends of each of the first electrodes 121 and 122 and expose a portion of each of the first electrodes 121 and 122. As a result, the bank (BN) can prevent or suppress the problem of current concentration at the ends of each of the first electrodes 121 and 122, which would result in a decrease in luminous efficiency.

[0103] The banks (BN) may define the light-emitting areas (EA) of each of the sub-pixels (SP1, SP2, SP3). The light-emitting areas (EA) of each of the sub-pixels (SP1, SP2, SP3) are regions where the first electrode 120, the light-emitting layer 130, and the second electrode 140 are stacked in order, and where holes from the first electrode 120 and electrons from the second electrode 140 combine with each other in the light-emitting layer 130 to emit light. In this case, the regions where the banks (BN) are formed do not emit light and become non-light-emitting areas (NEA), while the regions where the banks (BN) are not formed and the first electrode 120 is exposed become light-emitting areas (EA).

[0104] The bank (BN) can be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0105] The light-emitting layer 130 may be provided on the first electrode 120. The light-emitting layer 130 may include a hole transport layer, a light-emitting material layer, and an electron transport layer. In this case, when a voltage is applied to the first electrode 120 and the second electrode 140, holes and electrons move to the light-emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light-emitting layer to emit light.

[0106] In one embodiment, the light-emitting layer 130 may be a common layer formed in common to the sub-pixels (SP1, SP2, SP3), where the light-emitting layer may be a white light-emitting layer that emits white light.

[0107] In another embodiment, the light emitting layer 130 may have light emitting material layers formed separately for the sub-pixels SP1, SP2, and SP3. For example, a red light emitting layer that emits red light may be formed in the first sub-pixel SP1, a green light emitting layer that emits green light may be formed in the second sub-pixel SP2, and a blue light emitting layer that emits blue light may be formed in the third sub-pixel SP3.

[0108] The second electrode 140 may be provided on the light-emitting layer 130. The second electrode 140 may be a common layer formed in common to the sub-pixels (SP1, SP2, SP3) to apply the same voltage.

[0109] The second electrode 140 may be formed of a transparent conductive material (TCO) such as ITO or IZO, which can transmit light, or a semi-transmissive metal material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 140 is formed of a semi-transmissive metal material, the light output efficiency may be increased due to microcavities. Such a second electrode 140 may be a cathode electrode of the light emitting element (ED).

[0110] An encapsulation layer 150 may be provided on the light emitting element (ED). The encapsulation layer 150 may be formed on the second electrode 140 to cover the second electrode 140. The encapsulation layer 150 serves to prevent oxygen and moisture from penetrating into the light emitting layer 130 and the second electrode 140. For example, the encapsulation layer 150 may include at least one inorganic film and may further include at least one organic film. For example, the encapsulation layer 150 may have a structure in which at least one organic film is disposed between inorganic films.

[0111] A color filter (CF) may be provided on one surface of the second substrate 112 facing the first substrate 111. The color filter (CF) may be patterned for each sub-pixel (SP1, SP2, SP3).

[0112] Specifically, the color filter (CF) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (not shown). The first color filter (CF1) may be disposed to correspond to the light-emitting area (EA1) of the first sub-pixel (SP1) and may be a red color filter that transmits red light. The second color filter (CF2) may be disposed to correspond to the light-emitting area (EA2) of the second sub-pixel (SP2) and may be a green color filter that transmits green light. The third color filter (not shown) may be disposed to correspond to the light-emitting area (EA3) of the third sub-pixel (SP3) and may be a blue color filter that transmits blue light.

[0113] A black matrix (BM) may be provided between the color filters (CF). The black matrix (BM) is provided between the sub-pixels (SP1, SP2, SP3) to prevent or suppress color mixing between adjacent sub-pixels (SP1, SP2, SP3). In addition, the black matrix (BM) may prevent or suppress reflection of externally incident light on a plurality of signal lines, such as scan lines, data lines, pixel power lines, common power lines, and reference lines, provided between the sub-pixels (SP1, SP2, SP3).

[0114] Such a black matrix (BM) can contain a light-absorbing substance, for example, a black dye that absorbs all light in the visible light wavelength range.

[0115] A filler 160 may be provided between the first substrate 111 having the light emitting elements (ED) and the second substrate 112 having the color filters (CF) and black matrix (BM). Here, the filler 160 may be a thermosetting resin or a UV curable resin, and may be made of an organic material having adhesive properties. In one embodiment, the filler 160 may include a material that absorbs hydrogen.

[0116] The display panel 110 may be configured such that the circuit elements (CE1, CE2, CE3) corresponding to the sub-pixels (SP1, SP2, SP3) having relatively small areas at least partially overlap the adjacent sub-pixels (SP1, SP2, SP3) when there is a surplus space in the adjacent sub-pixels (SP1, SP2, SP3). For example, the display panel 110 may have a second sub-pixel (SP2) having a smaller area than the first sub-pixel (SP1). In this case, the display panel 110 may be configured such that the circuit element (CE2) of the second sub-pixel (SP2) at least partially overlaps the first sub-pixel (SP1) adjacent to the second sub-pixel (SP2). As shown in FIG. 8, the display panel 110 may be configured such that the second driving transistor (DT2) of the second sub-pixel (SP2) overlaps the first light-emitting element (ED1) of the first sub-pixel (SP1). In this case, a parasitic capacitance may occur between the second driving transistor DT2 of the second sub-pixel SP2 and the first light emitting element ED1 of the first sub-pixel SP1.

[0117] Specifically, a first parasitic capacitance (C_DTG) may occur between the gate electrode (GE) of the second drive transistor (DT2) and the anode electrode 121 of the first light-emitting element (ED1), as shown in Figures 8 and 9. When the first light-emitting element (ED1) is driven, the voltage of the gate electrode (GE) of the second drive transistor (DT2) may increase due to the first parasitic capacitance (C_DTG). The increase in the voltage of the gate electrode (GE) of the second drive transistor (DT2) may increase the drive voltage (Vgs) of the second capacitor (Cst2), and further increase the drive current (Ids) supplied to the anode electrode 122 of the second light-emitting element (ED2).

[0118] Furthermore, as shown in FIGS. 8 and 9, a second parasitic capacitance (C_DTS) may occur between the source electrode (SE) (or drain electrode) of the second driving transistor (DT2) and the anode electrode 121 of the first light-emitting element (ED1). When the first light-emitting element (ED1) is driven, the voltage of the source electrode (SE) (or drain electrode) of the second driving transistor (DT2) may increase due to the second parasitic capacitance (C_DTS). The increase in the voltage of the source electrode (SE) (or drain electrode) of the second driving transistor (DT2) may reduce the driving voltage (Vgs) of the second capacitor (Cst2), which may further reduce the driving current (Ids) supplied to the anode electrode 122 of the second light-emitting element (ED2).

[0119] In this manner, when the second driving transistor DT2 of the second sub-pixel SP2 overlaps with the first light-emitting element ED1 of the first sub-pixel SP1, the driving current Ids supplied to the anode electrode 122 of the second light-emitting element ED2 by the second driving transistor DT2 may fluctuate, increasing or decreasing, due to the first parasitic capacitance C_DTG and the second parasitic capacitance C_DTS when driving the first light-emitting element ED1. As a result, the luminance of the second sub-pixel SP2 may increase or decrease, and the second sub-pixel SP2 may not emit light at the desired luminance. For example, a grayscale defect may occur in the second sub-pixel SP2.

[0120] The display panel 110 according to one embodiment of the present specification can eliminate a first parasitic capacitance (C_DTG) that may occur between the gate electrode (GE) of the second driving transistor (DT2) and the anode electrode 121 of the first light-emitting element (ED1) using a first metal layer (M1).

[0121] Specifically, the display panel 110 according to an embodiment of the present disclosure may include a first metal layer (M1) disposed between the second driving transistor (DT2) of the second sub-pixel (SP2) and the first light-emitting element (ED1) of the first sub-pixel (SP1). The first metal layer (M1) may be disposed on at least one of the source electrode (SE) and the drain electrode (DE) of the second driving transistor (DT2) and electrically connected to the source electrode (SE) and the drain electrode (DE) of the second driving transistor (DT2). For example, as shown in FIG. 7, the first metal layer (M1) may be disposed on the source electrode (SE) of the second driving transistor (DT2) and electrically connected to the source electrode (SE) of the second driving transistor (DT2) through a second contact hole (CH2). Here, the first metal layer (M1) may be formed on the source electrode (SE) of the second driving transistor (DT2) to cover the source electrode (SE), as shown in FIG. 7. Although not shown in FIG. 7, the first metal layer (M1) can be formed so as to cover not only the source electrode (SE) but also the drain electrode (DE) of the second drive transistor (DT2).

[0122] The first metal layer (M1) may be disposed in an area where the second driving transistor (DT2) of the second sub-pixel (SP2) and the first light-emitting element (ED1) of the first sub-pixel (SP1) overlap. The first metal layer (M1) may extend from the area where the first light-emitting element (ED1) of the first sub-pixel (SP1) overlaps to an area where the second light-emitting element (ED2) of the second sub-pixel (SP2) is disposed, and may be electrically connected to the anode electrode 122 of the second light-emitting element (ED2). The anode electrode 122 of the second light-emitting element (ED2) may be electrically connected to the source electrode (SE) of the second driving transistor (DT2) via the first metal layer (M1).

[0123] The first metal layer (M1) may be formed to planarly cover the gate electrode (GE) of the second driving transistor (DT2) in an overlapping region between the second driving transistor (DT2) and the first light emitting element (ED1). The gate electrode (GE) of the second driving transistor (DT2) may be in a floating state during a period when a scan signal (Scan, see FIG. 4) is not applied. The floating gate electrode (GE) may be significantly affected by peripheral signals. Therefore, when a voltage is applied to the anode electrode 121 of the first light emitting element (ED1) disposed above the gate electrode (GE) of the second driving transistor (DT2), a voltage may also be applied to the floating gate electrode (GE) due to a first parasitic capacitance (C_DTG) generated between the anode electrode 121 of the first light emitting element (ED1) and the gate electrode (GE) of the second driving transistor (DT2), causing the voltage to increase. As a result, the second light emitting element (ED2), which is affected by the voltage applied to the gate electrode (GE), may also increase in brightness. Here, since a voltage is applied to the gate electrode (GE) which should be in a floating state, the second light emitting element (ED2) which is affected by the voltage of the gate electrode (GE) may exhibit a large increase in brightness relative to a desired brightness.

[0124] A display panel 110 according to an embodiment of the present disclosure may include a first metal layer (M1) disposed between a gate electrode (GE) of a second driving transistor (DT2) and an anode electrode 121 of a first light emitting element (ED1), and the first metal layer (M1) may be electrically connected to a source electrode (SE) or a drain electrode (DE) of the second driving transistor (DT2). The source electrode (SE) or the drain electrode (DE) of the second driving transistor (DT2) may be fixed to a driving voltage (Vgs) even during a period when a scan signal (Scan, see FIG. 4) is not applied. The first metal layer (M1) may be connected to the source electrode (SE) or the drain electrode (DE) of the second driving transistor (DT2) and fixed to a driving voltage (Vgs). In one embodiment of the present specification, the display panel 110 has a first metal layer (M1) to which a driving voltage (Vgs) that is not in a floating state is applied between the gate electrode (GE) of the second driving transistor (DT2) and the anode electrode 121 of the first light-emitting element (ED1), thereby eliminating a first parasitic capacitance (C_DTG) that may occur between the anode electrode 121 of the first light-emitting element (ED1) and the gate electrode (GE) of the second driving transistor (DT2), as shown in FIG. 10.

[0125] In addition, since the first metal layer (M1) is connected to the source electrode (SE) or the drain electrode (DE) of the second driving transistor (DT2), a second parasitic capacitance (C_DTS) may occur between the first metal layer (M1) and the anode electrode 121 of the first light emitting element (ED1). However, since the driving voltage (Vgs) is applied to the first metal layer (M1), it is less affected by peripheral signals than the gate electrode (GE). Therefore, even if a voltage is applied to the anode electrode 121 of the first light emitting element (ED1), the voltage fluctuation rate of the first metal layer (M1) may be small because the driving voltage (Vgs) is applied to the first metal layer (M1).

[0126] Parasitic capacitance may also occur between the gate electrode (GE) of the second driving transistor (DT2) and the first metal layer (M1). However, because the same signal or driving voltage (Vgs) for the subpixel (SP2) as the gate electrode (GE) of the second driving transistor (DT2) is applied to the first metal layer (M1), the voltage may not fluctuate when the gate electrode (GE) of the second driving transistor (DT2) is in a floating state. As a result, in the display panel 110 according to an embodiment of the present specification, even when a voltage is applied to the anode electrode 121 of the first light-emitting element (ED1), the voltage of the gate electrode (GE) of the second driving transistor (DT2) may not fluctuate significantly. Furthermore, the parasitic capacitance occurring between the gate electrode (GE) of the second driving transistor (DT2) and the first metal layer (M1) may become part of the second capacitor (Cst2), thereby reducing the area required to form the second capacitor (Cst2).

[0127] Furthermore, the display panel 110 according to an embodiment of the present specification may have a second metal layer (M2) disposed between the first metal layer (M1) and the first light emitting element (ED1) of the first sub-pixel (SP1). The second metal layer (M2) may be disposed in a region where the first metal layer (M1) and the first light emitting element (ED1) of the first sub-pixel (SP1) overlap. The second metal layer (M2) may be provided to planarly cover a region of the first metal layer (M1) that overlaps with the first light emitting element (ED1). The second metal layer (M2) may be in a floating state, not electrically connected to any layer.

[0128] The display panel 110 according to an embodiment of the present specification may have a floating second metal layer (M2) disposed between the first metal layer (M1) and the anode electrode 121 of the first light-emitting element (ED1). Here, the second metal layer (M2) may overlap the first sub-pixel (SP1) but not the second sub-pixel (SP2). The second metal layer (M2) may have a smaller formation area than an area in which the second driving transistor (DT2) is disposed. The display panel 110 according to an embodiment of the present specification may reduce the second parasitic capacitance (C_DTS) by using the second metal layer (M2).

[0129] The floating second metal layer (M2) cannot completely eliminate the parasitic capacitance between the first metal layer (M1) and the anode electrode 121 of the first light emitting element (ED1). Here, the parasitic capacitance may correspond to the second parasitic capacitance (C_DTS) because the first metal layer (M1) is electrically connected to the source electrode (SE) or the drain electrode (DE) of the second driving transistor (DT2).

[0130] However, because the source electrode (SE) or drain electrode (DE) of the second driving transistor (DT2) is fixed at the driving voltage (Vgs) even during periods when the scan signal (Scan, see FIG. 4) is not applied, the first metal layer (M1) is less affected by peripheral signals than the gate electrode (GE), which is in a floating state. When a voltage is applied to the anode electrode 121 of the first light emitting element (ED1) disposed on top of the source electrode (SE) or drain electrode (DE), the voltage of the source electrode (SE) or drain electrode (DE) of the second driving transistor (DT2), which is connected to the first metal layer (M1), may also increase due to the second parasitic capacitance (C_DTS). However, because the source electrode (SE) or drain electrode (DE) of the second driving transistor (DT2) is not in a floating state but is in a state where the driving voltage (Vgs) is applied, the voltage fluctuation rate of the source electrode (SE) or drain electrode (DE) may be smaller than that of the gate electrode (GE).

[0131] In addition, when a floating second metal layer (M2) is disposed between the first metal layer (M1) and the anode electrode 121 of the first light emitting element (ED1), a third parasitic capacitance may be generated between the first metal layer (M1) and the second metal layer (M2), and a fourth parasitic capacitance may be generated between the second metal layer (M2) and the anode electrode 121 of the first light emitting element (ED1). Here, the third parasitic capacitance and the fourth parasitic capacitance may be connected in series. A second parasitic capacitance (C_DTS) obtained by combining the third and fourth parasitic capacitances connected in series may be expressed as the reciprocal of the sum of the reciprocal of the third parasitic capacitance and the reciprocal of the fourth parasitic capacitance. When the second metal layer (M2) is present, the second parasitic capacitance (C_DTS) obtained by combining the third and fourth parasitic capacitances connected in series may be smaller than the second parasitic capacitance (C_DTS) that occurs between the first metal layer (M1) and the anode electrode 121 of the first light emitting element (ED1) when the second metal layer (M2) is not present. Therefore, the display panel 110 according to an embodiment of the present specification can reduce the second parasitic capacitance (C_DTS) by using the second metal layer (M2).

[0132] As a result, the display panel 110 according to one embodiment of the present specification can improve the gradation defect of the second sub-pixel (SP2) caused by driving the adjacent first sub-pixel (SP1) by eliminating the first parasitic capacitance (C_GTS) and reducing the second parasitic capacitance (C_DTS).

[0133] FIG. 11 is a diagram schematically showing another example in which a first metal layer is arranged in a circuit region, and FIG. 12 is a diagram schematically showing an example in which a shield layer is arranged in a circuit region.

[0134] The second circuit element (CE2) corresponding to the second sub-pixel (SP2) may include a second driving transistor (DT2), a second capacitor (Cst2), and at least one second switching transistor (SWT2, SWT2'). The second driving transistor (DT2) of the second sub-pixel (SP2) may at least partially overlap with the first light-emitting element (ED1) of the first sub-pixel (SP1), and the second capacitor (Cst2) and the at least one second switching transistor (SWT2, SWT2') of the second sub-pixel (SP2) may at least partially overlap with the second light-emitting element (ED2) of the second sub-pixel (SP2).

[0135] 11 and 12, the first metal layer M1 may extend from a region where the first light emitting element ED1 of the first sub-pixel SP1 is disposed to a region where the second light emitting element ED2 of the second sub-pixel SP2 is disposed, and may extend to a region where the second capacitor Cst2 of the second sub-pixel SP2 is formed.

[0136] The first metal layer M1 may be disposed in a region where the first light emitting element ED1 of the first sub-pixel SP1 is disposed, so as to overlap the gate electrode GE of the second driving transistor DT2. Here, the first metal layer M1 may serve to eliminate a first parasitic capacitance C_DTG between the gate electrode GE of the second driving transistor DT2 and the anode electrode 121 of the first light emitting element ED1.

[0137] In addition, the first metal layer (M1) may be disposed so as to overlap with the second capacitor (Cst2) in the region where the second light emitting element (ED2) of the second sub-pixel (SP2) is disposed. Here, the first metal layer (M1) may be configured as one capacitor electrode (CstE3) constituting the second capacitor (Cst2) in the region where it overlaps with the second capacitor (Cst2).

[0138] The second capacitor (Cst2) may include at least two capacitor electrodes. For example, the second capacitor (Cst2) may include a first capacitor electrode (CstE1), a second capacitor electrode (CstE2), and a third capacitor electrode (CstE3). The first capacitor electrode (CstE1) may be formed in the same layer as the light-shielding layer (LS) and made of the same material, and the second capacitor electrode (CstE2) may be formed in the same layer as the gate electrode (GE) and made of the same material. The third capacitor electrode (CstE3) may be formed in the same layer as the first metal layer (M1) and made of the same material. According to one embodiment of the present specification, for example, the first capacitor electrode (CstE1) may be connected to the light-shielding layer (LS), the second capacitor electrode (CstE2) may be connected to the gate electrode (GE), and the third capacitor electrode (CstE3) may be connected to the first metal layer (M1).

[0139] The display panel 110 according to one embodiment of the present specification can increase the capacitance of the second capacitor (Cst2) within a limited space by extending the first metal layer (M1) to the area where the second light-emitting element (ED2) of the second sub-pixel (SP2) is arranged to form a third capacitor electrode (CstE3).

[0140] In addition, the display panel 110 according to an embodiment of the present disclosure may simultaneously form the first metal layer M1, which eliminates the first parasitic capacitance C_DTG, and the third capacitor electrode CstE3 through a simple process, thereby enabling the display panel 110 according to an embodiment of the present disclosure to implement process optimization and reduce production energy.

[0141] In addition, the first metal layer (M1) may be disposed in a region where the second light emitting element (ED2) of the second sub-pixel (SP2) is disposed so as not to overlap at least one of the second switching transistors (SWT2, SWT2'). The first metal layer (M1) may be disposed in a planar manner and spaced a predetermined distance (S1) from at least one of the second switching transistors (SWT2, SWT2'), as shown in FIG.

[0142] As described above, the first metal layer (M1) may be electrically connected to the source electrode (SE) or drain electrode (DE) of the second driving transistor (DT2). Therefore, if the first metal layer (M1) overlaps the second switching transistors (SWT2, SWT2'), the second switching transistors (SWT2, SWT2') may be affected by a signal applied to the source electrode (SE) or drain electrode (DE) of the second driving transistor (DT2). This may cause characteristic abnormalities in the second switching transistors (SWT2, SWT2'), resulting in a black floating defect where the luminance increases when the second sub-pixel (SP2) is driven in black.

[0143] The display panel 110 according to an embodiment of the present disclosure may prevent or suppress a signal applied to the source electrode (SE) or the drain electrode (DE) of the second driving transistor (DT2) from affecting the at least one second switching transistor (SWT2, SWT2') by spacing the first metal layer (M1) and the at least one second switching transistor (SWT2, SWT2'). As a result, the display panel 110 according to an embodiment of the present disclosure may prevent or suppress a black floating defect.

[0144] As shown in FIG. 12, a display panel 110 according to an embodiment of the present specification further includes a shield layer (SD) disposed on at least one second switching transistor (SWT2, SWT2′) to more reliably block or prevent a signal applied to the source electrode (SE) or drain electrode (DE) of the second drive transistor (DT2) from affecting the at least one second switching transistor (SWT2, SWT2′). The shield layer (SD) may be provided in the same layer as the source electrode (SE) or drain electrode (DE) of the second drive transistor (DT2). The shield layer (SD) may be connected to the source region or drain region of the active layer (ACT′) of the at least one second switching transistor (SWT2, SWT2′) through a fourth contact hole (CH4) penetrating the interlayer insulating layer (ILD).

[0145] Fig. 13 is a diagram schematically showing another embodiment of the pixel provided in region A of Fig. 2, and Fig. 14 is a diagram schematically showing an example in which pixel circuits are arranged in the circuit region of Fig. 13. Fig. 15 is a diagram schematically showing an example in which the area of ​​the transmissive region is reduced by pixel circuit arrangement.

[0146] The display panel 110 shown in Figures 13 and 14 differs from the display panel 110 shown in Figures 3 to 12 in that it is provided with a transmissive area (TA). The following description will focus on the differences, and essentially the same content will be omitted or briefly described.

[0147] A display panel 110 according to another embodiment of the present disclosure may include a display area (DA) and a non-display area (NDA, FIG. 2). The display area (DA) may include a first area (NTA) in which a plurality of sub-pixels (SP1, SP2, SP3, SP4) are arranged, and a second area (TA) in which the plurality of sub-pixels (SP1, SP2, SP3, SP4) are not arranged, as shown in FIG. 13. The first area (NTA) may be a non-transmissive area that does not transmit most of the light incident from the outside. The second area (TA) may be a transmissive area that transmits most of the light incident from the outside. For example, the transmissive area (TA) is an area with a light transmittance greater than α%, and the non-transmissive area (NTA) is an area with a light transmittance less than β%, where α may be a value greater than β. In the display panel 110 according to another embodiment of the present disclosure, an object or background located behind the display panel 110 can be seen through the transmissive area (TA).

[0148] The non-transmissive area (NTA) includes a plurality of pixels (P), each of which may include light-emitting areas (EA1, EA2, EA3, EA4) and non-emitting areas provided between the light-emitting areas (EA1, EA2, EA3, EA4). Each pixel (P) may include at least two sub-pixels (SP). For example, each pixel (P) may include, but is not limited to, a first sub-pixel (SP1) that emits red light, a second sub-pixel (SP2) that emits green light, and a third sub-pixel (SP3) that emits blue light. Each pixel (P) may further include a fourth sub-pixel (SP4) that emits white light.

[0149] The non-transmitting area (NTA) may include a signal line area (SLA) in which a plurality of signal lines (DL, VDDL, VSSL, REFL) (see FIG. 4) are arranged, and a circuit area (CA) in which circuit elements (DT, SWT, SWT', Cst) (see FIG. 4) are arranged. Here, the plurality of signal lines (DL, VDDL, VSSL, REFL) arranged in the signal line area (SLA) may include signal lines extending in a second direction (e.g., the Y-axis direction).

[0150] In the display panel 110 according to another embodiment of the present specification, a transmissive area (TA) is provided in the display area (DA), thereby reducing the area of ​​the non-transmissive area (NTA) including the light-emitting areas (EA1, EA2, EA3, EA4). In the display panel 110 according to another embodiment of the present specification, a plurality of light-emitting elements, a plurality of signal lines, and a plurality of circuit elements must be provided in the narrow non-transmissive area (NTA), so the light-emitting elements have to be formed overlapping the plurality of signal lines and the plurality of circuit elements. Therefore, in the display panel 110 according to another embodiment of the present specification, a signal line area (SLA) in which a plurality of signal lines (DL, VDDL, VSSL, REFL) are arranged and a circuit area (CA) in which circuit elements (DT, SWT, SWT', Cst) are arranged can be arranged to overlap the light-emitting areas (EA1, EA2, EA3, EA4).

[0151] In addition, in a display panel 110 according to another embodiment of the present specification, the signal line area (SLA) and the circuit area (CA) may be arranged so as not to overlap each other. When the circuit elements (CE1, CE2, CE3) are arranged between the signal lines (DL, VDDL, VSSL, REFL), the circuit elements (CE1, CE2, CE3) require spaces above, below, left, and right to ensure a minimum separation distance from the signal lines (DL, VDDL, VSSL, REFL), which may increase the area of ​​the area in which the signal lines (DL, VDDL, VSSL, REFL) and the circuit elements (CE1, CE2, CE3) are formed.

[0152] A display panel 110 according to another embodiment of the present specification can minimize or reduce the space required to separate the circuit elements (CE1, CE2, CE3) from multiple signal lines (DL, VDDL, VSSL, REFL) by concentrating and arranging the circuit elements (CE1, CE2, CE3) on one side of the signal line area (SLA).

[0153] A display panel 110 according to another embodiment of the present specification may arrange circuit elements (CE1, CE2, CE3) corresponding to each of a plurality of sub-pixels (SP1, SP2, SP3, SP4) in a second direction (e.g., the Y-axis direction) along one side end region of each of the plurality of sub-pixels (SP1, SP2, SP3, SP4). Here, a display panel 110 according to another embodiment of the present specification may arrange only a portion of the circuit elements (CE1, CE2, CE3) to overlap with the corresponding sub-pixels (SP1, SP2, SP3, SP4), and arrange other portions to overlap with adjacent sub-pixels (SP1, SP2, SP3, SP4).

[0154] 14, the second circuit element (CE2) corresponding to the second subpixel (SP2) may partially overlap with the second subpixel (SP2), but may partially overlap with the adjacent first subpixel (SP1). For example, the second capacitor (Cst2) of the second circuit element (CE2) may overlap with the second subpixel (SP2), but the second driving transistor (DT2) of the second circuit element (CE2) may overlap with the first subpixel (SP1).

[0155] As a result, the display panel 110 according to another embodiment of the present specification can minimize or at least reduce the area of ​​the circuit region (CA). All of the circuit elements (CE1, CE2, CE3) can be arranged to overlap the corresponding sub-pixels (SP1, SP2, SP3, SP4). The first circuit element (CE1) for driving the first sub-pixel (SP1) can include a first driving transistor (DT1), a first capacitor (Cst1), and at least one first switching transistor (SWT1, SWT1'; see FIG. 4). The first driving transistor (DT1), the first capacitor (Cst1), and at least one first switching transistor (SWT1, SWT1'; see FIG. 4) included in the first circuit element (CE1) are all arranged in one side end region of the first sub-pixel (SP1) and can overlap the first light-emitting element of the first sub-pixel (SP1). In addition, the second circuit element CE2 for driving the second sub-pixel SP2 may include a second driving transistor DT2, a second capacitor Cst2, and at least one second switching transistor SWT2, SWT2', see FIG. 4. The second driving transistor DT2, the second capacitor Cst2, and at least one second switching transistor SWT2, SWT2', see FIG. 4, included in the second circuit element CE2, are all disposed in one side end region of the second sub-pixel SP2 and may overlap with the second light-emitting element of the second sub-pixel SP2.

[0156] In this case, the first sub-pixel (SP1) and the second sub-pixel (SP2) must have a minimum area required to arrange the first circuit element (CE1) and the second circuit element (CE2) in one side region. For this reason, there is a limit to how much the area of ​​each of the first sub-pixel (SP1) and the second sub-pixel (SP2) can be reduced, which may result in a limit to the light transmittance.

[0157] A display panel 110 according to another embodiment of the present specification may reduce the circuit area (CA) and increase the transmissive area (TA) in the pixel arrangement shown in Figure 15. A display panel 110 according to another embodiment of the present specification may arrange the circuit elements (CE1, CE2, CE3) within the minimum circuit area (CA). In this case, some of the circuit elements (CE1, CE2, CE3) may not be arranged in the area where the corresponding sub-pixels (SP1, SP2, SP3, SP4) are formed, and some of the areas may overlap with the area where the sub-pixels (SP1, SP2, SP3, SP4) are formed.

[0158] The subpixels (SP1, SP2, SP3, SP4) may have different areas. Each of the subpixels (SP1, SP2, SP3, SP4) may have different lifetimes depending on the material of the light-emitting layer that emits light. In such cases, the light-emitting areas of each of the subpixels (SP1, SP2, SP3, SP4) can be designed to be the same or different so that the subpixels (SP1, SP2, SP3, SP4) have the same or substantially similar lifetimes.

[0159] At least one of the sub-pixels (SP1, SP2, SP3, SP4) may have a relatively large area or a relatively small area compared to the other sub-pixels. The circuit elements (CE1, CE2, CE3) corresponding to the sub-pixels (SP1, SP2, SP3, SP4) having a relatively small area may be formed to at least partially overlap the adjacent sub-pixels (SP1, SP2, SP3, SP4) if there is a surplus space between the adjacent sub-pixels (SP1, SP2, SP3, SP4).

[0160] 14, the second sub-pixel (SP2) may have a smaller area than the first sub-pixel (SP1). The second circuit element (CE2) corresponding to the second sub-pixel (SP2) may be formed so that a portion thereof overlaps with the second sub-pixel (SP2) and another portion thereof overlaps with the adjacent first sub-pixel (SP1). For example, the second capacitor (Cst2) of the second circuit element (CE2) may overlap with the second sub-pixel (SP2), and the second driving transistor (DT2) of the second circuit element (CE2) may overlap with the first sub-pixel (SP1).

[0161] The display panel 110 according to another embodiment of the present disclosure may have a reduced area of ​​the circuit area (CA) and an increased area of ​​the transmissive area (TA), thereby improving light transmittance.

[0162] Fig. 16A is a diagram schematically illustrating an example in which a first metal layer is arranged in the circuit region of Fig. 13, Fig. 16B is a diagram schematically illustrating an example in which a second metal layer is arranged in the circuit region of Fig. 13, Fig. 17 is a cross-sectional view showing an embodiment of II-II' in Fig. 16A and Fig. 16B, and Fig. 18 is a diagram schematically illustrating another example in which a first metal layer is arranged in the circuit region of Fig. 13.

[0163] The display panel 110 shown in Figures 16A, 16B, and 17 is different from the display panel 110 shown in Figures 3 to 12 in that it has a transmissive area (TA). The following description will focus on the differences, and descriptions of substantially the same content will be omitted or simplified.

[0164] 16A, 16B, and 17, for convenience of explanation, a portion of the second circuit element CE2 connected to the second sub-pixel SP2 overlaps with the first sub-pixel SP1, but this is not necessarily limited to this. The following description can be applied to all cases where a portion of a pixel circuit connected to one sub-pixel overlaps with another adjacent sub-pixel.

[0165] 16A, 16B, and 17, the second sub-pixel SP2 may include a second circuit element CE2 including a second driving transistor DT2 and a second capacitor Cst2. The second driving transistor DT2 of the second sub-pixel SP2 may at least partially overlap with the first light-emitting element ED1 of the adjacent first sub-pixel SP1.

[0166] A light-shielding layer (LS) may be provided on the first substrate 111. The light-shielding layer (LS) is provided in the non-transmitting area (NTA) in an area where the driving transistor (DT) is formed, and can block external light from entering the active layer (ACT) of the driving transistor (DT).

[0167] A buffer layer (BF) may be provided on the light-shielding layer (LS). The buffer layer (BF) can protect the driving transistor (DT) from impurities such as hydrogen and moisture that may penetrate through the first substrate 111, which is susceptible to moisture permeation. As shown in FIG. 17, such a buffer layer (BF) may be provided in the non-transmissive area (NTA) as well as the transmissive area (TA), but is not limited to this. In other embodiments, the buffer layer (BF) may be provided only in the non-transmissive area (NTA) and not in the transmissive area (TA).

[0168] A drive transistor (DT) can be disposed on the buffer layer (BF), and the drive transistor (DT) can include an active layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE) disposed on the buffer layer (BF) in the non-transparent region (NTA).

[0169] A gate insulating film (GI) may be provided between the active layer (ACT) and the gate electrode (GE). An interlayer insulating layer (ILD) may be disposed between the gate electrode (GE) and the source electrode (SE) and drain electrode (DE).

[0170] A first insulating layer (PAS1) may be provided on the driving transistor (DT), and a second insulating layer (PAS2) may be provided on the first insulating layer (PAS1). The first insulating layer (PAS1) and the second insulating layer (PAS2) may be provided in the non-transmissive area (NTA) and not in at least a portion of the transmissive area (TA). For example, the first insulating layer (PAS1) and the second insulating layer (PAS2) may include an opening region overlapping at least a portion of the transmissive area (TA). The first insulating layer (PAS1) and the second insulating layer (PAS2) may induce light refraction as light passes through them, thereby reducing transparency. Therefore, in a display panel 110 according to another embodiment of the present specification, transparency can be improved by removing portions of the first insulating layer (PAS1) and the second insulating layer (PAS2) in the transmissive area (TA).

[0171] A first metal layer (M1) may be provided between the first insulating layer (PAS1) and the second insulating layer (PAS2). The first metal layer (M1) may be disposed on the drive transistor (DT) in the non-transmitting area (NTA). The first metal layer (M1) may be provided to cover the gate electrode (GE) of the drive transistor (DT) in a planar manner. The first metal layer (M1) may be electrically connected to one of the source electrode (SE) and the drain electrode (DE) of the drive transistor (DT).

[0172] A planarization layer (PLN) for planarizing steps caused by the drive transistors (DT) may be provided on the second insulating layer (PAS2). The planarization layer (PLN) may be provided in the non-transmissive area (NTA) and not in at least a portion of the transmissive area (TA). For example, the planarization layer (PLN) may include an opening area overlapping at least a portion of the transmissive area (TA). The planarization layer (PLN) may induce light refraction while transmitting light, thereby impairing transparency. Therefore, in a display panel 110 according to another embodiment of the present specification, transparency can be improved by removing a portion of the planarization layer (PLN) in the transmissive area (TA).

[0173] A second metal layer (M2) may be provided between the second insulating layer (PAS2) and the planarization layer (PLN). The second metal layer (M2) may be disposed on the first metal layer (M1) in the non-transmitting area (NTA). The second metal layer (M2) may be provided to cover a portion of the first metal layer (M1) in a planar manner. The second metal layer (M2) may be provided to cover an area where the first metal layer (M1) overlaps with the first sub-pixel (SP1). The second metal layer (M2) may be in a floating state, not electrically connected to any layer.

[0174] A light emitting element (ED) including a first electrode 120, a light emitting layer 130, and a second electrode 140, and a bank (BN) may be provided on the planarization layer (PLN).

[0175] The first electrode 120 is disposed on the planarization layer (PLN) in the non-transmitting region (NTA) and may be provided for each sub-pixel (SP1, SP2, SP3). The first electrode 120 may be electrically connected to one of the source electrode (SE) and drain electrode (DE) of the driving transistor (DT) via the first metal layer (M1). The first electrode 120 may be an anode electrode of the light-emitting element (ED).

[0176] The bank (BN) may be provided on the planarization layer (PLN) in the non-transparent area (NTA). The bank (BN) may be formed to cover the edge of each of the first electrodes 120 and expose a portion of each of the first electrodes 120.

[0177] The bank (BN) may be provided in the non-transmissive area (NTA) and may not be provided in at least a portion of the transmissive area (TA). For example, the bank (BN) may include an opening area overlapping at least a portion of the transmissive area (TA). The bank (BN) may cause light refraction as light passes through it, thereby impairing transparency. Therefore, in a display panel 110 according to another embodiment of the present disclosure, transparency can be improved by removing a portion of the bank (BN) in the transmissive area (TA).

[0178] The light-emitting layer 130 may be provided on the first electrode 120. The light-emitting layer 130 may include a hole transport layer, a light-emitting material layer, and an electron transport layer.

[0179] In one embodiment, the light-emitting layer 130 may be a common layer formed in common to the subpixels (SP1, SP2, SP3, and SP4). Here, the light-emitting layer 130 may be a white light-emitting layer that emits white light. In this case, the light-emitting layer 130 may be formed not only in the subpixels (SP1, SP2, SP3, and SP4) but also in the non-emitting areas (NEA) between the subpixels (SP1, SP2, SP3, and SP4). The light-emitting layer 130 may be formed continuously between the subpixels (SP1, SP2, SP3, and SP4) and the subpixels (SP1, SP2, SP3, and SP4). In addition, the light-emitting layer 130 may be provided not only in the non-transmitting areas (NTA) including the light-emitting areas (EA1, EA2, EA3, and EA4) and the non-emitting areas (NEA) but also in the transmissive areas (TA), but is not necessarily limited thereto. The light-emitting layer 130 can also be patterned into only non-transmitting areas (NTA), including light-emitting areas (EA1, EA2, EA3, EA4) and non-light-emitting areas (NEA).

[0180] In another embodiment, the light-emitting layer 130 may have light-emitting material layers formed separately for each sub-pixel (SP1, SP2, SP3, SP4). For example, a red light-emitting layer emitting red light may be formed in the first sub-pixel (SP1), a green light-emitting layer emitting green light may be formed in the second sub-pixel (SP2), and a blue light-emitting layer emitting blue light may be formed in the third sub-pixel (SP3). In this case, the light-emitting material layer of the light-emitting layer 130 may not be formed in the transmissive region (TA). However, the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL), excluding the light-emitting material layer, may be formed in common to the sub-pixels (SP1, SP2, SP3, SP4) and may also be formed in the transmissive region (TA).

[0181] The second electrode 140 may be provided on the light-emitting layer 130. The second electrode 140 may be a common layer formed in common to the subpixels (SP1, SP2, SP3, SP4). The second electrode 140 may be formed not only in the light-emitting areas (EA1, EA2, EA3, EA4) of the subpixels (SP1, SP2, SP3, SP4) but also in the non-light-emitting areas (NEA) between the subpixels (SP1, SP2, SP3, SP4). The second electrode 140 may be continuously formed between the subpixels (SP1, SP2, SP3, SP4) and the subpixels (SP1, SP2, SP3, SP4).

[0182] In addition, the second electrode 140 may be provided not only in the non-transmitting area (NTA) including the light-emitting areas (EA1, EA2, EA3, EA4) and the non-light-emitting area (NEA) but also in the transmissive area (TA), but is not necessarily limited thereto. The second electrode 140 may also be patterned only in the non-transmitting area (NTA) including the light-emitting areas (EA1, EA2, EA3, EA4) and the non-light-emitting area (NEA).

[0183] The light emitting element (ED) may be provided with an encapsulation layer 150. The encapsulation layer 150 may be formed on the second electrode 140 to cover the second electrode 140.

[0184] A color filter (CF) may be provided on one surface of the second substrate 112 facing the first substrate 111. The color filter (CF) may be patterned for each sub-pixel (SP1, SP2, SP3, SP4).

[0185] A black matrix (BM) may be provided between the color filters (CF) patterned for each sub-pixel (SP1, SP2, SP3, SP4). The black matrix (BM) is provided between the sub-pixels (SP1, SP2, SP3, SP4) to prevent or suppress color mixing between adjacent sub-pixels (SP1, SP2, SP3, SP4). In addition, the black matrix (BM) may prevent or suppress reflection of externally incident light on a plurality of signal lines provided between the sub-pixels (SP1, SP2, SP3, SP4).

[0186] In addition, the black matrix (BM) is provided between the transmissive region (TA) and the plurality of sub-pixels (SP1, SP2, SP3, SP4) and can prevent or suppress light emitted from each of the plurality of sub-pixels (SP1, SP2, SP3, SP4) from traveling into the transmissive region (TA). Thus, the black matrix (BM) can define the boundary between the transmissive region (TA) and the non-transmissive region (NTA). Specifically, the black matrix (BM) can define the boundary between the non-transmissive region (NTA) and the transmissive region (TA) between the emissive region (EA) and the transmissive region (TA). Here, in the region excluding the emissive region (EA), the region where the black matrix (BM) is formed can be the non-transmissive region (NTA), and the region where the black matrix (BM) is not formed can be the transmissive region (TA). For example, the region where the emissive region (EA) and the black matrix (BM) are formed can be the non-transmissive region (NTA), and the remaining region can be the transmissive region (TA).

[0187] A filler 160 may be provided between the first substrate 111 having the light emitting element (ED) and the second substrate 112 having the color filter (CF) and the black matrix (BM).

[0188] The display panel 110 according to another embodiment of this specification, like the display panel 110 shown in Figures 3 to 12, can eliminate the first parasitic capacitance (C_DTG) that may occur between the gate electrode (GE) of the second driving transistor (DT2) and the anode electrode 121 of the first light-emitting element (ED1) using a first metal layer (M1).

[0189] Specifically, a display panel 110 according to another embodiment of the present disclosure may have a first metal layer (M1) disposed between the second driving transistor (DT2) of the second sub-pixel (SP2) and the first light-emitting element (ED1) of the first sub-pixel (SP1). The first metal layer (M1) may be disposed on at least one of the source electrode (SE) and the drain electrode (DE) of the second driving transistor (DT2) and electrically connected to the source electrode (SE) and the drain electrode (DE) of the second driving transistor (DT2). For example, as shown in FIG. 17, the first metal layer (M1) may be disposed on the source electrode (SE) of the second driving transistor (DT2) and electrically connected to the source electrode (SE) of the second driving transistor (DT2) through a second contact hole (CH2).

[0190] The first metal layer (M1) may be disposed in an area where the second driving transistor (DT2) of the second sub-pixel (SP2) and the first light-emitting element (ED1) of the first sub-pixel (SP1) overlap. The first metal layer (M1) may extend from the area where the first light-emitting element (ED1) of the first sub-pixel (SP1) overlaps to an area where the second light-emitting element (ED2) of the second sub-pixel (SP2) is disposed, and may be electrically connected to the anode electrode 122 of the second light-emitting element (ED2). The anode electrode 122 of the second light-emitting element (ED2) may be electrically connected to the source electrode (SE) of the second driving transistor (DT2) through the first metal layer (M1). In this case, the first metal layer (M1) may also be referred to as an intermediate electrode that connects the source electrode (SE) of the second driving transistor (DT2) and the anode electrode 122 of the second light-emitting element (ED2) and reduces contact resistance therebetween.

[0191] Such a first metal layer (M1) can be formed in a planar manner in the area where the second driving transistor (DT2) and the first light-emitting element (ED1) overlap, so as to cover the gate electrode (GE) of the second driving transistor (DT2).

[0192] The display panel 110 according to another embodiment of the present disclosure may eliminate the first parasitic capacitance (C_DTG) by disposing a first metal layer (M1) between the gate electrode (GE) of the second driving transistor (DT2) and the anode electrode 121 of the first light emitting element (ED1) and electrically connecting the first metal layer (M1) to the source electrode (SE) or the drain electrode (DE) of the second driving transistor (DT2). As a result, the display panel 110 according to another embodiment of the present disclosure may prevent fluctuations in the voltage of the gate electrode (GE) of the second driving transistor (DT2) even when a voltage is applied to the anode electrode 121 of the first light emitting element (ED1).

[0193] Furthermore, a display panel 110 according to another embodiment of the present specification may have a second metal layer (M2) disposed between the first metal layer (M1) and the first light-emitting element (ED1) of the first sub-pixel (SP1), similar to the display panel 110 shown in FIGS. 3 to 12. The second metal layer (M2) may be disposed in a region where the first metal layer (M1) and the first light-emitting element (ED1) of the first sub-pixel (SP1) overlap. The second metal layer (M2) may be provided to cover a region of the first metal layer (M1) that overlaps with the first light-emitting element (ED1) in a planar manner. Such a second metal layer (M2) may be in a floating state, not electrically connected to any layer.

[0194] A display panel 110 according to another embodiment of the present specification may have a floating second metal layer (M2) disposed between the first metal layer (M1) and the anode electrode 121 of the first light-emitting element (ED1). Here, the second metal layer (M2) may overlap the second sub-pixel (SP2) but not the first sub-pixel (SP1). Also, the second metal layer (M2) may have a smaller formation area than an area in which the second driving transistor (DT2) is disposed. A display panel 110 according to another embodiment of the present specification may reduce the second parasitic capacitance (C_DTS) by using the second metal layer (M2).

[0195] Because the source electrode (SE) or drain electrode (DE) of the second driving transistor (DT2) is fixed to the driving voltage (Vgs) even during periods when a scan signal (Scan, see FIG. 4) is not applied, the first metal layer (M1) is less affected by peripheral signals than the gate electrode (GE), which is in a floating state. When a voltage is applied to the anode electrode 121 of the first light emitting element (ED1) disposed on top of the source electrode (SE) or drain electrode (DE), the voltage of the source electrode (SE) or drain electrode (DE) of the second driving transistor (DT2), which is connected to the first metal layer (M1), may also increase due to the second parasitic capacitance (C_DTS). However, because the source electrode (SE) or drain electrode (DE) of the second driving transistor (DT2) is not in a floating state but is in a state where the driving voltage (Vgs) is applied, the voltage fluctuation rate of the source electrode (SE) or drain electrode (DE) may be smaller than that of the gate electrode (GE). A display panel 110 according to another embodiment of the present specification can minimize or reduce voltage fluctuations of the source electrode (SE) of the second driving transistor (DT2) even when a voltage is applied to the anode electrode 121 of the first light-emitting element (ED1).

[0196] In addition, when a floating second metal layer (M2) is disposed between the first metal layer (M1) and the anode electrode 121 of the first light emitting element (ED1), a third parasitic capacitance may occur between the first metal layer (M1) and the second metal layer (M2), and a fourth parasitic capacitance may occur between the second metal layer (M2) and the anode electrode 121 of the first light emitting element (ED1). Here, the third parasitic capacitance and the fourth parasitic capacitance may be connected in series. A second parasitic capacitance (C_DTS) obtained by combining the third and fourth parasitic capacitances connected in series may appear as the reciprocal of the sum of the reciprocal of the third parasitic capacitance and the reciprocal of the fourth parasitic capacitance. When the second metal layer (M2) is present, the second parasitic capacitance (C_DTS) obtained by combining the third and fourth parasitic capacitances connected in series may be smaller than the second parasitic capacitance (C_DTS) that occurs between the first metal layer (M1) and the anode electrode 121 of the first light emitting element (ED1) when the second metal layer (M2) is not present. Therefore, the display panel 110 according to another embodiment of the present specification can reduce the second parasitic capacitance (C_DTS) by using the second metal layer (M2).

[0197] The display panel 110 according to another embodiment of the present specification can prevent or suppress an increase in luminance of the second sub-pixel (SP2) due to driving of the adjacent first sub-pixel (SP1), and can improve the gradation defect of the second sub-pixel (SP2).

[0198] Although each sub-pixel (SP1, SP2, SP3, SP4) is shown to include one light-emitting area (EA1, EA2, EA3, EA4) in FIGS. 3 to 17, this is not necessarily limited to this.

[0199] As shown in FIG. 18, each of the sub-pixels (SP1, SP2, SP3, SP4) may include a plurality of divided light-emitting regions (EA1, EA2, EA3, EA4). Specifically, the first light-emitting region (EA1) included in the first sub-pixel (SP1) may include a first divided light-emitting region (EA11) and a second divided light-emitting region (EA12) that are divided into two. The second light-emitting region (EA2) included in the second sub-pixel (SP2) may include a first divided light-emitting region (EA21) and a second divided light-emitting region (EA22) that are divided into two. The third light-emitting region (EA3) included in the third sub-pixel (SP3) may include a first divided light-emitting region (EA31) and a second divided light-emitting region (EA32) that are divided into two. The fourth light-emitting region EA4 included in the fourth sub-pixel SP4 may include a first divided light-emitting region EA41 and a second divided light-emitting region EA42.

[0200] In this case, the first electrode 120 may be composed of a plurality of first electrodes 120 in each of the plurality of sub-pixels (SP1, SP2, SP3, SP4). The first electrode 120 may include a first anode electrode and a second anode electrode. The first anode electrodes may be disposed in the first divided light-emitting regions (EA11, EA21, EA31, EA41), and the second anode electrodes may be disposed in the second divided light-emitting regions (EA12, EA22, EA32, EA42). The first anode electrodes and the second anode electrodes may be disposed spaced apart from each other in the same layer.

[0201] The first anode electrode and the second anode electrode may be electrically connected to each other via an anode connecting electrode, which may be electrically connected to the first anode electrode at one end and to the second anode electrode at the other end, thereby electrically connecting the first anode electrode and the second anode electrode.

[0202] For example, the first electrode 121 included in the first sub-pixel SP1 may include a first anode electrode 1211 disposed in the first divided light-emitting area EA11, a second anode electrode 1212 disposed in the second divided light-emitting area EA12, and an anode connecting electrode ACE1 electrically connecting the first anode electrode 1211 and the second anode electrode 1212. The anode connecting electrode ACE1 is electrically connected to the first anode electrode 1211 at one end and to the second anode electrode 1212 at the other end, thereby electrically connecting the first anode electrode 1211 and the second anode electrode 1212 included in the first sub-pixel SP1.

[0203] The first electrode 122 provided in the second sub-pixel (SP2) may include a first anode electrode 1221 disposed in the first divided light-emitting area (EA21), a second anode electrode 1222 disposed in the second divided light-emitting area (EA22), and an anode connecting electrode (ACE2) electrically connecting the first anode electrode 1221 and the second anode electrode 1222.

[0204] The anode connecting electrodes (ACE1, AEC2) provided in each of the first sub-pixel (SP1) and the second sub-pixel (SP2) may be provided in the same layer as the first metal layer (M1) and may be connected to the first metal layer (M1). The anode connecting electrode (ACE1) provided in the first sub-pixel (SP1) may be connected to the first metal layer (M1) connected to the first driving transistor (DT1), and the anode connecting electrode (ACE2) provided in the second sub-pixel (SP2) may be connected to the first metal layer (M1) connected to the second driving transistor (DT2).

[0205] 14, 16A, 17, and 18, the first metal layer M1 connected to the source electrode SE of the second driving transistor DT2 may extend from an overlapping region of the second driving transistor DT2 and the first light emitting element ED1 of the first sub-pixel SP1 to an overlapping region of the second light emitting element ED2 of the second sub-pixel SP2. The first metal layer M1 may extend to one side of the anode connecting electrode ACE2 of the second sub-pixel SP2 and be connected to the anode connecting electrode ACE2 of the second sub-pixel SP2. The first metal layer M1 may be electrically connected to the first anode electrode 1221 and the second anode electrode 1222 of the second sub-pixel SP2 via the anode connecting electrode ACE2.

[0206] Although the embodiments illustrated in FIGS. 5 to 18 describe cases in which a driving transistor of one subpixel overlaps with a light-emitting element of another adjacent subpixel, the present specification is not limited thereto. For example, such parasitic capacitance may also occur when another element, such as a capacitor or switching transistor, of one subpixel overlaps with a light-emitting element of another adjacent subpixel, which may also result in an undesirable increase or decrease in the brightness of the subpixel. Therefore, when another element, such as a capacitor or switching transistor of one subpixel overlaps with a light-emitting element of another adjacent subpixel, the first metal layer or the second metal layer may be arranged similarly to the embodiments illustrated in FIGS. 5 to 18 to eliminate or reduce such parasitic capacitance.

[0207] FIG. 19 is a graph showing the increase rate of driving current depending on the driving voltage of adjacent subpixels when the first metal layer and the second metal layer are not provided, and FIG. 20 is a graph showing the increase rate of driving current depending on the driving voltage of adjacent subpixels when the first metal layer and the second metal layer are provided.

[0208] The display panel 110 may be arranged such that the driving transistor of a specific subpixel overlaps the light emitting element of an adjacent subpixel, in which case parasitic capacitance may occur between the driving transistor of the specific subpixel and the light emitting element of the adjacent subpixel, particularly the anode electrode.

[0209] A first parasitic capacitance may occur between the gate electrode of the driving transistor of a specific subpixel and the anode electrode of an adjacent subpixel, and a second parasitic capacitance may occur between the source electrode of the driving transistor of the specific subpixel and the anode electrode of the adjacent subpixel.

[0210] When driving an adjacent subpixel, the driving transistor of the specific subpixel may increase the driving current supplied to the anode electrode of the specific subpixel due to the first and second parasitic capacitances as shown in Figure 19. As a result, the specific subpixel may not emit light at a desired brightness even though the brightness increases, resulting in poor gradation.

[0211] 19, the higher the driving voltage applied to the adjacent sub-pixel, the higher the driving current increase rate for the specific sub-pixel, which can be visually recognized by the user.

[0212] Meanwhile, the display panel 110 according to the present disclosure may eliminate the first parasitic capacitance using the first metal layer and reduce the second parasitic capacitance using the second metal layer. As a result, the display panel 110 according to the present disclosure may be able to prevent significant fluctuations in the driving current supplied to the anode electrode of a specific subpixel even when an adjacent subpixel is driven, as shown in Figure 20. For example, the display panel 110 according to the present disclosure may be able to prevent gray scale defects from occurring in the subpixels.

[0213] The display panel 110 according to the present disclosure can reduce manufacturing process costs and time as well as production energy consumption as a result of a reduced product defect rate. Furthermore, the display panel 110 according to the present disclosure can reduce greenhouse gas emissions that may be generated during the manufacturing process, thereby achieving ESG (Environment / Social / Governance).

[0214] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to such embodiments and can be variously modified within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are intended to explain rather than limit the technical concept of the present specification, and the scope of the technical concept of the present specification is not limited by such embodiments. Therefore, the embodiments described above should be understood to be illustrative in all respects and not limiting. [Explanation of symbols]

[0215] 100:Display device 110: Display panel 210: Source drive integrated circuit 220: Flexible film 230: Circuit board 240: Timing control section TA: Transparent area NTA: non-transparent area P: pixel SP1, SP2, SP3, SP4: sub-pixels VDDL: Pixel power supply line VSSL: Common power line DL: Data line REFL: Reference Line SCANL: Scan line DT: drive transistor Cst: Capacitor SWT: Switching transistor 120: 1st electrode 130: Light-emitting layer 140:Second electrode ED: Light-emitting element 150: Sealing layer 160: Filling material CF: Color filter BM: Black matrix BF: Buffer layer ILD: Interlayer insulating layer PAS1: First insulating layer PAS2: Second insulating layer PLN: Planarization layer BN: Bank M1: 1st metal layer M2: 2nd metal layer

Claims

1. a first sub-pixel and a second sub-pixel arranged adjacent to each other; a first light emitting element provided in the first sub-pixel; a second light emitting element provided in the second sub-pixel; a first drive transistor configured to provide a drive current to the first light emitting element; a second drive transistor configured to provide a drive current to the second light emitting element and to overlap at least a portion of the first light emitting element; and a first metal layer between the second driving transistor and the first light emitting element.

2. the second drive transistor includes an active layer, a gate electrode, a source electrode, and a drain electrode; The display device according to claim 1 , wherein the first metal layer covers a gate electrode of the second driving transistor arranged in a region where the second driving transistor and the first light-emitting element overlap each other in a plan view of the display device.

3. The display device of claim 2 , wherein the first metal layer is disposed on one of the source electrode and the drain electrode.

4. The display device of claim 2 , wherein the first metal layer is electrically connected to one of the source electrode and the drain electrode.

5. 5. The display device of claim 4, wherein the first metal layer extends from an area where the second driving transistor and the first light emitting element overlap to an area where the second light emitting element is disposed and is electrically connected to an anode electrode of the second light emitting element.

6. The display device of claim 1 , further comprising a second metal layer between the first metal layer and the first light-emitting element.

7. The display device according to claim 6 , wherein the second metal layer is in a floating state.

8. The display device according to claim 6 , wherein the second metal layer covers a region of the first metal layer that overlaps with the first light-emitting element in a plan view of the display device.

9. The display device of claim 1 , wherein the first sub-pixel and the second sub-pixel have different areas.

10. The display device of claim 1 , wherein the second driving transistor is disposed in one side end region of the first sub-pixel.

11. The display device of claim 1 , further comprising a capacitor disposed in an end region of the second sub-pixel.

12. the capacitor includes a first capacitor electrode and a second capacitor electrode; the second driving transistor includes an active layer, a gate electrode, a source electrode, and a drain electrode; The display device of claim 11 , wherein one of the first capacitor electrode and the second capacitor electrode is disposed in the same layer as the gate electrode of the second driving transistor and is connected to the gate electrode of the second driving transistor.

13. 13. The display device of claim 12, further comprising: a light-shielding layer disposed below the second driving transistor, electrically connected to one of the source electrode and the drain electrode of the second driving transistor, and connected to another of the first capacitor electrode and the second capacitor electrode.

14. the capacitor further includes a third capacitor electrode; The display device of claim 11 , wherein the third capacitor electrode is disposed on the same layer as the first metal layer and is connected to the first metal layer.

15. the second light-emitting element includes an anode electrode, a light-emitting layer, and a cathode electrode; the anode electrodes include a first anode electrode, a second anode electrode, and an anode connecting electrode electrically connecting the first anode electrode and the second anode electrode to each other; The display device according to claim 1 , wherein the anode linking electrode is disposed in the same layer as the first metal layer.

16. The display device of claim 15 , wherein the first metal layer extends from a region where the second driving transistor and the first light emitting element overlap to a region where the second light emitting element is disposed and is connected to the anode connecting electrode.

17. The display device of claim 1 , further comprising at least one switching transistor disposed in an end region on one side of the second sub-pixel.

18. The display device according to claim 17 , wherein the first metal layer is spaced apart from the at least one switching transistor in a plan view of the display device.

19. 20. The display device of claim 17, further comprising a shielding layer disposed over the at least one switching transistor.

20. a display area including transparent and non-transparent areas; a first light-emitting element and a second light-emitting element disposed adjacent to each other in the non-transmissive region; a first circuit element disposed in the non-transmissive region for driving the first light-emitting element; and a second circuit element disposed in the non-transmissive region for driving the second light-emitting element; At least a portion of the second circuit element overlaps with the first light-emitting element.

21. the non-transmissive region includes a signal line region in which a plurality of signal lines extending in a first direction are arranged, 21. The display device according to claim 20, wherein the first circuit element and the second circuit element are disposed between the signal line region and the transmissive region.

22. 21. The display device according to claim 20, wherein the second circuit element includes a drive transistor arranged in a region overlapping with the first light-emitting element, and a capacitor arranged in a region overlapping with the second light-emitting element.

23. The display device of claim 22 , further comprising a first metal layer disposed between the driving transistor of the second circuit element and the first light-emitting element.

24. the non-transmissive region includes a signal line region in which a plurality of signal lines extending in a first direction are arranged, The display device of claim 23 , wherein the first metal layer extends in the first direction between the signal line region and the transmissive region.

25. 24. The display device of claim 23, wherein the first metal layer extends from a region where the driving transistor of the second circuit element and the first light emitting element overlap to a region where the second light emitting element is disposed, and is electrically connected to the second light emitting element.

26. the drive transistor of the second circuit element includes an active layer, a gate electrode, a source electrode, and a drain electrode; The display device according to claim 23 , wherein the first metal layer covers the gate electrode of the driving transistor in a plan view of the display device.

27. 27. The display device of claim 26, wherein the first metal layer is electrically coupled to one of the source electrode and the drain electrode of the driving transistor.

28. The display device of claim 23 , further comprising a second metal layer disposed between the first metal layer and the first light-emitting element.

29. the non-transmissive region includes a signal line region in which a plurality of signal lines extending in a first direction are arranged, 29. The display device of claim 28, wherein the second metal layer is disposed between the signal line region and the transmissive region.

30. 29. The display device of claim 28, wherein the second metal layer is floating.

31. a first insulating layer between the first metal layer and the drive transistor of the second circuit element; a second insulating layer between the first metal layer and the second metal layer; and a planarization layer between the second metal layer and the first light emitting element; 30. The display of claim 28, wherein the first insulating layer, the second insulating layer, and the planarizing layer are removed from the transmissive area.

32. a first light-emitting element and a second light-emitting element disposed adjacent to each other; a first circuit element that drives the first light-emitting element; a second circuit element that drives the second light-emitting element and is arranged to at least partially overlap the first light-emitting element; and a first metal layer between the second circuit element and the first light emitting element.

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