Display device

Abstract

To provide a display device with a reduced bezel.SOLUTION: A display device according to an example embodiment of the present disclosure comprises: a substrate having a display area having a plurality of sub-pixels arranged therein and a non-display area surrounding the display area; a constant voltage line with a plurality of openings provided in the non-display area; and a plurality of electrostatic dischargers disposed in the plurality of openings.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present specification relates to a display device, and more particularly to a display device that can minimize a bezel. [Background technology]

[0002] As technology in modern society advances, display devices are being used in a variety of ways to provide information to users. Display devices range from electronic boards that simply transmit visual information in one direction to various electronic devices that require more advanced technology to confirm user input and provide information corresponding to the confirmed input.

[0003] Representative display devices include liquid crystal display devices (LCDs), field emission display devices (FEDs), electro-wetting display devices (EWDs), and organic light emitting display devices (OLEDs).

[0004] Among these, OLED displays are self-emitting displays that do not require a separate light source, unlike LCDs, and can be manufactured to be lightweight and thin. Furthermore, OLED displays are advantageous in terms of power consumption due to their low voltage operation, and also have excellent color realization, response speed, viewing angle, and contrast ratio (CR), making them expected to be used in a variety of fields. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by this specification is to provide a display device with a reduced bezel.

[0006] The problem to be solved by the present specification is to provide a display device that can minimize defects caused by static electricity while ensuring reliability.

[0007] However, the problems to be solved in this specification are not limited to those mentioned above, and other technical problems can be inferred from the following examples. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems, a display device according to one embodiment of the present specification includes a substrate including a display area in which a plurality of sub-pixels are arranged and a non-display area surrounding the display area, a constant voltage line arranged in the non-display area and including a plurality of openings, and a plurality of electrostatic discharge units arranged in the plurality of openings.

[0009] Further details of the embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0010] In this specification, an electrostatic discharge unit is disposed in a constant voltage line disposed in a power supply area of ​​a non-display area, thereby minimizing the bezel.

[0011] In the present specification, the electrostatic discharge part is disposed inside the sealing part, thereby ensuring reliability and minimizing defects caused by static electricity.

[0012] The effects of this specification are not limited to the examples given above, and various other effects are included within this specification. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram of a display device according to an embodiment of the present specification. [Figure 2] 1 is a plan view of a display device according to an embodiment of the present specification; [Figure 3] 1 is a cross-sectional view of a display area of ​​a display device according to an embodiment of the present specification. [Figure 4]1 is a schematic plan view of a display device according to an embodiment of the present specification; [Figure 5] 1 is a plan view showing a part of a non-display area of ​​a display device according to an embodiment of the present specification. [Figure 6] 1 is a circuit diagram illustrating an electrostatic discharge unit of a display device according to an embodiment of the present specification; [Figure 7] 1 is a plan view showing an electrostatic discharge unit of a display device according to an embodiment of the present specification; [Figure 8] FIG. 6 is a cross-sectional view taken along line AA' in FIG. 5. [Figure 9] FIG. 6 is a cross-sectional view taken along line BB' in FIG. 5. [Figure 10] FIG. 6 is a cross-sectional view taken along the line CC' in FIG. 5. [Figure 11] FIG. 10 is a plan view showing a part of a non-display area of ​​a display device according to another embodiment of the present specification. [Figure 12] FIG. 12 is a cross-sectional view taken along line DD' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0014] The advantages and features of the present invention, and methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely so that this disclosure will be complete and will fully convey the scope of the invention to those skilled in the art.

[0015] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are illustrative only and are not intended to limit the scope of this specification. The same reference symbols refer to the same elements throughout this specification. Furthermore, when describing this specification, if it is deemed that a detailed description of related prior art would unnecessarily obscure the gist of this specification, such a detailed description will be omitted. When using words such as "include," "have," and "be made" in this specification, other parts may be added unless "only" is used. When describing an element in the singular, this also includes the plural unless otherwise explicitly stated.

[0016] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0017] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0018] When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0019] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0020] Like reference numbers refer to like elements throughout the specification.

[0021] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0022] The features of the various embodiments of this specification may be partially or wholly combined or combined with each other, may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the other or may be implemented together in a related relationship.

[0023] In the following, the present specification will be described with reference to the drawings.

[0024] FIG. 1 is a block diagram of a display device according to an embodiment of the present specification.

[0025] Referring to FIG. 1, a display device 100 according to an embodiment of the present disclosure includes a display panel PN, a timing control unit TC, a data driver DD, and a gate driver GD.

[0026] A plurality of sub-pixels P can be arranged on the display panel PN to display an image.

[0027] The display panel PN may have a plurality of gate lines GL arranged in a first direction and a plurality of data lines DL arranged in a second direction different from the first direction. The plurality of gate lines GL and the plurality of data lines DL may cross each other, and the plurality of sub-pixels P may be arranged in a matrix form.

[0028] A plurality of sub-pixels P may be electrically connected to a plurality of gate lines GL and a plurality of data lines DL, and a gate signal and a data voltage may be applied to each sub-pixel P through the gate lines GL and the data lines DL. Each sub-pixel P may implement a gray scale according to the gate signal and the data voltage, and an image may be displayed on the display panel PN.

[0029] Each of the plurality of sub-pixels P may be one of a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. The red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may constitute one unit pixel to realize a color. The color expressed by the unit pixel may be determined by the emission ratio of the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel. Meanwhile, the white sub-pixel may be omitted from the unit sub-pixel. Each of the plurality of sub-pixels P may be connected to one data line DL and one gate line GL.

[0030] The timing controller TC can transmit the input image signals RGB received from the host system to the data driver DD.

[0031] The timing controller TC can generate control signals GCS and DCS for controlling the operation timing of the data driver DD and the gate driver GD using timing signals received together with the image data RGB.

[0032] In other words, the timing control unit TC receives the timing signal, outputs a gate control signal GCS to the gate driver GD, and outputs a data control signal DCS to the data driver DD.

[0033] The data driver DD receives a data control signal DCS and outputs a data voltage to the data line DL.

[0034] Specifically, the data driver DD generates a sampling signal according to a data control signal DCS, latches the image data RGB according to the sampling signal to convert it into a data voltage, and then supplies the data voltage to the data line DL in response to a Source Output Enable (SOE) signal.

[0035] The data driver DD may be connected to a bonding pad of the display panel PN in a chip-on-glass (COG) manner, or may be directly disposed on the display panel PN, or may be integrated into the display panel PN in some cases. The data driver DD may also be disposed in a chip-on-film (COF) manner.

[0036] The gate driver GD can generate a scan signal and an emission signal (or emission control signal) based on the gate control signal GCS. The gate driver GD can include a scan driver and an emission signal driver. The scan driver can generate scan signals in a row sequential manner to drive at least one scan line connected to each row of pixels and supply them to the scan lines. The emission signal driver can generate emission signals in a row sequential manner to drive at least one emission signal line connected to each row of pixels and supply them to the emission signal lines.

[0037] 2 is a schematic plan view of a display device according to an embodiment of the present disclosure. For ease of explanation, only a plurality of flexible films COF, a printed circuit board PCB, and a display panel PN are shown in FIG. 2 among various components of the display device 100.

[0038] Referring to FIG. 2, the display device 100 includes a plurality of flexible films COF, a printed circuit board PCB, and a display panel PN.

[0039] A plurality of flexible film COFs may be disposed at one end of the substrate 110. A plurality of flexible film COFs may be disposed on one side of the substrate 110. For example, if the substrate 110 has four sides, the flexible film COFs may be disposed at regular intervals in the longitudinal direction on one side.

[0040] The flexible film COFs are films in which various components are arranged on a flexible base film, and are used to supply signals to the sub-pixels and driving circuits, and can be electrically connected to the substrate 110. For example, the flexible film COFs can supply power supply voltages, gate control signals, data voltages, etc. to the sub-pixels and driving circuits.

[0041] Meanwhile, a driving IC such as a data driver IC may be disposed on each of the flexible film COFs. The driving IC is a component that processes data for displaying images and driving signals for processing the data. The driving IC may be disposed in a chip-on-glass (COG), chip-on-film (COF), tape carrier package (TCP), or other manner depending on the mounting method. For convenience of explanation, the driving IC is described as being mounted on each of the flexible film COFs in a chip-on-film manner, but this is not intended to be limiting. The driving IC may also be integrated with a timing controller and disposed on a single chip. Meanwhile, while FIG. 2 illustrates ten flexible film COFs, the number of the flexible film COFs may vary depending on the design, such as the size, of the display panel PN, and is not limited thereto.

[0042] A printed circuit board PCB is electrically connected to the multiple flexible film COFs. The printed circuit board PCB is a component that supplies signals to a driving IC. Various components may be arranged on the printed circuit board PCB to supply various signals, such as driving signals and data signals, to the driving IC. While FIG. 2 illustrates multiple flexible film COFs electrically connected to one printed circuit board PCB, this is not limited thereto, and multiple flexible film COFs may be electrically connected to multiple printed circuit boards PCBs, respectively.

[0043] The display panel PN is a panel for displaying images. The display panel PN may include various circuits, lines, and light-emitting elements arranged on a substrate. For example, the display panel PN may be divided into a display area AA and a non-display area NA.

[0044] The display area AA is an area for displaying an image, and may include a plurality of sub-pixels P arranged in row and column directions to display an image.

[0045] The non-display area NA surrounds the display area AA and is an area where no image is displayed. The non-display area NA is an area where various lines for driving the sub-pixels P arranged in the display area AA are arranged. The non-display area NA may also be referred to as a bezel area. A non-display area NA1 located on one side of the display panel PN may have a plurality of pads arranged therein. A plurality of flexible films COF may be connected to the pads. However, the components arranged in the non-display area NA of the display panel PN are not limited thereto, and various circuits and lines may also be arranged therein.

[0046] A constant voltage line VCL may be arranged in the non-display area NA to apply a constant voltage for driving the sub-pixels P. For example, the constant voltage line VCL may be arranged in a non-display area NA1 located on one side of the display panel PN to which the flexible films COF are connected. However, the present invention is not limited to this, and the constant voltage line VCL may be arranged throughout the non-display area NA along the periphery of the display area AA depending on the design. The constant voltage line VCL may be any one of a high potential power supply voltage line, a reference voltage line, and a low potential power supply voltage line.

[0047] The constant voltage line VCL may be provided with a plurality of electrostatic discharge units 130. The plurality of electrostatic discharge units 130 will be described in detail later.

[0048] The display panel PN may have a sealing unit 120 disposed thereon to cover the entire display area AA and at least a portion of the non-display area NA. The sealing unit 120 may protect components disposed in the display area AA and the non-display area NA from external moisture, oxygen, impact, etc. The area where the sealing unit 120 is disposed may be defined as a sealing area. The sealing unit 120 will be described in detail below.

[0049] The constant voltage line VCL may be disposed inside the sealing region. The constant voltage line VCL may be disposed within the sealing region in which the sealing unit 120 is disposed. The constant voltage line VCL may be disposed closer to the display area AA than an end of the sealing region. For example, one end of the constant voltage line VCL may be disposed closer to the display area AA, which is inside the end of the sealing unit 120, and the plurality of electrostatic discharge units 130 may also be disposed inside the end of the sealing unit 120. Therefore, the plurality of electrostatic discharge units 130 may prevent external moisture or oxygen from penetrating and causing damage to the electrostatic discharge units 130, such as total corrosion.

[0050] FIG. 3 is a cross-sectional view of a display area of ​​a display device according to an embodiment of the present specification.

[0051] For ease of explanation, FIG. 3 only shows the substrate 101, the driving transistor DT, the storage capacitor Cst, the buffer layer 102, the gate insulating layer 103, the first interlayer insulating layer 104, the second interlayer insulating layer 105, the passivation layer 106, the first planarization layer 107, the second planarization layer 108, the light-emitting element 110, the bank layer 109, and the encapsulation portion 120.

[0052] Referring to FIG. 3, a display device 100 according to one embodiment of the present specification includes a substrate 101, a driving transistor DT, a storage capacitor Cst, a buffer layer 102, a gate insulating layer 103, a first interlayer insulating layer 104, a second interlayer insulating layer 105, a passivation layer 106, a first planarization layer 107, a second planarization layer 108, a light-emitting element 110, a bank layer 109, and an encapsulation portion 120.

[0053] The substrate 101 can support various components of the display device 100. The substrate 101 can be made of a flexible plastic material. When the substrate 101 is made of a plastic material, it may be made of, for example, polyimide (PI). When the substrate 101 is made of polyimide (PI), moisture may penetrate the substrate 101 made of polyimide (PI) and reach the driving transistor DT or the light emitting element 110, which may degrade the performance of the display device 100.

[0054] The display device 100 according to an embodiment of the present specification may be configured with a double polyimide (PI) to prevent moisture permeation from deteriorating the performance of the display device 100. In addition, by forming an inorganic layer between the two polyimides (PI), moisture components can be prevented from penetrating through the lower polyimide (PI), thereby improving the reliability of product performance.

[0055] Furthermore, if an inorganic layer is formed between two polyimides (PI), charges stored in the underlying polyimide (PI) may form a back bias, affecting transistor T3. Therefore, a separate metal layer needs to be formed to block the charges stored in the polyimide (PI). However, in the display device 100 according to an embodiment of the present disclosure, by forming an inorganic layer between the two polyimides (PI), charges stored in the underlying polyimide (PI) can be blocked, improving product reliability. Furthermore, the process of forming a metal layer to block charges stored in the polyimide (PI) can be omitted, simplifying the process and reducing production costs.

[0056] For example, the substrate 101 of the display device 100 may include a first plastic substrate 101a, a second plastic substrate 101c, and an inorganic layer 101b formed between the first plastic substrate 101a and the second plastic substrate 101c. The first plastic substrate 101a may also be referred to as a first organic layer, and the second plastic substrate 101c may also be referred to as a second organic layer. The inorganic layer 101b may function to prevent the charge from affecting the driving transistor DT through the second plastic substrate 101c when the charge is applied to the first plastic substrate 101a. The inorganic layer 101b formed between the first plastic substrate 101a and the second plastic substrate 101c may also function to prevent moisture from penetrating through the first plastic substrate 101a. The inorganic layer 101b may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

[0057] A buffer layer 102 may be disposed on the substrate 101. The buffer layer 102 may be formed on the entire surface of the substrate 101. The buffer layer 102 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. The buffer layer 102 may improve adhesion between the substrate 101 and a layer formed on the buffer layer 102, and may serve to block alkaline components that may leak out from the substrate 101. The buffer layer 102 is not an essential component and may be omitted depending on the type and material of the substrate 101, the structure and type of transistor, etc.

[0058] The drive transistor DT may be disposed on the buffer layer 102. The drive transistor DT may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The active layer ACT of the drive transistor DT may be disposed on the buffer layer 102.

[0059] The active layer ACT may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0060] A gate insulating layer 103 may be disposed on the active layer ACT of the drive transistor DT. The gate insulating layer 103 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. Contact holes may be formed in the gate insulating layer 103 to connect the source electrode SE and drain electrode DE of the drive transistor DT to the active layer ACT of the drive transistor DT, respectively.

[0061] A gate electrode GE of the drive transistor DT may be disposed on the gate insulating layer 103. The gate electrode GE may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The gate electrode GE may be formed on the gate insulating layer 103 so as to overlap with the active layer ACT of the drive transistor DT.

[0062] A first interlayer insulating layer 104 may be disposed on the gate insulating layer 103 and the gate electrode GE. The first interlayer insulating layer 104 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof. A contact hole may be formed in the first interlayer insulating layer 104 to expose the active layer ACT of the drive transistor DT.

[0063] A second interlayer insulating layer 105 may be disposed on the first interlayer insulating layer 104. A contact hole for exposing the active layer ACT of the drive transistor DT may be formed in the second interlayer insulating layer 105. The second interlayer insulating layer 105 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof.

[0064] On the second interlayer insulating layer 105, the source electrode SE and the drain electrode DE of the driving transistor DT may be disposed.

[0065] The source electrode SE and drain electrode DE of the driving transistor DT can be connected to the active layer ACT of the driving transistor DT through contact holes formed in the gate insulating layer 103, the first interlayer insulating layer 104, and the second interlayer insulating layer 105. Therefore, the source electrode SE of the driving transistor DT can be connected to the active layer ACT through contact holes formed in the gate insulating layer 103, the first interlayer insulating layer 104, and the second interlayer insulating layer 105. And the drain electrode DE of the driving transistor DT can be connected to the active layer ACT through contact holes formed in the gate insulating layer 103, the first interlayer insulating layer 104, and the second interlayer insulating layer 105.

[0066] The storage capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2.

[0067] The first capacitor electrode Cst1 may be disposed on the gate insulating layer 103. The first capacitor electrode Cst1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first capacitor electrode Cst1 may be made of the same material as the gate electrode GE, but is not limited thereto.

[0068] The second capacitor electrode Cst2 may be disposed on the first interlayer insulating layer 104. The second capacitor electrode Cst2 may be disposed on the first interlayer insulating layer 104 so as to overlap the first capacitor electrode Cst1. For example, the second capacitor electrode Cst2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0069] A passivation layer 106 may be disposed on the source electrode SE and drain electrode DE of the drive transistor DT and the second interlayer insulating layer 105. The passivation layer 106 is an insulating layer that protects the underlying elements, and may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of these.

[0070] A first planarization layer 107 may be disposed on the passivation layer 106. The first planarization layer 107 may be a planarization layer for reducing steps in the underlying structure, and may be formed of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0071] A connection electrode CE may be disposed on the first planarization layer 107. The connection electrode CE may be electrically connected to the drain electrode DE of the driving transistor DT through a contact hole formed in the passivation layer 106 and the first planarization layer 107. The connection electrode CE may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0072] A second planarization layer 108 may be disposed on the connection electrode CE and the first planarization layer 107. The second planarization layer 108 is intended to reduce steps in the underlying structure and may be made of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0073] A light emitting element 110 may be disposed on the second planarization layer 108. The light emitting element 110 may include a first electrode 111, a light emitting structure 112, and a second electrode 113. The first electrode 111 is an anode electrode and may be electrically connected to the drain electrode DE of the driving transistor DT through a contact hole.

[0074] Since the display device 100 according to an embodiment of the present disclosure is a top-emission display device, the first electrode 111 may be formed as a multi-layer structure including a transparent conductive layer and a reflective layer with high reflectivity. The transparent conductive layer may be made of a material with a relatively high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opaque conductive layer may be formed as a single layer or a multi-layer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. For example, the first electrode 111 may be formed as a structure in which a transparent conductive layer, an opaque conductive layer, and another transparent conductive layer are sequentially stacked. However, the present disclosure is not limited thereto, and the first electrode 111 may also be formed as a structure in which a transparent conductive layer and an opaque conductive layer are sequentially stacked.

[0075] A bank layer 109a may be disposed on the first electrode 111 and the second planarization layer .

[0076] The bank layer 109a may have an opening region formed therein to expose the first electrode 111. The bank layer 109a may also be referred to as a pixel defining layer because the opening region may define a light-emitting region of the display device 100. For example, the bank layer 109a may be formed of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0077] Spacers 109b may further be disposed on the bank layer 109a.

[0078] The spacers 109b may serve to support a mask when the mask is aligned on the bank layer 109a in a process for depositing the first electrode 111. The spacers 109b may be formed integrally with the bank layer 109a. For example, the spacers 109b may be formed of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0079] The light emitting structure 112 may be disposed on the first electrode 111. The light emitting structure 112 may include a material capable of emitting light of a specific color. For example, the light emitting structure 112 may include a light emitting material capable of emitting any one of red, green, and blue light. Specifically, the light emitting structure 112 may include at least one layer selected from a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). Some components of the light emitting structure 112 may be omitted depending on the structure and characteristics of the display device 100.

[0080] A second electrode 113 may be further disposed on the light emitting structure 112. The second electrode 113 is a cathode electrode and may be disposed on the light emitting structure 112 to face the first electrode 111 across the light emitting structure 112. The second electrode 113 supplies electrons to the light emitting structure 112. For example, the second electrode 113 may be made of a conductive material with a low work function. When the display device 100 is a top emission display device, the second electrode 113 may be made of a transparent conductive oxide such as indium tin oxide or indium zinc oxide, or a transparent conductive material such as ytterbium (Yb), but is not limited thereto.

[0081] A sealing portion 120 for suppressing moisture penetration may further be disposed on the second electrode 113 .

[0082] The encapsulating portion 120 may include a first encapsulating layer 121 , a second encapsulating layer 122 , and a third encapsulating layer 123 .

[0083] The first encapsulation layer 121 may be disposed on the second electrode 113. The first encapsulation layer 121 may be formed of a transparent inorganic material that has an excellent effect of blocking moisture penetration into the light emitting element 110 and that can be deposited at low temperatures. For example, the first encapsulation layer 121 may be made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0084] The second encapsulation layer 122 may be disposed on the first encapsulation layer 121. The second encapsulation layer 122 is an organic layer that can cover foreign matter that may occur during the manufacturing process and compensate for unevenness caused by the foreign matter. Foreign matter that occurs during the manufacturing process may cause defects in the light emitting device 110 and may also cause cracks in inorganic layers such as the first encapsulation layer 121 or the third encapsulation layer 123. Therefore, the second encapsulation layer 122 may cover cracks caused by the foreign matter or compensate for unevenness caused by the foreign matter. The second encapsulation layer 122 may also serve to flatten the surface of the light emitting device 110. The second encapsulation layer 122 may be made of an organic material. For example, the second encapsulation layer 122 may be made of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0085] The third encapsulation layer 123 may be disposed on the second encapsulation layer 122. The third encapsulation layer 123 may be formed of a transparent inorganic material that has an excellent effect of blocking moisture penetration into the light emitting element 130 and that can be deposited at low temperatures. For example, the third encapsulation layer 123 may be made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0086] 4 is a plan view showing a portion of a display area and a portion of a non-display area of ​​a display device according to an embodiment of the present specification. For convenience of explanation, only a portion of the display area AA is shown in FIG. 4, and only the gate signal line GSL, the reference voltage line VRL, the high potential power supply voltage line VDDL, the low potential power supply voltage line VSSL, the first electrostatic discharge unit 131, the second electrostatic discharge unit 132, and the opening 140 are shown in the non-display area NA.

[0087] Referring to FIG. 4, a plurality of pixel blocks PB and a plurality of gate blocks GB can be arranged in the display area AA.

[0088] The pixel blocks PB are regions in which the sub-pixels P are arranged, and may be arranged in the column and row directions in the display area AA. For example, the pixel blocks PB may include red sub-pixels, green sub-pixels, and blue sub-pixels.

[0089] The gate blocks GB are regions into which the gate drivers GD are divided and arranged, and may be arranged in the column direction in the display area AA. The gate blocks GB may be arranged alongside the pixel blocks PB arranged in the row direction in the display area AA. The gate blocks GB may be arranged between the pixel blocks PB arranged in the row direction in the display area AA. For example, one gate driver GD may be divided into three gate blocks GB, but this is not limited thereto.

[0090] 4 and 5, the non-display area NA may include a gate signal line GSL, a reference voltage line VRL, a high potential power supply voltage line VDDL, and a low potential power supply voltage line VSSL.

[0091] The gate signal lines GSL may transmit gate driving signals to the gate blocks GB. For example, the gate signal lines GSL may include a clock signal line for transmitting a clock signal, a gate high voltage line for transmitting a gate high voltage, and a gate low voltage line for transmitting a gate low voltage. For example, the gate signal lines GSL may be disposed in a non-display area NA1 located on one side of the display panel PN to which the flexible films COF are connected in the non-display area NA.

[0092] The reference voltage line VRL may supply a reference voltage to the plurality of subpixels P. For example, the reference voltage line VRL may supply a reference voltage for operating transistors constituting the plurality of subpixels P. For example, the reference voltage line VRL may be disposed in a non-display area NA1 located on one side of the display panel PN to which the plurality of flexible films COF are connected in the non-display area NA.

[0093] The high potential power supply voltage line VDDL may supply a high potential power supply voltage to the plurality of sub-pixels P. For example, the high potential power supply voltage line VDDL may supply a driving voltage for causing light emitting elements included in the plurality of sub-pixels P to emit light. For example, the high potential power supply voltage line VDDL may be disposed in a non-display area NA1 located on one side of the display panel PN to which the plurality of flexible film COFs are connected in the non-display area NA. For example, the high potential power supply voltage line VDDL may be connected to the flexible film COFs.

[0094] The low potential power supply voltage line VSSL may supply a low potential power supply voltage to the plurality of sub-pixels P. For example, the low potential power supply voltage line VSSL may supply a low potential power supply voltage to light emitting elements included in the plurality of sub-pixels P. For example, the low potential power supply voltage line VSSL may be disposed in a non-display area NA1 located on one side of the display panel PN to which the plurality of flexible films COFs are connected in the non-display area NA. For example, the low potential power supply voltage line VSSL may be connected to the flexible film COFs.

[0095] A plurality of electrostatic discharge units 130 may be arranged in the non-display area NA. The plurality of electrostatic discharge units 130 may discharge static electricity applied to the display panel PN. The plurality of electrostatic discharge units 130 may be arranged in a region of the non-display area NA corresponding to one side of the display area AA. For example, the plurality of electrostatic discharge units 130 may be arranged in the non-display area NA1 located on one side of the display panel PN to which the plurality of flexible film COFs are connected. The plurality of electrostatic discharge units 130 may be arranged to correspond to both sides of the flexible film COFs. For example, the plurality of electrostatic discharge units 130 may be arranged in a region between the plurality of flexible film COFs. The plurality of electrostatic discharge units 130 may be arranged in a region where a constant voltage line VCL for applying a constant voltage is arranged. The plurality of electrostatic discharge units 130 may include a plurality of first electrostatic discharge units 131 and a plurality of second electrostatic discharge units 132.

[0096] The plurality of first electrostatic discharge units 131 may be disposed in the constant voltage line VCL. A plurality of openings 140 exposing a lower layer of the constant voltage line VCL may be disposed in the constant voltage line VCL. For example, a plurality of openings 140 may be disposed in the high potential power supply voltage line VDDL, spaced apart at a predetermined interval CI1. The plurality of openings 140 may have a form in which one side of the high potential power supply voltage line VDDL is opened. The plurality of openings 140 may be formed by etching a portion of the high potential power supply voltage line VDDL.

[0097] A plurality of first electrostatic discharge units 131 may be disposed in each of the plurality of openings 140. For example, a plurality of first electrostatic discharge units 131 may be disposed in each of the plurality of openings 140 disposed in the high potential power supply voltage line VDDL. The plurality of first electrostatic discharge units 131 may be disposed apart from the high potential power supply voltage line VDDL.

[0098] The plurality of first electrostatic discharge units 131 may be connected to at least one gate block GB through a gate driving signal line, and the at least one gate block GB may be distributed in the display area AA, so that the gate driving signal line may be arranged in both the display area AA and the non-display area NA.

[0099] The first electrostatic discharge units 131 include a plurality of transistors, and when external static electricity is applied to one electrode of the transistors, the static electricity can be discharged through a line connected to the other electrode of the transistors. Therefore, external static electricity cannot be applied to the gate driver GD, and the first electrostatic discharge units 131 can protect the gate driver GD. In addition, external static electricity cannot be applied to the sub-pixels P connected to the gate driver GD, and the first electrostatic discharge units 131 can also protect the sub-pixels P.

[0100] The plurality of openings 140 and the plurality of first electrostatic discharge units 131 may correspond to an area where the gate drivers GB are arranged. For example, the number of the plurality of openings 140 and the plurality of first electrostatic discharge units 131 may be the same as the number of gate blocks GB arranged in the column direction among the plurality of gate blocks GB arranged in the display area AA. For example, the number of the plurality of openings 140 and the plurality of first electrostatic discharge units 131 may be the same as the number of gate blocks GB arranged in one row.

[0101] The plurality of second electrostatic discharge units 132 may be arranged between the display area AA and the constant voltage line VCL. For example, the plurality of second electrostatic discharge units 132 may be arranged in a region between the display area AA and the reference voltage line VRL. The plurality of second electrostatic discharge units 132 may be connected to at least one sub-pixel P through a data line.

[0102] The second electrostatic discharge units 132 each include a plurality of transistors, and when external static electricity is applied to one electrode of the transistors, the static electricity can be discharged through a line connected to the other electrode of the transistors, thereby discharging external static electricity that may be applied to the sub-pixels P and protecting the sub-pixels P.

[0103] On the other hand, in FIG. 4, the plurality of second electrostatic discharge units 132 are shown to be arranged in the non-display area NA between the display area AA and the constant voltage line VCL, but this is not limited to this, and a plurality of openings 140 may be further arranged between the plurality of openings 140 in which the plurality of first electrostatic discharge units 131 are arranged, and a plurality of second electrostatic discharge units 132 may be arranged in the plurality of openings 140 between the plurality of first electrostatic discharge units 131.

[0104] 4, the plurality of openings 140 and the plurality of first electrostatic discharge units 131 are shown to be arranged on a high-potential power supply voltage line VDDL to which a high-potential power supply voltage is supplied, but the present invention is not limited to this. The plurality of openings 140 and the plurality of first electrostatic discharge units 131 may also be arranged on a low-potential power supply voltage line VSSL to which a low-potential power supply voltage is supplied or on a reference voltage line VRL to which a reference voltage is supplied.

[0105] FIG. 5 is a plan view showing a portion of a non-display area of ​​a display device according to an embodiment of the present specification. FIG. 6 is a circuit diagram showing an electrostatic discharge unit of a display device according to an embodiment of the present specification. FIG. 7 is a plan view showing an electrostatic discharge unit of a display device according to an embodiment of the present specification. FIG. 8 is a cross-sectional view taken along line A-A' in FIG. 5. FIG. 9 is a cross-sectional view taken along line B-B' in FIG. 5. FIG. 10 is a cross-sectional view taken along line C-C' in FIG. 5. FIG. 5 shows only a portion of the non-display area of ​​the display device where the first electrostatic discharge unit 131 is arranged. FIGS. 6 and 7 show the first electrostatic discharge unit 131.

[0106] 5, a high potential power supply voltage line VDDL may extend in the row direction in the non-display area NA. The high potential power supply voltage line VDDL may have a plurality of openings 140 spaced apart from one another at regular intervals. For example, the high potential power supply voltage line VDDL may have a plurality of openings 140 with one surface opened at the bottom. A plurality of first electrostatic discharge units 131 may be disposed in each of the plurality of openings 140. For example, a plurality of first electrostatic discharge units 131 may be disposed in a plurality of openings 140 disposed in the high potential power supply voltage line VDDL. The plurality of first electrostatic discharge units 131 may be disposed at a predetermined distance from the high potential power supply voltage line VDDL.

[0107] 5 to 7, gate driving signal lines GDL extending in the column direction may be arranged in the non-display area NA. Also, a first voltage line VL1 extending in the column direction and a second voltage line VL2 extending in the column direction may be arranged in the non-display area NA. For example, the gate driving signal line GDL may be one of a clock signal line that supplies a clock signal to the gate block GB, a start signal line that supplies a start signal to the gate block GB, a gate high signal line that supplies a gate high signal to the gate block GB, and a gate low signal line that supplies a gate low signal to the gate block GB.

[0108] 6 and 7, each of the plurality of first electrostatic discharge units 131 and the plurality of second electrostatic discharge units 132 may include a first transistor T1 and a second transistor T2.

[0109] The first transistor T1 may be connected between a gate driving signal line GDL and a first voltage line VL1 to which a first voltage is supplied. For example, a first gate electrode G1 and a first source electrode S1 of the first transistor T1 may be connected to the first voltage line VL1. A first drain electrode D1 of the first transistor T1 may be connected to the gate driving signal line GDL. For example, the first voltage line VL1 may be one of a low potential voltage line to which a low potential voltage is applied or a gate low signal line to which a gate low signal is applied.

[0110] Therefore, when high electrostatic charge is applied to the gate driving signal line GDL, high electrostatic charge may be input to the first drain electrode D1 of the first transistor T1. At this time, a low first voltage is applied to the first gate electrode G1 and the first source electrode S1 of the first transistor T1, and a voltage equal to or greater than a breakdown voltage may be applied between the first drain electrode D1 and the first source electrode S1 of the first transistor T1. As a result, the first transistor T1 is broken down, and the low electrostatic charge applied to the first drain electrode D1 of the first transistor T1 may be discharged through the first voltage line VL1.

[0111] The second transistor T2 may be connected between the gate driving signal line GDL and a second voltage line VL2 to which a second voltage is supplied. For example, a second gate electrode G2 and a second source electrode S2 of the second transistor T2 may be connected to the gate driving signal line GDL. A second drain electrode D2 of the second transistor T2 may be connected to the second voltage line VL2. For example, the second voltage line VL2 may be one of a high potential voltage line to which a high potential voltage is applied or a gate high signal line to which a gate high signal is applied.

[0112] Therefore, when low electrostatic charge is applied to the gate driving signal line GDL, the low electrostatic charge may be input to the second source electrode S2 and the second gate electrode G2 of the second transistor T2. At this time, a high second voltage is applied to the second drain electrode D2 of the second transistor T2, and a voltage equal to or greater than the breakdown voltage may be applied between the second drain electrode D2 and the second source electrode S2 of the second transistor T2. As a result, the second transistor T2 is destroyed, and the low electrostatic charge applied to the second source electrode S2 of the second transistor T2 may be discharged through the first voltage line VL1.

[0113] 5 to 8, the first transistor T1 may include a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

[0114] The first active layer A1 may be disposed on the buffer layer 102. The first active layer A1 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0115] A gate insulating layer 103 may be disposed on the first active layer A1. The gate insulating layer 103 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof.

[0116] A first gate electrode G1 of the first transistor T1 may be disposed on the gate insulating layer 103. The first gate electrode G1 may be formed on the gate insulating layer 103 to overlap the first active layer A1. For example, the first gate electrode G1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0117] A first source electrode S1 and a first drain electrode D1 of the first transistor T1 may be disposed on the second interlayer insulating layer 105. The first source electrode S1 and the first drain electrode D1 of the first transistor T1 may be connected to a first active layer A1 of the first transistor T1 through contact holes formed in the gate insulating layer 103, the first interlayer insulating layer 104, and the second interlayer insulating layer 105.

[0118] The first source electrode S1 of the first transistor T1 may be connected to the gate drive signal line GDL, and the first drain electrode D1 of the first transistor T1 may be connected to the first voltage line VL1. For example, the first source electrode S1 of the first transistor T1 may be integrated with the gate drive signal line GDL, and the first drain electrode D1 of the first transistor T1 may be integrated with the first voltage line VL1.

[0119] A high-potential power supply voltage line VDDL, to which a high-potential power supply voltage is supplied, may be disposed on the second interlayer insulating layer 105. The high-potential power supply voltage line VDDL may be disposed in the same layer as the first source electrode S1 and the first drain electrode D1 of the first transistor T1 and may be made of the same material. For example, the high-potential power supply voltage line VDDL may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0120] Referring to FIGS. 5 and 9, the low potential power supply voltage lines VSSL may be arranged in the row direction in the non-display area NA.

[0121] The low potential power supply voltage lines VSSL may be arranged in the form of a plurality of island structures spaced apart from one another in the row direction. The low potential power supply voltage lines VSSL may be arranged in parallel to the high potential power supply voltage line VDDL at a predetermined distance apart.

[0122] The low-potential power supply voltage line VSSL may be disposed on the second interlayer insulating layer 105. The low-potential power supply voltage line VSSL may be disposed in the same layer as the high-potential power supply voltage line VDDL and may be made of the same material. For example, the low-potential power supply voltage line VSSL may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0123] A metal layer ML may be disposed on the low potential power supply voltage line VSSL.

[0124] The metal layer ML may have an area larger than the width of the low-potential power supply voltage line VSSL. The metal layer ML may extend in the row direction and overlap the low-potential power supply voltage line VSSL. For example, the metal layer ML may be disposed on the first planarization layer 107. The metal layer ML may be disposed on the same layer as the connection electrodes CE and may be made of the same material. For example, the metal layer ML may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0125] The metal layer ML may be connected to the low-potential power supply voltage line VSSL through an interconnect structure. For example, referring to FIG. 10, the metal layer ML may be electrically connected to the low-potential power supply voltage line VSSL through a contact hole. That is, the metal layer ML may be electrically connected to the low-potential power supply voltage line VSSL and a low-potential power supply voltage may be applied to the metal layer ML. Thus, the low-potential power supply voltage is applied to the metal layer ML, and the metal layer ML may function as a low-potential power supply voltage line.

[0126] 5 and 9, each of the plurality of first electrostatic discharge units 131 may be connected to a first connection line CL1 and a second connection line CL2.

[0127] The first connection line CL1 is a line that transmits a gate driving signal and may be referred to as a gate driving signal line. The first connection line CL1 may be connected between the plurality of first electrostatic discharge units 131 and the flexible film COF. The first connection line CL1 may extend between the low potential power supply voltage lines VSSL. For example, the first connection line CL1 may extend to a region between the low potential power supply voltage lines VSSL that are spaced apart from each other.

[0128] The first connection line CL1 may be disposed on the second interlayer insulating layer 105. The first connection line CL1 may be disposed in the same layer as the low potential power supply voltage line VSSL and may be made of the same material. For example, the first connection line CL1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0129] For example, one end of the first connection line CL1 may be connected to the link line, and the other end of the first connection line CL1 may be connected to the first electrostatic discharge unit 131. For example, when the link line is disposed on the gate insulating layer 103, one end of the first connection line CL1 may be electrically connected to the link line through contact holes formed in the first interlayer insulating layer 104 and the second interlayer insulating layer 105.

[0130] The second connection line CL2 is a line that transmits a gate driving signal and may be referred to as a gate driving signal line. The second connection line CL2 may be disposed between the plurality of first electrostatic discharge units 131 and the plurality of gate blocks GB. The second connection line CL2 may also be connected between the plurality of first electrostatic discharge units 131 and the plurality of pixel blocks PB. The second connection line CL2 may be connected to the first electrostatic discharge units 131 and extend in the column direction.

[0131] The second connection line CL2 may be disposed on the first planarization layer 107. The second connection line CL2 may be disposed in the same layer as the metal layer ML and may be made of the same material. For example, the metal layer ML may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0132] For example, one end of the second connection line CL2 may be connected to the first electrostatic discharge unit 131, and the other end of the second connection line CL2 may be connected to a plurality of gate blocks GB or a plurality of pixel blocks PB. For example, one end of the second connection line CL2 may be electrically connected to the first electrostatic discharge unit 131 through a contact hole formed in the first planarization layer 107.

[0133] When the gate driver is disposed in the non-display area around the display area, the bezel inevitably increases in size in accordance with the area of ​​the gate driver.

[0134] Therefore, in the display device 100 according to one embodiment of the present specification, a plurality of gate blocks GB in which the gate driving units are divided and arranged are arranged in the display area AA, thereby minimizing the non-display area NA on both the left and right sides of the display panel PN.

[0135] However, as the area of ​​the non-display area NA is minimized by disposing the gate driver within the display area AA, there is a problem in that there is no area for disposing the electrostatic discharge unit connected to the gate driver.

[0136] Therefore, in the display device 100 according to an embodiment of the present specification, an opening 140 exposed to a lower layer is disposed in the constant voltage line VCL disposed in the power supply region of the non-display region NA, and the electrostatic discharge unit 130 may be disposed in the opening 140. Therefore, the electrostatic discharge unit 130 connected to the gate driver may be disposed while minimizing the non-display region NA on both the left and right sides of the display panel PN, and the bezel may be minimized while minimizing defects caused by static electricity.

[0137] Furthermore, if the electrostatic discharge part is disposed outside the sealing part, there is a problem that defects such as total corrosion may occur in a reliable environment.

[0138] Therefore, in the display device 100 according to an embodiment of the present specification, the electrostatic discharge unit 130 may be disposed within the region where the sealing unit 120 is disposed. Therefore, the electrostatic discharge unit 130 may be prevented from being disposed outside the sealing unit 120, thereby ensuring reliability of the electrostatic discharge unit 130 and minimizing defects caused by static electricity.

[0139] Fig. 11 is a plan view showing a portion of a non-display area of ​​a display device according to another embodiment of the present specification. Fig. 12 is a cross-sectional view taken along line DD' in Fig. 11. The display device 200 according to Fig. 11 has the same configuration as the display device 100 of Fig. 5 except for the first metal layer ML1 and the second metal layer ML2, and therefore detailed description thereof will be omitted.

[0140] 11 and 12, a high potential power supply voltage line VDDL may extend in the row direction in the non-display area NA. The high potential power supply voltage line VDDL may have a plurality of openings 140 spaced apart from one another at regular intervals. For example, the high potential power supply voltage line VDDL may have a plurality of openings 140 with one surface open at the bottom. A plurality of first electrostatic discharge units 131 may be disposed in each of the plurality of openings 140. For example, a plurality of first electrostatic discharge units 131 may be disposed in a plurality of openings 140 disposed in the high potential power supply voltage line VDDL. The plurality of first electrostatic discharge units 131 may be disposed at a predetermined distance from the high potential power supply voltage line VDDL.

[0141] The high-potential power supply voltage line VDDL may be disposed on the second interlayer insulating layer 105. The high-potential power supply voltage line VDDL may be disposed in the same layer as the first source electrode S1 and the first drain electrode D1 of the first transistor T1 and may be made of the same material. For example, the high-potential power supply voltage line VDDL may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0142] A first metal layer ML1 may be disposed on the high potential power supply voltage line VDDL.

[0143] The first metal layer ML1 may have an area larger than the width of the high potential power supply voltage line VDDL. The first metal layer ML1 may extend in the row direction and overlap with the high potential power supply voltage line VDDL. The first metal layer ML1 may be arranged to overlap at least a portion of the first electrostatic discharge unit 131. The first metal layer ML1 may be arranged to cover an upper portion of the first electrostatic discharge unit 131. For example, the first metal layer ML1 may be arranged on the upper portion of the first electrostatic discharge unit 131 to overlap with the remainder of the first electrostatic discharge unit 131 except for a portion of the first electrostatic discharge unit 131.

[0144] A plurality of second openings 240 exposing the underlying layer may be arranged in the first metal layer ML1. For example, the plurality of second openings 240 may be arranged in the first metal layer ML1, spaced apart at a predetermined interval CI2. The plurality of second openings 240 may have a form in which one side of the first metal layer ML1 is opened. For example, the plurality of second openings 240 may be arranged in regions corresponding to a portion of the first electrostatic discharge portion 131 and the second connection electrode CL2. The plurality of second openings 240 may be formed by etching a portion of the first metal layer ML1.

[0145] For example, the first metal layer ML1 may be disposed on the first planarization layer 107. The first metal layer ML1 may be disposed on the same layer as the second connection electrode CL2 and may be made of the same material. For example, the first metal layer ML1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0146] The first metal layer ML1 may be connected to a high-potential power supply voltage line VDDL through an interconnect structure. For example, the first metal layer ML1 may be electrically connected to the high-potential power supply voltage line VDDL through a contact hole. That is, the first metal layer ML1 may be electrically connected to the high-potential power supply voltage line VDDL and a high-potential power supply voltage may be applied to the first metal layer ML1. Thus, the high-potential power supply voltage may be applied to the first metal layer ML1 and the first metal layer ML1 may function as a high-potential power supply voltage line.

[0147] The low potential power supply voltage lines VSSL can be arranged in the row direction in the non-display area NA.

[0148] The low potential power supply voltage lines VSSL may be arranged in the form of a plurality of island structures spaced apart from one another in the row direction. The low potential power supply voltage lines VSSL may be arranged in parallel to the high potential power supply voltage line VDDL at a predetermined distance apart.

[0149] The low-potential power supply voltage line VSSL may be disposed on the second interlayer insulating layer 105. The low-potential power supply voltage line VSSL may be disposed in the same layer as the high-potential power supply voltage line VDDL and may be made of the same material. For example, the low-potential power supply voltage line VSSL may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0150] A second metal layer ML2 may be disposed on the low potential power supply voltage line VSSL.

[0151] The second metal layer ML2 may have an area larger than the width of the low potential power supply voltage line VSSL. The second metal layer ML2 may extend in the row direction and overlap the low potential power supply voltage line VSSL. For example, the second metal layer ML2 may be disposed on the first planarization layer 107. The second metal layer ML2 may be disposed on the same layer as the connection electrode CE and may be made of the same material. For example, the second metal layer ML2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0152] The second metal layer ML2 may be connected to the low potential power supply voltage line VSSL through an interconnect structure. For example, the second metal layer ML2 may be electrically connected to the low potential power supply voltage line VSSL through a contact hole. That is, the second metal layer ML2 may be electrically connected to the low potential power supply voltage line VSSL and a low potential power supply voltage may be applied to the second metal layer ML2. Thus, the low potential power supply voltage is applied to the second metal layer ML2 and the second metal layer ML2 may function as a low potential power supply voltage line.

[0153] A display device according to an embodiment of the present specification can be described as follows.

[0154] A display device according to an embodiment of the present specification includes a substrate including a display area in which a plurality of sub-pixels are arranged and a non-display area surrounding the display area, a constant voltage line arranged in the non-display area and including a plurality of openings, and a plurality of electrostatic discharge units arranged in the plurality of openings.

[0155] According to another feature of the present specification, the display device may further include a sealing portion that covers at least a portion of the display area and the non-display area on the substrate, and the plurality of electrostatic discharge portions may be disposed inside an end of the sealing portion.

[0156] According to another aspect of the present disclosure, the constant voltage line supplies a constant voltage to the plurality of sub-pixels, and the constant voltage may be one of a low potential power supply voltage, a reference voltage, and a high potential power supply voltage.

[0157] According to another feature of the present specification, the display device may further include at least one flexible substrate connected to one side of the non-display area, and the plurality of electrostatic discharge units may be disposed on the one side of the non-display area to which the flexible substrate is connected.

[0158] According to another feature of the present specification, the display device may further include at least one flexible substrate connected to one side of the non-display area, and the plurality of electrostatic discharge units may be disposed in the non-display area to which the flexible substrate is connected, and may be disposed on one side of the flexible substrate.

[0159] According to another feature of the present specification, the display device may further include gate drivers distributed over a display area on the substrate and configured to output gate signals to the plurality of sub-pixels, and the plurality of electrostatic discharge units may correspond to the areas where the gate drivers are disposed.

[0160] According to still another feature of the present disclosure, the display device may further include a plurality of gate drive signal lines disposed on the substrate and supplying gate drive signals to the gate driver, and the plurality of electrostatic discharge units may be connected to the plurality of gate drive signal lines.

[0161] According to another aspect of the present disclosure, the plurality of gate driving signal lines may be at least one of a clock signal line, a start signal line, a gate high voltage line, and a gate low voltage line.

[0162] According to another feature of the present disclosure, the display device may further include a planarization layer disposed on the constant voltage line and the plurality of electrostatic discharge portions, and a metal layer disposed on the planarization layer.

[0163] A display device according to another embodiment of the present specification may include a substrate including a display area including a plurality of sub-pixels and a non-display area surrounding the display area, a first constant voltage line disposed in the non-display area and including a plurality of first openings, a plurality of island structures separated from the first constant voltage line and disposed in the non-display area, a plurality of first electrostatic discharge units disposed in the plurality of first openings, and a plurality of first connection lines each connected to the first electrostatic discharge units and extending between two of the plurality of island structures.

[0164] According to another feature of the present specification, a first first connection line among the plurality of first connection lines is connected to a first first electrostatic discharge portion among the plurality of first electrostatic discharge portions and a flexible film, and the flexible film is coupled to a non-display area, and the non-display area may be between the flexible film and the display area.

[0165] According to another feature of the present disclosure, the semiconductor device may further include a metal layer on the plurality of island structures, and each of the plurality of island structures may be connected to the metal layer through an interconnect structure.

[0166] According to another feature of the present disclosure, the metal layer and the plurality of island structures may be configured to form a second constant voltage line having a voltage level different from that of the first constant voltage line.

[0167] According to another feature of the present specification, the display area may include one or more gate blocks and one or more pixel blocks, and the display device may further include a plurality of second connection lines connected between a first electrostatic discharge unit of the plurality of first electrostatic discharge units and one of the one or more gate blocks and the one or more pixel blocks.

[0168] According to yet another feature of the present disclosure, the plurality of second connection lines may be disposed in the same layer as the metal layer.

[0169] According to another feature of the present disclosure, the pixel block may include a plurality of sub-pixels of different colors, and the plurality of sub-pixels may be connected to a second connection line of the plurality of second connection lines.

[0170] According to another feature of the present specification, the metal layer may not overlap each of the plurality of first electrostatic discharge portions.

[0171] According to another feature of the present disclosure, the first constant voltage line and the plurality of island structures may be disposed on the same layer.

[0172] According to still another feature of the present disclosure, a width of the gate block may be substantially the same as a width of the first opening of the first constant voltage line.

[0173] According to still another feature of the present specification, the first electrostatic discharge unit may include a first transistor having a first source electrode, a first drain electrode, and a first gate electrode, and the first source electrode and the first drain electrode may be disposed in the same layer as the first constant voltage line.

[0174] According to another feature of the present specification, the display device may further include a sealing portion overlapping at least a portion of the display area and the non-display area, and overlapping the first constant voltage line, the plurality of first electrostatic discharge portions, and the plurality of island structures.

[0175] According to still another feature of the present disclosure, the first constant voltage line may include a first opening having at least one side not surrounded by the first constant voltage line.

[0176] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are intended to be illustrative rather than limiting the technical concept of the present specification, and the scope of the technical concept of the present specification is not limited by these embodiments. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not restrictive. The scope of protection of the present specification should be interpreted by the scope of the following claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included in the scope of the present specification.

Claims

1. a substrate including a display area in which a plurality of sub-pixels are arranged and a non-display area surrounding the display area; a constant voltage line disposed in the non-display area and including a plurality of openings; a plurality of electrostatic discharge portions disposed in the plurality of openings.

2. a sealing portion disposed on the substrate and covering at least a part of the display area and the non-display area; The display device according to claim 1 , wherein the plurality of electrostatic discharge portions are arranged inside an edge of the sealing portion.

3. The constant voltage line is The display device according to claim 1 , wherein a constant voltage is supplied to the plurality of sub-pixels, and the constant voltage is one of a low potential power supply voltage, a reference voltage, and a high potential power supply voltage.

4. Further comprising at least one flexible substrate connected to one side of the non-display area, The display device of claim 1 , wherein the plurality of electrostatic discharge units are disposed in the non-display area to which the flexible substrate is connected, and are disposed on one side of the flexible substrate.

5. the display region on the substrate, and further comprising gate drivers for outputting gate signals to the plurality of sub-pixels; The display device of claim 1 , wherein the plurality of electrostatic discharge units correspond to an area where the gate driver is arranged.

6. The gate driver further includes a plurality of gate driving signal lines disposed on the substrate for supplying gate driving signals to the gate driver; The display device according to claim 5 , wherein the plurality of electrostatic discharge units are connected to the plurality of gate drive signal lines.

7. The plurality of gate drive signal lines are 7. The display device according to claim 6, wherein the line is at least one of a clock signal line, a start signal line, a gate high voltage line, and a gate low voltage line.

8. a planarization layer disposed on the constant voltage line and the plurality of electrostatic discharge portions; The display device of claim 1 , further comprising: a metal layer disposed on the planarization layer.

9. a substrate including a display area including a plurality of sub-pixels and a non-display area surrounding the display area; a first constant voltage line disposed in the non-display area and including a plurality of first openings; a plurality of island structures separated from the first constant voltage line and disposed in the non-display area; a plurality of first electrostatic discharge units disposed in the plurality of first openings; a plurality of first connection lines each connected to the first electrostatic discharge portion and extending between two of the plurality of island structures.

10. 10. The display device of claim 9, wherein each of the plurality of first connection lines is connected to each of the plurality of first electrostatic discharge units and a flexible film, the flexible film is coupled to the non-display area, and the non-display area is between the flexible film and the display area.

11. further comprising a metal layer on the plurality of island structures; The display device according to claim 9 , wherein each of the plurality of island structures is connected to the metal layer through an interconnect structure.

12. The display device of claim 11, wherein the metal layer and the plurality of island structures are configured to form a second constant voltage line having a voltage level different from that of the first constant voltage line.

13. the display area includes one or more gate blocks and one or more pixel blocks; 12. The display device of claim 11, further comprising a plurality of second connection lines connected between a first electrostatic discharge unit of the plurality of first electrostatic discharge units and one of the one or more gate blocks and the one or more pixel blocks.

14. The display device according to claim 13 , wherein the plurality of second connection lines are disposed in the same layer as the metal layer.

15. The pixel block includes a plurality of sub-pixels of different hues, The display device according to claim 13 , wherein the plurality of sub-pixels are connected to respective second connection lines among the plurality of second connection lines.

16. The display device of claim 9 , wherein the first constant voltage line and the plurality of island structures are disposed on the same layer.

17. The display device of claim 13 , wherein the width of the gate block is substantially the same as the width of the first opening of the first constant voltage line.

18. 10. The display device of claim 9, wherein the first electrostatic discharge unit includes a first transistor having a first source electrode, a first drain electrode, and a first gate electrode, the first source electrode and the first drain electrode being disposed in the same layer as the first constant voltage line.

19. The display device of claim 9 , further comprising a sealing portion overlapping the display area and at least a portion of the non-display area, and overlapping the first constant voltage line, the plurality of first electrostatic discharge portions, and the plurality of island structures.

20. The display device of claim 9 , wherein the first constant voltage line includes a first opening having at least one side not surrounded by the first constant voltage line.

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