Display device

Abstract

To provide a display device with a heterogeneous structure which compensates for an output of a signal according to the position.SOLUTION: A display device according to an exemplary embodiment of the present disclosure comprises: a substrate having a display area having a heterogeneous side, a non-display area surrounding the display area, and a notch area defined by a shape of the heterogeneous side of the display area; a gate driver including a plurality of gate blocks distributed in the display area and configured to output a gate signal; a plurality of gate lines connected to the plurality of gate blocks to transmit the gate signal; and a first compensation pattern disposed in at least one of the plurality of gate blocks to overlap the plurality of gate lines.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present specification relates to a display device, and more particularly to a display device that can minimize a bezel. [Background technology]

[0002] As technology in modern society advances, display devices are being used in a variety of ways to provide information to users. Display devices range from electronic boards that simply transmit visual information in one direction to various electronic devices that require more advanced technology to confirm user input and provide information corresponding to the confirmed input.

[0003] For example, a display device may be installed in a vehicle to provide various information to the driver and passengers of the vehicle. However, the display device of the vehicle must display content appropriately so as not to interfere with the operation of the vehicle. For example, the display device must limit the display of content that may distract the driver from driving while the vehicle is in operation. Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present specification is to provide a display device having a irregular structure, which can compensate for signal output depending on the position.

[0005] The problem to be solved by this specification is to provide a display device with a reduced bezel.

[0006] However, the problems to be solved in this specification are not limited to those mentioned above, and other technical problems can be inferred from the following examples. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems, a display device according to one embodiment of the present specification includes a substrate including a display area having irregular sides and a non-display area surrounding the display area, wherein a notch area is defined by the shape of the irregular sides of the display area; a gate driver including a plurality of gate blocks distributed in the display area and outputting gate signals; a plurality of gate lines connected to the plurality of gate blocks and transmitting gate signals; and a first compensation pattern disposed in at least one of the plurality of gate blocks and overlapping with the plurality of gate lines.

[0008] Further details of the embodiments are included in the detailed description and drawings.

[0009] The present invention can compensate for the output of gate signals and clock signals that differ depending on the position by using a different structure.

[0010] In this specification, a gate driver that outputs a gate signal is disposed within the display area, and a compensation pattern that compensates for the gate signal and the clock signal is disposed within the display area, thereby minimizing the bezel area.

[0011] The effects of the present invention are not limited to the above-mentioned examples, and various other effects are included within the scope of the present invention. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is an exemplary plan view of a display device according to an embodiment of the present specification; [Figure 2] 1 is an exemplary plan view of a display device according to an embodiment of the present specification; [Figure 3] 1 is an exemplary circuit diagram of a pixel circuit of a display device according to an embodiment of the present specification; [Figure 4] 1 is a cross-sectional view of a display device according to an embodiment of the present specification. [Figure 5] 1 is an enlarged plan view of one pixel of a display device according to an embodiment of the present specification; [Figure 6]FIG. 2 is a schematic diagram for explaining a first region in FIG. [Figure 7] 7 is an enlarged plan view of one of the gate drivers of FIG. 6. FIG. [Figure 8] FIG. 2 is a schematic diagram for explaining a second region of FIG. 1. [Figure 9] FIG. 9 is an enlarged plan view of one of the gate blocks of FIG. 8. [Figure 10] FIG. 10 is a cross-sectional view taken along line VIII-VIII' in FIG. [Figure 11] 10 is an enlarged plan view of one of gate blocks of a display device according to another embodiment of the present disclosure; FIG. [Figure 12] 10 is an enlarged plan view of one of gate blocks of a display device according to still another embodiment of the present disclosure; FIG. [Figure 13] FIG. 10 is a cross-sectional view of a display device according to still another embodiment of the present specification. [Figure 14] 10 is a cross-sectional view of one of gate blocks of a display device according to still another embodiment of the present disclosure. [Figure 15] FIG. 10 is an exemplary plan view of a display device according to still another embodiment of the present specification. [Figure 16] 16 is a plan view of one of the gate blocks in the fourth region of FIG. 15. FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along the line XV-XV′ of FIG. 16. [Figure 18] 10 is a cross-sectional view of one of gate blocks of a display device according to still another embodiment of the present disclosure. [Figure 19] 10 is a cross-sectional view of one of gate blocks of a display device according to still another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] The advantages and features of the present invention, and methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely so that this disclosure will be complete and will fully convey the scope of the invention to those skilled in the art.

[0014] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are illustrative only and are not intended to limit the scope of this specification. The same reference symbols refer to the same elements throughout this specification. Furthermore, when describing this specification, if it is deemed that a detailed description of related prior art would unnecessarily obscure the gist of this specification, such a detailed description will be omitted. When using words such as "include," "have," and "be made" in this specification, other parts may be added unless "only" is used. When describing an element in the singular, this also includes the plural unless otherwise explicitly stated.

[0015] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0016] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0017] When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0018] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0019] Like reference numbers refer to like elements throughout the specification.

[0020] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0021] The features of the various embodiments of this specification may be partially or wholly combined or combined with each other, may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the other or may be implemented together in a related relationship.

[0022] In the following, the present specification will be described with reference to the drawings.

[0023] Fig. 1 is an exemplary plan view of a display device according to an embodiment of the present specification. Fig. 2 is an exemplary plan view of a display device according to an embodiment of the present specification. For convenience of explanation, Figs. 1 and 2 only show a substrate 110 and a plurality of flexible film COFs among various components of a display device 100.

[0024] The substrate 110 is a base member for supporting various components of the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of a plastic material such as polyimide (PI) or glass, but is not limited thereto.

[0025] The substrate 110 includes a display area AA and a non-display area NA.

[0026] The display area AA is an area where an image is displayed. Pixels each consisting of a plurality of sub-pixels may be arranged in the display area AA to display an image. For example, a pixel may be composed of a plurality of sub-pixels each including a light-emitting element and a driving circuit, and may display an image.

[0027] The display area AA may have an irregular side, where at least one of the four sides of the display area AA has an irregular structure. That is, referring to FIG. 1, the active area AA has a first side FS, a second side SS, a third side TS, and a fourth side HTRS. The second side SS faces the third side TS, and the first side FS is located between the second side SS and the third side TS. The fourth side HTRS faces the first side FS. The irregular side HTRS refers to a side that is not a straight side but has a curved shape. For example, referring to FIG. 1, the lower side of the four sides of the display area AA may be the irregular side HTRS. That is, the irregular side HTRS located at the bottom of the display area AA is recessed toward the top of the display area AA, so that a recessed irregular structure corresponding to the irregular side HTRS may be defined. 1, the irregular structure is shown as a rectangular recessed structure, but is not limited thereto, and the irregular structure is a structure generated by the irregular side HTRS, and may refer to a shape that is difficult to define as a polygon due to a deformation of the polygon, such as a circle, triangle, square, rhombus, pentagon, hexagon, etc. Since pixels are not arranged in the position where the irregular side HTRS is recessed, no image is displayed, and this can be defined as a notch area (NTA).

[0028] The display area AA may include a plurality of first regions A1 and at least one second region A2 divided into a grid pattern. The plurality of first regions A1 and at least one second region A2 may be regions in which gate drivers are distributed. The plurality of first regions A1 may all have a uniform area, and the at least one second region A2 may be positioned to correspond to the notch region NTA and have a smaller area than the plurality of first regions A1. For design convenience, the second region A2 may be positioned adjacent to the notch region NTA. While FIG. 1 illustrates the display area AA as including one second region A2, this is not intended to be limiting, and two or more second regions A2 may be disposed depending on the shape, position, and size of the notch region. Referring to FIG. 2, the display area AA may include a plurality of first regions A1 and a plurality of second regions A2. For example, a row region corresponding to the notch region NTA may include one first region A1 and a plurality of second regions A2. However, this is not intended to be limiting.

[0029] The non-display area NA is an area where no image is displayed, and is an area where various wirings for driving the sub-pixels arranged in the display area AA are arranged. The non-display area may be called a bezel area.

[0030] A plurality of flexible film COFs are disposed at one end of the substrate 110. The plurality of flexible film COFs may be electrically connected to one end of the substrate 110. The plurality of flexible film COFs are films in which various components are disposed on a ductile base film and which supply signals to a plurality of sub-pixels in the display area AA. One end of the plurality of flexible film COFs is disposed in the non-display area NA of the substrate 110, and the plurality of flexible film COFs may supply data voltages, etc. to a plurality of sub-pixels in the display area AA. While FIG. 1 illustrates four flexible film COFs, the number of the plurality of flexible film COFs may vary depending on the design and is not limited thereto.

[0031] Meanwhile, a driving IC such as a data driver IC may be disposed on each of the flexible film COFs. The driving IC is a component that processes data for displaying an image and a driving signal for processing the data. The driving IC may be disposed in a chip-on-glass (COG), chip-on-film (COF), tape carrier package (TCP), or other manner depending on the mounting method. For the sake of convenience, this specification describes the driving IC as being mounted on each of the flexible film COFs in a chip-on-film manner, but the present invention is not limited thereto.

[0032] 3 is an exemplary circuit diagram of a pixel circuit of a display device according to an embodiment of the present specification. A pixel PX may include multiple sub-pixels each exhibiting a different color, and a pixel circuit corresponding to each of the multiple sub-pixels. FIG. 3 shows an example of a pixel circuit for one sub-pixel arranged in the pixel PX.

[0033] Referring to FIG. 3, the pixel circuit may include eight transistors and one capacitor.

[0034] The pixel circuit may include a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor Cstg.

[0035] The eight transistors included in the pixel circuit may be n-type transistors or p-type transistors. In the case of p-type transistors, the low level voltage of each driving signal may be a voltage that turns on the TFT, and the high level voltage of each driving signal may be a voltage that turns off the TFT.

[0036] Here, the low-level voltage may correspond to a pre-specified voltage lower than the high-level voltage. For example, the low-level voltage may include a voltage within the range of -8V to -12V. The high-level voltage may correspond to a pre-specified voltage higher than the low-level voltage. For example, the high-level voltage may include a voltage within the range of 12V to 16V. Depending on the embodiment, the low-level voltage may be referred to as a first voltage, and the high-level voltage may be referred to as a second voltage. In such a case, the first voltage may be lower than the second voltage. However, the above-mentioned ranges of the low-level voltage and the high-level voltage are merely examples and are not limited thereto.

[0037] Hereinafter, the first electrode or second electrode of a transistor may refer to a source electrode or a drain electrode. However, the terms first electrode and second electrode are merely terms used to distinguish between the electrodes and do not limit what each electrode corresponds to. Also, the first electrode for each electrode may not refer to the same electrode. For example, the first electrode of the first transistor T1 may refer to the source electrode of the first transistor T1, and the first electrode of the sixth transistor T6 may refer to the drain electrode of the sixth transistor T6.

[0038] The driving transistor DT may be connected to a first transistor T1 connected to the first light emitting element ED1 and a second transistor T2 connected to the second light emitting element ED2. For example, a second electrode of the driving transistor DT may be connected to the first transistor T1 and the second transistor T2.

[0039] The driving transistor DT may be connected to a high-potential power supply line that provides a high-potential power supply voltage ELVDD. For example, a first electrode of the driving transistor DT may be connected to the high-potential power supply line. When the driving transistor DT is turned on, the high-potential power supply voltage ELVDD provided through the high-potential power supply line may be transferred from the first electrode to the second electrode of the driving transistor DT.

[0040] The first transistor T1 may be connected to at least one of the first light emitting element ED1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5.

[0041] For example, a first electrode of the first transistor T1 may be connected to the second transistor T2 and the fourth transistor T4. A second electrode of the first transistor T1 may be connected to the first light emitting element ED1 and the fifth transistor T5. A gate electrode of the first transistor T1 may be connected to a wide-angle signal line to which a wide-angle signal CS1 is applied. The first transistor T1 may be turned on or off by the wide-angle signal CS1 provided through the wide-angle signal line. Therefore, when the first transistor T1 is turned on, a voltage through the driving transistor DT may be applied to the first light emitting element ED1 (e.g., the anode electrode of the first light emitting element ED1).

[0042] Here, the wide-view signal CS1 is provided by a mode control section (or a mode control circuit) and can control the driving (or light emission) of the first light-emitting element ED1 on which the first lens is disposed.

[0043] The second transistor T2 may be connected to at least one of the second light emitting element ED2, the first transistor T1, the fourth transistor T4, and the sixth transistor T6.

[0044] For example, a first electrode of the second transistor T2 may be connected to the first transistor T1 and the fourth transistor T4. A second electrode of the second transistor T2 may be connected to the sixth transistor T6 and the second light-emitting element ED2. A gate electrode of the second transistor T2 may be connected to a narrow-viewpoint signal line to which a narrow-viewpoint signal CS2 is applied. The second transistor T2 may be turned on or off by the narrow-viewpoint signal CS2 provided through the narrow-viewpoint signal line. Therefore, when the second transistor T2 is turned on, a voltage through the driving transistor DT may be applied to the second light-emitting element ED2 (e.g., the anode electrode of the second light-emitting element ED2).

[0045] Here, the narrow-view signal CS2 is provided by the mode control section (or mode control circuit), and can control the driving (or light emission) of the second light-emitting element ED2 on which the second lens is disposed.

[0046] In the embodiment, a first lens may be disposed on the first light-emitting element ED1. The viewing angle of the region where the first light-emitting element ED1 is disposed may correspond to a first value due to the first lens. For example, the viewing angle of the region where the first light-emitting element ED1 is disposed may be equal to or greater than the first value. A second lens may be disposed on the second light-emitting element ED2. The viewing angle of the region where the second light-emitting element ED2 is disposed due to the second lens may correspond to a second value. The second value may be smaller than the first value. For example, the viewing angle of the region where the second light-emitting element ED2 is disposed may be equal to or smaller than the second value.

[0047] In the embodiment, the region where the first light-emitting element ED1 of the pixel circuit is arranged may have a first viewing angle value that provides light to a range corresponding to the passenger seat and the driver's seat next to the passenger seat, and the region where the second light-emitting element ED2 is arranged may have a second viewing angle value that provides light to a range corresponding to the passenger seat.

[0048] For example, content (or an image) provided through the first light-emitting element ED1 of the pixel PX can be shared with the user and people nearby in the first direction. When content is provided through the first light-emitting element ED1, it is a mode in which content is provided in a first viewing angle range that is wider than a second viewing angle range provided by the second light-emitting element ED2, and can be referred to as a first mode. Also, content provided by the second light-emitting element ED2 does not need to be shared with people nearby the user. When content is provided through the second light-emitting element ED2, it is a mode in which content is provided in a second viewing angle range that is narrower than the first viewing angle range provided by the first light-emitting element ED1, and can be referred to as a second mode.

[0049] The third transistor T3 may be connected to at least one of the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the capacitor Cstg.

[0050] For example, a first electrode of the third transistor T3 may be connected to a reference voltage line that supplies a reference voltage Vref. A first electrode of the third transistor T3 may be connected to the fifth transistor T5 and the sixth transistor T6. A second electrode of the third transistor T3 may be connected to the sixth transistor T6 and the capacitor Cstg. A gate electrode of the third transistor T3 may be connected to an emission signal line that supplies an emission signal EM. The third transistor T3 may be turned on or off by the emission signal EM. Therefore, when the third transistor T3 is turned on, the reference voltage Vref may be applied to the first electrode of the capacitor Cstg.

[0051] The fourth transistor T4 may be connected to at least one of the driving transistor DT, the first transistor T1, the second transistor T2, and the capacitor Cstg.

[0052] For example, a first electrode of the fourth transistor T4 may be connected to the driving transistor DT and the capacitor Cstg. A second electrode of the fourth transistor T4 may be connected to the driving transistor DT, the first transistor T1, and the second transistor T2. A gate electrode of the fourth transistor T4 may be connected to the second scan line for the second scan signal SCAN2. The fourth transistor T4 may receive the second scan signal SCAN2 and be turned on or off in response to the second scan signal SCAN2. Therefore, when the fourth transistor T4 is turned on, the gate electrode and the second electrode of the driving transistor DT may be diode-connected and connected in a diode configuration.

[0053] The fifth transistor T5 may be connected to at least one of the first transistor T1, the third transistor T3, and the first light emitting element ED1.

[0054] For example, a first electrode of the fifth transistor T5 may be connected to the third transistor T3 and a reference voltage line that supplies the reference voltage Vref. A second electrode of the fifth transistor T5 may be connected to the first transistor T1 and the first light emitting element ED1. A gate electrode of the fifth transistor T5 may be connected to the second scan line. Thus, the fifth transistor T5 may receive the second scan signal SCAN2 and be turned on or off in response to the second scan signal SCAN2. Therefore, when the fifth transistor T5 is turned on, the reference voltage Vref may be applied to the first light emitting element ED1 (e.g., the anode electrode of the first light emitting element ED1).

[0055] The sixth transistor T6 may be connected to at least one of the second transistor T2, the third transistor T3, and the second light emitting element ED2.

[0056] For example, a first electrode of the sixth transistor T6 may be connected to the third transistor T3 and a reference voltage line that supplies the reference voltage Vref. A second electrode of the sixth transistor T6 may be connected to the second transistor T2 and the second light-emitting element ED2. A gate electrode of the sixth transistor T6 may be connected to the second scan line. Thus, the sixth transistor T6 may receive a second scan signal SCAN2 and be turned on or off in response to the second scan signal SCAN2. Therefore, when the sixth transistor T6 is turned on, the reference voltage Vref may be applied to the second light-emitting element ED2 (e.g., the anode electrode of the second light-emitting element ED2).

[0057] The seventh transistor T7 may be connected to at least one of the third transistor T3 and the capacitor Cstg.

[0058] For example, a first electrode of the seventh transistor T7 may be connected to a data line supplying the data voltage Vdata. A second electrode of the seventh transistor T7 may be connected to the third transistor T3 and the capacitor Cstg. A gate electrode of the seventh transistor T7 may be connected to a first scan line supplying the first scan signal SCAN1. The seventh transistor T7 may receive the first scan signal SCAN1 and be turned on or off in response to the first scan signal SCAN1. Therefore, when the seventh transistor T7 is turned on, the data voltage Vdata may be applied to the first electrode of the capacitor Cstg.

[0059] The first light emitting element ED1 and the second light emitting element ED2 may be connected to a low potential power supply line that supplies a low potential power supply voltage ELVSS. For example, the cathode electrode of the first light emitting element ED1 and the cathode electrode of the second light emitting element ED2 may be connected to the low potential power supply line and receive the low potential power supply voltage ELVSS. The low potential power supply voltage may be a ground voltage (e.g., 0V (volt)). For example, the cathode electrode of the first light emitting element ED1 and the cathode electrode of the second light emitting element ED2 may receive a voltage corresponding to ground, but is not limited thereto.

[0060] 4 is a cross-sectional view of a display device according to an embodiment of the present disclosure. For convenience of explanation, only the substrate 110, the first transistor T1, the storage capacitor Cst, the buffer layer 111, the gate insulating layer 112, the first interlayer insulating layer 113, the second interlayer insulating layer 114, the first planarization layer 115, the second planarization layer 116, the connecting electrode CE, the light emitting element 120, the bank layer 117, and the spacer 117a are shown in FIG. 4.

[0061] Referring to FIG. 4, a display device 100 according to one embodiment of the present specification includes a substrate 110, a first transistor T1, a storage capacitor Cst, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarization layer 115, a second planarization layer 116, a light-emitting element 120, and a bank layer 117.

[0062] The substrate 110 is a base member for supporting various components of the display device 100 and may be made of an insulating material. For example, the substrate may be made of glass or plastic, but is not limited thereto.

[0063] A buffer layer 111 may be disposed on the substrate 110. The buffer layer 111 may be formed on the entire surface of the substrate 110. The buffer layer 111 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. The buffer layer 111 may improve adhesion between the substrate 110 and a layer formed on the buffer layer 111. The buffer layer 111 is not an essential component and may be omitted depending on the type and material of the substrate 110, the structure and type of the transistor, etc.

[0064] The first transistor T1 may be disposed on the buffer layer 111. The first transistor T1 may include a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. The first active layer ACT1 of the first transistor T1 may be disposed on the buffer layer 111.

[0065] The first active layer ACT1 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0066] A gate insulating layer 112 may be disposed on the first active layer ACT1 of the first transistor T1. The gate insulating layer 112 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. Contact holes may be formed in the gate insulating layer 112 to connect the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1 to the first active layer ACT1 of the first transistor T1.

[0067] A first gate electrode GE1 of the first transistor T1 may be disposed on the gate insulating layer 112. The first gate electrode GE1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first gate electrode GE1 may be formed on the gate insulating layer 112 to overlap with the first active layer ACT1 of the first transistor T1.

[0068] A first interlayer insulating layer 113 may be disposed on the gate insulating layer 112 and the first gate electrode GE1. The first interlayer insulating layer 113 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. A contact hole may be formed in the first interlayer insulating layer 113 to expose the first active layer ACT1 of the first transistor T1.

[0069] A second interlayer insulating layer 114 may be disposed on the first interlayer insulating layer 113. A contact hole for exposing the first active layer ACT1 of the first transistor T1 may be formed in the second interlayer insulating layer 114. The second interlayer insulating layer 114 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof.

[0070] A first source electrode SE1 and a first drain electrode DE1 of the first transistor T1 may be disposed on the second interlayer insulating layer 114.

[0071] The first source electrode SE1 and the first drain electrode DE1 of the first transistor T1 may be connected to the first active layer ACT1 of the first transistor T1 through contact holes formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. Therefore, the first source electrode SE1 of the first transistor T1 may be connected to the first source region of the first active layer ACT1 through contact holes formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. And, the first drain electrode DE1 of the first transistor T1 may be connected to the first drain region of the first active layer ACT1 through contact holes formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114.

[0072] The storage capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2.

[0073] The first capacitor electrode Cst1 may be disposed on the gate insulating layer 112. The first capacitor electrode Cst1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first capacitor electrode Cst1 may be made of the same material as the first gate electrode GE1, but is not limited thereto.

[0074] The second capacitor electrode Cst2 may be disposed on the first interlayer insulating layer 113. The second capacitor electrode Cst2 may be disposed on the first interlayer insulating layer 113 so as to overlap the first capacitor electrode Cst1. For example, the second capacitor electrode Cst2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0075] A passivation layer may be disposed on the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1 and the second interlayer insulating layer 114. The passivation layer is an insulating layer that protects the underlying elements and may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

[0076] A first planarization layer 115 may be disposed on the second interlayer insulating layer 114. The first planarization layer 115 is intended to reduce steps in the underlying structure and may be formed of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0077] A connecting electrode CE may be disposed on the first planarization layer 115. The connecting electrode CE may be electrically connected to the first drain electrode DE1 of the first transistor T1 through a contact hole formed in the first planarization layer 115. The connecting electrode CE may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0078] A second planarization layer 116 may be disposed on the connecting electrode CE and the first planarization layer 115. The second planarization layer 116 is intended to reduce steps in the underlying structure and may be made of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0079] The light emitting element 120 may be disposed on the second planarization layer 116. The light emitting element 120 may include a first electrode 121, a light emitting structure 122, and a second electrode 123.

[0080] The first electrode 121 may be disposed on the second planarization layer 116. The first electrode 121 is an anode electrode and may be electrically connected to the first drain electrode DE1 of the first transistor T1 through a contact hole.

[0081] Since the display device 100 according to an embodiment of the present specification is a top-emission display device, the first electrode 121 may be formed as a multi-layer structure including a transparent conductive layer and a reflective layer with high reflectivity. The transparent conductive layer may be made of a material with a relatively high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The reflective layer may be formed as a single layer or a multi-layer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. For example, the first electrode 121 may be formed as a structure in which a transparent conductive layer, a reflective layer, and another transparent conductive layer are sequentially stacked. However, the present invention is not limited thereto, and the first electrode 121 may also be formed as a structure in which a transparent conductive layer and a reflective layer are sequentially stacked.

[0082] A bank layer 117 may be disposed on the first electrode 121 and the second planarization layer 116 .

[0083] An opening for exposing the first electrode 121 may be formed in the bank layer 117. The bank layer 117 may also be referred to as a pixel defining layer because it may define a light emitting region of the display device 100. The bank layer 117 may be formed of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0084] Spacers 117a may further be disposed on the bank layer 117.

[0085] The spacers 117a may serve to support a mask when the mask is aligned on the bank layer 117 during a process for depositing the first electrode 121. The spacers 117a may be formed integrally with the bank layer 117. The spacers 117a may be formed of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0086] The light emitting structure 122 may be disposed on the first electrode 121. The light emitting structure 122 may include a material capable of emitting light of a specific color. For example, the light emitting structure 122 may include a light emitting material capable of emitting any one of red, green, and blue light. Specifically, the light emitting structure 122 may include at least one layer selected from a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). Some components of the light emitting structure 122 may be omitted depending on the structure and characteristics of the display device 100.

[0087] A second electrode 123 may be further disposed on the light emitting structure 122, the bank layer 117, and the spacers 117a. The second electrode 123 is a cathode electrode and may be disposed on the light emitting structure 122 to face the first electrode 121 across the light emitting structure 122. The second electrode 123 supplies electrons to the light emitting structure 122. For example, the second electrode 123 may be made of a conductive material with a low work function. When the display device 100 is a top emission display device, the second electrode 123 may be made of a transparent conductive oxide such as indium tin oxide or indium zinc oxide, or a transparent conductive material such as ytterbium (Yb), but is not limited thereto.

[0088] 5 is an enlarged plan view of one pixel of a display device according to an embodiment of the present specification. FIG. 5 is an enlarged plan view of the red subpixel SPR, green subpixel SPG, and blue subpixel SPB constituting one pixel PX. For ease of explanation, FIG. 5 only shows the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, driving transistor DT, storage capacitor Cst, data line DL, high-potential power supply line VDDL, reference voltage line RL, first scan signal line SL1, second scan signal line SL2, emission signal line EML, first wide-viewpoint signal line SHL1, second wide-viewpoint signal line SHL2, first narrow-viewpoint signal line PRL1, second narrow-viewpoint signal line PRL2, clock signal line CLKL, gate high voltage line VGHL, and gate low voltage line VGLL.

[0089] Referring to FIG. 5, the display device 100 may include a plurality of red subpixels SPR, a plurality of green subpixels SPG, a plurality of blue subpixels SPB, and a plurality of gate blocks GB.

[0090] The gate blocks GB may include a plurality of first gate blocks GB1 and a plurality of second gate blocks GB2. The gate blocks GB1 and GB2 may be disposed on one side of one of the red subpixel SPR, green subpixel SPG, and blue subpixel SPB. For example, when the red subpixel SPR, green subpixel SPG, and blue subpixel SPB are sequentially arranged along the row direction, the first gate block GB1 may be disposed to the right of the blue subpixel SPB, and the second gate block GB2 may be disposed to the left of the red subpixel SPR. However, the arrangement order of the red subpixel SPR, green subpixel SPG, blue subpixel SPB, and gate blocks GB1 and GB2 is not limited thereto. The first gate block GB1 may include a divided gate driver. For example, the first gate block GB1 may include a clock signal line CLKL for supplying a clock signal to the gate driver, a gate high voltage line VGHL for supplying a gate high voltage, and a gate low voltage line VGLL for supplying a gate low voltage. The second gate block GB2 may be arranged with a first narrow-field signal wiring PRL1 extending along the column direction to provide a narrow-field mode signal, a first wide-field signal wiring SHL1 to provide a wide-field mode signal, a high-potential power supply wiring VDDL to supply a high-potential power supply, and a low-potential power supply wiring VSSL to supply a low-potential power supply.

[0091] 5, a data line DL, a high potential power line VDDL, and a reference voltage line RL may be arranged in a column direction on the substrate 110. For example, the data line DL, the high potential power line VDDL, and the reference voltage line RL may be arranged in this order from left to right. The data line DL, the high potential power line VDDL, and the reference voltage line RL may be arranged in the same layer on the substrate 110 and may be made of the same material. For example, the data line DL, the high potential power line VDDL, and the reference voltage line RL may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0092] The data wirings DL extend in a column direction on the substrate 110 and can transmit data voltages supplied from a data driver to the sub-pixels SPR, SPG, and SPB.

[0093] The high potential power supply wiring VDDL extends in the column direction on the substrate 110 and can transmit a high potential voltage for driving the light emitting elements to the sub-pixels SPR, SPG, and SPB.

[0094] The reference voltage line RL extends in the column direction on the substrate 110 and can transmit a reference voltage to each of the sub-pixels SPR, SPG, and SPB.

[0095] 5, a plurality of gate lines GL extending in the row direction may be disposed on the substrate 110. The plurality of gate lines GL may include a first scan signal line SL1, a second scan signal line SL2, an emission signal line EML, a second wide-viewpoint signal line SHL2, and a second narrow-viewpoint signal line PRL2. The first scan signal line SL1, the second scan signal line SL2, the emission signal line EML, the second wide-viewpoint signal line SHL2, and the second narrow-viewpoint signal line PRL2 may be disposed parallel to and spaced apart from each other. The first scan signal line SL1, the second scan signal line SL2, the emission signal line EML, the second wide-viewpoint signal line SHL2, and the second narrow-viewpoint signal line PRL2 may be disposed on the same layer on the substrate 110 and made of the same material. For example, the first scan signal line SL1, the second scan signal line SL2, the light emitting signal line EML, the second wide-view signal line SHL2, and the second narrow-view signal line PRL2 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0096] The first scan signal line SL1 may extend in a row direction on the substrate 110 and intersect with the data line DL, the high potential power line VDDL, and the reference voltage line RL, which extend in a column direction. The first scan signal line SL1 may transmit first scan signals supplied from the gate driver to the sub-pixels SPR, SPG, and SPB.

[0097] The second scan signal line SL2 extends in the row direction on the substrate 110 and may intersect with the data line DL, the high potential power supply line VDDL, and the reference voltage line RL, which extend in the column direction. The second scan signal line SL2 may transmit second scan signals supplied from the gate driver to each of the sub-pixels SPR, SPG, and SPB. Although FIG. 3 illustrates two second scan signal lines SL2 transmitting the second scan signals, this is not limiting and one second scan signal line SL2 may be disposed depending on the design.

[0098] The light emitting signal wiring EML extends in the row direction on the substrate 110 and may intersect with the data wiring DL, the high potential power supply wiring VDDL, and the reference voltage wiring RL, which extend in the column direction. The light emitting signal wiring EML may transmit light emitting signals supplied from the gate driver to each of the sub-pixels SPR, SPG, and SPB. Although FIG. 4 illustrates two light emitting signal wirings EML transmitting light emitting signals, this is not limiting and one light emitting signal wiring EML may be disposed depending on the design.

[0099] The second wide-view signal line SHL2 extends in a row direction on the substrate 110 and may be electrically connected to the first wide-view signal line SHL1 extending in a column direction through contact holes. The second wide-view signal line SHL2 may transmit wide-view mode signals to the sub-pixels SPR, SPG, and SPB.

[0100] The second narrow-viewing signal line PRL2 extends in a row direction on the substrate 110 and may be electrically connected to the first narrow-viewing signal line PRL1 extending in a column direction through contact holes. The second narrow-viewing signal line PRL2 may transmit a narrow-viewing mode signal to each of the sub-pixels SPR, SPG, and SPB.

[0101] Figure 6 is a schematic diagram illustrating the first region of Figure 1. For ease of explanation, Figure 6 only shows the first scan driver region SDA1, the second scan driver region SDA2, the light emitting driver region EMA, and a plurality of gate blocks GB arranged in region A.

[0102] The display device 100 according to an embodiment of the present disclosure includes a gate driver.

[0103] The gate driver includes a first scan driver, a second scan driver, and an emission driver that output scan signals and emission signals in response to gate timing control signals. The gate driver receives clock signals, gate control signals, etc., and generates and outputs signals that can turn on or off transistors disposed on the substrate 110. Specifically, the first scan driver, the second scan driver, and the emission driver output scan signals or emission signals of low or high voltages to transistors disposed in each subpixel. For example, the first scan driver outputs a first scan signal SCAN1 to a first scan signal line SL1 connected to the first scan driver in response to a gate control signal from the timing controller. The second scan driver outputs a second scan signal SCAN2 to a second scan signal line SL2 connected to the second scan driver in response to a gate control signal from the timing controller. The emission driver outputs an emission signal EM to an emission signal line EML connected to the emission driver in response to a gate control signal from the timing controller.

[0104] Referring to FIG. 6, a first scan driver area SDA1, a second scan driver area SDA2, and a light emitting driver area EMA may be arranged in a display area AA.

[0105] The first scan driver region SDA1 is a region where the first scan driver is arranged, the second scan driver region SDA2 is a region where the second scan driver is arranged, and the light emitting driver region EMA is a region where the light emitting driver is arranged. The first scan driver region SDA1, the second scan driver region SDA2, and the light emitting driver region EMA each include a plurality of first gate blocks GB1 and a plurality of second gate blocks GB2.

[0106] The plurality of first gate blocks GB1 and the plurality of second gate blocks GB2 may be arranged in the column direction in the display area AA. For example, the first scan driver area SDA1, the second scan driver area SDA2, and the light emitting driver area EMA may each have three first gate blocks GB1 and two second gate blocks GB2 arranged in the column direction. The first scan driver area SDA1, the second scan driver area SDA2, and the light emitting driver area EMA may each have a plurality of first gate blocks GB1 and a plurality of second gate blocks GB2 arranged alternately in the row direction. However, this is not limited thereto, and the number and arrangement of the plurality of first gate blocks GB1 and the plurality of second gate blocks GB2 may be changed according to design.

[0107] The first gate blocks GB1 may include a first scan driver, a second scan driver, and a light emission driver, which are respectively arranged separately. The second gate blocks GB2 may include a plurality of power supply lines for transmitting constant voltages to the subpixels SPR, SPG, and SPB, a plurality of first narrow-viewpoint signal lines PRL1 for providing narrow-viewpoint mode signals, and a plurality of first wide-viewpoint signal lines SHL1 for providing wide-viewpoint mode signals. For example, the power supply lines may include a high-potential power supply line VDDL and a low-potential power supply line VSSL.

[0108] Figure 7 is an enlarged plan view of one of the gate drivers of Figure 6. Figure 7 shows only some gate blocks GB1 and GB2 arranged in the first scan driver area SDA1.

[0109] 7, the plurality of first gate blocks GB1 may include a 1-1 gate block GB1-1, a 1-2 gate block GB1-2, and a 1-3 gate block GB1-3. The 1-1 gate block GB1-1, the 1-2 gate block GB1-2, and the 1-3 gate block GB1-3 may be arranged such that the first scan driver configuration is divided.

[0110] The 1-1 gate block GB1-1 may include a 1-1 transistor T1-1, a 1-2 transistor T1-2, a 1-3 transistor T1-3, and a first capacitor CB.

[0111] The first transistor T1-1 may include a first source electrode SE1-1, a first drain electrode DE1-1, a first gate electrode GE1-1, and a first active layer ACT1-1. The first source electrode SE1-1 may be electrically connected to a gate low voltage line VGLL to which a gate low voltage is applied. The first drain electrode DE1-1 may be electrically connected to a first gate electrode GE1-2 of the first transistor T1-2 and a first gate electrode G1-3 of the first transistor T1-3. The first gate electrode GE1-1 may be electrically connected to a clock line CLKL to which a clock signal is applied. The first active layer ACT1-1 may overlap the first gate electrode GE1-1 below the first gate electrode GE1-1.

[0112] The first-second transistor T1-2 may include a first-second source electrode SE1-2, a first-second drain electrode DE1-2, a first-second gate electrode GE1-2, and a first-second active layer ACT1-2. The first-second source electrode SE1-2 may be electrically connected to a gate high voltage line VGHL to which a gate high voltage is applied. The first-second drain electrode DE1-2 may be electrically connected to the first-second gate block GB1-2. The first-second gate electrode GE1-2 may be electrically connected to the drain electrode DE1-1 of the first-first transistor T1-1 and the first-third gate electrode G1-3 of the first-third transistor T1-3. The first-second active layer ACT1-2 may overlap the first-second gate electrode GE1-2 below the first-second gate electrode GE1-2.

[0113] The first-third transistor T1-3 may include a first-third source electrode SE1-3, a first-third drain electrode DE1-3, a first-third gate electrode GE1-3, and a first-third active layer ACT1-3. The first-third source electrode SE1-3 may be electrically connected to a gate high voltage line VGHL. The first-third drain electrode DE1-3 may be electrically connected to a first scan signal line SL1 through which a first scan signal is transmitted. The first-third gate electrode GE1-3 may be electrically connected to the drain electrode DE1-1 of the first-first transistor T1-1 and the first-second gate electrode G1-2 of the first-second transistor T1-2. The first-third active layer ACT1-3 may overlap the first-third gate electrode GE1-3 below the first-third gate electrode GE1-3.

[0114] The first capacitor CB may be electrically connected to the first-third gate electrode GE1-3 of the first-third transistor T1-3 and the gate high voltage line VGHL.

[0115] The first-second gate block GB1-2 may include a fourth transistor T1-4, a fifth transistor T1-5, and a sixth transistor T1-6.

[0116] The 1-4th transistor T1-4 may include a 1-4th source electrode SE1-4, a 1-4th drain electrode DE1-4, a 1-4th gate electrode GE1-4, and a 1-4th active layer ACT1-4. The 1-4th source electrode SE1-4 may be electrically connected to a gate-low voltage line VGLL to which a gate-low voltage is applied. The 1-4th drain electrode DE1-4 may be electrically connected to the 1-2th drain electrode DE1-2 of the 1-2th transistor T1-2, the 1-7th transistor T1-7 of the 1-3th gate block GB1-3, and the 1-6th gate electrode GE1-6 of the 1-6th transistor T1-6. The 1-4th gate electrode GE1-4 may be electrically connected to the 1-5th gate electrode GE1-5 of the 1-5th transistor T1-5. The 1-4th active layer ACT1-4 may overlap the 1-4th gate electrode GE1-4 below the 1-4th gate electrode GE1-4.

[0117] The 1-5th transistor T1-5 may include a 1-5th source electrode SE1-5, a 1-5th drain electrode DE1-5, a 1-5th gate electrode GE1-5, and a 1-5th active layer ACT1-5. The 1-5th source electrode SE1-5 may be electrically connected to the 1-6th source electrode SE1-6 of the 1-6th transistor T1-6, the first capacitor CB, and the 1-3rd gate electrode GE1-3 of the 1-3th transistor T1-3. The 1-5th drain electrode DE1-5 may be electrically connected to a gate high voltage line VGHL to which a gate high voltage is applied. The 1-5th gate electrode GE1-5 may be electrically connected to the 1-4th gate electrode GE1-4 of the 1-4th gate electrode GE1-4. The 1-5th active layer ACT1-5 may overlap the 1-5th gate electrode GE1-5 below the 1-5th gate electrode GE1-5.

[0118] The 1-6th transistor T1-6 may include a 1-6th source electrode SE1-6, a 1-6th drain electrode DE1-6, a 1-6th gate electrode GE1-6, and a 1-6th active layer ACT1-6. The 1-6th source electrode SE1-6 may be electrically connected to the 1-5th source electrode SE1-5 of the 1-5th transistor T1-5, the first capacitor CB, and the 1-3rd gate electrode GE1-3 of the 1-3th transistor T1-3. The 1-6th drain electrode DE1-6 may be electrically connected to a gate high voltage line VGHL to which a gate high voltage is applied. The 1-6th gate electrode GE1-6 may be electrically connected to the 1-4th drain electrode DE1-4 of the 1-4th gate electrode GE1-4. The 1-6th active layer ACT1-6 may overlap the 1-6th gate electrode GE1-6 below the 1-6th gate electrode GE1-6.

[0119] The 1-3 gate block GB1-3 may include a 1-7 transistor T1-7, a 1-8 transistor T1-8, and a second capacitor CQ.

[0120] The 1-7th transistor T1-7 may include a 1-7th source electrode SE1-7, a 1-7th drain electrode DE1-7, a 1-7th gate electrode GE1-7, and a 1-7th active layer ACT1-7. The 1-7th source electrode SE1-7 may be electrically connected to the 1-4th drain electrode DE1-4 of the 1-4th transistor T1-4 and the 1-2nd drain electrode DE1-2 of the 1-2nd transistor T1-2. The 1-7th drain electrode DE1-7 may be electrically connected to the 1-8th gate electrode GE1-8 of the 1-8th transistor T1-8. The 1-7th gate electrode GE1-7 may be electrically connected to a gate-low voltage line VGLL to which a gate-low voltage is applied. The 1-7th active layer ACT1-7 may overlap the 1-7th gate electrode GE1-7 below the 1-7th gate electrode GE1-7.

[0121] The 1-8th transistor T1-8 may include a 1-8th source electrode SE1-8, a 1-8th drain electrode DE1-8, a 1-8th gate electrode GE1-8, and a 1-8th active layer ACT1-8. The 1-8th source electrode SE1-8 may be electrically connected to a gate high voltage line VGHL to which a gate high voltage is applied. The 1-8th drain electrode DE1-8 may be electrically connected to the second capacitor CQ. The 1-8th gate electrode GE1-8 may be electrically connected to the 1-7th drain electrode DE1-7 of the 1-7th transistor T1-7 and the second capacitor CQ. The 1-8th active layer ACT1-8 may overlap the 1-8th gate electrode GE1-8 below the 1-8th gate electrode GE1-8.

[0122] The second capacitor CQ may be electrically connected to the 1-8 gate electrode GE1-8 of the 1-8 transistor T1-8, the 1-8 drain electrode DE1-8 of the 1-8 transistor T1-8, and the first scan signal line SL1 through which the first scan signal is transmitted.

[0123] In the second gate blocks GB2, a plurality of gate lines GL extending in the row direction and a power supply line VDDL extending in the column direction so as to intersect with the plurality of gate lines GL can be arranged.

[0124] Figure 8 is a schematic diagram illustrating the second region A2 of Figure 1. For ease of explanation, Figure 8 only shows the first scan driver region SDA1, the second scan driver region SDA2, the light emitting driver region EMA, and a plurality of gate blocks GB arranged in the second region A2 of Figure 1. In the following, the remaining configuration is the same as that of Figure 6 except for the plurality of gate blocks GB, which is the difference, and therefore will not be described again.

[0125] 8, the second region A2 may have a smaller area than the first region A1 due to the notch region NTA. Therefore, the number of gate blocks GB arranged in each of the first scan driver region SDA1, the second scan driver region SDA2, and the light emitting driver region EMA may be smaller than that of the first region A1. For example, the first scan driver region SDA1, the second scan driver region SDA2, and the light emitting driver region EMA arranged in the second region A2 may each have two first gate blocks GB1 and two second gate blocks GB2 arranged in the column direction. While FIG. 6 shows one less first gate block GB1 than FIG. 4, the number of first gate blocks GB1 and second gate blocks GB2 arranged in the second region A2 may vary depending on the area and design, and is not limited thereto.

[0126] Fig. 9 is an enlarged plan view of one of the gate blocks in Fig. 8. Fig. 9 shows an enlarged view of a part of the second gate block GB2 out of the plurality of gate blocks GB in Fig. 8.

[0127] Referring to FIG. 9, a plurality of gate lines GL, a high potential power line VDDL, and a first compensation pattern 130 may be arranged in the second gate block GB2 arranged in the second region A2.

[0128] The plurality of gate lines GL may extend in the row direction in the second gate block GB2 and be arranged in parallel to each other and spaced apart from each other in the column direction.

[0129] The high-potential power supply wiring VDDL can be arranged in the second gate block GB2 so as to extend in the column direction and intersect with the plurality of gate wirings GL.

[0130] The first compensation pattern 130 may be arranged in the second gate block GB2 so as to extend in the column direction and overlap with the gate lines GL. The first compensation pattern 130 may extend in the row direction from the high-potential power supply line VDDL and be integrated with the high-potential power supply line VDDL. Thus, the first compensation pattern may function as the high-potential power supply line, and the high-potential power supply line may also function as the first compensation pattern.

[0131] The first compensation pattern 130 may have a constant width from the top to the bottom of the second gate block GB2. The width of the high potential power line VDDL and the first compensation pattern 130 arranged in the second gate block GB2 in the second region A2 may be larger than the width of the high potential power line VDDL arranged in the second gate block GB2 in the first region A1. That is, the area of ​​the high potential power line VDDL and the first compensation pattern 130 arranged in the second gate block GB2 in the second region A2 overlapping with the plurality of gate lines GL may be larger than the area of ​​the high potential power line VDDL and the plurality of gate lines GL overlapping with the second gate block GB2 in the first region A1.

[0132] 10 is a cross-sectional view taken along line VIII-VIII' in FIG. 9. For ease of explanation, FIG. 10 only shows the substrate 110, buffer layer 111, gate insulating layer 112, gate line GL, first interlayer insulating layer 113, second interlayer insulating layer 114, first compensation pattern 130, first planarization layer 115, and second planarization layer 116. Hereinafter, the remaining configuration is the same as FIG. 4 except for the gate line GL and first compensation pattern 130, and therefore detailed description thereof will be omitted.

[0133] Referring to FIG. 10, a gate line GL may be disposed on the gate insulating layer 112.

[0134] The gate line GL may be formed in the same layer and made of the same material as the first gate electrode GE1 of the first transistor T1. For example, the gate line GL may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0135] A first compensation pattern 130 may be disposed on the second interlayer insulating layer 114 .

[0136] The first compensation pattern 130 may be disposed on the second interlayer insulating layer 114 to overlap the gate line GL. The first compensation pattern 130 may be formed in the same layer and made of the same material as the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1. For example, the first compensation pattern 130 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0137] In the conventional display device, the substrate is a rectangular substrate without any irregular structure on any side, and the output characteristics of the gate signal output from the gate driver are the same at all positions in the display area. However, in the case of an irregular display device in which one or more of the four sides of the substrate that is not a rectangular substrate have an irregular structure, the output characteristics of the gate signal are the same in the area without the irregular structure, but the output characteristics of the gate signal are different in the area with the irregular structure compared to the area without the irregular structure, resulting in non-uniform brightness.

[0138] Therefore, in a display device 100 according to an embodiment of the present specification, a display area AA is divided into a plurality of first areas A1 and at least one second area A2 arranged to correspond to the notch area. A plurality of gate blocks GB1 and GB2, in which gate drivers are divided, are arranged in each of the first area A1 and the second area A2. The second area A2, which is smaller in area than the first area A1 due to the notch area, has fewer gate blocks GB1 and GB2 than the first area A1, resulting in different gate signal output characteristics. Accordingly, a first compensation pattern 130 is arranged in at least one gate block GB2 of the plurality of gate blocks GB1 and GB2 arranged in the second area A2 to overlap with the gate line GL. A capacitor is formed between the gate line GL and the first compensation pattern 130, thereby compensating for RC delays of gate signals output from the plurality of gate blocks GB1 and GB2 arranged in the second area A2. That is, the output characteristics of the gate signals output from the gate blocks GB1 and GB2 arranged in the second region A2 can be made the same as the output characteristics of the gate signals output from the gate blocks GB1 and GB2 arranged in the first region A1. Therefore, in the display device 100 according to an embodiment of the present specification, the RC delay of the gate signals changed due to the irregular structure can be compensated to be the same as that in a region without the irregular structure, thereby reducing brightness unevenness and improving display quality.

[0139] Furthermore, if a gate driver that outputs a gate signal and a compensation pattern for compensating for RC delay deviation due to a non-uniform structure are disposed in the non-display area, the area of ​​the non-display area increases, resulting in a problem of an increased bezel area.

[0140] Therefore, in the display device 100 according to an embodiment of the present specification, a plurality of gate blocks GB1, GB2 in which the gate drivers are divided and arranged are distributed in the display area AA, and a compensation pattern 130 for compensating for the RC delay deviation is arranged in at least one gate block GB2 of the plurality of gate blocks GB1, GB2 arranged in the second area A2, thereby minimizing the area of ​​the non-display area NA. Therefore, in the display device 100 according to an embodiment of the present specification, the gate drivers and the compensation pattern 130 are arranged within the display area, thereby minimizing the bezel area.

[0141] 11 is an enlarged plan view of one of the gate blocks of a display device according to another embodiment of the present specification. Fig. 11 shows an enlarged view of a portion of a second gate block GB2 among the gate blocks GB of a display device 200 according to another embodiment of the present specification.

[0142] Referring to FIG. 11, a high potential power supply line VDDL, a first compensation pattern 230, and a plurality of gate lines GL may be arranged in the second gate block GB2 arranged in the second region A2.

[0143] The high-potential power supply wiring VDDL can be arranged in the second gate block GB2 so as to extend in the column direction and intersect with the plurality of gate wirings GL.

[0144] The first compensation pattern 230 may be arranged in the second gate block GB2 to extend in the column direction and overlap with the gate lines GL. The first compensation pattern 230 may extend in the row direction from the high-potential power supply line VDDL and be integrated with the high-potential power supply line VDDL. Therefore, the first compensation pattern may function as the high-potential power supply line, and the high-potential power supply line may also function as the first compensation pattern.

[0145] The first compensation pattern 230 may have a constant width from the top to the bottom of the second gate block GB2. The width of the high potential power line VDDL and the first compensation pattern 230 arranged in the second gate block GB2 in the second region A2 may be larger than the width of the high potential power line VDDL arranged in the second gate block GB2 in the first region A1. That is, the area of ​​the high potential power line VDDL and the first compensation pattern 230 arranged in the second gate block GB2 in the second region A2 overlapping with the plurality of gate lines GL may be larger than the area of ​​the high potential power line VDDL and the plurality of gate lines GL overlapping with the second gate block GB2 in the first region A1.

[0146] The plurality of gate lines GL may extend in the row direction in the second gate block GB2 and be arranged parallel to and spaced apart from each other in the column direction. The width of the portions of the plurality of gate lines GL overlapping with the first compensation pattern 230 may be greater than the width of the portions of the plurality of gate lines GL not overlapping with the first compensation pattern 230. For example, the portions of the plurality of gate lines GL overlapping with the high potential power supply line VDDL and the first compensation pattern 230 may be greater in width than the portions not overlapping with the high potential power supply line VDDL and the first compensation pattern 230. For example, the portions of the plurality of gate lines GL having a greater width may be portions of the plurality of gate lines GL overlapping with the high potential power supply line VDDL and the first compensation pattern 230 extending in the column direction.

[0147] In addition, the width of the wide portion of each of the gate lines GL may differ depending on the output of the gate driver connected to each gate line GL. For example, if the output of the gate driver connected to a gate line GL is greater than the output of the gate driver connected to another gate line GL, the width of the portion of the corresponding gate line GL overlapping with the high potential power line VDDL and the first compensation pattern 230 may be wider than the width of the portion of the other gate lines GL overlapping with the high potential power line VDDL and the first compensation pattern 230.

[0148] In a display device 200 according to another embodiment of the present specification, a first compensation pattern 230 is disposed in at least one gate block GB2 of the plurality of gate blocks GB1 and GB2 disposed in the second region A2 so as to overlap with the gate line GL. A capacitor is formed between the gate line GL and the first compensation pattern 230, thereby compensating for the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second region A2. Therefore, in the display device 200 according to another embodiment of the present specification, the RC delay of the gate signals changed due to the irregular structure is compensated to be the same as that in a region without the irregular structure, thereby reducing brightness unevenness and improving display quality.

[0149] In a display device 200 according to another embodiment of the present specification, a plurality of gate blocks GB1 and GB2, into which a gate driver is divided, are distributed in the display area AA, and a first compensation pattern 230 for compensating for an RC delay deviation is disposed in at least one gate block GB2 of the plurality of gate blocks GB1 and GB2 disposed in the second area A2, thereby minimizing the area of ​​the non-display area NA. Therefore, in a display device 200 according to another embodiment of the present specification, the gate driver and the first compensation pattern 230 are disposed within the display area, thereby minimizing the bezel area.

[0150] In a display device 200 according to another embodiment of the present specification, the width of a portion of the plurality of gate lines GL overlapping with the first compensation pattern 230 may be greater than the width of a portion of the plurality of gate lines GL not overlapping with the first compensation pattern 230. In this case, the width of the portion overlapping with the first compensation pattern 230 can be designed to vary depending on the output of the gate driver to which the gate line GL is connected. Thus, RC delay can be compensated for in accordance with the output characteristics of the gate signals output from the plurality of gate blocks GB1 and GB2 arranged in the second region A2. Therefore, in the display device 200 according to another embodiment of the present specification, RC delay can be compensated for depending on the output of the gate driver to which the gate line GL is connected, thereby improving design flexibility and display quality.

[0151] FIG. 12 is an enlarged plan view of one of the gate blocks of a display device according to still another embodiment of the present disclosure.

[0152] FIG. 12 shows an enlarged view of a part of a second gate block GB2 among a plurality of gate blocks GB of a display device 300 according to still another embodiment of the present specification.

[0153] Referring to FIG. 12, the second gate block GB2 disposed in the second region A2 may include a high potential power supply line VDDL, a first compensation pattern 230, and a plurality of gate lines GL.

[0154] The plurality of gate lines GL may extend in the row direction in the second gate block GB2 and may be arranged in parallel to each other and spaced apart from each other in the column direction. The plurality of gate lines GL may have a uniform width.

[0155] The high-potential power supply wiring VDDL may be arranged to extend in the column direction in the second gate block GB2 and intersect with the gate wirings GL. The high-potential power supply wiring VDDL may have a constant width from the top end to the bottom end of the second gate block GB2.

[0156] The first compensation pattern 330 may be arranged in the second gate block GB2 to extend in the column direction and overlap with the gate lines GL. The first compensation pattern 330 may extend in the row direction from the high potential power supply line VDDL and may be integrated with the high potential power supply line VDDL.

[0157] The width of the high potential power supply wiring VDDL and the first compensation pattern 230 arranged in the second gate block GB2 in the second region A2 may be larger than the width of the high potential power supply wiring VDDL arranged in the second gate block GB2 in the first region A1. That is, the area of ​​the high potential power supply wiring VDDL and the first compensation pattern 230 arranged in the second gate block GB2 in the second region A2 overlapping with the plurality of gate wirings GL may be larger than the area of ​​the high potential power supply wiring VDDL and the plurality of gate wirings GL overlapping with the second gate block GB2 in the first region A1.

[0158] Meanwhile, the width of the first compensation pattern 330 may vary depending on the position. Because the high potential power line VDDL is constant, the combined width of the high potential power line VDDL and the first compensation pattern 330 may vary depending on the position. The width of the first compensation pattern 330 may vary depending on the output of the gate driver connected to each gate line GL. For example, if the output of the gate driver connected to a gate line GL is greater than the output of the gate driver connected to another gate line GL, the width of the first compensation pattern 330 overlapping the corresponding gate line GL may be wider than the width of the first compensation pattern 330 overlapping the other gate line GL. Although FIG. 12 illustrates a configuration in which the widths of the high potential power line VDDL and the first compensation pattern 330 become narrower at the center toward the bottom, this is not limiting.

[0159] Therefore, in a display device 300 according to another embodiment of the present specification, a first compensation pattern 330 is disposed in at least one gate block GB2 of the plurality of gate blocks GB1 and GB2 disposed in the second region A2 so as to overlap with the gate line GL, and a capacitor is formed between the gate line GL and the first compensation pattern 330, thereby compensating for the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second region A2. Therefore, in the display device 300 according to another embodiment of the present specification, the RC delay of the gate signals changed due to the irregular structure is compensated to be the same as that in a region without the irregular structure, thereby reducing brightness unevenness and improving display quality.

[0160] In a display device 300 according to another embodiment of the present specification, a plurality of gate blocks GB1 and GB2, into which a gate driver is divided, are distributed in the display area AA, and a first compensation pattern 330 for compensating for an RC delay deviation is disposed in at least one gate block GB2 of the plurality of gate blocks GB1 and GB2 disposed in the second area A2, thereby minimizing the area of ​​the non-display area NA. Therefore, in a display device 300 according to another embodiment of the present specification, the gate driver and the first compensation pattern 330 are disposed within the display area, thereby minimizing the bezel area.

[0161] In a display device 300 according to another embodiment of the present disclosure, the width of the gate lines GL is constant, and the width of the first compensation pattern 330 overlapping the gate lines GL may vary depending on the position. Therefore, various capacitors may be formed between the gate lines GL and the first compensation pattern 330, and RC delay may be compensated for in accordance with the output characteristics of the gate signals output from the gate blocks GB1 and GB2 arranged in the second region A2. Therefore, in the display device 300 according to another embodiment of the present disclosure, RC delay may be compensated for according to the output of the gate driver to which the gate lines GL are connected, thereby improving design flexibility and display quality.

[0162] 13 is a cross-sectional view of a display device according to another embodiment of the present disclosure. For convenience of explanation, only the substrate 410, the first transistor T1, the storage capacitor Cst, the first buffer layer 411, the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second transistor T2, the second gate insulating layer 415, the second interlayer insulating layer 416, the first planarization layer 417, the connecting electrode CE, the second planarization layer 418, the light emitting element 420, the bank layer 419, and the spacer 419a are shown in FIG. 13 among various components of the display device 400 according to the embodiment of the present disclosure.

[0163] Referring to FIG. 13, a display device 400 according to another embodiment of the present specification includes a substrate 410, a first transistor T1, a storage capacitor Cst, a first buffer layer 411, a first gate insulating layer 412, a first interlayer insulating layer 413, a second buffer layer 414, a second transistor T2, a second gate insulating layer 415, a second interlayer insulating layer 416, a first planarization layer 417, a connecting electrode CE, a second planarization layer 418, a light-emitting element 420, and a bank layer 419.

[0164] The substrate 410 is a base member for supporting various components of the display device 400 and may be made of an insulating material. For example, the substrate may be made of glass or plastic, but is not limited thereto.

[0165] A first buffer layer 411 may be disposed on the substrate 410. The first buffer layer 411 may be formed on the entire surface of the substrate 410. The first buffer layer 411 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. The first buffer layer 411 may improve adhesion between the substrate 410 and a layer formed on the first buffer layer 411. The first buffer layer 411 is not an essential component and may be omitted depending on the type and material of the substrate 410, the structure and type of the transistor, etc.

[0166] The first transistor T1 may be disposed on the first buffer layer 411. The first transistor T1 may include a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. The first active layer ACT1 of the first transistor T1 may be disposed on the buffer layer 411.

[0167] The first active layer ACT1 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0168] A first gate insulating layer 412 may be disposed on the first active layer ACT1 of the first transistor T1. The first gate insulating layer 412 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or a multi-layer thereof. Contact holes may be formed in the first gate insulating layer 412 to connect the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1 to the first active layer ACT1 of the first transistor T1.

[0169] A first gate electrode GE1 of the first transistor T1 may be disposed on the first gate insulating layer 412. The first gate electrode GE1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first gate electrode GE1 may be formed on the first gate insulating layer 412 to overlap with the first active layer ACT1 of the first transistor T1.

[0170] A first interlayer insulating layer 413 may be disposed on the first gate insulating layer 412 and the first gate electrode GE1. The first interlayer insulating layer 413 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. A contact hole may be formed in the first interlayer insulating layer 413 to expose the first active layer ACT1 of the first transistor T1.

[0171] A second buffer layer 414 may be disposed on the first interlayer insulating layer 413. The second buffer layer 414 may be formed on the entire surface of the substrate 410. The second buffer layer 414 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. A contact hole may be formed in the second buffer layer 414 to expose the first active layer ACT1 of the first transistor T1.

[0172] A second transistor T2 may be disposed on the second buffer layer 414. The second transistor T2 may include a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2. The second active layer ACT2 of the second transistor T2 may be disposed on the second buffer layer 414.

[0173] The second active layer ACT2 may be made of an oxide semiconductor. For example, the second active layer ACT2 may be made of a metal oxide, such as various metal oxides, such as IGZO (indium-gallium-zinc-oxide). While the second active layer ACT2 of the second transistor T2 has been described as being formed based on an IGZO layer, assuming that it is made of IGZO among various metal oxides, the second active layer ACT2 is not limited thereto and may be formed of other metal oxides such as IZO (indium-zinc-oxide), IGTO (indium-gallium-tin-oxide), or IGO (indium-gallium-oxide).

[0174] A second gate insulating layer 415 may be disposed on the second active layer ACT2 of the second transistor T2. The second gate insulating layer 415 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. Contact holes may be formed in the second gate insulating layer 415 to connect the second source electrode SE2 and the second drain electrode DE2 of the second transistor T2 to the second active layer ACT2 of the second transistor T2.

[0175] A second gate electrode GE2 of the second transistor T2 may be disposed on the second gate insulating layer 415. The second gate electrode GE2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof. The second gate electrode GE2 may be formed on the second gate insulating layer 415 to overlap the second active layer ACT2 of the second transistor T2. Contact holes may be formed in the second gate insulating layer 415 to expose the first active layer ACT1 of the first transistor T1 and the second active layer ACT2 of the second transistor T2.

[0176] A second interlayer insulating layer 416 may be disposed on the second gate insulating layer 415 and the second gate electrode GE2. The second interlayer insulating layer 416 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. Contact holes may be formed in the second interlayer insulating layer 416 to expose the first active layer ACT1 of the first transistor T1 and the second active layer ACT2 of the second transistor T2.

[0177] A first source electrode SE1 and a first drain electrode DE1 of the first transistor T1, and a second source electrode SE2 and a second drain electrode DE2 of the second transistor T2 may be disposed on the second interlayer insulating layer 416.

[0178] The first source electrode SE1 and the first drain electrode DE1 of the first transistor T1 may be connected to the first active layer ACT1 of the first transistor T1 through contact holes formed in the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second gate insulating layer 415, and the second interlayer insulating layer 416. Therefore, the first source electrode SE1 of the first transistor T1 may be connected to the first source region of the first active layer ACT1 through contact holes formed in the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second gate insulating layer 415, and the second interlayer insulating layer 416. And, the first drain electrode DE1 of the first transistor T1 may be connected to the first drain region of the first active layer ACT1 through contact holes formed in the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second gate insulating layer 415, and the second interlayer insulating layer 416.

[0179] The second source electrode SE2 and the second drain electrode DE2 of the second transistor T2 may be connected to the second active layer ACT2 of the second transistor T2 through contact holes formed in the second gate insulating layer 415 and the second interlayer insulating layer 416. Therefore, the second source electrode SE2 of the second transistor T2 may be connected to the second source region of the second active layer ACT2 through the contact holes formed in the second gate insulating layer 415 and the second interlayer insulating layer 416. And, the second drain electrode DE2 of the second transistor T2 may be connected to the second drain region of the second active layer ACT2 through the contact holes formed in the second gate insulating layer 415 and the second interlayer insulating layer 416.

[0180] The storage capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2.

[0181] The first capacitor electrode Cst1 may be disposed on the gate insulating layer 112. The first capacitor electrode Cst1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first capacitor electrode Cst1 may be made of the same material as the first gate electrode GE1, but is not limited thereto.

[0182] The second capacitor electrode Cst2 may be disposed on the first interlayer insulating layer 113. The second capacitor electrode Cst2 may be disposed on the first interlayer insulating layer 113 so as to overlap the first capacitor electrode Cst1. For example, the second capacitor electrode Cst2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0183] A passivation layer may be disposed on the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1, the second source electrode SE2 and the second drain electrode DE2 of the second transistor T2, and the second interlayer insulating layer 416. The passivation layer is an insulating layer that protects the underlying elements and may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

[0184] A first planarization layer 417 may be disposed on the second interlayer insulating layer 416. The first planarization layer 417 is intended to reduce steps in the underlying structure and may be formed of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0185] A connecting electrode CE may be disposed on the first planarization layer 417. The connecting electrode CE may be electrically connected to the first drain electrode DE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2 through contact holes formed in the first planarization layer 417. The connecting electrode CE may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0186] A second planarization layer 418 may be disposed on the connecting electrode CE and the first planarization layer 417. The second planarization layer 418 is intended to reduce steps in the underlying structure and may be made of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0187] The light emitting element 420 may be disposed on the second planarization layer 418. The light emitting element 420 may include a first electrode 421, a light emitting structure 422, and a second electrode 423.

[0188] The first electrode 421 may be disposed on the second planarization layer 418. The first electrode 421 is an anode electrode and may be electrically connected to the first drain electrode DE1 of the first transistor T1 through a contact hole.

[0189] A bank layer 419 may be disposed on the first electrode 421 and the second planarization layer 418 .

[0190] An opening for exposing the first electrode 421 may be formed in the bank layer 419. The bank layer 419 may also be referred to as a pixel defining layer since it may define a light emitting region of the display device 400. The bank layer 419 may be formed of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0191] Spacers 419a may be further disposed on the bank layer 419. The spacers 419a may serve to support a mask when the mask is aligned on the bank layer 419 in a process for depositing the first electrode 421. The spacers 419a may be integrally formed with the bank layer 419. The spacers 419a may be formed of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0192] The light emitting structure 422 may be disposed on the first electrode 421. The light emitting structure 422 may include a material capable of emitting light of a specific color. For example, the light emitting structure 422 may include a light emitting material capable of emitting any one of red, green, and blue light. Specifically, the light emitting structure 422 may include at least one layer selected from a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). Some components of the light emitting structure 422 may be omitted depending on the structure and characteristics of the display device 400.

[0193] A second electrode 423 may be further disposed on the light emitting structure 422, the bank layer 419, and the spacers 419a. The second electrode 423 is a cathode electrode and may be disposed on the light emitting structure 422 to face the first electrode 421 across the light emitting structure 422. The second electrode 423 supplies electrons to the light emitting structure 422. The second electrode 423 may be made of a transparent conductive oxide such as indium tin oxide or indium zinc oxide, or a transparent conductive material such as ytterbium (Yb), but is not limited thereto.

[0194] Figure 14 is a cross-sectional view of one of the gate blocks of a display device according to another embodiment of the present disclosure. Figure 14 is a cross-sectional view of a second gate block GB2 among the gate blocks GB of a display device 400 according to another embodiment of the present disclosure. Figure 14 is a cross-sectional view taken at the same position as Figure 10.

[0195] 14, for ease of explanation, only the substrate 410, the first buffer layer 411, the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second gate insulating layer 415, the gate line GL, the second interlayer insulating layer 416, the first compensation pattern 430, the first planarization layer 417, and the second planarization layer 418 are shown. In the following, the remaining configuration is the same as in FIG. 11 except for the gate line GL and the first compensation pattern 430, and therefore detailed explanations thereof will be omitted.

[0196] Referring to FIG. 14, a gate line GL may be disposed on the second gate insulating layer 415.

[0197] The gate line GL may be formed in the same layer and made of the same material as the second gate electrode GE2 of the second transistor T2. For example, the gate line GL may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0198] A first compensation pattern 430 may be disposed on the second interlayer insulating layer 416 .

[0199] The first compensation pattern 430 may be disposed on the second interlayer insulating layer 416 to overlap the gate line GL. The first compensation pattern 430 may overlap the gate line GL to form a capacitor between the first compensation pattern 430 and the gate line GL. The first compensation pattern 430 may be formed in the same layer and made of the same material as the first source electrode SE1 and first drain electrode DE1 of the first transistor T1 and the second source electrode SE2 and second drain electrode DE2 of the second transistor T2. For example, the first compensation pattern 430 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0200] Therefore, in a display device 400 according to another embodiment of the present specification, a first compensation pattern 430 is disposed in at least one gate block GB2 of the plurality of gate blocks GB1 and GB2 disposed in the second region A2 so as to overlap with the gate line GL, and a capacitor is formed between the gate line GL and the first compensation pattern 430, thereby compensating for the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second region A2. Therefore, in the display device 400 according to another embodiment of the present specification, the RC delay of the gate signals changed due to the irregular structure is compensated to be the same as that in a region without the irregular structure, thereby reducing brightness unevenness and improving display quality.

[0201] In a display device 400 according to another embodiment of the present specification, a plurality of gate blocks GB1, GB2 into which a gate driver is divided are distributed in the display area AA, and a first compensation pattern 430 for compensating for an RC delay deviation is disposed in at least one gate block GB2 of the plurality of gate blocks GB1, GB2 disposed in the second area A2, thereby minimizing the area of ​​the non-display area NA. Therefore, in a display device 400 according to another embodiment of the present specification, the gate driver and the first compensation pattern 430 are disposed within the display area, thereby minimizing the bezel area.

[0202] Fig. 15 is an exemplary plan view of a display device according to still another embodiment of the present disclosure, Fig. 16 is a plan view of one of the gate blocks in the fourth region of Fig. 15, and Fig. 17 is a cross-sectional view taken along XV-XV' of Fig. 16.

[0203] For ease of explanation, Fig. 15 shows only the substrate 110 and the plurality of flexible films COF among the various components of the display device 500. In Fig. 15, the remaining configuration except for the plurality of third areas A3 and the plurality of fourth areas A4 of the display area AA is the same as Fig. 1, and therefore detailed description thereof will be omitted.

[0204] Referring to FIG. 15, the display area AA may include a plurality of third areas A3 and a plurality of fourth areas A4. The plurality of third areas A3 and the plurality of fourth areas A4 may be areas in which gate drivers are distributed. The plurality of third areas A3 may be areas having a first width in the column direction, and the plurality of fourth areas A4 may be areas arranged to correspond to the notch areas NTA and having a second width smaller than the first width of the plurality of third areas A3. For example, the fourth area A4 may be an area whose width in the column direction is smaller than the width of the third areas A3 due to the notch areas NTA. The plurality of third areas A3 may be the remaining areas excluding the fourth area A4.

[0205] 16 shows only the 1-1 gate block GB1-1 of the multiple gate blocks GB arranged in the fourth region A4. In FIG. 16, the remaining configuration except for the clock wiring CLKL and the second compensation pattern 540 is the same as in FIG. 5, so detailed description thereof will be omitted.

[0206] 16, a clock line CLKL may be connected to a plurality of gate blocks GB. A first-first gate block GB1-1 among the plurality of gate blocks GB may be provided with a clock line CLKL extending in the column direction to transmit a clock signal. The clock line CLKL may be arranged to intersect with a plurality of gate lines GL arranged in the row direction.

[0207] The second compensation pattern 540 may overlap the clock line CLKL. The second compensation pattern 540 may be disposed between the plurality of gate lines GL of the 1-1 gate block GB1-1. The second compensation pattern 540 may be disposed below the clock line CLKL to overlap the clock line CLKL. Although FIG. 16 illustrates the second compensation pattern being disposed below the clock line, the second compensation pattern 540 may be disposed above the clock line CLKL to overlap the clock line CLKL. For design convenience, the second compensation pattern 540 may be disposed adjacent to the notch region NTA. A constant voltage may be applied to the second compensation pattern 540. For example, the second compensation pattern 540 may be electrically connected to one of a low-potential power line VSSL to which a low-potential power supply is applied and a high-potential power line VDDL to which a high-potential power supply is applied, and a low-potential power supply or a high-potential power supply may be applied.

[0208] Meanwhile, the second compensation pattern 540 has a constant width, and the length of the clock line CLKL overlapping with the second compensation pattern may vary depending on the position. The second compensation pattern 540 is disposed between the plurality of gate lines GL and between the gate low voltage line VGLL and the gate high voltage line VGHL, and may have a constant width.

[0209] The length of the clock wiring CLKL arranged in the fourth region A4 may be the same as the length of the clock wiring CLKL arranged in the third region A3. For example, the clock wiring CLKL arranged in the fourth region A4 adjacent to the notch region NTA may have a zigzag shape. For example, a portion of the clock wiring CLKL arranged in the fourth region A4 that overlaps with the second compensation pattern 540 may have a zigzag shape. Therefore, even if the width of the fourth region A4 is smaller than the width of the third region A3, the total length of the clock wiring CLKL arranged in the fourth region A4 may be the same as the total length of the clock wiring CLKL arranged in the third region A3.

[0210] 17, for ease of explanation, only the substrate 110, buffer layer 111, gate insulating layer 112, first interlayer insulating layer 113, second compensation pattern 540, second interlayer insulating layer 114, clock line CLKL, intermediate electrode CEE, first planarization layer 115, and third compensation pattern 550 are shown. In the following, the remaining configurations are the same as those in FIG. 4 except for the second compensation pattern 540, clock line CLKL, intermediate electrode CEE, and third compensation pattern 550, and therefore detailed description thereof will be omitted.

[0211] Referring to FIG. 17, a second compensation pattern 540 may be disposed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114.

[0212] The second compensation pattern 540 may be formed in the same layer and made of the same material as the second capacitor electrode Cst2. For example, the second compensation pattern 540 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0213] A clock line CLKL may be disposed on the second interlayer insulating layer 114.

[0214] The clock line CLKL may be disposed on the second interlayer insulating layer 114 to overlap the second compensation pattern 540. The clock line CLKL may be formed in the same layer and made of the same material as the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1. For example, the clock line CLKL may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0215] An intermediate electrode CEE may be disposed on the second interlayer insulating layer 114 .

[0216] The intermediate electrode CEE may be disposed in the same layer and made of the same material as the clock line CLKL. The intermediate electrode CEE may be electrically connected to the second compensation pattern 540 through a contact hole formed in the second interlayer insulating layer 114.

[0217] A third compensation pattern 550 may be disposed on the first planarization layer 115 .

[0218] The third compensation pattern 550 may overlap the clock line CLKL. The third compensation pattern 550 may be electrically connected to the intermediate electrode CEE through a contact hole formed in the first planarization layer 115. The third compensation pattern 550 may be disposed in the same layer as the connecting electrode CE and may be made of the same material. For example, the third compensation pattern 550 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0219] That is, the clock line CLKL overlaps the second compensation pattern 540 and the third compensation pattern 550, and the third compensation pattern 550, to which a constant voltage is applied, may be electrically connected to the second compensation pattern 540 through the contact hole and the intermediate electrode CEE. Thus, a capacitor is formed between the clock line CLKL and the second compensation pattern 540, and a capacitor is formed between the clock line CLKL and the third compensation pattern 550, thereby delaying the clock signal applied to the clock line CLKL.

[0220] Therefore, in a display device 500 according to another embodiment of the present specification, a first compensation pattern 230 is disposed in at least one gate block GB2 of the plurality of gate blocks GB1 and GB2 disposed in the second region A2 so as to overlap with the gate line GL, and a capacitor is formed between the gate line GL and the first compensation pattern 230, thereby compensating for the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second region A2. Therefore, in the display device 500 according to another embodiment of the present specification, the RC delay of the gate signals changed due to the irregular structure is compensated to be the same as that in a region without the irregular structure, thereby reducing brightness unevenness and improving display quality.

[0221] In a display device 500 according to another embodiment of the present specification, a plurality of gate blocks GB1 and GB2, into which a gate driver is divided, are distributed in the display area AA, and a first compensation pattern 230 for compensating for an RC delay deviation is disposed in at least one gate block GB2 of the plurality of gate blocks GB1 and GB2 disposed in the second area A2, thereby minimizing the area of ​​the non-display area NA. Therefore, in a display device 500 according to another embodiment of the present specification, the gate driver and the first compensation pattern 230 are disposed within the display area, thereby minimizing the bezel area.

[0222] In the conventional display device, the substrate is a rectangular substrate without any irregular structure on one side, and the same clock signal is provided to the gate driver disposed at the bottom of the display area. However, in the case of an irregular display device in which one or more of the four sides of the substrate that is not a rectangular substrate have an irregular structure, the time at which the clock signal is provided to the gate driver disposed at the bottom of the third region A3, which is an area without an irregular structure, differs from the time at which the clock signal is provided to the gate driver disposed at the bottom of the fourth region A4, which is an area with an irregular structure, resulting in uneven brightness.

[0223] Therefore, in a display device 500 according to another embodiment of the present disclosure, a second compensation pattern 540 and a third compensation pattern 550 are disposed to overlap a clock line CLKL disposed in at least one gate block GB1-1 among the plurality of gate blocks GB disposed in the fourth region A4. A capacitor is formed between the clock line CLKL and the second compensation pattern 540, and a capacitor is formed between the clock line CLKL and the third compensation pattern 550, thereby compensating for the RC delay of the clock signal transmitted through the clock line CLKL disposed in the fourth region A4. That is, the clock signals transmitted through the clock line CLKL disposed in the fourth region A4 and the clock line CLKL disposed in the third region A3 can be transmitted to the respective gate drivers in the same manner. Therefore, in the display device 500 according to another embodiment of the present disclosure, the RC delay difference between the clock signals in different regions is compensated for to be uniform, thereby reducing brightness unevenness and improving display quality.

[0224] FIG. 18 is a cross-sectional view of one of the gate blocks of a display device according to still another embodiment of the present disclosure.

[0225] 18 is a cross-sectional view of the 1-1st gate block GB1-1 among the gate blocks GB of a display device 600 according to still another embodiment of the present specification. FIG. 16 is a cross-sectional view taken at the same position as FIG.

[0226] 18, for ease of explanation, only shows the substrate 410, the first buffer layer 411, the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second gate insulating layer 415, the second compensation pattern 640, the second interlayer insulating layer 416, the clock line CLKL, the intermediate electrode CEE, the first planarization layer 417, and the third compensation pattern 650. Since the remaining configuration is the same as that of FIG. 11 except for the second compensation pattern 640, the clock line CLKL, the intermediate electrode CEE, and the third compensation pattern 650, detailed explanations will be omitted below.

[0227] Referring to FIG. 18, a second compensation pattern 640 may be disposed on the second gate insulating layer 415 .

[0228] The second compensation pattern 640 may be disposed in the same layer as the second gate electrode GE2 of the second transistor T2 and may be made of the same material. For example, the second compensation pattern 640 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0229] On the second interlayer insulating layer 416, the clock line CLKL and the intermediate electrode CEE can be disposed.

[0230] The clock line CLKL may be disposed on the second interlayer insulating layer 416 to overlap the second compensation pattern 640. The clock line CLKL may overlap the second compensation pattern 640 to form a capacitor between the clock line CLKL and the second compensation pattern 640. The clock line CLKL may be disposed in the same layer as the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1 and the second source electrode SE2 and the second drain electrode DE2 of the second transistor T2 and may be made of the same material. For example, the clock line CLKL may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0231] The intermediate electrode CEE may be disposed in the same layer as the clock line CLKL and may be made of the same material. The intermediate electrode CEE may be electrically connected to the second compensation pattern 640 through a contact hole formed in the second interlayer insulating layer 416.

[0232] A third compensation pattern 650 may be disposed on the first planarization layer 417 .

[0233] The third compensation pattern 650 may overlap the clock line CLKL. The third compensation pattern 650 may be electrically connected to the intermediate electrode CEE through a contact hole formed in the first planarization layer 417. The third compensation pattern 650 may be disposed in the same layer as the connecting electrode CE and may be made of the same material. For example, the third compensation pattern 650 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0234] That is, the clock line CLKL overlaps the second compensation pattern 640 and the third compensation pattern 650, and the third compensation pattern 650, to which a constant voltage is applied, may be electrically connected to the second compensation pattern 640 through the contact hole and the intermediate electrode CEE. Thus, a capacitor is formed between the clock line CLKL and the second compensation pattern 640, and a capacitor is formed between the clock line CLKL and the third compensation pattern 650, thereby delaying the clock signal applied through the clock line CLKL.

[0235] Therefore, in a display device 600 according to another embodiment of the present specification, a first compensation pattern 230 is disposed in at least one gate block GB2 of the plurality of gate blocks GB1 and GB2 disposed in the second region A2 so as to overlap with the gate line GL, and a capacitor is formed between the gate line GL and the first compensation pattern 230, thereby compensating for the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second region A2. Therefore, in the display device 600 according to another embodiment of the present specification, the RC delay of the gate signals changed due to the irregular structure is compensated to be the same as that in a region without the irregular structure, thereby reducing brightness unevenness and improving display quality.

[0236] In a display device 600 according to another embodiment of the present specification, a plurality of gate blocks GB1 and GB2, into which a gate driver is divided, are distributed in the display area AA, and a first compensation pattern 230 for compensating for an RC delay deviation is disposed in at least one gate block GB2 of the plurality of gate blocks GB1 and GB2 disposed in the second area A2, thereby minimizing the area of ​​the non-display area NA. Therefore, in the display device 600 according to another embodiment of the present specification, the gate driver and the first compensation pattern 230 are disposed within the display area, thereby minimizing the bezel area.

[0237] In display device 600 according to another embodiment of the present disclosure, second compensation pattern 640 and third compensation pattern 650 are arranged to overlap with clock line CLKL arranged in at least one gate block GB1-1 among the plurality of gate blocks GB arranged in the fourth region A4. A capacitor is formed between clock line CLKL and second compensation pattern 640, and a capacitor is formed between clock line CLKL and third compensation pattern 650, thereby compensating for the RC delay of the clock signal transmitted through clock line CLKL arranged in the fourth region A4. That is, clock signals transmitted through clock line CLKL arranged in the fourth region A4 and clock line CLKL arranged in the third region A3 can be transmitted to the respective gate drivers in the same manner. Therefore, in display device 600 according to another embodiment of the present disclosure, the irregular structure compensates for the RC delay difference of the clock signal depending on the region to be uniform, thereby reducing brightness unevenness and improving display quality.

[0238] FIG. 19 is a cross-sectional view of one of the gate blocks of a display device according to still another embodiment of the present disclosure.

[0239] 19 is a cross-sectional view of the 1-1st gate block GB1-1 of the gate blocks GB of a display device 700 according to still another embodiment of the present specification. FIG. 19 is a cross-sectional view taken at the same position as FIG.

[0240] 19, for ease of explanation, only shows the substrate 410, the first buffer layer 411, the first gate insulating layer 412, the first interlayer insulating layer 413, the fourth compensation pattern 760, the second buffer layer 414, the second gate insulating layer 415, the second compensation pattern 640, the second interlayer insulating layer 416, the clock line CLKL, the intermediate electrode CEE, the first planarization layer 417, and the third compensation pattern 650. Since the remaining configuration is the same as that of FIG. 16 except for the fourth compensation pattern 760, detailed explanations will be omitted below.

[0241] Referring to FIG. 19, a fourth compensation pattern 760 may be disposed between the first interlayer insulating layer 413 and the second compensation pattern 640.

[0242] The fourth compensation pattern 760 may be disposed between the first interlayer insulating layer 413 and the second buffer layer 414. The fourth compensation pattern 760 may be disposed to overlap the second compensation pattern 640. The fourth compensation pattern 760 may be electrically connected to the second compensation pattern 640 through a contact hole formed in the second buffer layer 414.

[0243] The fourth compensation pattern 760 may be disposed in the same layer as the second capacitor electrode Cst2 of the storage capacitor Cst and may be made of the same material. For example, the second capacitor electrode Cst2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0244] That is, the clock line CLKL overlaps with the second compensation pattern 640, the third compensation pattern 650, and the fourth compensation pattern 760, and the third compensation pattern 650, to which a constant voltage is applied, may be electrically connected to the fourth compensation pattern 760 through the contact hole, the intermediate electrode CEE, and the second compensation pattern 640. Thus, a capacitor is formed between the clock line CLKL and the second compensation pattern 640, a capacitor is formed between the clock line CLKL and the third compensation pattern 650, and a capacitor is formed between the second compensation pattern 640 and the fourth compensation pattern 760, thereby delaying the clock signal applied through the clock line CLKL.

[0245] Therefore, in a display device 700 according to another embodiment of the present specification, a first compensation pattern 230 is disposed in at least one gate block GB2 of the plurality of gate blocks GB1 and GB2 disposed in the second region A2 so as to overlap with the gate line GL, and a capacitor is formed between the gate line GL and the first compensation pattern 230, thereby compensating for the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second region A2. Therefore, in the display device 700 according to another embodiment of the present specification, the RC delay of the gate signals changed due to the irregular structure is compensated to be the same as that in a region without the irregular structure, thereby reducing brightness unevenness and improving display quality.

[0246] In a display device 700 according to another embodiment of the present specification, a plurality of gate blocks GB1, GB2 into which a gate driver is divided are distributed in the display area AA, and a first compensation pattern 230 for compensating for an RC delay deviation is disposed in at least one gate block GB2 of the plurality of gate blocks GB1, GB2 disposed in the second area A2, thereby minimizing the area of ​​the non-display area NA. Therefore, in the display device 700 according to another embodiment of the present specification, the gate driver and the first compensation pattern 230 are disposed within the display area, thereby minimizing the bezel area.

[0247] In a display device 700 according to another embodiment of the present disclosure, a second compensation pattern 640, a third compensation pattern 650, and a fourth compensation pattern 760 are arranged to overlap a clock line CLKL arranged in at least one gate block GB1-1 among the plurality of gate blocks GB arranged in the fourth region A4. Thus, a capacitor is formed between the clock line CLKL and the second compensation pattern 640, a capacitor is formed between the clock line CLKL and the third compensation pattern 650, and a capacitor is formed between the second compensation pattern 640 and the fourth compensation pattern 760, thereby compensating for the RC delay of the clock signal transmitted through the clock line CLKL arranged in the fourth region A4. That is, the clock signals transmitted through the clock line CLKL arranged in the fourth region A4 and the clock line CLKL arranged in the third region A3 can be transmitted to the respective gate drivers in the same manner. Therefore, in the display device 700 according to another embodiment of the present disclosure, the irregular structure compensates for the RC delay difference between the clock signals depending on the region to be uniform, thereby reducing brightness unevenness and improving display quality.

[0248] A display device according to an embodiment of the present invention can be described as follows.

[0249] A display device according to one embodiment of the present specification includes a substrate including a display area having irregular sides and a non-display area surrounding the display area, in which a notch area is defined by the shape of the irregular sides of the display area; a gate driver including a plurality of gate blocks distributed in the display area and outputting gate signals; a plurality of gate lines connected to the plurality of gate blocks and transmitting the gate signals; and a first compensation pattern disposed in at least one of the plurality of gate blocks and overlapping with the plurality of gate lines.

[0250] According to another feature of the present invention, the display area includes a plurality of first regions and at least one second region smaller in area than the plurality of first regions and arranged to correspond to the notch region, and the first compensation pattern may be arranged in the at least one second region.

[0251] According to another aspect of the present invention, the number of the gate blocks arranged in the at least one second region may be smaller than the number of the gate blocks arranged in the first regions.

[0252] According to another aspect of the invention, the at least one second region may be disposed adjacent to at least the notch region.

[0253] According to another feature of the present invention, the pixel may further include a plurality of power supply lines arranged to intersect with the plurality of gate lines, and the first compensation pattern may be integral with at least one of the plurality of power supply lines and extend from the plurality of power supply lines.

[0254] According to another aspect of the present invention, the width of the plurality of power supply wirings and the first compensation pattern in at least one second region may be greater than the width of the plurality of power supply wirings in the plurality of first regions.

[0255] According to another aspect of the present invention, the width of the first compensation pattern may be constant.

[0256] According to another aspect of the present invention, the width of the first compensation pattern may vary depending on the position.

[0257] According to another aspect of the present invention, a width of a portion of the plurality of gate lines overlapping with the first compensation pattern may be greater than a width of a portion of the plurality of gate lines not overlapping with the first compensation pattern.

[0258] According to another aspect of the present invention, a light emitting device includes an active layer on a substrate, a gate insulating layer on the active layer, a gate electrode overlapping the active layer on the gate insulating layer, a first interlayer insulating layer on the gate electrode, a source electrode and a drain electrode disposed on the first interlayer insulating layer and electrically connected to the active layer, a second interlayer insulating layer on the source electrode and the drain electrode, a connecting electrode disposed on the second interlayer insulating layer and electrically connected to one of the source electrode and the drain electrode, a first planarization layer on the connecting electrode, and a light emitting element disposed on the first planarization layer, wherein a plurality of gate lines are disposed on the same layer as the gate electrode, and a first compensation pattern is disposed on the same layer as the source electrode and the drain electrode.

[0259] According to another aspect of the present invention, there is provided a semiconductor device comprising: a first active layer on a substrate; a first gate insulating layer on the first active layer; a first gate electrode overlapping the first active layer on the first gate insulating layer; a first interlayer insulating layer on the first gate electrode; a second active layer on the first interlayer insulating layer; a second gate insulating layer on the second active layer; a second gate electrode overlapping the second active layer on the second gate insulating layer; a second interlayer insulating layer on the second gate electrode; a first source electrode and a first drain electrode disposed on the second interlayer insulating layer and electrically connected to the first active layer; The light-emitting device may include a second source electrode and a second drain electrode electrically connected to the active layer, a first planarization layer on the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode, a connecting electrode disposed on the first planarization layer and electrically connected to one of the first source electrode and the first drain electrode, a second planarization layer on the connecting electrode, and a light-emitting element disposed on the second planarization layer, wherein a plurality of gate wirings are disposed on the same layer as the second gate electrode, and a first compensation pattern is disposed on the same layer as the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

[0260] According to another aspect of the present invention, the display area may include a third region having a first width in a column direction and a fourth region having a second width smaller than the first width in the column direction, and may further include a second compensation pattern disposed in the fourth region.

[0261] According to another aspect of the present invention, the pixel circuit may further include a clock line connected to the plurality of gate blocks and crossing the plurality of gate lines, and the second compensation pattern may overlap the clock line.

[0262] According to another aspect of the present invention, the circuit may further include a third compensation pattern overlapping the clock wiring.

[0263] According to another aspect of the present invention, the width of the second compensation pattern may be constant, and the length of the clock wiring may vary depending on the position.

[0264] According to another aspect of the present invention, the clock wiring may be in a zigzag form.

[0265] According to another aspect of the present invention, a light emitting device may include an active layer on a substrate, a gate insulating layer on the active layer, a gate electrode overlapping the active layer on the gate insulating layer, a first interlayer insulating layer on the gate electrode, a source electrode and a drain electrode disposed on the first interlayer insulating layer and electrically connected to the active layer, a second interlayer insulating layer on the source electrode and the drain electrode, a connecting electrode disposed on the second interlayer insulating layer and electrically connected to one of the source electrode and the drain electrode, a first planarization layer on the connecting electrode, and a light emitting element disposed on the first planarization layer, wherein the second compensation pattern is disposed between the first interlayer insulating layer and the second interlayer insulating layer, and the third compensation pattern may be disposed in the same layer as the connecting electrode.

[0266] According to another aspect of the present invention, there is provided a semiconductor device comprising: a first active layer on a substrate; a first gate insulating layer on the first active layer; a first gate electrode overlapping the first active layer on the first gate insulating layer; a first interlayer insulating layer on the first gate electrode; a second active layer on the first interlayer insulating layer; a second gate insulating layer on the second active layer; a second gate electrode overlapping the second active layer on the second gate insulating layer; a second interlayer insulating layer on the second gate electrode; a first source electrode and a first drain electrode disposed on the second interlayer insulating layer and electrically connected to the first active layer; The light-emitting device may include: a second source electrode and a second drain electrode disposed on the insulating layer and electrically connected to the second active layer; a first planarization layer on the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode; a connecting electrode disposed on the first planarization layer and electrically connected to one of the first source electrode and the first drain electrode; a second planarization layer on the connecting electrode; and a light-emitting element disposed on the second planarization layer, wherein the second compensation pattern is disposed between the first interlayer insulating layer and the second interlayer insulating layer, and the third compensation pattern is disposed in the same layer as the connecting electrode.

[0267] According to another aspect of the present invention, the semiconductor device may further include a fourth compensation pattern overlapping the second compensation pattern and disposed between the first interlayer insulating layer and the second compensation pattern.

[0268] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are intended to be illustrative rather than limiting the technical concept of the present specification, and the scope of the technical concept of the present specification is not limited by these embodiments. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not restrictive. The scope of protection of the present specification should be interpreted by the scope of the following claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included in the scope of the present specification.

Claims

1. a substrate including a display area having irregularly shaped sides and a non-display area surrounding the display area, wherein a notch area is defined by the shape of the irregularly shaped sides of the display area; a gate driver including a plurality of gate blocks that are distributed in the display area and output gate signals; a plurality of gate wirings connected to the plurality of gate blocks and transmitting the gate signals; a first compensation pattern disposed in at least one of the gate blocks and overlapping the gate lines;

2. The display area is a plurality of first regions; and at least one second region having an area smaller than that of the plurality of first regions and arranged to correspond to the notch region; The display device of claim 1 , wherein the first compensation pattern is disposed in the at least one second region.

3. The display device according to claim 2 , wherein the number of the plurality of gate blocks arranged in the at least one second region is smaller than the number of the plurality of gate blocks arranged in the plurality of first regions.

4. The display device according to claim 2 , wherein the at least one second region is disposed adjacent to at least the notch region.

5. further including a plurality of power supply wirings arranged to intersect with the plurality of gate wirings; The display device of claim 2 , wherein the first compensation pattern is integral with at least one of the plurality of power supply wirings and extends from the plurality of power supply wirings.

6. The display device of claim 5 , wherein a width of the plurality of power supply lines and the first compensation pattern in the at least one second region is greater than a width of the plurality of power supply lines in the plurality of first regions.

7. The display device of claim 5 , wherein the width of the first compensation pattern is constant.

8. The display device of claim 5 , wherein the width of the first compensation pattern varies depending on the position.

9. The display device of claim 5 , wherein a width of a portion of the plurality of gate lines overlapping with the first compensation pattern is greater than a width of a portion of the plurality of gate lines not overlapping with the first compensation pattern.

10. an active layer on the substrate; a gate insulating layer on the active layer; a gate electrode on the gate insulating layer overlapping the active layer; a first interlayer insulating layer on the gate electrode; a second interlayer insulating layer on the first interlayer insulating layer; a source electrode and a drain electrode disposed on the second interlayer insulating layer and electrically connected to the active layer; a first planarization layer on the source electrode and the drain electrode; a connection electrode disposed on the first planarization layer and electrically connected to one of the source electrode and the drain electrode; a second planarization layer on the connecting electrode; and a light emitting element disposed on the first planarization layer; the plurality of gate wirings are arranged in the same layer as the gate electrode, The display device of claim 5 , wherein the first compensation pattern is disposed in the same layer as the source electrode and the drain electrode.

11. a first active layer on the substrate; a first gate insulating layer on the first active layer; a first gate electrode on the first gate insulating layer overlapping the first active layer; a first interlayer insulating layer on the first gate electrode; a second active layer on the first interlayer insulating layer; a second gate insulating layer on the second active layer; a second gate electrode on the second gate insulating layer overlapping the second active layer; a second interlayer insulating layer on the second gate electrode; a first source electrode and a first drain electrode disposed on the second interlayer insulating layer and electrically connected to the first active layer; a second source electrode and a second drain electrode disposed on the second interlayer insulating layer and electrically connected to the second active layer; a first planarization layer on the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode; a connection electrode disposed on the first planarization layer and electrically connected to one of the first source electrode and the first drain electrode; a second planarization layer on the connecting electrode; and a light emitting element disposed on the second planarization layer; the plurality of gate wirings are disposed in the same layer as the second gate electrode; The display device of claim 5 , wherein the first compensation pattern is disposed in the same layer as the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

12. The display area is a third region having a first width in the column direction; and a fourth region having a second width smaller than the first width in a column direction; The display device of claim 1 , further comprising a second compensation pattern disposed in the fourth region.

13. further comprising a clock line connected to the plurality of gate blocks and intersecting the plurality of gate lines; The display device according to claim 12 , wherein the second compensation pattern overlaps with the clock wiring.

14. The display device of claim 13 , further comprising a third compensation pattern overlapping the clock wiring.

15. The display device of claim 13 , wherein the width of the second compensation pattern is constant, and the length of the clock wiring varies depending on the position.

16. The display device of claim 15, wherein the clock wiring has a zigzag pattern.

17. an active layer on the substrate; a gate insulating layer on the active layer; a gate electrode on the gate insulating layer overlapping the active layer; a first interlayer insulating layer on the gate electrode; a second interlayer insulating layer on the first interlayer insulating layer; a source electrode and a drain electrode disposed on the second interlayer insulating layer and electrically connected to the active layer; a first planarization layer on the source electrode and the drain electrode; a connection electrode disposed on the first planarization layer and electrically connected to one of the source electrode and the drain electrode; a second planarization layer on the connecting electrode; and a light emitting element disposed on the second planarization layer; the second compensation pattern is disposed between the first interlayer insulating layer and the second interlayer insulating layer; The display device of claim 14 , wherein the third compensation pattern is disposed in the same layer as the connecting electrode.

18. a first active layer on the substrate; a first gate insulating layer on the first active layer; a first gate electrode on the first gate insulating layer overlapping the first active layer; a first interlayer insulating layer on the first gate electrode; a second active layer on the first interlayer insulating layer; a second gate insulating layer on the second active layer; a second gate electrode on the second gate insulating layer overlapping the second active layer; a second interlayer insulating layer on the second gate electrode; a first source electrode and a first drain electrode disposed on the second interlayer insulating layer and electrically connected to the first active layer; a second source electrode and a second drain electrode disposed on the second interlayer insulating layer and electrically connected to the second active layer; a first planarization layer on the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode; a connection electrode disposed on the first planarization layer and electrically connected to one of the first source electrode and the first drain electrode; a second planarization layer on the connecting electrode; and a light emitting element disposed on the second planarization layer; the second compensation pattern is disposed between the first interlayer insulating layer and the second interlayer insulating layer; The display device of claim 14 , wherein the third compensation pattern is disposed in the same layer as the connecting electrode.

19. The display device of claim 18 , further comprising a fourth compensation pattern overlapping the second compensation pattern and disposed between the first interlayer insulating layer and the second compensation pattern.

20. The display device of claim 1 , further comprising a capacitor disposed between the first compensation pattern and the plurality of gate lines.

21. 6. The display device according to claim 5, wherein an area where the plurality of power supply wirings and the first compensation pattern overlap with the plurality of gate wirings in the at least one second region is larger than an area where the plurality of power supply wirings and the plurality of gate wirings overlap with each other in the plurality of first regions.

22. The display device according to claim 12 , wherein the second compensation pattern is electrically connected to one of a plurality of power supply wirings.

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