Method and device for integrated circuit

Abstract

To enable monitoring of the transmission quality of a test signal in a number of examples.SOLUTION: A method for a first integrated circuit that is arranged on a substrate together with at least one further, for example, second integrated circuit is provided, the method comprising sending a test signal to the at least one further integrated circuit, and receiving a response associated with the test signal from the at least one further integrated circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to at least one method for an integrated circuit. The present disclosure further relates to at least one device for an integrated circuit. Summary of the Invention

[0002] A number of examples relate to a method, e.g., a computer-implemented method, for a first integrated circuit disposed on a substrate together with at least one further, e.g., second, integrated circuit, comprising transmitting a test signal to the at least one further integrated circuit and receiving a response associated with the test signal from the at least one further integrated circuit, which in a number of examples allows monitoring of transmission quality associated with the test signal.

[0003] It is contemplated that in numerous instances, the method will include affecting operation of at least one component of the first integrated circuit based on the response. It is contemplated that in a significant number of instances, the first integrated circuit and the at least one further integrated circuit are each formed as a chip, e.g., a chiplet, and that, for example, the first integrated circuit and the at least one further integrated circuit comprise a multi-chiplet system.

[0004] In a significant number of examples, a first communication channel is used for transmitting the test signal, in which case it is for example the main band of a communication interface interconnecting at least the first integrated circuit and the second integrated circuit, in which case it is for example contemplated that this communication interface is, for example, a unified chiplet interface, for example of the Universal Chiplet Interconnect Express (UCIe) type, for example UCIe 1.0.

[0005] In a significant number of instances, a second communication channel is used for receiving the response, in which case, for example, this second communication channel is a sideband of a or said communication interface interconnecting at least the first and second integrated circuits, in which case, for example, this communication interface is, for example, a unified chiplet interface, for example of the UCIe type, for example UCIe 1.0.

[0006] In a number of examples, it is contemplated that influencing operation comprises controlling, e.g., influencing, a signal level at which a first integrated circuit transmits information, e.g., data, to at least one further integrated circuit, e.g., via one or the first communication channel.

[0007] In a number of examples, it is contemplated that the method comprises a step of providing a test signal, whereby for example the test signal has at least one, for example a configurable signal pattern, for example a test pattern, and optionally comprises a step of using the test signal.

[0008] It is contemplated that in many instances the provision will include provision of encrypted test signals or test patterns. For example, a standardized method for encryption may be used. In a number of examples, the method comprises a step of controlling, e.g., influencing, a signal level, e.g., based on a response, as the first integrated circuit transmits information, e.g., data, to at least one further integrated circuit, e.g., via the first communication channel, and in this regard it is contemplated that, for example, the controlling, e.g., influencing, is performed dynamically, e.g., during operation of the at least first integrated circuit, and is performed, e.g., repeatedly, e.g., periodically, e.g., multiple times within a fault-tolerant time interval.

[0009] A significant number of examples relate to methods, e.g., computer-implemented methods, for a second integrated circuit disposed on a substrate together with at least a first integrated circuit, the method comprising receiving a test signal from the first integrated circuit, evaluating the received test signal, generating a response associated with the test signal based on the evaluation, and transmitting the response to the first integrated circuit.

[0010] In a number of examples, as already explained above, it is contemplated that the first integrated circuit and the second integrated circuit are each formed as a chip, e.g., a chiplet, and that, for example, the first integrated circuit and at least one further integrated circuit form a multi-chiplet system.

[0011] In a significant number of examples, a first communication channel is used for receiving the test signal, in which case it is for example contemplated that this first communication channel is the main band of a communication interface interconnecting at least the first integrated circuit and the second integrated circuit, in which case it is for example contemplated that this communication interface is for example a unified chiplet interface, for example of the Universal Chiplet Interconnect Express (UCIe) type, for example UCIe 1.0.

[0012] In a significant number of instances, it is contemplated that a second communication channel is used for transmitting the response, in which case, for example, this second communication channel is a sideband of a or said communication interface interconnecting at least the first and second integrated circuits, in which case, for example, this communication interface is, for example, a unified chiplet interface, for example of the UCIe type, for example UCIe 1.0.

[0013] In a significant number of examples, it is contemplated that the evaluation will comprise at least one of the following elements: a) checking the received test signal, e.g., for correctness or for matching with, e.g., a configurable signal pattern, e.g., a test pattern; or b) analyzing the signal level of the received test signal; or c) analyzing the signal quality of the received test signal; or d) using at least one method based on artificial intelligence, e.g., machine learning; or e) using a multi-stage decision system.

[0014] A number of examples relate to apparatus for carrying out methods according to the present disclosure. A number of examples relate to integrated circuits comprising at least one device according to the present disclosure, e.g., for a multi-chiplet system having multiple chiplets, where the device or the functionality of the device is incorporated into the integrated circuit.

[0015] A number of examples relate to systems, such as multi-chiplet systems, that include at least one device according to the present disclosure or at least one integrated circuit according to the present disclosure. A significant number of examples relate to products, such as controls, for example for automobiles, that include at least one device according to the present disclosure.

[0016] A significant number of examples relate to vehicles, such as automobiles, having at least one apparatus according to the present disclosure and / or at least one article of manufacture, such as a control device, according to the present disclosure. A number of examples relate to computer-readable memory media containing instructions that, when executed by a computer, cause the computer to perform methods according to the present disclosure.

[0017] A number of examples relate to computer programs that include instructions that, when executed by a computer, cause the computer to perform a method according to the present disclosure. A number of examples relate to data carrier signals that characterize and / or carry computer programs according to the present disclosure.

[0018] A significant number of examples relate to the use of a method based on the present disclosure and / or an apparatus based on the present disclosure and / or an integrated circuit based on the present disclosure and / or a system based on the present disclosure and / or a product based on the present disclosure and / or a vehicle based on the present disclosure and / or a computer-readable memory medium based on the present disclosure and / or a computer program based on the present disclosure and / or a data carrier signal based on the present disclosure for at least one of the following factors: a) ensuring data communication between a first integrated circuit and at least one further, e.g., a second integrated circuit; or b) improving the robustness of data communication relating to the first integrated circuit, e.g., between the first integrated circuit and at least one further, e.g., a second integrated circuit; or c) improving the reliability of data communication relating to the first integrated circuit; or d) improving the availability of the first integrated circuit and / or a system comprising the first integrated circuit; or e) improving design quality and / or manufacturing quality, e.g., based on feedback of insights from the operation of the first integrated circuit.

[0019] Further features, applicability and advantages of the present invention will become apparent from the following description of examples of the invention illustrated in the drawing figures, in which all described or illustrated features, alone or in any combination, are subject to the present invention, regardless of the arrangement of features in the claims or their dependency on the claims, and regardless of the expression or illustration of the features in the description of the invention or in the drawings. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a schematic diagram showing a simplified flow diagram. [Figure 2] FIG. 1 is a schematic diagram showing a simplified block diagram. [Figure 3] FIG. 1 is a schematic diagram showing a simplified flow diagram. [Figure 4] FIG. 1 is a schematic diagram showing a simplified flow diagram. [Figure 5] FIG. 1 is a schematic diagram showing a simplified flow diagram. [Figure 6] FIG. 1 is a schematic diagram showing a simplified block diagram. [Figure 7] FIG. 1 is a schematic diagram showing a simplified diagram. [Figure 8] FIG. 1 is a schematic diagram showing a simplified block diagram. [Figure 9] FIG. 1 is a schematic diagram showing an example of use. DETAILED DESCRIPTION OF THE INVENTION

[0021] 1 and 2 relate to a method, e.g. a computer-implemented method, for a first integrated circuit 101 arranged on a substrate 104 together with at least one further, e.g. a second, integrated circuit 102, comprising a step 200 of transmitting a test signal TS to the at least one further integrated circuit 102 and a step 202 of receiving from the at least one further integrated circuit 102 a response RM associated with (e.g. dependent on or generated on the basis of) the test signal TS, which in a number of examples allows monitoring of a transmission quality associated with the test signal TS.

[0022] In a number of examples, in FIG. 1, it is contemplated that the method comprises a step 204 of influencing the operation BETR-101 of at least one component of the first integrated circuit 101 based on the response RM.

[0023] In a number of examples, such as FIG. 2, it is contemplated that the first integrated circuit 101 and the at least one further integrated circuit 102 are each formed as a chip, e.g., a chiplet, and that, for example, the first integrated circuit 101 and the at least one further integrated circuit 102 constitute a multi-chiplet system 1000.

[0024] In a number of examples, in FIG. 1, a first communication channel K-1 is used for transmitting 200 the test signal TS (see block 200a), in which case it is envisaged that this first communication channel K-1 is, for example, the main band of a communication interface 110 (FIG. 2) interconnecting at least the first integrated circuit 101 and the second integrated circuit 102, in which case it is envisaged that this communication interface 110 is, for example, a unified chiplet interface, for example of the Universal Chiplet Interconnect Express (UCIe) type, for example UCIe 1.0.

[0025] In a number of examples, in FIG. 1, a second communication channel K-2 is used for receiving 202 the response RM (see block 202a), and in this regard, it is contemplated that, for example, this second communication channel K-2 is a sideband of one or the above-mentioned communication interface 110 interconnecting at least the first integrated circuit 101 and the second integrated circuit 102.

[0026] 1, it is contemplated that the step 204 of influencing the operation BETR-101 comprises controlling, e.g., a step 204a of influencing a signal level TX-PEG, at which the first integrated circuit 101 transmits information, e.g., data, via, e.g., the or said first communication channel K-1, to the at least one further integrated circuit 102. This makes it possible in numerous examples to control the signal level TX-PEG based on the response RM, e.g., in the sense of a closed-loop control.

[0027] In a number of examples, in FIG. 3, it is contemplated that the method comprises a step 210 of preparing a test signal TS, whereby for example this test signal TS has at least one, for example, configurable signal pattern, for example a test pattern TP, and optionally comprises a step 212 of using the test signal TS, for example for transmission 200 (FIG. 1).

[0028] In a number of examples, in FIG. 3, it is contemplated that the preparation 210 comprises a preparation 210a of an encrypted test signal TS' or test pattern TP'. 4, the method comprises a step 220, e.g., influencing 220a, of controlling, e.g., based on the response RM, a certain or said signal level TX-PEG in association with the first integrated circuit 101 transmitting information, e.g., data, e.g., via the certain or said first communication channel K-1 (FIG. 2), to at least one further integrated circuit 102, in which it is contemplated, for example, that this control 220, e.g., influencing 220a, is performed dynamically, e.g., during operation of at least the first integrated circuit 101, and is performed, e.g., repeatedly, e.g., periodically, e.g., multiple times within a fault-tolerant time interval (see block 220b). Optional block 222 symbolizes an optional communication KOMM between the components 101, 102, e.g., using the signal level TX-PEG influenced based on block 220.

[0029] A number of examples, FIG. 5, relate to a method, e.g., a computer-implemented method, for a second integrated circuit 102 (FIG. 2) arranged on a substrate 104 together with at least a first integrated circuit 101, the method comprising a step 250 of receiving a test signal TS from the first integrated circuit 101, a step 252 of evaluating the received test signal TS, a step 254 of generating a response RM associated with the test signal TS based on the evaluation 252, and a step 256 of transmitting the response RM to the first integrated circuit 101.

[0030] In a number of examples, as already explained above, it is contemplated that the first integrated circuit 101 and the second integrated circuit 102 are each formed as a chip, e.g., a chiplet, and that, for example, the first integrated circuit 101 and at least one further integrated circuit 102 form a multi-chiplet system 1000.

[0031] In a number of examples, in FIG. 5, a first communication channel K-1 is used for receiving 250 the test signal TS (see block 250a), in which case it is envisaged that this first communication channel is, for example, the main band of a communication interface 110 interconnecting at least the first integrated circuit 101 and the second integrated circuit 102, in which case it is, for example, envisaged that this communication interface 110 is, for example, a unified chiplet interface of the UCIe type, for example UCIe 1.0.

[0032] In a number of examples, in FIG. 5, a second communication channel K-2 is used for transmitting 256 the response RM (see block 256a), in which case it is contemplated that for example this second communication channel K-2 is a sideband of a certain or said communication interface 110 interconnecting at least the first integrated circuit and the second integrated circuit, in which case it is contemplated that for example this communication interface is, for example, a unified chiplet interface of the UCIe type, for example UCIe 1.0.

[0033] In a number of examples, in FIG. 5, it is contemplated that the evaluation 252 may have at least one of the following elements: a) a check 252a of the received test signal TS, for example for correctness or for example for correspondence with a configurable signal pattern, for example a test pattern TP, or b) an analysis 252b of the signal level of the received test signal TS, or c) an analysis 252c of the signal quality of the received test signal TS, or d) the use 252d of at least one method based on artificial intelligence (AI), for example machine learning (ML), for example for the check 252a and / or for the analysis 252b and / or 252c, or e) the use 252e of a multi-stage decision system, for example instead of a binary decision (e.g. pass / fail), for example to determine the result of the evaluation 252.

[0034] By way of example, FIG. 6 relates to an apparatus 300 for carrying out the method according to the present disclosure. In a number of examples, in FIG. 6, it is contemplated that the apparatus 300 has a computing mechanism ("computer") 302 with at least one computing core 302a and a memory mechanism 304 allocated to the computing mechanism 302 for at least temporarily storing at least one of the following elements: a) data DAT (e.g., data associated with the test signal TS and / or data associated with the response RM and / or data associated with the evaluation 252); b) a computer program PRG, for example for performing a method according to the present disclosure.

[0035] In further examples, the memory mechanism 304 includes volatile memory (e.g., main memory (RAM)) 304a and / or non-volatile (NVM) memory (e.g., flash EEPROM) 304b, or a combination thereof, or a combination with other memory types not specifically listed.

[0036] In a further example, the device 300 is formed as a hardware circuit, for example a pure hardware circuit (not shown). A further example, FIG. 6 relates to a computer-readable memory medium SM containing instructions PRG that, when executed by computer 302, cause computer 302 to perform a method according to the present disclosure.

[0037] A further example relates to a computer program PRG that includes instructions that, when executed by the computer 302, cause the computer 302 to carry out a method according to the present disclosure.

[0038] A further example relates to a data carrier signal DCS characterizing and / or carrying a computer program PRG according to the present disclosure, which can be received, for example, via the optional data interface 306 of the device 300.

[0039] In a number of examples, FIG. 2 relates to an integrated circuit comprising at least one device 300 according to the present disclosure, e.g., chiplets 101, 102, e.g., for a multi-chiplet system 1000 having multiple chiplets, where e.g., device 300 or functionality of device 300 is integrated into integrated circuit 101, 102 (or in a number of examples, located on, e.g., a common substrate 104).

[0040] In a number of examples, FIG. 2 relates to a system, such as a multi-chiplet system 1000, having at least one device 300 according to the present disclosure or at least one integrated circuit 101, 102 according to the present disclosure.

[0041] 7 shows a simplified diagram based on a number of examples. Element E1 represents a first transmitting mechanism of a first chiplet 101′, configured, for example, to transmit data via a UCIe main band channel K-1′ to a first receiving mechanism E2 of a second chiplet 102′. Element E3 represents the provision of a test signal, for example, an encrypted test signal TS′, which, in a number of examples, can be transmitted by the first transmitting mechanism E1 to the first receiving mechanism E2 via the UCIe main band channel K-1′, and element TS″ represents the test signal received by the second chiplet 102′.

[0042] In many instances, the second chiplet 102′ may generate a response RM′ based on the received encrypted test signal TS″, and this response RM′ may be transmitted by a transmitter E4 of the second chiplet 102′ to a corresponding receiver E5 of the first chiplet 101′ via a UCIe sideband channel K-2′.

[0043] In a number of examples, the first chiplet 101′ performs a level adaptation E6 of the level of information to be transmitted to the second chiplet 102′ over the UCIe main band channel K-1′, for example based on the response RM′ obtained from the second chiplet 102′.

[0044] Element E7 represents an analog-to-digital conversion, according to a number of examples, of, for example, at least a part of, the received test signal TS'', for example by analog-to-digital conversion according to the delta-sigma principle.

[0045] Element E8 represents an evaluation of the test signal TS"' digitized by element E7 based on a number of examples, for example using an AI, for example ML-based method. Element E9 represents a determination of the result of evaluation E8 based on a number of examples, e.g., using a multi-stage determination system, which results in, e.g., a response RM′. The response RM′ may, e.g., indicate whether, or how, or to what extent, the first chiplet 101′ should adapt its transmit level (see block E6).

[0046] In a further example, the knowledge gained by element E8 may be used, for example, for manufacturing further chiplets or systems containing chiplets, and / or for testing of the chiplets or systems, for example testing within the context of manufacturing.

[0047] Element E10 represents an error recognition based on a number of examples, for example recognizing at least one of the following elements: a) electrical errors, such as DC errors (e.g., open, short plus / ground, crosstalk), or b) timing errors (e.g., regarding edge steepness, latency time, ...), or c) likelihood checking errors (e.g., frozen data, value range, ...).

[0048] Further aspects and examples are described below, which - in further examples - can each be combined individually alone or in any combination, with each other, and with at least one of the above-described aspects and / or examples.

[0049] In many examples, such as FIG. 7, communication between chiplets 101′ and 102′, e.g., payload communication, is unidirectional, e.g., via respective main band channels, of which FIG. 7 exemplarily shows channel K-1′ from chiplet 101′ to chiplet 102′ (however, a possible further main band channel from chiplet 102′ to chiplet 101′ is not shown).

[0050] In many examples, in FIG. 7, via the sideband channel K-2′, in addition to eg the response RM′, eg Stati and / or other eg operational information may be transmitted via elements E4, E5.

[0051] Principles according to the present disclosure allow, in numerous examples, for example, to provide a multi-chiplet system 1000 in which different chiplets 101, 102, ... may be allocated to different domains, for example application-specific domains, for example body, chassis, ADAS, IVI in the automotive range. In further examples, chiplets of different types and / or chiplets with different architectures (e.g. GPU, CPU, HWA, ...) may be combined into one multi-chiplet system, in which communication between the chiplets may be ensured according to principles according to the present disclosure.

[0052] A number of examples, such as FIG. 8, relate to a product, such as a control device 12, for example for a motor vehicle 10, that includes at least one device 300 according to the present disclosure. A number of examples, such as FIG. 8, relate to a vehicle, such as an automobile 10, having at least one apparatus 300 according to the present disclosure and / or at least one product, such as a control device 12, according to the present disclosure.

[0053] In a number of examples, FIG. 9 illustrates the following elements: a) ensuring 401 data communication between the first integrated circuit 101 and at least one further, e.g., second, integrated circuit 102; or b) increasing 402 robustness of data communication regarding the first integrated circuit, e.g., between the first integrated circuit and at least one further, e.g., second, integrated circuit; or c) increasing 403 reliability of data communication regarding the first integrated circuit; or d) increasing 404 availability of the first integrated circuit and / or the system 1000 comprising the first integrated circuit; or e) utilizing knowledge from the operation of, e.g., the first integrated circuit. and / or the use 400 of a method based on the present disclosure and / or an apparatus 300 based on the present disclosure and / or an integrated circuit 101, 102 based on the present disclosure and / or a system 1000 based on the present disclosure and / or a product 12 based on the present disclosure and / or a vehicle 10 based on the present disclosure and / or a computer readable memory medium SM based on the present disclosure and / or a computer program PRG based on the present disclosure and / or a data carrier signal DCS based on the present disclosure for at least one of improving 405 design quality and / or manufacturing quality based on feedback. [Explanation of symbols]

[0054] 10. Automobiles 12 Control equipment 101 First Integrated Circuit 102 Second Integrated Circuit 104 PCB 110 Communication Interface 300 equipment 302 Computer 1000 Multi-Chiplet Systems BETR-101 Operation DCS Data Carrier Signal K-1 First Communication Channel K-2 Second Communication Channel PRG instruction, computer program RM Response SM Memory Media TS, TS', TS"' test signals TP, TP' test patterns TX-PEG signal level

Claims

1. A method for a first integrated circuit (101) arranged on a substrate (104) together with at least one further, e.g., second, integrated circuit (102), comprising the steps of: transmitting (200) a test signal (TS) to the at least one further integrated circuit (102); and receiving (202) a response (RM) associated with the test signal (TS) from the at least one further integrated circuit (102).

2. 2. The method of claim 1, further comprising a step (204) of influencing the operation (BETR-101) of at least one component of said first integrated circuit (101) based on said response (RM).

3. 3. The method according to claim 1 or 2, wherein the first integrated circuit (101) and the at least one further integrated circuit (102) are each formed as a chip, e.g., a chiplet, e.g., the first integrated circuit (101) and the at least one further integrated circuit (102) constitute a multi-chiplet system (1000).

4. 4. The method according to claim 1, wherein a first communication channel (K-1) is used (200a) for the transmission (200) of the test signal (TS), wherein the first communication channel (K-1) is e.g. a main band of a communication interface (110) interconnecting at least the first integrated circuit (101) and the second integrated circuit (102), wherein the communication interface (110) is e.g. a unified chiplet interface, e.g. of the Universal Chiplet Interconnect Express (UCIe) type.

5. 5. The method according to claim 1, wherein a second communication channel (K-2) is used (202a) for the reception (202) of the response (RM), wherein the second communication channel (K-2) is e.g. a sideband of a communication interface (110) interconnecting at least the first integrated circuit (101) and the second integrated circuit (102), wherein the communication interface (110) is e.g. a unified chiplet interface, e.g. of the UCIe type.

6. 6. The method according to claim 1, wherein the step of influencing (204) the operation (BETR-101) comprises a step (204a) of controlling, e.g. influencing, a signal level (TX-PEG), at which the first integrated circuit (101) transmits information, e.g. data, to the at least one further integrated circuit (102), e.g. via one or the first communication channel (K-1).

7. 7. The method according to claim 1, comprising a step (210) of preparing the test signal (TS), wherein for example the test signal (TS) has at least one, for example configurable signal pattern, for example a test pattern (TP), and optionally a step (212) of using the test signal (TS; TS').

8. 8. The method of claim 7, wherein said preparing (210) comprises preparing (210a) an encrypted test signal (TS') or test pattern (TP').

9. 9. The method according to claim 1, further comprising a step of controlling (220), e.g. influencing (220a), a signal level (TX-PEG) associated with the first integrated circuit (101) transmitting information, e.g. data, via the first communication channel (K-1) to the at least one further integrated circuit (102), e.g. based on the response (RM), wherein e.g. the controlling (220), e.g. influencing (220a), is performed dynamically, e.g. during operation of at least the first integrated circuit (101), e.g. repeatedly, e.g. periodically, e.g. multiple times within a fault-tolerant time interval (220b).

10. A method for a second integrated circuit (102) disposed on a substrate (104) together with at least one first integrated circuit (101), comprising the steps of: receiving (250) a test signal (TS) from the first integrated circuit (101); evaluating (252) the received test signal (TS); creating (254) a response (RM) associated with the test signal (TS) based on the evaluation (252); and transmitting (256) the response (RM) to the first integrated circuit (101).

11. 11. The method of claim 10, wherein the first integrated circuit (101) and the second integrated circuit (102) are each formed as a chip, e.g., a chiplet, e.g., the first integrated circuit (101) and the at least one further integrated circuit (102) constitute a multi-chiplet system (1000).

12. 12. The method according to claim 10 or 11, wherein a first communication channel (K-1) is used (250a) for the reception (250) of the test signal (TS), wherein for example the first communication channel (K-1) is a main band of a communication interface (110) interconnecting at least the first integrated circuit (101) and the second integrated circuit (102), wherein for example the communication interface (110) is for example a unified chiplet interface, for example of the Universal Chiplet Interconnect Express (UCIe) type.

13. 13. The method according to claim 10, wherein a second communication channel (K-2) is used (256a) for the transmission (256) of the response (RM), wherein the second communication channel (K-2) is e.g. a sideband of a communication interface (110) interconnecting at least the first integrated circuit (101) and the second integrated circuit (102), wherein the communication interface (110) is e.g. a unified chiplet interface, e.g. of the UCIe type.

14. 14. The method according to claim 10, wherein the evaluation (252) comprises at least one of the following elements: a) checking (252a) the received test signal (TS), e.g. for correctness or for correspondence with a configurable signal pattern, e.g. a test pattern (TP), or b) analyzing (252b) the signal level of the received test signal (TS), or c) analyzing (252c) the signal quality of the received test signal (TS), or d) using at least one method based on artificial intelligence, e.g. machine learning (252d), or e) using a multi-stage decision system (252e).

15. Apparatus (300) for carrying out the method according to any one of claims 1 to 14.

16. An integrated circuit (101; 102) comprising at least one device (300) according to claim 15, for example for a multi-chiplet system (1000) having a plurality of chiplets, wherein for example the device (300) or the functionality of the device (300) is integrated in the integrated circuit (101; 102).

17. A system, such as a multichiplet system (1000), comprising at least one device (300) according to claim 15 or at least one integrated circuit (101; 102) according to claim 16.

18. A product, for example a control device (12), for example a motor vehicle (10), comprising at least one device (300) according to claim 15.

19. A vehicle, e.g., an automobile (10), comprising at least one device (300) according to claim 15 and / or at least one product, e.g., a control device (12), according to claim 18.

20. A computer readable memory medium (SM) comprising instructions (PRG) which, when executed by a computer (302), cause said computer (302) to perform the method of any one of claims 1 to 14.

21. A computer program (PRG) comprising instructions which, when executed by a computer (302), cause said computer (302) to carry out the method of any one of claims 1 to 14.

22. A data carrier signal (DCS) characterised by and / or carrying a computer program (PRG) according to claim 21.

23. The following elements are provided: a) ensuring (401) data communication between the first integrated circuit (101) and the at least one further, e.g., second, integrated circuit (102); or b) improving (402) robustness of data communication regarding the first integrated circuit (101), e.g., between the first integrated circuit (101) and the at least one further, e.g., second, integrated circuit (102); or c) improving (403) reliability of data communication regarding the first integrated circuit (101); or d) improving (404) availability of the first integrated circuit (101) and / or a system (1000) including the first integrated circuit (101); or e) operation of, e.g., the first integrated circuit (101). Use (400) of the method according to any one of claims 1 to 14 and / or the apparatus (300) according to claim 15 and / or the integrated circuit (101; 102) according to claim 16 and / or the system (1000) according to claim 17 and / or the product (12) according to claim 18 and / or the vehicle (10) according to claim 19 and / or the computer readable memory medium (SM) according to claim 20 and / or the computer program (PRG) according to claim 21 and / or the data carrier signal (DCS) according to claim 22 for at least one of improving design quality and / or manufacturing quality (405) based on feedback of knowledge from the

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