Electronic apparatus

The electronic device prevents display unit activation during power-saving mode by using a power supply unit to output different voltage levels and an input prohibition circuit to block the reset signal, addressing CPU-related malfunctions.

JP2025135629APending Publication Date: 2025-09-19KYOCERA DOCUMENT SOLUTIONS INC
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Patent Information

Application Number
JP2024033456
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-03-06
Publication Date
2025-09-19

AI Technical Summary

Technical Problem

In electronic devices, the CPU may output a reset signal before determining the operating mode, causing malfunctions such as the display unit being turned on even in the power-saving mode.

Method used

An electronic device with a display unit, power supply unit, and input prohibition circuit, where the power supply outputs different voltage levels based on the operating mode, and the input prohibition circuit prevents the reset signal from being input to the display unit during power-saving mode.

Benefits of technology

Prevents the display unit from activating during power-saving mode, thereby avoiding malfunctions.

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Abstract

To provide an electronic apparatus that can prevent a display from starting up during a power saving mode.SOLUTION: An image forming apparatus 100 comprises: an operation display unit 5 that starts up in response to input of a reset signal X2; a power supply unit 6 that outputs a voltage of a first value when an operation mode is a normal mode, and outputs a voltage of a second value lower than the first value when the operation mode is a power saving mode; a main CPU 73 that determines the operation mode after start-up, and when determining that the operation mode is the normal mode, inputs the reset signal X2 to the operation display unit 5; and an input inhibition circuit 74 that inhibits the main CPU 73 from inputting the reset signal X2 to the operation display unit 5 when the voltage output from the power supply unit 6 is of the second value.SELECTED DRAWING: Figure 2
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Description

[Technical Field]

[0001] The present invention relates to an electronic device. [Background technology]

[0002] A control circuit that starts up in response to input of a reset signal is known (see, for example, Patent Document 1). For example, an electronic device such as a printer includes a display unit that starts up in response to input of the reset signal.

[0003] Also, there is known an electronic device that can switch its operating mode between a normal mode and a power-saving mode that consumes less power than the normal mode. For example, in this type of electronic device, when a CPU is started, the CPU determines the operating mode. If the CPU determines that the operating mode is the normal mode, the CPU inputs the reset signal to the display unit. On the other hand, if the CPU determines that the operating mode is the power-saving mode, the CPU does not input the reset signal to the display unit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-129400 Summary of the Invention [Problem to be solved by the invention]

[0005] In the electronic device, the CPU may output the reset signal before determining the operating mode, and if the operating mode is the power-saving mode, a malfunction such as the backlight of the display unit being turned on may occur even in the power-saving mode.

[0006] An object of the present invention is to provide an electronic device that can prevent a display unit from activating during a power saving mode. [Means for solving the problem]

[0007] According to one aspect of the present invention, an electronic device includes a display unit, a power supply unit, a processor, and an input prohibition circuit. The display unit is activated in response to input of a reset signal. The power supply unit outputs a voltage of a predetermined first value when the operating mode of the device is a normal mode, and outputs a voltage of a second value lower than the first value when the operating mode is a power-saving mode in which power consumption is reduced compared to the normal mode. The processor determines the operating mode after activation, and inputs the reset signal to the display unit when it determines that the operating mode is the normal mode, and does not input the reset signal to the display unit when it determines that the operating mode is the power-saving mode. The input prohibition circuit prohibits the processor from inputting the reset signal to the display unit when the voltage output from the power supply unit is the second value. [Effects of the Invention]

[0008] According to the present invention, it is possible to prevent the display unit from activating during the power saving mode. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view showing the configuration of an image forming apparatus according to an embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing the configuration of an operation display unit, a power supply unit, and a control unit of the image forming apparatus according to the embodiment of the present invention. [Figure 3] FIG. 3 is a circuit diagram showing the configuration of the input prohibition circuit of the image forming apparatus according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. Note that the following embodiment is an example of a specific embodiment of the present invention and does not limit the technical scope of the present invention.

[0011] [Configuration of image forming apparatus 100] First, the configuration of an image forming apparatus 100 according to an embodiment of the present invention will be described with reference to Figures 1 and 2. In Figure 2, the image forming apparatus 100 is indicated by a dashed line.

[0012] The image forming apparatus 100 is a multifunction peripheral that has multiple functions, such as a scanning function for reading an image from a document, a printing function for forming an image on a sheet based on image data, a fax function, and a copy function. The image forming apparatus 100 is an example of an electronic device of the present invention. The present invention may also be applied to electronic devices such as scanners, printers, fax machines, copy machines, personal computers, laptop computers, televisions, microwave ovens, and refrigerators.

[0013] 1, the image forming apparatus 100 includes an ADF (Auto Document Feeder) 1, an image reading unit 2, an image forming unit 3, and a paper feeding unit 4. The image forming apparatus 100 also includes an operation display unit 5, a power supply unit 6, and a control unit 7 shown in FIG.

[0014] The ADF 1 transports documents to be scanned by the scanning function, and includes a document setting unit, a plurality of document transport rollers, a document holder, and a paper ejection unit.

[0015] The image reading unit 2 realizes the scanning function and includes a document table, a light source, a plurality of mirrors, an optical lens, and a CCD (Charge Coupled Device).

[0016] The image forming unit 3 realizes the printing function and includes a photosensitive drum, a charging roller, an optical scanning device, a developing device, a toner container, a transfer roller, a cleaning device, a fixing device, and a paper discharge tray.

[0017] The paper feed unit 4 supplies sheets to the image forming unit 3. The paper feed unit 4 includes a paper feed cassette, a pickup roller, a paper feed roller, a plurality of sheet transport rollers, and a registration roller.

[0018] The operation display unit 5 is a user interface of the image forming apparatus 100. The operation display unit 5 includes a display unit and an operation unit. The display unit displays various information in response to control instructions from the control unit 7. For example, the display unit is a flat panel display such as a liquid crystal display. The operation unit inputs various information to the control unit 7 in response to user operations. For example, the operation unit includes operation keys and a touch panel.

[0019] As shown in FIG. 2, the operation display unit 5 includes a substrate 51, a panel CPU 52, and a backlight LED 53.

[0020] On the substrate 51, the components of the operation display unit 5 are mounted.

[0021] The panel CPU 52 is a processor that executes various types of arithmetic processing and controls the operation and display unit 5.

[0022] The backlight LED 53 is used as a backlight for the display unit.

[0023] The operation and display unit 5 is activated in response to input of a reset signal X2 (see FIG. 2). Specifically, a signal line L1 (see FIG. 2) used for inputting the reset signal X2 is connected to the panel CPU 52 of the operation and display unit 5. The reset signal X2 is input to the panel CPU 52 when the voltage level of the signal line L1 is switched from low to high. The panel CPU 52 does not operate unless the reset signal X2 is input. The panel CPU 52 is activated in response to input of the reset signal X2. After activation, the panel CPU 52 turns on the backlight LED 53 and performs information display processing using the display unit. After activation, the panel CPU 52 also accepts user operations on the operation unit. The operation and display unit 5 is an example of a display unit of the present invention.

[0024] The power supply unit 6 receives power from an external commercial power supply 200 (see FIG. 2) and outputs power.

[0025] As shown in FIG. 2, the power supply unit 6 includes a substrate 61 and an AC / DC converter 62.

[0026] On the substrate 61, the components of the power supply unit 6 are mounted.

[0027] The AC / DC converter 62 converts the AC voltage input from the commercial power supply 200 into a DC voltage of a predetermined voltage value and outputs it.

[0028] When the operation mode of the image forming apparatus 100 is a normal mode, the power supply unit 6 outputs a voltage of a predetermined first value. When the operation mode of the image forming apparatus 100 is a power saving mode in which power consumption is reduced compared to the normal mode, the power supply unit 6 outputs a voltage of a second value lower than the first value. For example, the first value is 24V (volts). The second value is 8V (volts).

[0029] For example, the image forming apparatus 100 includes a power switch (not shown) used to switch between operation modes.

[0030] The AC / DC converter 62 determines the state of the power switch when started in response to power supply from the commercial power source 200. If the AC / DC converter 62 determines that the power switch is in the ON state, it outputs the voltage of the first value. If the AC / DC converter 62 determines that the power switch is in the OFF state, it outputs the voltage of the second value.

[0031] Furthermore, when the state of the power switch is switched during startup, the AC / DC converter 62 switches the voltage value of the output voltage between the first value and the second value.

[0032] The control unit 7 controls the image forming apparatus 100 in an overall manner.

[0033] As shown in FIG. 2, the control unit 7 includes a substrate 71, a DC-DC converter 72, a main CPU 73, and an input prohibition circuit 74.

[0034] On the board 71, the components of the control unit 7 are mounted.

[0035] The DC-DC converter 72 converts the DC voltage input from the AC-DC converter 62 into a DC voltage of a third value lower than the second value and outputs the converted DC voltage. For example, the third value is 3.3 V (volts).

[0036] 2, the third voltage value output from the DC-DC converter 72 is supplied to the main CPU 73. The main CPU 73 receives power from the DC-DC converter 72 to operate.

[0037] 2, the third voltage value output from the DC-DC converter 72 is supplied to the panel CPU 52 of the operation display unit 5. The panel CPU 52 receives power from the DC-DC converter 72 and operates.

[0038] 2, the third voltage value output from the DC-DC converter 72 is used to generate a reset signal X2. Specifically, the output terminal of the DC-DC converter 72 is connected to a signal line L1 via a resistor R1 (see FIG. 2).

[0039] The main CPU 73 is a processor that executes various types of arithmetic processing and is an example of the processor of the present invention.

[0040] The main CPU 73 inputs a reset signal X2 to the panel CPU 52. Specifically, the main CPU 73 is connected to a signal line L1 via a transistor Q1. The transistor Q1 is a PNP-type transistor. The emitter terminal of the transistor Q1 is connected to the signal line L1. The base terminal of the transistor Q1 is connected to the main CPU 73. The collector terminal of the transistor Q1 is connected to ground. The main CPU 73 inputs an output signal X1 to the base terminal of the transistor Q1 (applies a voltage) to turn the transistor Q1 off. This causes the voltage level of the signal line L1 to become high, and the reset signal X2 is input to the panel CPU 52. The main CPU 73 also stops the input of the output signal X1 to the base terminal of the transistor Q1 (stops the application of voltage), turning the transistor Q1 on. This connects the signal line L1 to ground, and the input of the reset signal X2 to the panel CPU 52 is stopped.

[0041] In the image forming apparatus 100, when the operation mode of the image forming apparatus 100 is the power saving mode, the operation and display unit 5 is stopped.

[0042] Specifically, the main CPU 73 determines the operation mode of the image forming apparatus 100 when started up in response to power supply from the DC-DC converter 72. For example, the main CPU 73 determines the operation mode by inquiring about the operation mode of the image forming apparatus 100 from the DC-DC converter 62 of the power supply unit 6.

[0043] When the main CPU 73 determines that the operation mode of the image forming apparatus 100 is the normal mode, the main CPU 73 inputs a reset signal X2 to the panel CPU 52 of the operation display unit 5.

[0044] Furthermore, when the main CPU 73 determines that the operation mode of the image forming apparatus 100 is the power saving mode, the main CPU 73 does not input the reset signal X2 to the panel CPU 52 of the operation display unit 5.

[0045] Incidentally, in the image forming apparatus 100, the reset signal X2 may be output from the main CPU 73 before the operation mode is determined by the main CPU 73. In this case, if the operation mode of the image forming apparatus 100 is the power saving mode, a problem may occur, such as the backlight of the operation display unit 5 being turned on even though the image forming apparatus 100 is in the power saving mode.

[0046] In contrast to this, in the image forming apparatus 100 according to the embodiment of the present invention, it is possible to prevent the operation display unit 5 from starting up during the power saving mode, as will be described below.

[0047] [Configuration of input prohibition circuit 74] Next, the configuration of the input prohibition circuit 74 will be described with reference to Figures 2 and 3. In Figure 3, the input prohibition circuit 74 is indicated by a broken line.

[0048] The input prohibition circuit 74 prohibits the main CPU 73 from inputting the reset signal X2 to the operation display unit 5 when the voltage output from the power supply unit 6 is the second value.

[0049] As shown in FIG. 3, the input prohibition circuit 74 includes a voltage dividing circuit 81, a generating circuit 82, and a comparator 83.

[0050] The voltage divider circuit 81 divides the voltage output from the power supply unit 6. Specifically, the voltage divider circuit 81 divides the voltage of the first value or the second value input from the AC / DC converter 62 of the power supply unit 6. As shown in FIG. 3, the voltage divider circuit 81 includes resistors R11 and R12 connected in series. For example, the resistance of the resistor R11 is set to be seven times the resistance of the resistor R12. In this case, the voltage divider circuit 81 divides the voltage input from the AC / DC converter 62 of the power supply unit 6 by eighth and outputs the divided voltage.

[0051] The generation circuit 82 generates a predetermined reference voltage based on the voltage output from the power supply unit 6. Specifically, the reference voltage is lower than the output voltage of the voltage divider circuit 81 when the voltage output from the power supply unit 6 is the first value and higher than the output voltage of the voltage divider circuit 81 when the voltage output from the power supply unit 6 is the second value. As shown in FIG. 3 , the generation circuit 82 includes a resistor R21 and a Zener diode D1 connected in series. The anode terminal of the Zener diode D1 is connected to ground. The cathode terminal of the Zener diode D1 is connected to the AC / DC converter 62 via the resistor R21. For example, the Zener voltage of the Zener diode D1 is set to 2.2 V (volts). In this case, the generation circuit 82 outputs the reference voltage of 2.2 V (volts) in response to the voltage input from the AC / DC converter 62 of the power supply unit 6.

[0052] The comparator 83 switches whether to set the voltage level of the signal line L1 (see FIG. 3) used to input the reset signal X2 to a low level, based on the magnitude relationship between the output voltage of the voltage-dividing circuit 81 and the reference voltage. As shown in FIG. 3, the output voltage of the voltage-dividing circuit 81 is input to a non-inverting input terminal of the comparator 83. The reference voltage generated by the generation circuit 82 is input to an inverting input terminal of the comparator 83.

[0053] The comparator 83 outputs a high-level electrical signal when the voltage input to the non-inverting input terminal is higher than the voltage input to the inverting input terminal. In other words, the comparator 83 outputs a high-level electrical signal when the voltage output from the AC / DC converter 62 of the power supply unit 6 is the first value.

[0054] On the other hand, the comparator 83 outputs a low-level electrical signal when the voltage input to the non-inverting input terminal is lower than the voltage input to the inverting input terminal. That is, the comparator 83 outputs a low-level electrical signal when the voltage output from the AC / DC converter 62 of the power supply unit 6 is the second value. This sets the voltage level of the signal line L1 (see FIG. 3) to a low level. Therefore, input of the reset signal X2 by the main CPU 73 to the operation display unit 5 is prohibited.

[0055] In this way, in the image forming apparatus 100, when the operating mode is the power saving mode, the input prohibition circuit 74 prohibits the main CPU 73 from inputting the reset signal X2 to the operation and display unit 5. Therefore, even if the output signal X1 (see FIG. 2) is output from the main CPU 73 after the main CPU 73 has started up but before the main CPU 73 has determined the operating mode, the input of the reset signal X2 in response to the output of the output signal X1 is prohibited. Therefore, it is possible to prevent the operation and display unit 5 from starting up during the power saving mode.

[0056] [Notes on the Invention] The following is a summary of the invention extracted from the above-described embodiment. Note that the configurations and processing functions described in the following supplementary notes can be selected and combined as desired.

[0057] <Appendix 1> an input prohibition circuit that prohibits the processor from inputting the reset signal to the display unit when the voltage output from the power supply unit is the second value; an input prohibition circuit that prohibits the processor from inputting the reset signal to the display unit when the voltage output from the power supply unit is the second value; an input prohibition circuit that prohibits the processor from inputting the reset signal to the display unit when the voltage output from the power supply unit is the second value; and an input prohibition circuit that prohibits the processor from inputting the reset signal to the display unit when the voltage output from the power supply unit is the second value.

[0058] <Appendix 2> the input prohibition circuit includes: a voltage divider circuit that divides the voltage output from the power supply unit; a generation circuit that generates, based on the voltage output from the power supply unit, a reference voltage that is lower than the output voltage of the voltage divider circuit when the voltage output from the power supply unit is the first value and higher than the output voltage of the voltage divider circuit when the voltage output from the power supply unit is the second value; and a comparator that switches whether to set the voltage level of a signal line used for inputting the reset signal to a low level based on the magnitude relationship between the output voltage of the voltage divider circuit and the reference voltage.

[0059] <Appendix 3> 3. The electronic device according to claim 1, further comprising: an image reading unit that reads an image of a document; and an image forming unit that forms an image on a sheet, or both of these. [Explanation of symbols]

[0060] 1 ADF 2 Image reading unit 3 Image forming unit 4 Paper feed section 5 Operation display section 6 Power supply section 7 Control Unit 51 PCB 52 Panel CPU 53 Backlight LED 61 PCB 62 ACDC converter 71 PCB 72 DC-DC converter 73 Main CPU 74 Input prohibition circuit 81 Voltage divider circuit 82 Generation circuit 83 Comparator 100 Image forming device

Claims

1. a display unit that is activated in response to an input of a reset signal; a power supply unit that outputs a voltage of a predetermined first value when the operation mode of the device itself is a normal mode, and outputs a voltage of a second value lower than the first value when the operation mode is a power saving mode in which power consumption is reduced compared to the normal mode; a processor that determines the operation mode after startup, and inputs the reset signal to the display unit when it determines that the operation mode is the normal mode, and does not input the reset signal to the display unit when it determines that the operation mode is the power saving mode; an input prohibition circuit that prohibits the processor from inputting the reset signal to the display unit when the voltage output from the power supply unit is the second value; An electronic device comprising:

2. The input prohibition circuit includes: a voltage dividing circuit that divides the voltage output from the power supply unit; a generation circuit that generates, based on the voltage output from the power supply unit, a reference voltage that is lower than the output voltage of the voltage divider circuit when the voltage output from the power supply unit is the first value and higher than the output voltage of the voltage divider circuit when the voltage output from the power supply unit is the second value; a comparator that switches whether or not to set the voltage level of a signal line used for inputting the reset signal to a low level based on the magnitude relationship between the output voltage of the voltage divider circuit and the reference voltage; The electronic device according to claim 1 , comprising:

3. The image reading unit reads an image of a document, and / or the image forming unit forms an image on a sheet.

3. The electronic device according to claim 1 or 2.

Citation Information

Patent Citations

  • Electronic equipment having reset signal output circuit

    JP2006129400A