Arithmetic circuit, memory system and control method

Abstract

To suppress the scale of an arithmetic circuit.SOLUTION: An arithmetic circuit comprises a first substitution circuit and a second substitution circuit. The first substitution circuit calculates p / 2 pieces of first evaluation values by substituting inspection values in first input polynomials represented by primary to s-th order coefficients of an error position polynomial. The second substitution circuit calculates second evaluation values. In a case where an error number is t / 2 or less, the arithmetic circuit outputs (p) pieces of error position information including error position information calculated from the first evaluation values, which are calculated by substituting p / 2 pieces of first inspection values, and error position information calculated from second evaluation values calculated by substituting the first inspection values in second input polynomials represented by coefficients obtained by converting the coefficients of the first input polynomials. In a case where the error number is more than t / 2, the arithmetic circuit outputs p / 2 pieces of error position information calculated based on the first evaluation values and third evaluation values, for which the second evaluation values are converted, calculated by third polynomials represented by (s+1)th order to t-th order coefficients of the error position polynomial.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to an arithmetic circuit, a memory system, and a control method. [Background technology]

[0002] In a memory system, in order to protect data stored in a memory such as a NAND flash memory, error correction coded data is stored in the memory. Therefore, when reading data stored in the memory, the error correction coded data (also called a received word) read from the memory is decoded to restore the data before being error correction coded.

[0003] For error-correcting codes, decoding techniques using error locator polynomials are known. For example, Chien search is known as a method for calculating error locations using an error locator polynomial. Chien search is a method in which values ​​are sequentially substituted into the error locator polynomial and the error location is searched for based on the value that makes the output value of the error locator polynomial zero. In the decoding process, the scale of the calculation circuitry for the process of searching for the root of the error locator polynomial, such as Chien search, tends to become large. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2018 / 0241415 [Patent Document 2] US Patent Application Publication No. 2021 / 0263797 [Patent Document 3] US Patent Application Publication No. 2011 / 0072334 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the embodiment of the present invention is to reduce the scale of an arithmetic circuit used for operations such as decoding processing. [Means for solving the problem]

[0006] The arithmetic circuit of the embodiment includes a first substitution circuit and a second substitution circuit. The first substitution circuit calculates p / 2 first evaluation values ​​by substituting inspection values ​​into a first input polynomial expressed by coefficients of degrees 1 to s of the error locator polynomial. The second substitution circuit calculates a second evaluation value. When the number of errors is t / 2 or less, the arithmetic circuit outputs p pieces of error location information including error location information calculated from first evaluation values ​​calculated by substituting the p / 2 first inspection values ​​and error location information calculated from second evaluation values ​​calculated by substituting the first inspection values ​​into a second input polynomial expressed by coefficients obtained by converting the coefficients of the first input polynomial. When the number of errors is greater than t / 2, the arithmetic circuit outputs p / 2 pieces of error location information calculated based on the first evaluation values ​​and third evaluation values ​​obtained by converting second evaluation values ​​calculated using a third polynomial expressed by coefficients of degrees (s+1) to t of the error locator polynomial. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of a memory system according to an embodiment. [Figure 2] FIG. 2 is a block diagram of a decoding unit according to the embodiment. [Figure 3] FIG. 2 is a block diagram showing an error position calculation unit of the first configuration example. [Figure 4] FIG. 10 is a diagram for explaining an example of an output from a computing unit. [Figure 5] FIG. 2 is a block diagram showing an error position calculation unit of the first configuration example. [Figure 6] FIG. 10 is a diagram showing an example of calculation when the number of errors is small. [Figure 7] FIG. 10 is a diagram showing an example of calculation when the number of errors is large. [Figure 8] FIG. 10 is a diagram for explaining the operation of an error position calculation unit in the second configuration example. [Figure 9] FIG. 10 is a diagram for explaining the operation of an error position calculation unit in the second configuration example. [Figure 10] FIG. 10 is a diagram for explaining the operation of an error position calculation unit in the configuration example 3. [Figure 11]FIG. 10 is a diagram for explaining the operation of an error position calculation unit in the configuration example 3. [Figure 12] FIG. 2 is a block diagram showing an example of the configuration of an error position calculation unit according to the embodiment. [Figure 13] FIG. 10 is a diagram showing an example of calculation by the error position calculation unit when there are a large number of errors. [Figure 14] FIG. 4 is a block diagram showing a more detailed configuration example of an error position calculation unit. [Figure 15] FIG. 4 is a block diagram showing a more detailed configuration example of an error position calculation unit. [Figure 16] FIG. 4 is a block diagram showing a more detailed configuration example of an error position calculation unit. [Figure 17] 10 is a flowchart showing an example of a decoding process according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] A preferred embodiment of an arithmetic circuit according to the present invention will be described in detail below with reference to the accompanying drawings. The following description will be given taking as an example a memory system including an arithmetic circuit that searches for the roots of an error locator polynomial when decoding an error correction code. The configuration using the arithmetic circuit is not limited to this example, and any system (device, equipment) may be used.

[0009] First, a memory system according to this embodiment will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration example of a memory system according to this embodiment. As shown in FIG. 1, the memory system 1 includes a memory controller 10 and a nonvolatile memory 20. The memory system 1 can be connected to a host 30, and FIG. 1 shows the memory system 1 connected to the host 30. The host 30 may be, for example, an electronic device such as a personal computer or a mobile terminal.

[0010] The nonvolatile memory 20 is a nonvolatile memory that stores data nonvolatilely, such as a NAND flash memory (hereinafter simply referred to as a NAND memory). In the following description, a case where a NAND memory is used as the nonvolatile memory 20 will be exemplified, but it is also possible to use storage devices other than a NAND memory, such as a three-dimensional structure flash memory, a ReRAM (Resistive Random Access Memory), or an FeRAM (Ferroelectric Random Access Memory), as the nonvolatile memory 20. Furthermore, it is not essential that the nonvolatile memory 20 be a semiconductor memory, and this embodiment can also be applied to various storage media other than semiconductor memories.

[0011] The memory system 1 may be any of various memory systems equipped with a nonvolatile memory 20, such as a so-called SSD (Solid State Drive) or a memory card in which a memory controller 10 and a nonvolatile memory 20 are configured as a single package.

[0012] The memory controller 10 controls writing to the nonvolatile memory 20 in accordance with a write request from the host 30. The memory controller 10 also controls reading from the nonvolatile memory 20 in accordance with a read request from the host 30. The memory controller 10 is a semiconductor integrated circuit configured as, for example, an SoC (System on a Chip). The memory controller 10 includes a host I / F (host interface) 15, a memory I / F (memory interface) 13, a control unit 11, an encoding / decoding unit (codec) 14, and a data buffer 12. The host I / F 15, the memory I / F 13, the control unit 11, the encoding / decoding unit 14, and the data buffer 12 are interconnected by an internal bus 16. Some or all of the operations of the components of the memory controller 10 described below may be implemented by a CPU (Central Processing Unit) executing firmware, or may be implemented by hardware.

[0013] The host I / F 15 performs processing in accordance with the interface standard with the host 30, and outputs commands received from the host 30, user data to be written, etc. to the internal bus 16. The host I / F 15 also transmits user data read and restored from the nonvolatile memory 20, responses from the control unit 11, etc. to the host 30.

[0014] The memory I / F 13 performs a write process to the nonvolatile memory 20 based on an instruction from the control unit 11. The memory I / F 13 also performs a read process from the nonvolatile memory 20 based on an instruction from the control unit 11.

[0015] The control unit 11 performs overall control of each component of the memory system 1. When the control unit 11 receives an instruction from the host 30 via the host I / F 15, it performs control in accordance with the instruction. For example, the control unit 11 instructs the memory I / F 13 to write user data and parity to the nonvolatile memory 20 in accordance with the instruction from the host 30. The control unit 11 also instructs the memory I / F 13 to read user data and parity from the nonvolatile memory 20 in accordance with the instruction from the host 30.

[0016] Furthermore, when the control unit 11 receives a write request from the host 30, it determines a storage area (memory area) on the nonvolatile memory 20 for the user data stored in the data buffer 12. That is, the control unit 11 manages the write destination of the user data. The correspondence between the logical address of the user data received from the host 30 and the physical address indicating the storage area on the nonvolatile memory 20 where the user data is stored is stored as an address conversion table.

[0017] Furthermore, when the control unit 11 receives a read request from the host 30, it converts the logical address specified by the read request into a physical address using the address conversion table described above, and instructs the memory I / F 13 to read from the physical address.

[0018] In NAND memory, data is generally written and read in units of data called pages, and erased in units of data called blocks. In this embodiment, a plurality of memory cells connected to the same word line are called a memory cell group. When the memory cells are single-level cells (SLC: Single Level Cell), one memory cell group corresponds to one page. When the memory cells are multi-level cells (MLC: Multiple Level Cell), one memory cell group corresponds to multiple pages. In this description, MLC includes triple-level cells (TLC) and quad-level cells (QLC). Each memory cell is connected to a word line and also to a bit line. Therefore, each memory cell can be identified by an address that identifies the word line and an address that identifies the bit line.

[0019] The data buffer 12 temporarily stores user data received by the memory controller 10 from the host 30 before storing the data in the nonvolatile memory 20. The data buffer 12 also temporarily stores user data read from the nonvolatile memory 20 before transmitting the data to the host 30. The data buffer 12 may be a general-purpose memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory). The data buffer 12 may not be built into the memory controller 10 but may be mounted outside the memory controller 10.

[0020] User data transmitted from the host 30 is transferred to the internal bus 16 and temporarily stored in the data buffer 12. The encoding / decoding unit 14 encodes the user data stored in the nonvolatile memory 20 to generate code words. The encoding / decoding unit 14 also decodes received words read from the nonvolatile memory 20 to restore the user data. Therefore, the encoding / decoding unit 14 includes an encoding unit (Encoder) 17 and a decoding unit (Decoder) 18. Note that the data encoded by the encoding / decoding unit 14 may include control data used inside the memory controller 10 in addition to the user data.

[0021] Next, the write process of this embodiment will be described. When writing user data to the nonvolatile memory 20, the control unit 11 instructs the encoding unit 17 to encode the user data. At that time, the control unit 11 determines a storage location (storage address) of the code word in the nonvolatile memory 20, and also instructs the memory I / F 13 of the determined storage location.

[0022] The encoding unit 17 encodes the user data in the data buffer 12 to generate code words based on instructions from the control unit 11. Examples of encoding methods that can be used include encoding methods using algebraic codes such as BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon) codes, as well as encoding methods (such as product codes) that use these codes as row- and column-oriented component codes. The memory I / F 13 controls the storage of code words in memory locations in the nonvolatile memory 20 instructed by the control unit 11. The following describes an example in which a BCH code that corrects errors of t bits or less is used.

[0023] As will be described below, in this embodiment, the t coefficients of the t-th degree error locator polynomial are divided into coefficients from 1st to (t / 2)th degrees and coefficients from (t / 2+1)th to tth degrees for calculation.

[0024] Next, a description will be given of the processing performed when reading from the nonvolatile memory 20 in this embodiment. When reading from the nonvolatile memory 20, the control unit 11 specifies an address on the nonvolatile memory 20 and instructs the memory I / F 13 to read. The control unit 11 also instructs the decoding unit 18 to start decoding. In accordance with the instruction from the control unit 11, the memory I / F 13 reads the received word from the specified address in the nonvolatile memory 20 and inputs the read received word to the decoding unit 18. The decoding unit 18 decodes the received word read from the nonvolatile memory 20.

[0025] The decoding unit 18 decodes the received word read from the nonvolatile memory 20. The decoding unit 18 performs calculation of an error locator polynomial using, for example, the PGZ (Peterson-Gorenstein-Zierler) method, the BM (Berlekamp-Massey) method, or the Euclidean method.

[0026] Fig. 2 is a block diagram showing an example of the configuration of the decoding unit 18 according to this embodiment. As shown in Fig. 2, the decoding unit 18 includes a syndrome calculation unit 101, an error position polynomial calculation unit 102, an error position calculation unit 103 as an arithmetic circuit, and a correction unit 104.

[0027] The syndrome calculation unit 101 calculates a syndrome using the received word (read sequence) read from the non-volatile memory 20. The syndrome calculation unit 101 may calculate the syndrome using any conventional method. Depending on the number of corrections, multiple syndromes may be calculated. If all the syndrome values ​​are 0, it can be determined that there is no error in the received word, and the decoding unit 18 can terminate the decoding process without performing any further processing.

[0028] The error locator polynomial calculation unit 102 uses the syndrome to calculate the error locator polynomial by the PGZ method, the BM method, the Euclidean method, etc. Some of the coefficients of the error locator polynomial are calculated by adding and multiplying the syndrome.

[0029] The syndrome and the coefficient σ calculated using the syndrome are elements of the Galois field. m It is a set with m elements (m is an integer greater than or equal to 1) and the four arithmetic operations are defined and characterized by a primitive polynomial of degree m.

[0030] The error locator polynomial calculation unit 102 outputs the coefficients of the calculated error locator polynomial and the degree of the error locator polynomial. The degree of the error locator polynomial corresponds to the estimated number of errors. The coefficients of the t-th degree error locator polynomial are expressed as σ i (i is an integer satisfying 0≦i≦t). The t-th degree error locator polynomial σ(x) is expressed by, for example, the following equation (1).

number

[0031] Coefficient σ i is expressed in the Galois field GF(2 m ) where α is a primitive element of a Galois field. Non-zero elements of a Galois field can be expressed as powers of the primitive element α.

number

[0032] The following equation (3) is for t=6 and m=9 (GF(2 9 )) and an example of the error locator polynomial when the number of errors is 3 is shown below. Since the number of errors is 3, the coefficients corresponding to the fourth to sixth orders are 0.

number

[0033] The error location calculation unit 103 calculates an error location using the error location polynomial calculated by the error location polynomial calculation unit 102. The process of calculating the error location (searching process) may be realized by any method, but for example, Chien search can be used. Chien search is a method of sequentially substituting values ​​into the error location polynomial and searching for the error location based on the value (root of the error location polynomial) that makes the output value of the error location polynomial 0.

[0034] The correction unit 104 performs error correction by inverting (bit flipping) the bit at the error position calculated by the search process.

[0035] The error location calculation unit 103 is realized by, for example, a register, an adder, a multiplier, a selector, and other computing units. The syndrome calculation unit 101 and the error location polynomial calculation unit 102 are also realized by, for example, a register, an adder, a multiplier, a selector, and other computing units. The correction unit 104 is realized by, for example, an adder for adding a bit sequence reflecting the error location information output from the error location calculation unit 103 and a read sequence, but may be realized by other computing units. Here, the bit sequence reflecting the error location information is, for example, a sequence in which the output HITi of a computing unit 341 (described later) is arranged. The register is realized by, for example, a logic circuit such as a flip-flop. The adder, multiplier, selector, and other computing units are realized by, for example, a logic circuit.

[0036] Next, the details of the function of the error position calculation unit 103 will be described. In this embodiment, the error position calculation unit 103 calculates the error position by Chien search. Also, in this embodiment, the error position calculation unit 103 searches for multiple error positions in parallel by substituting multiple check values ​​in parallel into the error position polynomial. The search process is performed in parallel, for example, to reduce the latency of the entire decoding process. Hereinafter, the Chien search that searches for multiple error positions in parallel may be referred to as a parallel Chien search.

[0037] First, a parallel Chien search will be described. An example of the configuration of the error location calculation unit 103 will be described later. Below, an example of a parallel Chien search will be described in which the maximum number of correctable bits t by the BCH code is 4 and the parallelism p is 2. The parallelism p means that calculations of p error locations are performed in parallel. In this example, two values ​​obtained by substituting two check values ​​x1 and x2 as shown in the following equation (4) into the error location polynomial are calculated in parallel.

number

[0038] x1 and x2 are, for example, α i , α i+1 In the first cycle, for example, starting from i=1, (x1, =α 1 , x2=α 2 ), and in the next cycle, x1 and x2 are assigned α p =α 2 is multiplied (x1, = α 3 , x2=α 4 ), the process is repeated.

[0039] Equation (5) is equivalent to the matrix representation of equation (4). The 2-by-4 matrix in the second term on the right-hand side is sometimes called the Vandermonde Matrix.

number

[0040] An explanation will be given of a configuration example 1 of an error position calculation unit that realizes a parallel Chien search. Fig. 3 is a block diagram showing the error position calculation unit of configuration example 1. Note that Fig. 3 shows a configuration of a parallel Chien search with a parallelism p=2.

[0041] The calculation for a parallelism of 2 is similar to equations (4) and (5), for example, x1 = α i , x2=α i+1 This corresponds to an example in which the inspection values ​​x1 and x2 are calculated in parallel. In this case, equation (5) can be rewritten as equation (6) below.

number

[0042] σ L is a vector containing the low-order coefficients σ1 and σ2 as elements. σ H is a vector containing the high-order coefficients σ3 and σ4 as elements. The Vandermonde matrix in the first row of equation (6) is a matrix with 1 row and 2 columns, as follows: Low Normal , V High Normal , V Low Extra , V High Extra It can be expressed as: V Low Normal =(α i α 2i ) V High Normal =(α 3i α 4i ) V Low Extra =(α i+1 α 2(i+1) ) V High Extra =(α 3(i+1) α 4(i+1) )

[0043] Normal corresponds to the first half of the two parallelized calculations, and Extra corresponds to the second half of the two parallelized calculations. Normal corresponds to the check value (e.g., x1 = α i , x2=α i+1 ) among the test values ​​with the smallest exponent (x1=α i ), and Extra corresponds to the test value with a large exponent (x2=α i+1 ) can also be interpreted as equivalent to

[0044] As shown in FIG. 3, the error-position calculation unit of the first configuration example includes a register 301, circuits 310a and 310b, circuits 320a to 320d, adders 331 and 332, and calculators 341 and 342.

[0045] The register 301 (third register) is a register that stores the coefficient σ 0 (third coefficient) of the error locator polynomial. The circuit 310a stores the vector σ 0 including the low-order coefficients (first coefficients). L It corresponds to a circuit that outputs the vector σ L The polynomial with coefficients is a low-degree polynomial σ L The circuit 310b may be referred to as a vector σ (x) (first polynomial). H It corresponds to a circuit that outputs the vector σ H The polynomial with coefficients is a high-order polynomial σ H This is sometimes called (x).

[0046] The low-order coefficients are the 1st to sth order coefficients, and the high-order coefficients are the (s+1)th to tth order coefficients. s is, for example, the smallest integer equal to or greater than t / 2 (s=ceiling(t / 2)), or the largest integer equal to or less than t / 2 (s=floor(t / 2)). The following mainly describes an example where t is an even number, i.e., s=t / 2.

[0047] low-order polynomial σ L (x) and high-order polynomial σ H (x) has the relationship with the error locator polynomial σ(x) shown in the following equation (7).

number

[0048] The circuit 310a includes registers 311 and 313 (first registers) and multipliers 312 and 314.

[0049] The registers 311 and 313 are registers that store either of two elements of the Galois field in m-bit representation based on two low-order coefficients. The multiplier 312 multiplies the value stored in the register 311 by a fixed value (α1·p =α 1·2 ) to output a low-order coefficient to be used in the next cycle. The multiplier 314 multiplies the value stored in the register 313 by a fixed value (α 2·p =α 2·2 ) and outputs a low-order coefficient to be used in the next cycle. Note that the two selectors in 310a select the coefficient σ1 or σ2 in the first cycle (cycle 0), and select the output of multiplier 312 or multiplier 314 in subsequent cycles (cycle 1 and onward).

[0050] The circuit 310b receives the input coefficients (σ3, σ4) and the fixed value (α 3·p =α 3·2 , α 4·p =α 4·2 ) and has the same configuration as circuit 310a, so description thereof will be omitted. Registers 311 and 313 of circuit 310b correspond to registers (second registers) that store high-order coefficients.

[0051] The circuits 320a, 320b, 320c, and 320d each calculate a matrix V Low Normal , V High Normal , V Low Extra , V High Extra The circuit 320a includes multipliers 321 and 322 and an adder 323.

[0052] Multiplier 321 multiplies the matrix V Low Normal The value α, which is the first element of i and the input coefficient σ L The multiplier 322 multiplies the first element of the matrix V by the first element of the matrix V and outputs the result to the adder 323. Low Normal The value α, which is the second element of 2i and the input coefficient σ L The adder 323 outputs the result of multiplying the second element of by to the adder 323. The adder 323 adds the two input values ​​and outputs the result to the adder 331.

[0053] The circuits 320b, 320c, and 320d only differ in the coefficients input thereto or the values ​​to be multiplied thereto, and have the same configuration as the circuit 320a, and therefore a description thereof will be omitted.

[0054] Adder 331 adds the value of register 301, the output of circuit 320a, and the output of circuit 320b, and outputs the result to calculator 341. Adder 332 adds the value of register 301, the output of circuit 320c, and the output of circuit 320d, and outputs the result to calculator 342.

[0055] The arithmetic unit 341 outputs a bit 1 as the output HITi when the output of the adder 331 is 0 of the Galois field, and outputs a bit 0 as HITi when the output is a value other than 0 of the Galois field. The arithmetic unit 342 outputs a bit 1 as HIT(i+1) when the output of the adder 332 is 0 of the Galois field, and outputs a bit 0 as HIT(i+1) when the output is a value other than 0 of the Galois field.

[0056] 4 is a diagram for explaining an example of the output of the calculators 341 and 342. As shown in FIG. 4, in the process of cycle 1, the value of HITi is x1=α i is the root of the error locator polynomial (σ(α i )=0) the value is 1, which indicates a root, and x1=α i is not a root of the error locator polynomial (σ(α i )≠0), the value is 0, which indicates that it is not a root. Also, the value of HIT(i+1) is x1=α i+1 is the root of the error locator polynomial (σ(α i+1 )=0) the value is 1, which indicates a root, and x1=α i+1 is not a root of the error locator polynomial (σ(α i+1 )≠0), the value is 0, indicating that it is not a root.

[0057] In the process of cycle 2, the value of HITi is x1=α i+2 is the root of the error locator polynomial (σ(α i+2)=0) the value is 1, which indicates a root, and x1=α i+2 is not a root of the error locator polynomial (σ(α i+2 )≠0), the value is 0, which indicates that it is not a root. Also, the value of HIT(i+1) is x1=α i+3 is the root of the error locator polynomial (σ(α i+3 )=0) the value is 1, which indicates a root, and x1=α i+3 is not a root of the error locator polynomial (σ(α i+3 )≠0), the value is 0, indicating that it is not a root.

[0058] Such multiple cycles of processing are repeated using the Galois field element that becomes the next check value.

[0059] The configuration of the error location calculation unit that realizes the parallel Chien search is not limited to the configuration shown in FIG. 3. Moreover, the configuration shown in FIG. 3 can be expressed by omitting the internal description of each unit, as shown in FIG. 5. FIG. 5 is a block diagram showing the error location calculation unit of configuration example 1. For example, in FIG. 5, the description of the configuration corresponding to the register 301, the circuits 310a and 310b, and the arithmetic units 341 and 342 shown in FIG. 3 is omitted, but the error location calculation unit may further include these configurations. The same applies to the error location calculation units shown in the subsequent figures.

[0060] The output of adder 331 can be interpreted as the output for p / 2 test values ​​corresponding to Normal out of the p test values ​​substituted in parallel. The output of adder 332 can be interpreted as the output for p / 2 test values ​​corresponding to Extra out of the p test values ​​substituted in parallel. For this reason, in FIG. 5, the outputs of adder 331 and adder 332 are respectively σ(x 1:p / 2 ) and σ(x p / 2+1:p ) is expressed as follows.

[0061] The output of adder 331 is σ(x 1:p / 2 ) is the number from x1 to x p / 2 The output of the adder 332, σ(x p / 2+1:p ) is xp / 2+1 From x p This means that it contains p / 2 outputs of the error locator polynomial when p / 2 check values ​​up to are substituted.

[0062] Output σ(x 1:p / 2 ) is σ(x1)~σ(x p / 2 ) corresponds to a vector containing p / 2 elements. Each element σ(x i ) (1≦i≦p / 2) can be interpreted as corresponding to the error location information LA (first error location information) indicating whether i is an error location. Similarly, the output σ(x p / 2+1:p ) is σ(x p / 2+1 )~σ(x p ) corresponds to a vector containing p / 2 elements. Each element σ(x i )(p / 2+1≦i≦p) can be interpreted as corresponding to error location information LB (second error location information) indicating whether i is an error location or not. Note that HITi and HIT(i+1), which are outputs of the calculators 341 and 342, can also be interpreted as corresponding to error location information indicating whether i and i+1 are error locations or not.

[0063] Here, the representation format of the error locator polynomial will be further explained. The t-th degree error locator polynomial σ(x) is expressed by the above equation (1). i The equation substituted with can be expressed in the form of an inner product of vectors as in the following equation (8).

number

[0064] In a parallel Chien search with a parallelism degree of p, the error location polynomial has p inspection values ​​(x1, x2, . . . , x p ) are assigned in parallel. The p test values ​​are assigned to the vector x 1:p Then, the calculation of substituting p check values ​​into the error locator polynomial in parallel can be expressed in the form of a matrix operation as shown in the following equation (9). i 1:t (1≦i≦p) is (x i 1 ,x i2 ,···,x i t ) means that the matrix V 1:p 1:t means the Vandermonde matrix with p rows and t columns.

number

[0065] 5 can be interpreted as a configuration example of an error location calculation unit that realizes a parallel Chien search with a parallelism degree of p. The calculation of the t-th degree error location polynomial by the parallel Chien search with a parallelism degree of p as shown in FIG. 5 is expressed by the following equation (10).

number

[0066] An example of calculation according to configuration example 1 of FIG. 5 will be described with reference to FIG. 6 and FIG. 7. FIG. 6 is a diagram showing an example of calculation when the number of errors is small. FIG. 7 is a diagram showing an example of calculation when the number of errors is large. A case where the number of errors is small is, for example, when the number of errors is t / 2 or less. A case where the number of errors is large is, for example, when the number of errors is greater than t / 2.

[0067] When the number of errors is small (Fig. 6), the coefficients of the t-th order error locator polynomial are all 0. That is, σ H is a vector in which all elements are 0 (hereinafter referred to as a zero vector). L A circuit 320a (V Low Normal ), 320c(V Low Extra ) operates (activates), but σ H A circuit 320b (V High Normal Compatible with 320d(V High Extra Therefore, in the case of Figure 6, it is possible to reduce power consumption. Note that the dashed lines in Figure 6 indicate that the circuit does not operate.

[0068] On the other hand, when the number of errors is large (FIG. 7), at least some of the higher-order coefficients of the error-location polynomial at the t-th time become non-zero values. Therefore, all of the circuits 320a to 320d included in the error-location calculation unit of Configuration Example 1 operate (activate). As a result, there is a possibility that an increase in power consumption cannot be suppressed.

[0069] In FIGS. 6 and 7, examples of calculation formulas corresponding to the operations of the circuits are shown above the circuits.

[0070] In the parallel syndrome search, the power consumption of the circuit may increase as the number of errors increases. In order to suppress an increase in power consumption, a configuration in which the parallelism is halved when the number of errors increases is conceivable. Hereinafter, such a configuration may be referred to as a two-way parallel syndrome search. In the present embodiment, in order to divide the calculation of the parallelism p into two, p is an even integer satisfying 2 ≤ p < n. n is an integer of 2 or more representing the code length (number of bits) of the error correction code.

[0071] Hereinafter, Configuration Example 2 of the two-way parallel syndrome search that can suppress the power consumption even when the number of errors is large will be described. FIGS. 8 and 9 are diagrams for explaining the operation of the error-location calculation unit of Configuration Example 2 that realizes the two-way parallel syndrome search. In Configuration Example 2, selectors 801 and 802 for switching the circuits to be operated are added. [[ID=1s]]

[0072] Selector 801 selects a vector σ including lower-order coefficients when the number of errors is small (for example, the number of errors is t / 2 or less) (FIG. 8), and selects a zero vector when the number of errors is large (for example, the number of errors is greater than t / 2) (FIG. 9). L and selects a zero vector when the number of errors is large (for example, the number of errors is greater than t / 2) (FIG. 9).

[0073] Selector 802 selects a vector σ including higher-order coefficients when the number of errors is small (FIG. 8), and selects a zero vector when the number of errors is large (FIG. 9). When the number of errors is small, since the vector σ H becomes a vector in which all elements are 0, in FIG. 8, the vector σ H is a vector in which all elements are 0, so in FIG. 8, the vector σ HInstead of , a zero vector is listed.

[0074] As shown in Fig. 9, when the number of errors is large, the circuits 320c and 320d can be configured not to operate. This makes it possible to suppress an increase in power consumption compared to, for example, configuration example 1 in Fig. 5 (Fig. 7).

[0075] 8 and 9, in configuration example 2, circuit 320d does not operate whether the number of errors is small or large. Therefore, unnecessary circuit 320d is provided, which may make it difficult to suppress the circuit size.

[0076] Configuration example 3, which can reduce the circuit size, will be described. Figures 10 and 11 are diagrams for explaining the operation of the error position calculation unit of configuration example 3. Configuration example 3 differs from configuration example 2 in that the selector 802 and the circuit 320d are deleted.

[0077] When the number of errors is small, the selector 801 selects a vector σ L (Fig. 10), and if the number of errors is large, select the zero vector (Fig. 11).

[0078] In the configuration example 3, since the unnecessary circuit 320d and the selector 803 are not provided, an increase in the circuit size can be suppressed compared to the configuration example 2.

[0079] As described above, among circuits that implement decoding processing, the size of the arithmetic circuit for processing to search for the roots of the error locator polynomial, such as a Chien search, tends to be large. Therefore, in this embodiment, a configuration is realized that can further reduce the circuit size while suppressing power consumption.

[0080] 12 is a block diagram showing an example of the configuration of the error-position calculation unit 103 according to the embodiment. As shown in FIG. 12, the error-position calculation unit 103 includes two circuits 320a-1 and 320a-2, multipliers 401 and 402, selectors 411, 412, and 413, and adders 421 and 422.

[0081] 12 also shows an example of calculation by the error position calculation unit 103 when the number of errors is small. Fig. 13 is a diagram showing an example of calculation by the error position calculation unit 103 when the number of errors is large. The operation of the error position calculation unit 103 will be described below with reference to Figs. 12 and 13.

[0082] The circuits 320a-1 and 320a-2 each have a matrix V similar to the circuit 320a in FIG. Low Normal That is, the circuit 320a-1 and the circuit 320a-2 receive different input values, but perform the same operation.

[0083] The circuit 320a-1 (first circuit) corresponds to a substitution circuit (first substitution circuit) that calculates p / 2 evaluation values ​​EA (first evaluation values) by substituting p / 2 inspection values ​​into a t / 2-degree input polynomial PA (first input polynomial). The p / 2 evaluation values ​​EA are used to calculate p / 2 pieces of error location information LA that indicate whether or not an error location exists. The input polynomial PA corresponds to a low-degree polynomial that is a polynomial obtained from the error location polynomial.

[0084] The circuit 320a-2 (second circuit) corresponds to a substitution circuit (second substitution circuit) that calculates p / 2 evaluation values ​​EB (second evaluation values) by substituting p / 2 inspection values ​​into an input polynomial of degree t / 2. The p / 2 evaluation values ​​EB are used to calculate p / 2 pieces of error location information LB that indicate whether or not there is an error location.

[0085] The t / 2-degree input polynomial (second polynomial) used by circuit 320a-2 is input polynomial PB (second input polynomial) expressed by coefficients obtained by converting the coefficients of a lower-degree polynomial when the number of errors is small, and is input polynomial PC (third input polynomial) that is the same as the higher-degree polynomial when the number of errors is large.

[0086] For example, if the number of errors is t / 2 or less, the error position calculation unit 103 obtains the coefficients of the input polynomial PB by performing coefficient conversion of a low-order polynomial. p p test values ​​up to x 1:p p / 2 test values ​​x from 1st to p / 2nd of 1:p / 2 On the other hand, in the circuit 320a-2, p / 2 pieces of the inspection values ​​x (first inspection value) are substituted into the input polynomial PA (low-order polynomial) to calculate the evaluation value EA. 1:p / 2 The evaluation value EB is calculated by substituting the input polynomial PB into the input polynomial PA. The evaluation value EB is calculated by substituting the input polynomial PA with the p / 2 inspection values ​​x from the (p / 2+1)th to the pth. p / 2+1:p (second test value) is substituted. 1:p / 2 ) corresponds to the error location information LA obtained by adding σ0 to each of the p / 2 evaluation values ​​EA calculated by the circuit 320a-1. p / 2+1:p ) corresponds to the error location information LB obtained by adding σ0 to each of the p / 2 evaluation values ​​EB calculated by the circuit 320a-2. 1:p / 2 ) and output σ(x p / 2+1:p ) and the output σ(x 1:p ) corresponds to p pieces of error position information output by the error position calculation unit 103.

[0087] If the number of errors is greater than t / 2, the error position calculation unit 103 adds p / 2 check values ​​x 1:p / 2 The error position calculation unit 103 converts the p / 2 evaluation values ​​EB calculated by the circuit 320a-2 into p / 2 evaluation values ​​EC (third evaluation values) by using a predetermined diagonal matrix D2 (details will be described later). 1:p / 2 The circuit 320a-1 calculates p / 2 evaluation values ​​ED (fourth evaluation values) by adding the p / 2 evaluation values ​​EA calculated by the circuit 320a-1 and the p / 2 evaluation values ​​EC by substituting σ0 into the p / 2 evaluation values ​​EA. The error position calculation unit 103 outputs p / 2 pieces of error position information LA calculated by adding σ0 to each of the p / 2 evaluation values ​​ED.

[0088] The multiplier 401 (first multiplier) multiplies a vector σ L and a predetermined diagonal matrix D1(t / 2, p / 2), and outputs the multiplication result to the selector 411. The multiplication by the multiplier 401 corresponds to a process of converting the coefficient of the low-degree polynomial (input polynomial PA) to obtain the coefficient (fourth coefficient) of the input polynomial PB. For example, the multiplication by the multiplier 401 is performed by multiplying the coefficient of the kth degree (k is an integer satisfying 1≦k≦t / 2) of the low-degree polynomial by α kp / 2 This is equivalent to finding the coefficients of the input polynomial PB by multiplying by .

[0089] When the number of errors is small, the selector 411 (first selector) selects the multiplication result by the multiplier 401 and outputs it to the circuit 320a-2 (FIG. 12). When the number of errors is large, the selector 411 selects the vector σ H and outputs it to the circuit 320a-2 (FIG. 13). The selector 411 corresponds to a configuration that outputs the coefficient (fifth coefficient) of the input polynomial of degree t / 2 used by the circuit 320a-2.

[0090] As shown in FIG. 12, when the number of errors is small, two circuits 320a-1 and 320a-2 and an operation using the diagonal matrix D1(t / 2, p / 2) (multiplier 401) are activated.

[0091] Vector σ L Multiplying by a predetermined diagonal matrix D1(t / 2, p / 2) yields the matrix V, as shown in the upper equation of FIG. Low Normal The matrix obtained by multiplying by the diagonal matrix D1(t / 2, p / 2) is called the vector σ L The details of the diagonal matrix D1(t / 2, p / 2) and the reason for using the diagonal matrix D1(t / 2, p / 2) will be described later.

[0092] When the number of errors is small, selector 412 (second selector) selects a zero vector (first value) and outputs it to multiplier 402 (FIG. 12). A zero vector is a vector in which all p / 2 elements are 0. When the number of errors is large, selector 412 selects the output of circuit 320a-2 and outputs it to multiplier 402 (FIG. 13).

[0093] Multiplier 402 (second multiplier) multiplies the output (second value) of selector 412 by a predetermined diagonal matrix D2(t / 2, p / 2) and outputs the multiplication result to adder 421. When the number of errors is small, selector 412 outputs a zero vector, and the multiplication result of multiplier 402 is 0. Therefore, the output of multiplier 402 does not affect the result from adder 421. When the number of errors is large, selector 412 selects and outputs the output of circuit 320a-2, and multiplier 402 outputs the multiplication result of the output of circuit 320a-2 and diagonal matrix D2(t / 2, p / 2).

[0094] The multiplication by the multiplier 402 corresponds to a process of converting the evaluation value EB calculated by the circuit 320a-2 into an evaluation value EC using the diagonal matrix D2. For example, the multiplication by the multiplier 402 corresponds to multiplying the p / 2 evaluation values ​​EB calculated by the circuit 320a-2 by p / 2 predetermined multiplication values ​​(diagonal elements of the diagonal matrix D2) to obtain the evaluation value EC.

[0095] As shown in FIG. 13, when the number of errors is large, two circuits 320a-1 and 320a-2 and an operation using the diagonal matrix D2(t / 2, p / 2) (multiplier 402) are activated.

[0096] Outputting the multiplication result of the output of the circuit 320a-2 and the diagonal matrix D2(t / 2, p / 2) is equivalent to multiplying the diagonal matrix D2(t / 2, p / 2) and the matrix V Low Normal The matrix obtained by multiplying and is called the vector σ HThe details of the diagonal matrix D2(t / 2, p / 2) and the reason for using the diagonal matrix D2(t / 2, p / 2) will be described later.

[0097] The adder 421 (first adder) adds the output of the circuit 320a-1, the output of the multiplier 402, and the vector σ0 corresponding to the zero-order coefficient, and outputs the addition result as σ(x 1:p / 2 ) (first error location information).

[0098] The adder 422 (second adder) adds the output of the circuit 320a-2 and the vector σ0 corresponding to the zero-order coefficient, and outputs the sum σ(x p / 2+1:p ) (second error location information).

[0099] When the number of errors is small, the selector 413 (third selector) selects the output σ(x p / 2+1:p ) is selected and output, and if the number of errors is large, invalid data that is not error location information is selected and output. Invalid data is, for example, a vector containing p / 2 elements, where all p / 2 elements are zero.

[0100] When the number of errors is small, the output of the error position calculation unit 103 is the output σ(x 1:p / 2 ) and the output σ(x p / 2+1:p ) and the output σ(x 1:p ) The output σ(x 1:p ) corresponds to p pieces of error position information. When the number of errors is large, the output of the error position calculation unit 103 is the output σ(x 1:p / 2 ) That is, the output of the adder 422 is not included in the output of the error position calculation unit 103. 1:p / 2 ) corresponds to p / 2 pieces of error location information.

[0101] Next, the diagonal matrix D1(t / 2, p / 2) will be described in detail.

[0102] The error locator polynomial in the form of an inner product of vectors, such as equation (8), is x i as α i When using the above formula, it can be expressed as the following formula (11).

number

[0103] x i As, α i Alpha q α multiplied by i+q When using the above formula, the error locator polynomial can be expressed as in the following formula (12). Formula (12) can be interpreted as equivalent to the error locator polynomial obtained by shifting the error locator polynomial in formula (11) by the diagonal matrix D1(t, q) defined in the following formula (13). Below, such a shift will be referred to as a polynomial shift, and q may be referred to as the shift amount. As shown in formulas (12) and (13), the diagonal matrix D1(t, q) is a matrix that does not depend on i.

number

number

[0104] The inner product of the vectors in the first row of equation (12) can be rewritten into an inner product format using the same vectors as those used to calculate the inner product of equation (11) by using diagonal matrix D1.

[0105] Similar rewriting (polynomial shift) can also be applied to calculations using the Vandermonde matrix. In this embodiment, rewriting using a diagonal matrix is ​​applied to calculations of the matrix used in the two-division parallel Chien search.

[0106] An example of applying the rewriting using the diagonal matrix D1 to a two-division parallel Chien search will be described below. In the following, an example will be described in which t=4 and the parallelism p=4.

[0107] The following equation (14) shows an example of the Vandermonde matrix in this case. For example, if the element in the first row and the k-th column of the Vandermonde matrix in equation (14) is α kp / 2 =α 2k Similarly, multiplying the element in the kth column of the second row by α kp / 2 =α 2k Multiplying by , the elements of the fourth row are obtained. Therefore, to rewrite the first and second rows as the third and fourth rows, we can apply the diagonal matrix D1 similar to that in equation (12). In the example of equation (14), p / 2 (= 4 / 2) corresponds to the shift amount q, so the diagonal matrix is ​​expressed as D1(4, 2).

number

[0108] In equation (14), the matrix containing the first and second rows of the Vandermonde matrix is ​​V Normal The matrix containing the third and fourth rows of the Vandermonde matrix is ​​the matrix V Normal and the diagonal matrix D1(t, p / 2) = D1(4, 2). This rewriting is equivalent to the matrix used in the latter calculation (Extra) of the two parallelized calculations being rewritten as a multiplication of the matrix used in the first calculation (Normal) and the diagonal matrix.

[0109] For example, when the inspection value shown in equation (15) is used, the matrix V Normal and a matrix V with p / 2 rows and t columns Extra The p-by-t Vandermonde matrix containing Normal and the diagonal matrix D1(t, p / 2).

number

number

[0110] For the sake of convenience, the Vandermonde matrix is ​​not divided into low-order and high-order parts in the column direction in equations (14) and (16). For the error location calculation unit 103 of the embodiment shown in FIG. 12, the matrix V Low Normal and matrix V Low Extra For the matrix V, we can apply the rewriting formula (14). Low Extra is the matrix V Low Normal and the diagonal matrix D1(t / 2, p / 2). Low Extra matrix V Low Normal An example of a Vandermonde matrix is ​​shown, including a matrix rewritten as a multiplication of t / 2, p / 2 with a diagonal matrix D1(t / 2, p / 2).

[0111] Next, the diagonal matrix D2(t / 2, p / 2) will be described in detail.

[0112] The calculation of the inner product using high-order coefficients included in the substitution calculation of the error locator polynomial can be rewritten into a calculation including elements used in the calculation of the inner product using low-order coefficients by using factorization. The following equation (17) shows an example of such a rewriting of the error locator polynomial.

number

[0113] The first line of equation (17) is the low-order coefficient σ 1:2 and element (α i ,α 2i ) and the inner product with the higher order coefficient σ 3:4 and element (α 3i ,α 4i ) and the inner product using the elements (α i ,α 2i ) can be rewritten to include

[0114] A similar rewriting can be applied to the Vandermonde matrix. The following equation (18) shows an example of rewriting the Vandermonde matrix.

number

[0115] For example, the matrix in the first row of equation (18) corresponds to a matrix in which the elements of the higher-order columns (the third and fourth columns) of the Vandermonde matrix in the first row of equation (14) are rewritten as elements that include the elements of the lower-order columns (the first and second columns) as factors. The two higher-order columns are further rewritten in the form of a multiplication of a diagonal matrix as shown in the center of the second row by a matrix that includes the lower-order columns. This diagonal matrix corresponds to diagonal matrix D2.

[0116] The Vandermonde matrix V as shown in equation (9) 1:p 1:t In this case, we will rewrite the Vandermonde matrix V 1:p 1:t matrix V including higher-order columns 1:p t / 2+1:t is a matrix V with low-order columns 1:p 1:t / 2 and the diagonal matrix D2(t / 2,p). The following equation (19) is an example of such a rewriting.

number

[0117] The diagonal matrix D2(t, p) is defined by the following equation (20): As shown in equation (20), the diagonal matrix D2(t, p) is a matrix that does not depend on i.

number

[0118] Equation (20) corresponds to the definition of the diagonal matrix D2(t,p) in the general case where the Vandermonde matrix is ​​not divided into two parts, low and high. In the two-part parallel Chien search, the t-th order error locator polynomial is divided into two (t / 2)-th order error locator polynomials. Therefore, the divided matrix V 1:p t / 2+1:t is multiplied by the diagonal matrix D2(t / 2,p).

[0119] The Vandermonde matrix is ​​then converted into a matrix V with low-order columns. Low and a matrix V containing higher-order columns High When expressed as Low V High ) is expressed by the diagonal matrix D2(t / 2, p) and the matrix V Low can be rewritten in a form using

number

[0120] For the sake of convenience, the calculation of the parallelism p is not divided into two parts in equation (21). For the error position calculation unit 103 of the embodiment shown in FIG. 12 (FIG. 13), the matrix V High Normal For the matrix V, we can set the parallelism to p / 2 and rewrite it as in equation (21). High Normal is the diagonal matrix D2(t / 2, p / 2) and the matrix V Low Normal The upper part of Figure 13 shows the matrix V High Normal Diagonal matrix D2(t / 2, p / 2) and matrix V Low Normal An example of a Vandermonde matrix is ​​shown, including a matrix rewritten as a multiplication with

[0121] As mentioned above, the matrix V is used when the number of errors is small. Low Extra is the matrix V LowNormal and the diagonal matrix D1(t / 2, p / 2). Therefore, the matrix V Low Extra The circuit 320c corresponding to the matrix V Low Normal and a multiplier 401 that multiplies by a diagonal matrix D1(t / 2, p / 2).

[0122] On the other hand, the matrix V used when the number of errors is large High Normal is the diagonal matrix D2(t / 2, p / 2) and the matrix V Low Normal Therefore, the matrix V High Normal The circuit 320b corresponds to the multiplier 402 that multiplies the diagonal matrix D2(t / 2, p / 2) and the matrix V Low Normal and a circuit 320a-2 corresponding to:

[0123] Overall, the two circuits 320b and 320c are replaced by one circuit 320a-2 and two multipliers 401 and 402. In a comparison of the matrices used in the calculation, the two matrices V Low Extra and matrix V High Normal and one matrix V Low Normal and two diagonal matrices D1 and D2. A diagonal matrix is ​​a matrix that contains only diagonal elements, and therefore is essentially equivalent to a vector containing elements for one row or one column. Therefore, a circuit that performs operations using a diagonal matrix can be smaller in circuit scale than a circuit that performs operations using a non-diagonal matrix.

[0124] That is, the error-position calculation unit 103 of this embodiment can replace two circuits that perform calculations of a non-diagonal matrix with one circuit that performs calculations of a non-diagonal matrix and two circuits that perform calculations of a diagonal matrix, thereby reducing the scale of the calculation circuits used for calculations such as decoding.

[0125] Fig. 14 is a block diagram showing a more detailed example of the configuration of the error position calculation unit 103. The same components as those in other figures such as Fig. 3 and Fig. 12 are given the same reference numerals and descriptions thereof will be omitted.

[0126] Selector 1401 selects the output of multiplier 401, that is, the result of multiplication by diagonal matrix D1(t / 2, p / 2), when the number of errors is large, and selects the output of multiplier 312 when the number of errors is small.

[0127] The calculator 1411 corresponds to a calculator for multiplying the diagonal matrix D1(t / 2, p / 2). The calculator 1412 corresponds to a calculator for multiplying the diagonal matrix D2(t / 2, p / 2).

[0128] Note that UNIT_iP is σ(x i ) and σ(x i+p / 2 ) and output HITi, HIT(i+p). If the number of errors is large, σ(x i ) and outputs HITi. “UNIT_jP, j=0, 1, . . . i−1, i+1, . . . , p / 2−1” in FIG. 14 indicates that the error-position calculation unit 103 includes these circuits.

[0129] Up to now, the explanation has been given mainly on an example where the t coefficients of the t-th degree error locator polynomial are divided into coefficients from 1st to (t / 2)th degrees and coefficients from (t / 2+1)th degrees to t-th degrees. That is, the explanation has been given on an example where t is an even number equal to or greater than 2. t does not have to be an even number, and may be an odd number equal to or greater than 3.

[0130] When t is an odd number, the t coefficients can be divided into 1st to sth order coefficients and (s+1)th to tth order coefficients. s is the smallest integer greater than t / 2 or the largest integer smaller than t / 2. FIG. 15 is a block diagram showing an example of the configuration of the error position calculation unit 103 in the former case. FIG. 16 is a block diagram showing an example of the configuration of the error position calculation unit 103 in the latter case. When t is an odd number, the 1st to sth order coefficients are considered low-order coefficients and the (s+1)th to tth order coefficients are considered high-order coefficients, so that the same procedure as above can be applied.

[0131] Next, a description will be given of the flow of the decoding process performed by the memory system 1. Fig. 17 is a flowchart showing an example of the decoding process in this embodiment.

[0132] The control unit 11 reads out the error correction code from the nonvolatile memory 20 and obtains the received word (step S101). The control unit 11 also instructs the decoding unit 18 to start decoding.

[0133] The syndrome calculation unit 101 of the decoding unit 18 calculates syndromes from the received word (step S102). The decoding unit 18 determines whether or not the values ​​of all the calculated syndromes are 0 (step S103).

[0134] If all the syndromes are 0 (step S103: Yes), it can be determined that there is no error in the received word, and the decoding unit 18 ends the decoding process. If all the syndromes are not 0 (step S103: No), the error locator polynomial calculation unit 102 calculates an error locator polynomial using the syndromes (step S104).

[0135] The error position calculation unit 103 searches for an error position using the calculated error position polynomial (step S105). The correction unit 104 corrects the error by inverting (bit flipping) the bit at the error position found by the search (step S106), and the decoding process ends.

[0136] As described above, this embodiment can reduce the scale of the circuit used for the process of searching for the root of the error locator polynomial by Chien search, etc. In other words, it can reduce the scale of the arithmetic circuit used for the calculation of the decoding process, etc.

[0137] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0138] 1. Memory System 10 Memory Controller 11 Control section 12 Data Buffers 13 Memory I / F 14 Encoding / Decoding Unit 15 Host I / F 16 Internal Bus 17 Encoding section 18 Decoding section 20 Non-volatile memory 30 hosts 101 Syndrome Calculation Unit 102 Error location polynomial calculation unit 103 Error location calculation unit 104 Corrections Department

Claims

1. a first substitution circuit that calculates p / 2 first evaluation values ​​by substituting p / 2 check values ​​(p is an even integer satisfying 2≦p<n) into a first input polynomial expressed by coefficients of degree 1 to degree s (s is the smallest integer equal to or greater than t / 2, or the largest integer equal to or less than t / 2) of an error locator polynomial for an error-correcting code having a code length of n bits (n is an integer equal to or greater than 2) and correcting errors of t bits or less (t is an integer equal to or greater than 2); a second substitution circuit that calculates p / 2 second evaluation values; If the number of errors is t / 2 or less, output p pieces of error location information including: p / 2 pieces of error location information calculated based on the first evaluation value calculated by the first substitution circuit by substituting p / 2 first inspection values ​​from 1 to p / 2 out of p inspection values; and p / 2 pieces of error location information calculated based on the second evaluation value calculated by the second substitution circuit by substituting the first inspection values ​​into a second input polynomial expressed by coefficients obtained by converting coefficients of the first input polynomial; if the number of errors is greater than t / 2, convert the second evaluation value calculated by the second substitution circuit into a third evaluation value by substituting the first check value into a third input polynomial expressed by coefficients of degrees (s+1) to t of the error locator polynomial, and output p / 2 pieces of error location information calculated based on the first evaluation value calculated by the first substitution circuit by substituting the first check value into the third input polynomial and the third evaluation value. Arithmetic circuit.

2. If the number of errors is t / 2 or less, the coefficients of the second input polynomial are obtained by multiplying the coefficients of degree k (k is an integer satisfying 1≦k≦t / 2) of the first input polynomial by the (kp / 2)th power of the primitive element α. The arithmetic circuit according to claim 1 .

3. If the number of errors is greater than t / 2, calculate the third evaluation value by multiplying the p / 2 second evaluation values ​​by p / 2 predetermined multiplication values, respectively. The arithmetic circuit according to claim 1 .

4. the first assignment circuit assigns p / 2 inspection values ​​to the first input polynomial in parallel to calculate p / 2 first evaluation values; the second assignment circuit assigns p / 2 inspection values ​​to the second input polynomial or the third input polynomial in parallel to calculate p / 2 second evaluation values; The arithmetic circuit according to claim 1 .

5. calculating p / 2 fourth evaluation values ​​by adding the first evaluation value calculated by the first substitution circuit and the third evaluation value, and calculating the p / 2 pieces of error location information using the fourth evaluation values; The arithmetic circuit according to claim 1 .

6. The error correction code is a BCH (Bose-Chaudhuri-Hocquenghem) code or an RS (Reed-Solomon) code. The arithmetic circuit according to claim 1 .

7. a non-volatile memory; a memory controller that writes an error correction code having a code length of n bits (n is an integer of 2 or more) and for correcting errors of t bits or less (t is an integer of 2 or more) into the nonvolatile memory; The memory controller The error correction code is read from the nonvolatile memory. Calculating a syndrome using the read error correction code as a received word; determining coefficients of an error locator polynomial and a number of errors based on the syndrome; The memory controller a first register for storing first coefficients, which are coefficients of the first to sth orders (s is the smallest integer equal to or greater than t / 2, or the largest integer equal to or less than t / 2) of the error locator polynomial; a second register for storing second coefficients, which are coefficients of the (s+1)th order to the tth order of the error locator polynomial; a third register for storing a third coefficient, which is a zero-order coefficient of the error locator polynomial; a first circuit that outputs p / 2 first evaluation values ​​by substituting p / 2 first inspection values ​​(p is an even integer satisfying 2≦p<n) from 1st to p / 2nd into a first polynomial having the first coefficient as a coefficient; a first multiplier that converts the first coefficient and outputs a fourth coefficient; a first selector that outputs one of the fourth coefficient output from the first multiplier and the second coefficient; a second circuit that outputs p / 2 second evaluation values ​​by substituting the p / 2 first check values ​​into a second polynomial having a fifth coefficient output from the first selector as a coefficient; a second selector that outputs either the p / 2 first values ​​or the p / 2 second evaluation values; a second multiplier that converts the p / 2 second values ​​output from the second selector and outputs p / 2 third evaluation values; a first adder that outputs p / 2 pieces of first error location information based on the p / 2 first evaluation values, the p / 2 third evaluation values, and the third coefficient; a second adder that outputs p / 2 pieces of second error location information based on the p / 2 second evaluation values ​​and the third coefficient; Including, when the number of errors is t / 2 or less, the first selector outputs the fourth coefficient output from the first multiplier, the second selector outputs the p / 2 first values, and the memory controller determines an error location based on p pieces of error location information including the p / 2 pieces of first error location information and the p / 2 pieces of second error location information; If the number of errors is greater than t / 2, the first selector outputs the second coefficient, the second selector outputs the p / 2 second evaluation values, and the memory controller determines an error location based on the p / 2 pieces of first error location information. Memory system.

8. a third selector that outputs the p / 2 pieces of second error location information output by the second adder when the number of errors is t / 2 or less, and outputs invalid data when the number of errors is greater than t / 2; 8. The memory system of claim 7.

9. The first value is 0 8. The memory system of claim 7.

10. The first coefficient, the second coefficient, and the fourth coefficient are all 2 ｍ A Galois field GF(2) having elements (m is an integer equal to or greater than 1) ｍ ) is the origin of The transformation of the first coefficient by the first multiplier is performed by multiplying a k-th order coefficient (k is an integer satisfying 1≦k≦t / 2) of the first coefficient by a Galois field GF(2 ｍ ) by the (kp / 2)th power of the primitive element α of 8. The memory system of claim 7.

11. The second multiplier converts the p / 2 second values ​​by multiplying the p / 2 second evaluation values ​​by predetermined p / 2 second values, respectively.

8. The memory system of claim 7.

12. the first circuit substitutes the p / 2 first inspection values ​​in parallel into the first polynomial represented by the first coefficients, and outputs the p / 2 first evaluation values; The second circuit substitutes the p / 2 first inspection values ​​in parallel into the second polynomial represented by the fourth coefficient, and outputs the p / 2 second evaluation values.

8. The memory system of claim 7.

13. The first adder adds the p / 2 first evaluation values ​​and the p / 2 third evaluation values ​​to determine p / 2 fourth evaluation values, and adds the p / 2 fourth evaluation values ​​and the third coefficient to determine the p / 2 first error location information.

8. The memory system of claim 7.

14. The error correction code is a BCH (Bose-Chaudhuri-Hocquenghem) code or an RS (Reed-Solomon) code.

8. The memory system of claim 7.

15. A control method for controlling a nonvolatile memory, comprising: storing an error correction code having a code length of n bits (n is an integer of 2 or more) for correcting errors of t bits or less (t is an integer of 2 or more) in the nonvolatile memory; reading the error correction code from the nonvolatile memory; Calculating a syndrome using the read error correction code as a received word; determining coefficients of an error locator polynomial and a number of errors based on the syndrome; storing first coefficients, which are coefficients of the first to sth orders (s is the smallest integer equal to or greater than t / 2 or the largest integer equal to or less than t / 2) of the error locator polynomial, in a first register; storing second coefficients, which are coefficients of the (s+1)th order to the tth order of the error locator polynomial, in a second register; storing a third coefficient, which is a zero-order coefficient of the error locator polynomial, in a third register; determining p / 2 first evaluation values ​​by substituting p / 2 first inspection values ​​(p is an even integer satisfying 2≦p<n) from 1st to p / 2nd into a first polynomial having the first coefficient as a coefficient; transforming the first coefficient; selecting one of a fourth coefficient obtained by converting the first coefficient and the second coefficient as a fifth coefficient based on whether the number of errors is t / 2 or less; determining p / 2 second evaluation values ​​by substituting the p / 2 first inspection values ​​into a second polynomial having the selected fifth coefficient as a coefficient; selecting either the p / 2 first values ​​or the p / 2 second evaluation values ​​based on whether the number of errors is t / 2 or less; converting p / 2 second values ​​that are any of the selected p / 2 first values ​​and the p / 2 second evaluation values; determining p / 2 pieces of first error location information based on the p / 2 first evaluation values, the p / 2 third evaluation values ​​obtained by converting the p / 2 second values, and the third coefficient; determining p / 2 pieces of second error location information based on the p / 2 second evaluation values ​​and the third coefficient; determining an error location based on either p pieces of error location information including the p / 2 pieces of first error location information and the p / 2 pieces of second error location information, or the p / 2 pieces of first error location information, based on whether the number of errors is t / 2 or less; The method includes:

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