Capacitive load drive circuit and liquid discharge apparatus

Abstract

To provide a capacitive load drive circuit capable of reducing a possibility of the occurrence of distortion in a drive signal waveform.SOLUTION: A capacitive load drive circuit comprises: a first digital amplification circuit that outputs a first amplified signal to a first output node; a bootstrap circuit that includes a capacitor element connected between the first output node and a second output node, and a diode element having an anode terminal connected to a third propagation node and a cathode terminal connected to the second output node, and outputs a boot voltage signal to the second output node; a second digital amplification circuit that is connected between the first output node and the second output node and outputs a second amplified signal to a third output node; a smoothing circuit that smooths the second amplified signal and outputs it as a drive signal; and a voltage limiting circuit that is connected between the third propagation node and the second output node, and switches a conduction state between the third propagation node and the second output node in accordance with a potential difference between the third propagation node and the second output node.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present invention relates to a capacitive load drive circuit and a liquid ejection device. [Background technology]

[0002] Liquid ejection devices that eject liquid to form images or documents on a medium are known to use piezoelectric elements. In such liquid ejection devices, a piezoelectric element is provided corresponding to each of a plurality of nozzles that eject liquid, and each is driven according to a drive signal. Driving the piezoelectric element causes liquid to be ejected from the nozzle provided corresponding to that piezoelectric element. A sufficient current must be supplied to operate such a piezoelectric element. Therefore, a drive circuit that outputs a drive signal to drive the piezoelectric element includes an amplifier circuit that amplifies a source signal that is the basis of the drive signal.

[0003] Patent Document 1 discloses a drive circuit that can efficiently amplify signals by including a pulse modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal, an amplifier circuit that amplifies the modulated signal and outputs an amplified modulated signal from a first output point, a level shift circuit that shifts the potential of the amplified modulated signal and outputs a level-shifted amplified modulated signal from a second output point, and a demodulation circuit that demodulates the level-shifted amplified modulated signal and outputs a drive signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-057167 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the liquid ejection device described in Patent Document 1, there is a risk that distortion occurs in the waveform of the drive signal to be output depending on the amount of current supplied to the load, and there is room for improvement. [Means for solving the problem]

[0006] One aspect of the capacitive load drive circuit according to the present invention is A capacitive load drive circuit that outputs a drive signal for driving a capacitive load, a first digital amplifier circuit electrically connected to a first propagation node through which a first voltage signal of a first potential propagates and a second propagation node through which a second voltage signal of a second potential propagates, and which outputs a first amplified signal to a first output node; a bootstrap circuit electrically connected to a third propagation node through which a third voltage signal of a third potential propagates and the first output node, and configured to output a boot voltage signal to a second output node; a second digital amplifier circuit connected to the first output node and the second output node and outputting a second amplified signal to a third output node; a smoothing circuit that smoothes the second amplified signal and outputs the smoothed signal as the drive signal; a voltage limiting circuit electrically connected to the third propagation node and the second output node, and configured to switch a conduction state between the third propagation node and the second output node; Equipped with the bootstrap circuit includes a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node, and a diode element having an anode terminal electrically connected to the third propagation node and a cathode terminal electrically connected to the second output node; The voltage limiting circuit switches the conduction state between the third propagation node and the second output node in accordance with the potential difference between the third propagation node and the second output node.

[0007] One aspect of the liquid ejection device according to the present invention is a discharge unit that discharges liquid by driving a capacitive load; a capacitive load drive circuit that outputs a drive signal for driving the capacitive load; Equipped with The capacitive load drive circuit comprises: a first digital amplifier circuit electrically connected to a first propagation node through which a first voltage signal of a first potential propagates and a second propagation node through which a second voltage signal of a second potential propagates, and which outputs a first amplified signal to a first output node; a bootstrap circuit electrically connected to a third propagation node through which a third voltage signal of a third potential propagates and the first output node, and configured to output a boot voltage signal to a second output node; a second digital amplifier circuit connected to the first output node and the second output node and outputting a second amplified signal to a third output node; a smoothing circuit that smoothes the second amplified signal and outputs the smoothed signal as the drive signal; a voltage limiting circuit electrically connected to the third propagation node and the second output node, and configured to switch a conduction state between the third propagation node and the second output node; and the bootstrap circuit includes a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node, and a diode element having an anode terminal electrically connected to the third propagation node and a cathode terminal electrically connected to the second output node; The voltage limiting circuit switches the conduction state between the third propagation node and the second output node in accordance with the potential difference between the third propagation node and the second output node. [Brief explanation of the drawings]

[0008] [Figure 1] 1A and 1B are diagrams illustrating an example of the structure of a liquid ejection device. [Figure 2] FIG. 2 is a diagram illustrating a functional configuration of the liquid ejection device. [Figure 3] FIG. 2 is a diagram showing an example of the arrangement of a plurality of ejection sections in a head unit. [Figure 4] FIG. 2 is a diagram illustrating an example of a configuration of a discharge unit. [Figure 5] 10 is a diagram showing an example of a signal waveform of a drive signal COM. FIG. [Figure 6] FIG. 2 is a diagram illustrating an example of a functional configuration of a drive circuit. [Figure 7] FIG. 4 is a diagram for explaining the operation of a drive circuit. [Figure 8] FIG. 2 is a diagram showing an outline of a current flowing in a drive circuit. [Figure 9] FIG. 2 is a diagram showing an outline of a current flowing in a drive circuit. [Figure 10] FIG. 2 is a diagram showing an outline of a current flowing in a drive circuit. [Figure 11] FIG. 2 is a diagram showing an outline of a current flowing in a drive circuit. [Figure 12] FIG. 2 is a diagram illustrating an example of the configuration of a boost voltage limiting circuit. [Figure 13] FIG. 10 is a diagram illustrating an example of the configuration of a modified boost voltage limiting circuit. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings used are for the convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] In the following description, a serial inkjet printer for consumer use will be used as an example of a liquid ejection device according to the present invention. However, the liquid ejection device is not limited to a serial inkjet printer and may be a line inkjet printer. Furthermore, the liquid ejection device is not limited to an inkjet printer and may be a color material ejection device used in the manufacture of color filters for liquid crystal displays and the like, an electrode material ejection device used in the formation of electrodes for organic electroluminescence displays and surface-emitting displays, a bioorganic material ejection device used in the manufacture of biochips, or the like.

[0011] 1. Overview of the liquid ejection device Fig. 1 is a diagram showing an example of the structure of a liquid ejection device 1. As shown in Fig. 1, the liquid ejection device 1 includes a moving body 2 and a moving unit 3 that moves the moving body 2 back and forth along the main scanning direction.

[0012] The moving unit 3 has a carriage motor 31 which serves as the driving source for the reciprocating movement of the moving body 2 along the main scanning direction, a carriage guide shaft 32 with both ends fixed, and a timing belt 33 which extends approximately parallel to the carriage guide shaft 32 and is driven by the carriage motor 31.

[0013] The movable body 2 has a carriage 24. The carriage 24 is supported by a carriage guide shaft 32 so as to be freely movable back and forth, and is fixed to a part of a timing belt 33. The carriage motor 31 drives the timing belt 33 forward and backward, causing the movable body 2 having the carriage 24 to move back and forth while being guided by the carriage guide shaft 32. A head unit 20 is located on a portion of the movable body 2 that faces the medium P. In other words, the head unit 20 is mounted on the carriage 24. A number of nozzles that eject ink as a liquid are located on the surface of the head unit 20 that faces the medium P. Various control signals that control the operation of the head unit 20 are supplied to the head unit 20 via a cable 190. A flexible flat cable that can slide in accordance with the reciprocating movement of the movable body 2 can be used as this cable 190.

[0014] The liquid ejection device 1 also includes a transport unit 4 that transports the medium P along the transport direction on a platen 40. The transport unit 4 has a transport motor 41 that is a drive source for transporting the medium P, and a transport roller 42 that rotates in response to the driving force of the transport motor 41 to transport the medium P along the transport direction.

[0015] In the liquid ejection device 1 configured as described above, the head unit 20 ejects ink onto the medium P in synchronization with the timing at which the medium P is transported by the transport unit 4. As a result, the ink ejected by the head unit 20 lands at the desired position on the medium P, and the desired image or characters are formed on the surface of the medium P.

[0016] Next, we will explain the functional configuration of the liquid ejection device 1. Fig. 2 is a diagram showing the functional configuration of the liquid ejection device 1. As shown in Fig. 2, the liquid ejection device 1 includes a control unit 10, a head unit 20, a moving unit 3, a transport unit 4, and a cable 190. The cable 190 electrically connects the control unit 10 and the head unit 20.

[0017] The control unit 10 includes a power supply circuit 11, a control circuit 100, and a drive circuit 50.

[0018] The power supply circuit 11 generates voltage signals VHV, VMV1, VMV2, and VDG of predetermined voltage values ​​from a commercial AC power supply supplied from outside the liquid ejection device 1 and outputs them to each component of the liquid ejection device 1. Here, the voltage signal VHV is, for example, a DC voltage of 42 V, the voltage signal VMV1 is, for example, a DC voltage of 20 V, the voltage signal VMV2 is, for example, a DC voltage of 18 V, and the voltage signal VGD is, for example, a DC voltage of 7.5 V. Note that the power supply circuit 11 may output DC voltages of different voltage values ​​in addition to the voltage signals VHV, VMV1, VMV2, and VGD. Hereinafter, the voltage value of the voltage signal VHV may be referred to as voltage vhv, the voltage value of the voltage signal VMV1 as voltage vmv1, the voltage value of the voltage signal VMV2 as voltage vmv2, and the voltage value of the voltage signal VGD as voltage vgd.

[0019] Image data is supplied to the control circuit 100 from an external device (not shown), such as a host computer, that is provided outside the liquid ejection device 1. The control circuit 100 performs various image processing and the like on the supplied image data to generate various control signals for controlling each part of the liquid ejection device 1 and outputs the signals to each part.

[0020] Specifically, the control circuit 100 generates a control signal Ctrl1 for controlling the reciprocating movement of the movable body 2 based on the image data, and outputs it to a carriage motor 31 included in the movement unit 3. The control circuit 100 also generates a control signal Ctrl2 for controlling the transport of the medium P based on the image data, and outputs it to a transport motor 41 included in the transport unit 4. In this way, the control circuit 100 controls the reciprocating movement of the movable body 2 along the main scanning direction and the transport of the medium P along the transport direction. In other words, the head unit 20 can eject ink onto the medium P at a predetermined timing synchronized with the transport of the medium P. This makes it possible to cause ink to land at desired positions on the medium P, and to form desired images and characters on the medium P.

[0021] In addition, the control circuit 100 may convert the control signal Ctrl1 for controlling the reciprocating movement of the moving body 2 into a signal by a carriage motor driver not shown, and then supply it to the moving unit 3.Similarly, the control signal Ctrl2 for controlling the transport of the medium P may be converted into a signal by a transport motor driver not shown, and then supply it to the transport unit 4.

[0022] The control circuit 100 also outputs a basic drive signal dA to the drive circuit 50. This basic drive signal dA is a digital signal that includes information that defines the signal waveform of the drive signal COM that is supplied to the head unit 20. The drive circuit 50 converts the basic drive signal dA into an analog signal, and then amplifies the converted analog signal to generate the drive signal COM. The drive circuit 50 then supplies the generated drive signal COM to the head unit 20. The configuration and operation of the drive circuit 50 will be described in detail below.

[0023] The control circuit 100 also generates a drive data signal DATA for controlling the operation of the head unit 20 and outputs it to the head unit 20. The head unit 20 has a selection control unit 210, a plurality of selection units 230, and a liquid ejection head 21. The liquid ejection head 21 also has a plurality of ejection units 600, each including a piezoelectric element 60. Each of the plurality of selection units 230 is provided corresponding to the piezoelectric element 60 included in each of the plurality of ejection units 600 that the liquid ejection head 21 has.

[0024] The selection control unit 210 receives a drive data signal DATA. The selection control unit 210 operates using the voltage signal VHV as drive power. Based on the drive data signal DATA, the selection control unit 210 generates a signal for each of the selection units 230, instructing the selection unit 230 whether to select or deselect the drive signal COM. The selection control unit 210 then level-shifts the generated signal to a high-amplitude logic signal based on the voltage signal VHV to generate a selection signal S, which is then output to the corresponding selection unit 230. The drive signal COM and the corresponding selection signal S are input to each of the selection units 230. Based on the selection signal S, each of the selection units 230 generates and outputs a drive signal VOUT by selecting or deselecting the drive signal COM. That is, each of the selection units 230 generates a drive signal VOUT based on the drive signal COM, and supplies the drive signal VOUT to one end of the piezoelectric element 60 included in the corresponding ejection unit 600 included in the liquid ejection head 21.

[0025] A reference voltage signal VBS is commonly supplied to the other ends of the piezoelectric elements 60 included in the multiple ejection parts 600. The reference voltage signal VBS is a signal that functions as a reference potential for driving the piezoelectric elements 60 driven by the drive signal VOUT, and is a signal of a constant potential such as 5.5 V, 6 V, or 0 V.

[0026] The piezoelectric elements 60 are provided corresponding to each of the multiple nozzles in the head unit 20. The piezoelectric elements 60 are driven in response to the potential difference between a drive signal VOUT supplied to one end and a reference voltage signal VBS supplied to the other end. As a result, an amount of ink corresponding to the drive amount of the piezoelectric element 60 is ejected from an ejection section 600 including the piezoelectric element 60.

[0027] 2 illustrates a case where the head unit 20 has one liquid ejection head 21, but the number of liquid ejection heads 21 that the head unit 20 has is not limited to one. In other words, the head unit 20 may have multiple liquid ejection heads 21 depending on the type and number of inks to be ejected, etc.

[0028] As described above, the liquid ejection device 1 in this embodiment has a plurality of piezoelectric elements 60 that are driven by the supply of drive signals COM and VOUT, and is equipped with a liquid ejection head 21 that ejects ink as an example of a liquid by driving the plurality of piezoelectric elements 60, and a drive circuit 50 that outputs the drive signal COM.

[0029] 2. Discharge section configuration Next, an example of the configuration of the multiple ejection sections 600 included in the liquid ejection head 21 and an arrangement of the multiple ejection sections 600 in the head unit 20 will be described. Fig. 3 is a diagram showing an example of the arrangement of the multiple ejection sections 600 in the head unit 20. Fig. 3 illustrates an example where the head unit 20 has four liquid ejection heads 21.

[0030] 3, each of the four liquid ejection heads 21 has a plurality of ejection sections 600 arranged in a row in one direction. That is, the liquid ejection head 21 includes a nozzle row L in which nozzles 651 (described later) included in the ejection section 600 are arranged in one direction. The liquid ejection heads 21 are also positioned in the head unit 20 in a row intersecting the nozzle row L. That is, the head unit 20 has the same number of nozzle rows L as the liquid ejection heads 21. The arrangement of the nozzles 651 in the nozzle row L is not limited to one row. For example, the nozzles 651 may be arranged in a staggered pattern so that even-numbered nozzles 651 counting from one end of the plurality of nozzles 651 are positioned at different positions from odd-numbered nozzles 651 counting from one end of the plurality of nozzles 651. Alternatively, one nozzle row L may be formed by arranging a plurality of nozzles 651 side by side in two or more rows.

[0031] Next, an example of the configuration of the ejection unit 600 will be described. FIG. 4 is a diagram showing an example of the configuration of the ejection unit 600. As shown in FIG. 4, the ejection unit 600 includes a piezoelectric element 60, a diaphragm 621, a cavity 631, and a nozzle 651. The diaphragm 621 is displaced in response to the driving of the piezoelectric element 60 provided on the upper surface in FIG. 4. The diaphragm 621 functions as a diaphragm that expands and contracts the internal volume of the cavity 631. The cavity 631 is filled with ink. The cavity 631 functions as a pressure chamber whose internal volume changes in response to the displacement of the diaphragm 621 caused by the driving of the piezoelectric element 60. The nozzle 651 is formed in the nozzle plate 632 and is an opening portion that communicates with the cavity 631. Then, as the internal volume of the cavity 631 changes, ink stored in the cavity 631 is ejected from the nozzle 651.

[0032] Piezoelectric element 60 has a structure in which piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. In this structure, piezoelectric body 601 has electrodes 611 and 612 and a central portion of diaphragm 621 that bends in the vertical direction in FIG.

[0033] Specifically, a drive signal VOUT is supplied to an electrode 611 at one end of the piezoelectric element 60, and a reference voltage signal VBS is supplied to an electrode 612 at the other end. When the piezoelectric element 60 is driven upward in response to a change in the voltage of the drive signal VOUT, the vibration plate 621 is displaced upward. As a result, the internal volume of the cavity 631 expands. Therefore, ink stored in the reservoir 641 is drawn into the cavity 631. On the other hand, when the piezoelectric element 60 is driven downward in response to a change in the voltage value of the drive signal VOUT, the vibration plate 621 is displaced downward. As a result, the internal volume of the cavity 631 shrinks. Therefore, an amount of ink corresponding to the degree of shrinkage of the internal volume of the cavity 631 is ejected from the nozzle 651.

[0034] As described above, the liquid ejection head 21 includes the piezoelectric element 60, and ejects ink onto the medium P by driving the piezoelectric element 60. Note that the ejection section 600 and the piezoelectric element 60 included in the ejection section 600 are not limited to the configuration shown in the figure, and any configuration is acceptable as long as the piezoelectric element 60 is driven based on the drive signal VOUT and ink can be ejected from the corresponding nozzle 651 by driving the piezoelectric element 60.

[0035] 3. Configuration and operation of the drive circuit Next, the configuration and operation of the drive circuit 50 will be described.

[0036] 3.1 Signal waveform of drive signal COM Before describing the configuration and operation of the drive circuit 50, an example of the signal waveform of the drive signal COM output by the drive circuit 50 will be described. FIG. 5 is a diagram showing an example of the signal waveform of the drive signal COM. As shown in FIG. 5, the drive signal COM includes a trapezoidal waveform Adp for each period T. The trapezoidal waveform Adp includes a period during which the voltage value is a constant voltage vc, a period during which the voltage value is a constant voltage vb that is lower than voltage vc that follows the period during which the voltage value is a constant voltage vb that is higher than voltage vc that follows the period during which the voltage value is a constant voltage vt, and a period during which the voltage value is a constant voltage vt that is higher than voltage vc that follows the period during which the voltage value is a constant voltage vc. In other words, the drive signal COM includes a trapezoidal waveform Adp whose voltage value changes between voltage vt and voltage vb and that starts at voltage vc and ends at voltage vc during the period T.

[0037] The voltage vc corresponds to a potential that serves as a reference for the displacement of the piezoelectric element 60. When the voltage value of the drive signal COM supplied to the piezoelectric element 60 changes from voltage vc to voltage vb, the piezoelectric element 60 is driven in the upward direction shown in FIG. 4. As a result, the vibration plate 621 is displaced in the upward direction shown in FIG. 4. When the vibration plate 621 is displaced in the upward direction shown in FIG. 4, the internal volume of the cavity 631 expands, and ink stored in the reservoir 641 is drawn into the cavity 631. Thereafter, when the voltage value of the drive signal COM supplied to the piezoelectric element 60 changes from voltage vb to voltage vt, the piezoelectric element 60 is driven in the downward direction shown in FIG. 4. As a result, the vibration plate 621 is displaced in the downward direction shown in FIG. 4. When the vibration plate 621 is displaced in the downward direction shown in FIG. 4, the internal volume of the cavity 631 decreases, and ink stored in the cavity 631 is ejected from the nozzle 651.

[0038] Furthermore, the ink near the nozzle 651 and the diaphragm 621 may continue to vibrate for a certain period after ink is ejected from the nozzle 651 by driving the piezoelectric element 60. The period during which the voltage value included in the drive signal COM is constant at voltage vc also functions as a period for stopping such vibrations that occur in the ink and the diaphragm 621 and do not contribute to the ejection of ink.

[0039] Here, the signal waveform of the drive signal COM shown in Figure 5 is an example and is not limited to this, and may include signal waveforms of various shapes depending on the physical properties of the ink ejected by the liquid ejection head 21, the length of the period T of the drive signal COM, the transport speed of the medium P, etc.

[0040] 3.2 Drive circuit configuration Next, a description will be given of the configuration of the drive circuit 50. Fig. 6 is a diagram showing an example of the functional configuration of the drive circuit 50. As shown in Fig. 6, the drive circuit 50 has a D / A conversion circuit 510, an adder 511, a pulse modulation circuit 520, an inverter 521, an amplifier circuit 550, a demodulation circuit 560, a feedback circuit 570, a level switching signal output circuit 710, a level shift circuit 750, a boost circuit 760, and a boost voltage limiting circuit 800.

[0041] The D / A conversion circuit 510 receives a digital reference drive signal dA from the control circuit 100. The D / A conversion circuit 510 performs digital-to-analog conversion on the reference drive signal dA and then outputs the converted analog signal as the reference drive signal aA. That is, the D / A conversion circuit 510 converts the digital reference drive signal dA, which is the basis for the drive signal COM, into an analog reference drive signal aA. The voltage amplitude of this reference drive signal aA is, for example, 1 to 2 V, and the drive circuit 50 outputs a signal obtained by amplifying the reference drive signal aA as the drive signal COM. That is, the reference drive signal aA corresponds to a target signal before amplification of the drive signal COM.

[0042] The base drive signal aA is input to the positive input terminal of the adder 511. A feedback signal VFB, which is the drive signal COM fed back via a feedback circuit 570 (described later), is input to the negative input terminal of the adder 511. The adder 511 then outputs a signal obtained by subtracting the feedback signal VFB from the base drive signal aA to the pulse modulation circuit 520.

[0043] The pulse modulation circuit 520 generates a modulated signal MS by pulse-modulating the signal output by the adder 511. That is, the pulse modulation circuit 520 outputs a modulated signal MS obtained by modulating the analog basic drive signal aA. The modulated signal MS is a digital signal including an L-level potential and an H-level potential higher than the L-level. The pulse modulation circuit 520 then outputs the generated modulated signal MS to the amplifier circuit 550. The pulse modulation circuit 520 generates a pulse density modulated signal (PDM signal) by modulating the signal output by the adder 511 using a pulse density modulation (PDM) method, and outputs the PDM signal to the amplifier circuit 550 as the modulated signal MS. Specifically, the pulse modulation circuit 520 compares the voltage value of the output signal of the adder 511 with a reference voltage vref, which is a predetermined voltage value. The pulse modulation circuit 520 outputs a modulation signal MS that is at an H level when the voltage value of the output signal of the adder 511 is greater than the reference voltage vref, and is at an L level when the voltage value of the output signal of the adder 511 is less than the reference voltage vref.

[0044] The amplifier circuit 550 includes a gate drive circuit 530, a diode D1, a capacitor C1, and transistors M1 and M2. The amplifier circuit 550 amplifies the modulated signal MS to generate a first amplified modulated signal AMS1 and outputs it from a first output point OP1.

[0045] The gate drive circuit 530 outputs gate signals HGD1 and LGD1 based on the modulation signal MS. Specifically, the modulation signal MS is input to a gate driver 531 included in the gate drive circuit 530. The gate driver 531 generates a gate signal HGD1 by level-shifting the modulation signal MS and outputs it to transistor M1. The modulation signal MS has its logical level inverted by an inverter 521, and is then input to a gate driver 532 included in the gate drive circuit 530. The gate driver 532 generates a gate signal LGD1 by level-shifting a signal obtained by inverting the logical level of the modulation signal MS and outputs it to transistor M2.

[0046] The transistors M1 and M2 are both configured as N-channel MOSFETs. The source terminal of the transistor M1 is electrically connected to the first output point OP1, the drain terminal is supplied with the voltage vmv1 of the voltage signal VMV1 as a power supply voltage via a wiring Wvm1, and the transistor M1 operates based on a gate signal HGD1 input to the gate terminal. The drain terminal of the transistor M2 is electrically connected to the first output point OP1, and the source terminal is supplied with a ground signal GND, which is the ground potential gnd of 0 V, via a wiring Wgnd, and the transistor M2 operates based on a gate signal LGD1 input to the gate terminal.

[0047] Then, as a result of the transistor M1 operating based on the gate signal HGD1 and the transistor M2 operating based on the gate signal LGD1, a first amplified modulated signal AMS1 obtained by amplifying the modulated signal MS based on the ground potential gnd and the voltage vmv1 is generated at the first output point OP1. That is, the amplifier circuit 550 outputs the first amplified modulated signal AMS1 obtained by amplifying the modulated signal MS based on the ground potential gnd and the voltage vmv1.

[0048] Here, the operation of the gate drive circuit 530 will be described. The gate drive circuit 530 includes gate drivers 531 and 532. As described above, the gate driver 531 receives the modulation signal MS, and the gate driver 532 receives a signal obtained by inverting the logic level of the modulation signal MS by the inverter 521. That is, the signal input to the gate driver 531 and the signal input to the gate driver 532 are exclusively at the H level. Here, "exclusively at the H level" includes the case where an H level signal is not input to the gate driver 531 and the gate driver 532 at the same time. That is, it does not exclude the case where an L level signal is input to the gate driver 531 and the gate driver 532 at the same time.

[0049] The low-potential power supply terminal of the gate driver 531 is electrically connected to the first output point OP1. Therefore, the signal generated at the first output point OP1 is supplied to the low-potential power supply terminal of the gate driver 531 as a voltage signal HVS1. The high-potential power supply terminal of the gate driver 531 is electrically connected to the cathode terminal of the diode D1 and one end of the capacitor C1. The anode terminal of the diode D1 is supplied with a voltage signal VGD via a wiring Wvgd, and the other end of the capacitor C1 is electrically connected to the first output point OP1. That is, the diode D1 and the capacitor C1 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 531. Therefore, the high-potential power supply terminal of the gate driver 531 is supplied with a voltage signal HVD1 whose voltage value is higher than the voltage value of the voltage signal HVS1 input to the low-potential power supply terminal of the gate driver 531 by the voltage vgd, which is the voltage value of the voltage signal VGD.

[0050] Therefore, when an H-level modulation signal MS is input, the gate driver 531 outputs a gate signal HGD1 having a voltage value based on the voltage signal HVD1 having a voltage value that is higher than the voltage value of the first output point OP1 by the voltage vgd, and when an L-level modulation signal MS is input, the gate driver 531 outputs a gate signal HGD1 having a voltage value based on the voltage value of the voltage signal HVS1, which is the voltage value of the first output point OP1.

[0051] Here, the voltage vgm may be any voltage value that can drive the transistors M1 and M2 and the transistors M3 and M4 described later, and is not limited to a DC voltage of 7.5V.

[0052] A ground signal GND of ground potential gnd is supplied as a voltage signal LVS1 to a power supply terminal on the low potential side of the gate driver 532. Furthermore, a voltage signal VGD is supplied as a voltage signal LVD1 to a power supply terminal on the high potential side of the gate driver 532. Therefore, when an H-level signal obtained by inverting the logic level of an L-level modulation signal MS by the inverter 521 is input to the gate driver 532, the gate driver 532 outputs a gate signal LGD1 of a voltage value based on the voltage signal LVD1 of voltage vm, and when an L-level signal obtained by inverting the logic level of an H-level modulation signal MS by the inverter 521 is input to the gate driver 532, the gate driver 532 outputs a gate signal LGD1 of a voltage value based on the voltage signal LVS1 of ground potential gnd.

[0053] The level switching signal output circuit 710 receives the reference drive signal dA as input and generates a level switching signal LS based on the reference drive signal dA. The level switching signal LS is a digital signal that includes an L-level potential and an H-level potential that is higher than the L-level. Specifically, when the value of the reference drive signal dA is greater than a predetermined threshold, the level switching signal output circuit 710 outputs an H-level level switching signal LS, and when the value of the reference drive signal dA is smaller than the predetermined threshold, the level switching signal output circuit 710 outputs an L-level level switching signal LS. In other words, the level switching signal output circuit 710 outputs the level switching signal LS based on the reference drive signal dA.

[0054] The level shift circuit 750 includes a gate drive circuit 730, diodes D11 and D12, capacitors C11 and C12, and transistors M3 and M4. The level shift circuit 750 outputs the first amplified modulated signal AMS1 or a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 as a second amplified modulated signal AMS2 to a second output point OP2.

[0055] The gate drive circuit 730 outputs gate signals HGD2 and LGD2 based on the level switching signal LS. Specifically, the level switching signal LS is input to a gate driver 731 included in the gate drive circuit 730. The gate driver 731 generates a gate signal HGD2 by level-shifting the level switching signal LS and outputs it to transistor M3. The logical level of the level switching signal LS is inverted by an inverter 721, and then input to a gate driver 732 included in the gate drive circuit 730. The gate driver 732 generates a gate signal LGD2 by level-shifting a signal obtained by inverting the logical level of the level switching signal LS and outputs it to transistor M4.

[0056] The transistors M3 and M4 are both configured as N-channel MOSFETs. The source terminal of the transistor M3 is electrically connected to the second output point OP2, the drain terminal is supplied with the power supply voltage via the wiring Wbst, and the transistor M3 operates based on the gate signal HGD2 input to the gate terminal. The drain terminal of the transistor M4 is electrically connected to the second output point OP2, the source terminal is supplied with the first amplified modulation signal AMS1 via the wiring Wam1, and the transistor M4 operates based on the gate signal LGD2 input to the gate terminal.

[0057] Then, as a result of transistor M3 operating based on gate signal HGD2 and transistor M4 operating based on gate signal LGD2, the first amplified modulated signal AMS1 or a signal obtained by shifting the reference potential of the first amplified modulated signal AMS1 in level in accordance with the power supply voltage supplied to the drain terminal of transistor M3 is generated at second output point OP2 as second amplified modulated signal AMS2. That is, in accordance with level switching signal LS, level shift circuit 750 selects either a signal obtained by shifting the reference potential of the first amplified modulated signal AMS1 to the power supply voltage input via wiring Wbst, or a signal in which the reference potential of the first amplified modulated signal AMS1 is not shifted, and outputs it as second amplified modulated signal AMS2.

[0058] Here, the power supply voltage supplied to the drain terminal of transistor M3 is supplied from boost circuit 760 via wiring Wbst. Boost circuit 760 includes diode D13 and capacitor C13. One end of capacitor C13 is electrically connected to first output point OP1 via wiring Wam1, and the first amplified modulation signal AMS1 is supplied to this end. The other end is electrically connected to wiring Wbst, which supplies the power supply voltage to the drain terminal of transistor M3. The anode terminal of diode D13 is supplied with voltage signal VMV2 via wiring Wvm2, and the cathode terminal of diode D13 is electrically connected to wiring Wbst together with the other end of capacitor C13. Boost circuit 760 is the connection point where the other end of capacitor C13 and the cathode terminal of diode D13 are connected, and outputs the signal on wiring Wbst as voltage signal VMV3. The voltage signal VMV3 output by the boost circuit 760 is supplied to the drain terminal of the transistor M3 as the power supply voltage of the transistor M3. That is, the boost circuit 760 includes a capacitor C13 having one end electrically connected to the line Wam1 and the other end electrically connected to the line Wbst, and a diode D13 having an anode terminal electrically connected to the line Wvm2 and a cathode terminal electrically connected to the line Wam1.

[0059] In the boost circuit 760 configured as described above, a charge corresponding to the voltage vmv2, which is the voltage value of the voltage signal VMV2, is stored in the capacitor C13. The boost circuit 760 then outputs a signal obtained by adding the voltage value of the first amplified modulation signal AMS1 to the voltage value across the capacitor C13, which is a voltage value corresponding to the voltage vmv2, in accordance with the charge stored in the capacitor C13, as a voltage signal VMV3 to the drain terminal of the transistor M3. To be precise, the voltage value across the capacitor C13 is the value obtained by subtracting the forward voltage of the diode D13 from the voltage vmv2, which is the voltage value of the voltage signal VMV2. However, in this embodiment, the voltage value across the capacitor C13 will be described as being equal to the voltage vmv2, which is the voltage value of the voltage signal VMV2 supplied to the boost circuit 760. That is, the boost circuit 760 is electrically connected to the wiring Wvm2, through which the voltage signal VMV2 having a voltage value of voltage vmv2 propagates, and the wiring Wam1, and outputs the voltage signal VMV3 to the wiring Wbst.

[0060] The boost voltage limiting circuit 800 is electrically connected to the wiring Wvm2 through which the voltage signal VMV2 propagates and the wiring Wbst through which the voltage signal VMV3 propagates. The boost voltage limiting circuit 800 limits the voltage value of the voltage signal VMV3 output from the boost circuit 760 based on the voltage vmv2 that is the voltage value of the voltage signal VMV2. The configuration and operation of the boost voltage limiting circuit 800 will be described in detail later.

[0061] Here, the operation of the gate drive circuit 730 will be described. The gate drive circuit 730 includes gate drivers 731 and 732. As described above, the level switching signal LS is input to the gate driver 731, and a signal obtained by inverting the logical level of the level switching signal LS by the inverter 721 is input to the gate driver 732. That is, the signal input to the gate driver 731 and the signal input to the gate driver 732 are exclusively at H level. Here, "exclusively at H level" includes the case where an H level signal is not input to the gate driver 731 and the gate driver 732 at the same time. That is, it does not exclude the case where an L level signal is input to the gate driver 731 and the gate driver 732 at the same time.

[0062] The low-potential power supply terminal of the gate driver 731 is electrically connected to the second output point OP2. Therefore, the signal generated at the second output point OP2 is supplied to the low-potential power supply terminal of the gate driver 731 as a voltage signal HVS2. The high-potential power supply terminal of the gate driver 731 is electrically connected to the cathode terminal of the diode D11 and one end of the capacitor C11. The anode terminal of the diode D11 is supplied with a voltage signal VGD via a line Wvgd, and the other end of the capacitor C11 is electrically connected to the second output point OP2. In other words, the diode D11 and the capacitor C11 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 731. Therefore, a voltage signal HVD2 having a voltage value higher than the voltage value of the voltage signal HVS2 input to the low potential side power supply terminal of the gate driver 731 by the voltage vgd, which is the voltage value of the voltage signal VGD, is supplied to the high potential side power supply terminal of the gate driver 731.

[0063] Therefore, when an H-level level switching signal LS is input, the gate driver 731 outputs a gate signal HGD2 with a voltage value based on the voltage signal HVD2 with a voltage value that is higher by the voltage vgd than the voltage value of the second output point OP2, and when an L-level level switching signal LS is input, it outputs a gate signal HGD2 with a voltage value based on the voltage value of the voltage signal HVS2, which is the voltage value of the second output point OP2.

[0064] The low-potential power supply terminal of the gate driver 732 is electrically connected to the first output point OP1 via a wiring Wam1. Therefore, the first amplified modulation signal AMS1 generated at the first output point OP1 is supplied as a voltage signal LVS2 to the low-potential power supply terminal of the gate driver 732. In addition, the high-potential power supply terminal of the gate driver 732 is electrically connected to the cathode terminal of the diode D12 and one end of the capacitor C12. In addition, the voltage signal VGD is supplied to the anode terminal of the diode D12 via a wiring Wvgd, and the other end of the capacitor C12 is electrically connected to the first output point OP1 via a wiring Wam1. In other words, the diode D12 and the capacitor C12 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 732. Therefore, a voltage signal LVD2 having a voltage value higher than the voltage value of the voltage signal LVS2 input to the low potential side power supply terminal of the gate driver 732 by the voltage vgd, which is the voltage value of the voltage signal VGD, is supplied to the high potential side power supply terminal of the gate driver 732.

[0065] Therefore, when the gate driver 732 receives an H-level signal in which the logical level of the L-level level switching signal LS is inverted by the inverter 721, it outputs a gate signal LGD2 having a voltage value based on the voltage signal LVD2 having a voltage value that is higher by the voltage vgd than the voltage value of the first output point OP1, and when the gate driver 732 receives an L-level signal in which the logical level of the H-level level switching signal LS is inverted by the inverter 721, it outputs a gate signal HGD2 having a voltage value that is the voltage value of the first output point OP1 and is based on the voltage value of the voltage signal LVS2.

[0066] When the level switching signal LS of L level output by the level switching signal output circuit 710 is input to the level shift circuit 750 configured as described above, the first output point OP1 of the amplifier circuit 550 and the second output point OP2 of the level shift circuit 750 are electrically connected via the transistor M4. Therefore, when the level switching signal LS of L level is input, the level shift circuit 750 outputs the first amplified modulated signal AMS1 supplied to the second output point OP2 via the transistor M4 as the second amplified modulated signal AMS2.

[0067] On the other hand, when an H-level level switching signal LS output by the level switching signal output circuit 710 is input to the level shift circuit 750, the first output point OP1 of the amplifier circuit 550 and the second output point OP2 of the level shift circuit 750 are electrically connected via the boost circuit 760 and the transistor M3. Therefore, when an H-level level switching signal LS is input, the level shift circuit 750 outputs, as the second amplified modulation signal AMS2, a voltage signal VMV3 which is a signal obtained by level-shifting the reference potential of the first amplified modulation signal AMS1 by the voltage vmv2 which is the voltage value of the voltage signal VMV2.

[0068] In the following description, an operation mode in which the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 will be referred to as a first mode MD1, and an operation mode in which the level shift circuit 750 outputs a signal obtained by level-shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 will be referred to as a second mode MD2. That is, the level shift circuit 750 is in the first mode MD1 when the level switching signal LS is at an L level, and in the second mode MD2 when the level switching signal LS is at an H level.

[0069] Furthermore, as described above, when the value of the reference drive signal dA is smaller than a predetermined threshold, the level switching signal output circuit 710 outputs an L-level level switching signal LS. Therefore, when the value of the reference drive signal dA is smaller than the predetermined threshold, the operation mode of the level shift circuit 750 becomes the first mode MD1. Thereafter, when the value of the reference drive signal dA becomes larger than the predetermined threshold, the level switching signal output circuit 710 switches the level switching signal LS from L to H. This switches the operation mode of the level shift circuit 750 from the first mode MD1 to the second mode MD2. Furthermore, immediately after switching the logic level of the level switching signal LS from L to H, the level switching signal output circuit 710 outputs a pulse signal one or more times in which the logic level of the level switching signal LS to be output becomes L for a short period of time in order to reduce waveform distortion of the drive signal COM that may occur when the operation mode of the level shift circuit 750 is switched.

[0070] On the other hand, when the value of the reference drive signal dA is greater than a predetermined threshold, the level switching signal output circuit 710 outputs an H-level level switching signal LS. Therefore, the operation mode of the level shift circuit 750 switches to the second mode MD2. Thereafter, when the value of the reference drive signal dA becomes smaller than the predetermined threshold, the level switching signal output circuit 710 switches the level switching signal LS from H to L. This switches the operation mode of the level shift circuit 750 from the second mode MD2 to the first mode MD1. Furthermore, immediately after switching the logical level of the level switching signal LS from H to L, the level switching signal output circuit 710 outputs a pulse signal one or more times in which the logical level of the level switching signal LS to be output is H for a short period of time, in order to reduce waveform distortion of the drive signal COM that may occur when the operation mode of the level shift circuit 750 is switched.

[0071] In the following description, the pulse signal that becomes L level for a short period of time when the operation mode of the level shift circuit 750 is switched from the first mode MD1 to the second mode MD2, and the pulse signal that becomes H level for a short period of time when the operation mode of the level shift circuit 750 is switched from the second mode MD2 to the first mode MD1, may be referred to as a counter pulse CP.

[0072] The second amplified modulated signal AMS2 output by the level shift circuit 750 propagates through the wiring Wam2 and is input to the demodulation circuit 560. The demodulation circuit 560 smoothes and demodulates the second amplified modulated signal AMS2 output by the level shift circuit 750, thereby generating the drive signal COM. The drive signal COM generated by the demodulation circuit 560 propagates through the wiring Wcom and is output from the drive circuit 50.

[0073] The demodulation circuit 560 includes an inductor 561 and a capacitor 562. One end of the inductor 561 is electrically connected to the second output point OP2 via a wiring Wam2. The other end of the inductor 561 is electrically connected to one end of the capacitor 562 via a wiring Wcom. A ground signal GND at the ground potential gnd propagating through a wiring Wgnd is supplied to the other end of the capacitor 562. That is, the inductor 561 and the capacitor 562 form a low-pass filter circuit. The second amplified modulated signal AMS2 output from the level shift circuit 750 is smoothed by this low-pass filter circuit. The signal obtained by smoothing the second amplified modulated signal AMS2 by the demodulation circuit 560 is then propagated through the wiring Wcom as the drive signal COM and output from the drive circuit 50.

[0074] The feedback circuit 570 receives the drive signal COM generated by the demodulation circuit 560 and outputs a feedback signal VFB to the adder 511. Specifically, the feedback circuit 570 divides the drive signal COM and supplies the resulting feedback signal VFB to the adder 511. This causes the drive signal COM to be fed back to the pulse modulation circuit 520. As a result, the waveform accuracy of the drive signal COM output by the drive circuit 50 is improved. Here, the feedback circuit 570 may feed back, as the feedback signal VFB, multiple signals including a signal obtained by dividing the drive signal COM and a signal obtained by extracting high-frequency components from the drive signal COM. That is, the feedback circuit 570 may include multiple feedback circuits, each including a circuit that feeds back a signal obtained by dividing the drive signal COM and a circuit that feeds back a signal obtained by extracting high-frequency components from the drive signal COM. This makes it possible to individually feed back the high-frequency components included in the drive signal COM. As a result, the drive circuit 50 can self-oscillate based on the high-frequency components, and the frequency of the modulation signal MS can be increased to a level sufficient to ensure the accuracy of the drive signal COM. Therefore, the waveform accuracy of the drive signal COM output by the drive circuit 50 is further improved.

[0075] As described above, the drive circuit 50 of this embodiment is a capacitive load drive circuit that outputs a drive signal COM for driving the piezoelectric element 60, which is a capacitive load, and is electrically connected to the wiring Wgnd through which the ground signal GND of the ground potential gnd propagates and the wiring Wvm1 through which the voltage signal VMV1 of the voltage value vm1 propagates, and is connected to the amplifier circuit 550 that outputs the first amplified modulation signal AMS1 to the wiring Wam1, and is electrically connected to the wiring Wvm2 through which the voltage signal VMV2 of the voltage value vmv2 propagates and the wiring Wam1. and outputs a voltage signal VMV3 to the wiring Wbst; a level shift circuit 750 connected to the wiring Wam1 and the wiring Wbst and outputs a second amplified modulated signal AMS2 to the wiring Wam2; a demodulation circuit 560 that smoothes the second amplified modulated signal AMS2 and outputs it as a drive signal COM; and a boost voltage limiting circuit 800 that limits the voltage value of the voltage signal VMV3 output from the boost circuit 760 based on a voltage vmv2 that is the voltage value of the voltage signal VMV2.

[0076] 3.3 Operation of the drive circuit Next, the operation of the drive circuit 50 will be described. FIG. 7 is a diagram illustrating the operation of the drive circuit 50. Note that FIG. 7 illustrates only the drive signal COM at an arbitrary period T among the drive signals COM output by the drive circuit 50. For ease of illustration and explanation, FIG. 7 illustrates a signal waveform in an ideal case with no circuit delay or wiring delay. Also, in FIG. 7, a predetermined threshold value of the basic drive signal dA for switching the logical level of the level switching signal LS output by the level switching signal output circuit 710 is illustrated as threshold value dvth, and the voltage value of the drive signal COM corresponding to threshold value dvth is illustrated as voltage vth. Furthermore, in FIG. 7, the values ​​of the basic drive signal dA corresponding to voltages vt, vb, and vc of the drive signal COM are illustrated as digital values ​​dvt, dvb, and dvc, respectively. Note that FIG. 7 illustrates an example in which voltage vth is lower than voltage vc and threshold value dvth is smaller than digital value dvc, but the relationship between voltage vth and voltage vc and the relationship between threshold value dvth and digital value dvc are not limited to this.

[0077] 7, during the period from time t0 to time t10, a base drive signal dA having a digital value dvc is input to the D / A conversion circuit 510. Therefore, the voltage value of the drive signal COM output by the drive circuit 50 becomes voltage vc. At this time, the digital value dvc is greater than the threshold value dvth. Therefore, the level switching signal output circuit 710 outputs an H-level level switching signal LS. That is, during the period from time t0 to time t10, the operation mode of the level shift circuit 750 is the second mode MD2, and the level shift circuit 750 outputs a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to voltage vmv2 as the second amplified modulated signal AMS2.

[0078] During the period from time t10 to time t20, the D / A conversion circuit 510 is input with the basic drive signal dA decreasing from digital value dvc to digital value dvb. Therefore, the voltage value of the drive signal COM output by the drive circuit 50 decreases from voltage vc to voltage vb. Within the period from time t10 to time t20, during the period from time t10 to time tc1 when the value of the basic drive signal dA is greater than the threshold value dvth, the level switching signal output circuit 710 outputs an H-level level switching signal LS. That is, during the period from time t10 to time tc1, the operating mode of the level shift circuit 750 remains in the second mode MD2, and the level shift circuit 750 outputs a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to voltage vmv2 as the second amplified modulated signal AMS2. On the other hand, within the period from time t10 to time t20, during which the value of the basic drive signal dA is smaller than the threshold value dvth, the level switching signal output circuit 710 outputs an L-level level switching signal LS. This causes the operation mode of the level shift circuit 750 to transition to the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0079] When the operating mode of the level shift circuit 750 transitions from the second mode MD2 to the first mode MD1, the reference potential of the first amplified modulated signal AMS1, which is output as the second amplified modulated signal AMS2, changes abruptly from voltage vmv2 to ground potential. If the response speed of the drive circuit 50 cannot keep up with this abrupt change in the reference potential, distortion may occur in the signal waveform of the drive signal COM. In the drive circuit 50 of this embodiment, in order to reduce such signal waveform distortion that may occur in the drive signal COM, at time tc1, after the operating mode of the level shift circuit 750 transitions from the second mode MD2 to the first mode MD1, the level switching signal output circuit 710 outputs a counter pulse CP that inverts the logic level of the level switching signal LS for a short period of time. This counter pulse CP causes the reference potential of the first amplified modulated signal AMS1, which is output as the second amplified modulated signal AMS2, to change more gradually, thereby reducing the risk of distortion occurring in the signal waveform of the drive signal COM.

[0080] During the period from time t20 to time t30, the original drive signal dA of digital value dvb is input to the D / A conversion circuit 510. Therefore, the voltage value of the drive signal COM output by the drive circuit 50 becomes voltage vb. At this time, the digital value dvb is smaller than the threshold value dvth. Therefore, the level switching signal output circuit 710 outputs an L-level level switching signal LS. That is, during the period from time t20 to time t30, the operation mode of the level shift circuit 750 remains in the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0081] During the period from time t30 to time t40, the D / A conversion circuit 510 is input with the basic drive signal dA increasing from digital value dvb to digital value dvt. Therefore, the voltage value of the drive signal COM output by the drive circuit 50 increases from voltage vb to voltage vt. Within the period from time t30 to time t40, during the period from time t30 to time tc2 when the value of the basic drive signal dA is smaller than the threshold value dvth, the level switching signal output circuit 710 outputs an L-level level switching signal LS. That is, during the period from time t30 to time tc2, the operating mode of the level shift circuit 750 remains in the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2. On the other hand, within the period from time t30 to time t40, during which the value of the basic drive signal dA is greater than the threshold value dvth, the level switching signal output circuit 710 outputs an H-level level switching signal LS. This causes the operation mode of the level shift circuit 750 to transition to the second mode MD2, and the level shift circuit 750 outputs, as the second amplified modulated signal AMS2, a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to voltage vmv2.

[0082] When the operating mode of the level shift circuit 750 transitions from the first mode MD1 to the second mode MD2, the reference potential of the first amplified modulated signal AMS1, which is output as the second amplified modulated signal AMS2, changes abruptly from ground potential to voltage vmv2. If the response speed of the drive circuit 50 cannot keep up with this abrupt change in the reference potential, distortion may occur in the signal waveform of the drive signal COM. In the drive circuit 50 of this embodiment, in order to reduce such signal waveform distortion that may occur in the drive signal COM, at time tc2, after the operating mode of the level shift circuit 750 transitions from the first mode MD1 to the second mode MD2, the level switching signal output circuit 710 outputs a counter pulse CP that inverts the logic level of the level switching signal LS for a short period of time. This counter pulse CP causes the reference potential of the first amplified modulated signal AMS1, which is output as the second amplified modulated signal AMS2, to change more gradually, thereby reducing the risk of distortion in the signal waveform of the drive signal COM.

[0083] During the period from time t40 to time t50, the basic drive signal dA of digital value dvt is input to the D / A conversion circuit 510. Therefore, the voltage value of the drive signal COM output by the drive circuit 50 becomes voltage vt. At this time, the digital value dvt is greater than the threshold value dvth. Therefore, the level switching signal output circuit 710 outputs an H-level level switching signal LS. That is, during the period from time t40 to time t50, the operation mode of the level shift circuit 750 remains in the second mode MD2, and the level shift circuit 750 outputs a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to voltage vmv2 as the second amplified modulated signal AMS2.

[0084] During the period from time t50 to time t60, the D / A conversion circuit 510 is input with the basic drive signal dA decreasing from digital value dvt to digital value dvc. Therefore, the voltage value of the drive signal COM output by the drive circuit 50 decreases from voltage vt to voltage vc. At this time, the value of the basic drive signal dA is greater than the threshold value dvth. Therefore, the level switching signal output circuit 710 outputs an H-level level switching signal LS. That is, during the period from time t50 to time t60, the operating mode of the level shift circuit 750 remains in the second mode MD2, and the level shift circuit 750 outputs a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to voltage vmv2 as the second amplified modulated signal AMS2.

[0085] During the period from time t60 to time t70, the basic drive signal dA of digital value dvc is input to the D / A conversion circuit 510. Therefore, the voltage value of the drive signal COM output by the drive circuit 50 is voltage vc. At this time, the digital value dvc is greater than the threshold value dvth. Therefore, the level switching signal output circuit 710 outputs an H-level level switching signal LS. That is, during the period from time t60 to time t70, the operation mode of the level shift circuit 750 remains in the second mode MD2, and the level shift circuit 750 outputs a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to voltage vmv2 as the second amplified modulated signal AMS2.

[0086] 3.4 Configuration and operation of the boost voltage limiting circuit In the drive circuit 50 configured as described above, the amount of charge stored in the capacitor C13 of the boost circuit 760 varies depending on the signal waveform of the drive signal COM output and the number of piezoelectric elements 60 driven by the drive signal COM, which may result in fluctuations in the voltage value across the capacitor C13. Such fluctuations in the voltage value across the capacitor C13 may distort the signal waveform of the voltage signal VMV3 output by the boost circuit 760 and the signal waveform of the drive signal COM output by the drive circuit 50, thereby degrading the ejection accuracy of ink ejected from the ejection unit 600. Furthermore, if the fluctuations in the voltage value across the capacitor C13 exceed the withstand voltage of the various electronic components that make up the drive circuit 50, these electronic components may fail. The boost voltage limiting circuit 800 of the drive circuit 50 of this embodiment limits the fluctuation in the voltage value between both ends of the capacitor C13, i.e., the fluctuation in the voltage value of the voltage signal VMV3 output by the boost circuit 760, thereby reducing the risk of distortion in the signal waveform of the drive signal COM output by the drive circuit 50 and reducing the risk of deterioration in the ejection accuracy of the ink ejected from the ejection section 600.

[0087] Before describing the configuration and operation of the boost voltage limiting circuit 800, we will first describe the current flowing through the drive circuit 50, which is one of the factors that causes fluctuations in the voltage value across the capacitor C13. FIGS. 8 to 11 are diagrams illustrating an overview of the current flowing through the drive circuit 50. Specifically, FIG. 8 illustrates the direction of the current flowing through the drive circuit 50 when the level shift circuit 750 is in the first mode MD1 and the voltage value of the drive signal COM increases. FIG. 9 illustrates the direction of the current flowing through the drive circuit 50 when the level shift circuit 750 is in the first mode MD1 and the voltage value of the drive signal COM decreases. FIG. 10 illustrates the direction of the current flowing through the drive circuit 50 when the level shift circuit 750 is in the second mode MD2 and the voltage value of the drive signal COM increases. FIG. 11 illustrates the direction of the current flowing through the drive circuit 50 when the level shift circuit 750 is in the second mode MD2 and the voltage value of the drive signal COM decreases.

[0088] When the level shift circuit 750 is in the first mode MD1, the transistor M3 is non-conductive and the transistor M4 is conductive. As a result, the first output point OP1 and the second output point OP2 are electrically connected via the transistor M4. Therefore, the first amplified modulated signal AMS1 output from the first output point OP1 propagates through the wiring Wam1, Wam2, and Wcom and the transistor M4, and is output from the second output point OP2 as the second amplified modulated signal AMS2. The second amplified modulated signal AMS2 output from the second output point OP2 is smoothed by the demodulation circuit 560, and the drive circuit 50 outputs the drive signal COM. In this first mode MD1, when the voltage value of the drive signal COM output by the drive circuit 50 is rising, a charge is stored in the piezoelectric element 60 due to the current flowing due to the propagation of the drive signal COM. Therefore, when the level shift circuit 750 is in the first mode MD1 and the voltage value of the drive signal COM is rising, current flows in the drive circuit 50 in the direction from the first output point OP1 to the second output point OP2, in the order of wire Wam1, transistor M4, wire Wam2, and wire Wcom, as shown in Figure 8.

[0089] On the other hand, in the first mode MD1, when the voltage value of the drive signal COM output by the drive circuit 50 decreases, the charge stored in the piezoelectric element 60 is released. Therefore, when the level shift circuit 750 is in the first mode MD1 and the voltage value of the drive signal COM decreases, a current flows in the drive circuit 50 from the second output point OP2 to the first output point OP1, in this order, through the wire Wcom, the wire Wam2, the transistor M4, and the wire Wam1, as shown in FIG.

[0090] Furthermore, when the level shift circuit 750 is in the second mode MD2, the transistor M3 is conductive and the transistor M4 is non-conductive. This electrically connects the first output point OP1 and the second output point OP2 via the transistor M4 and the boost circuit 760. Therefore, the first amplified modulated signal AMS1 output from the first output point OP1 is level-shifted from its reference potential to voltage vmv2 in the boost circuit 760, propagates through the transistor M3, and is output from the second output point OP2 as the second amplified modulated signal AMS2. The second amplified modulated signal AMS2 output from the second output point OP2 is smoothed in the demodulation circuit 560, causing the drive circuit 50 to output the drive signal COM. In this second mode MD2, when the voltage value of the drive signal COM output by the drive circuit 50 is rising, a current flows due to the propagation of the drive signal COM, and an electric charge is stored in the piezoelectric element 60. Therefore, when the level shift circuit 750 is in the second mode MD2 and the voltage value of the drive signal COM is rising, current flows in the drive circuit 50 in the direction from the first output point OP1 to the second output point OP2, in the order of wire Wam1, capacitor C13, wire Wbst, transistor M3, wire Wam2, and wire Wcom, as shown in Figure 10.

[0091] On the other hand, in the second mode MD2, when the voltage value of the drive signal COM output by the drive circuit 50 decreases, the charge stored in the piezoelectric element 60 is released. Therefore, when the level shift circuit 750 is in the second mode MD2 and the voltage value of the drive signal COM decreases, a current flows in the drive circuit 50 from the second output point OP2 to the first output point OP1, in this order, through the wire Wcom, wire Wam2, transistor M3, wire Wbst, capacitor C13, and wire Wam1, as shown in FIG.

[0092] As described above, in the drive circuit 50 of this embodiment, the capacitor C13 of the boost circuit 760 is provided in the path of the current that flows in association with the propagation of the drive signal COM that is output. Therefore, the amount of charge stored in the capacitor C13 fluctuates in association with the propagation of the drive signal COM that is output by the drive circuit 50, which increases the risk of fluctuations in the voltage value generated across the capacitor C13.

[0093] The following describes the configuration of a boost voltage limiting circuit 800 that limits fluctuations in the voltage value that may occur across such capacitor C13. Fig. 12 is a diagram showing an example of the configuration of the boost voltage limiting circuit 800. As shown in Fig. 12, the boost voltage limiting circuit 800 includes a voltage drop limiting circuit 810, a voltage rise limiting circuit 820, and a voltage rise protection circuit 830.

[0094] The voltage drop limiting circuit 810 includes a transistor 811, a zener diode 812, and a resistor 813. The transistor 811 is an NPN bipolar transistor, and its collector terminal is electrically connected to the wiring Wvm2 and its emitter terminal is electrically connected to the wiring Wbst. The base terminal of the transistor 811 is electrically connected to the anode terminal of the zener diode 812 and one end of the resistor 813. The cathode terminal of the zener diode 812 is electrically connected to the wiring Wvm2, and the other end of the resistor 813 is electrically connected to the wiring Wbst. The voltage drop limiting circuit 810 configured as described above limits the drop in the voltage value across the capacitor C13 by controlling the conduction state between the collector terminal and the emitter terminal of the transistor 811 based on the potential difference between the wiring Wvm2 and the wiring Wbst.

[0095] The voltage rise limiting circuit 820 includes a transistor 821, a zener diode 822, and a resistor 823. The transistor 821 is an NPN bipolar transistor, and its collector terminal is electrically connected to the wiring Wbst and its emitter terminal is electrically connected to the wiring Wvm2. The base terminal of the transistor 821 is electrically connected to the anode terminal of the zener diode 822 and one end of the resistor 823. The cathode terminal of the zener diode 822 is electrically connected to the wiring Wbst, and the other end of the resistor 823 is electrically connected to the wiring Wvm2. The voltage rise limiting circuit 820 configured as described above limits the rise in the voltage value across the capacitor C13 by controlling the conduction state between the collector terminal and the emitter terminal of the transistor 821 based on the potential difference between the wiring Wvm2 and the wiring Wbst.

[0096] The voltage rise protection circuit 830 includes a diode 831. The anode terminal of the diode 831 is electrically connected to the wiring Wbst, and the voltage signal VHV is supplied to the cathode terminal. When the voltage value of the wiring Wbst becomes larger than the voltage vhv, which is the voltage value of the voltage signal VHV, the voltage rise protection circuit 830 releases the charge of the wiring Wbst that is stored in the capacitor C13 electrically connected to the wiring Wbst via the diode 831. This reduces the risk that the voltage value of the wiring Wbst, which is the voltage value at the other end of the capacitor C13, will become larger than the voltage vhv.

[0097] The voltage signal VHV is a signal with a voltage value used by the selection control unit 210 and the like to switch whether or not to supply the drive signal COM to the piezoelectric element 60, and is the signal with the highest potential among the voltage values ​​used in various circuits provided in the propagation path along which the drive signal COM propagates. The voltage rise protection circuit 830 reduces the risk that the voltage value of the wiring Wbst will exceed the voltage vhv, thereby reducing the risk that excessive voltage will be applied to circuit elements provided in the propagation path as the drive signal COM based on the voltage signal VMV3 propagates, and as a result, the reliability of the liquid ejection device 1 including the drive circuit 50 is improved.

[0098] A specific example of the operation of limiting fluctuations in the voltage value that can occur across the capacitor C13 in the boost voltage limiting circuit 800 configured as above will now be described.

[0099] When charge based on voltage vmv2, which is the voltage value of voltage signal VMV2, is normally stored across capacitor C13 in boost circuit 760, the voltage value at the other end of capacitor C13, i.e., the voltage value of line Wbst, is the sum of the voltage value of first amplified modulation signal AMS1 and voltage vmv2. Here, as described above, the voltage value of first amplified modulation signal AMS1 is voltage vmv1 based on voltage signal VMV1 when transistor M1 is conductive, and is ground potential gnd (0 V) when transistor M2 is conductive. Therefore, when charge based on voltage vmv2 is normally stored across capacitor C13, the voltage value at the other end of capacitor C13 varies between voltage vmv2 and the sum of voltage vmv2 and voltage vmv1 in accordance with the first amplified modulation signal AMS1.

[0100] When the charge stored in capacitor C13 is released by the current generated by the propagation of drive signal COM, the voltage across capacitor C13 decreases. As the voltage across capacitor C13 decreases, the voltage across voltage signal VMV3 also decreases. At this time, the voltage across voltage signal VMV2 propagating through line Wvm2 remains constant at voltage vmv2. Therefore, as the voltage across capacitor C13 decreases, the potential difference ΔVlow between the voltages on lines Wvm2 and Wbst, which is the difference between the voltages of voltage signal VMV2 and VMV3 and is calculated by subtracting the voltage of voltage signal VMV3 from the voltage of voltage signal VMV2, increases. When the increasing potential difference ΔVlow exceeds a threshold voltage vtz1 defined by the Zener voltage vzd1 of zener diode 812 and the resistance of resistor 813, a current corresponding to the difference between the potential difference ΔVlow and the threshold voltage vtz1 is supplied to the base terminal of transistor 811 via zener diode 812.

[0101] The transistor 811 controls the conduction state between the collector terminal and the emitter terminal in accordance with the amount of current supplied to the base terminal. That is, the transistor 811 supplies a current from the wiring Wvm2 to the wiring Wbst in an amount corresponding to the amount of current supplied to the base terminal. The current supplied via this transistor 811 accumulates charge in the capacitor C13 electrically connected to the wiring Wbst. As a result, the voltage drop across the capacitor C13 is limited. That is, the voltage drop limiting circuit 810 limits the voltage drop across the capacitor C13 in accordance with the potential difference ΔVlow between the voltage of the wiring Wvm2 and the voltage of the wiring Wbst, which is the value obtained by subtracting the voltage of the voltage signal VMV3 from the voltage of the voltage signal VMV2.

[0102] As described above, the lower-limit voltage value of the voltage signal VMV3 is determined by the threshold voltage vtz1, which is determined by the Zener voltage vzd1 of the constant voltage diode 812 and the resistance value of the resistor 813. That is, the lower-limit voltage value of the voltage signal VMV3 is determined based on the value obtained by subtracting the threshold voltage vtz1 from the voltage vmv2, which is the voltage value of the voltage signal VMV2. The value of the threshold voltage vtz1, which determines the lower-limit voltage value of the voltage signal VMV3, is set within an allowable range for fluctuation in the voltage value of the voltage signal VMV3 when the voltage value of the first amplified modulation signal AMS1 is the ground potential gnd, for example, so that the lower-limit voltage value of the voltage signal VMV3 is equal to or greater than 80% of the voltage vmv2, which is the voltage value of the voltage signal VMV2.

[0103] Meanwhile, when charge accumulates in capacitor C13 due to the current generated by the propagation of drive signal COM, the voltage across capacitor C13 increases. As the voltage across capacitor C13 increases, the voltage across voltage signal VMV3 also increases. At this time, the voltage across voltage signal VMV2 propagating through line Wvm2 remains constant at voltage vmv2. Therefore, as the voltage across capacitor C13 increases, the potential difference ΔVhi between the voltages on lines Wbst and Wvm2, which is the difference between the voltages of voltage signal VMV2 and voltage signal VMV3, increases. When the increasing potential difference ΔVhi exceeds a threshold voltage vtz2 defined by the Zener voltage vzd2 of zener diode 822 and the resistance of resistor 823, a current corresponding to the difference between the potential difference ΔVhi and the threshold voltage vtz2 is supplied to the base terminal of transistor 821 via zener diode 822.

[0104] The transistor 821 controls the conduction state between the collector terminal and the emitter terminal in accordance with the amount of current supplied to the base terminal. That is, the transistor 821 supplies a current from the wiring Wbst to the wiring Wvm2 in an amount corresponding to the amount of current supplied to the base terminal. The current flowing through this transistor 821 discharges the charge stored in the capacitor C13 electrically connected to the wiring Wbst. As a result, the increase in the voltage value across the capacitor C13 is limited. That is, the voltage increase limiting circuit 820 limits the increase in the voltage value across the capacitor C13 in accordance with the potential difference ΔVhi between the voltage value of the wiring Wbst and the voltage value of the wiring Wvm2, which is the value obtained by subtracting the voltage value of the voltage signal VMV2 from the voltage value of the voltage signal VMV3.

[0105] As described above, the upper limit voltage value of the voltage signal VMV3 is determined by the threshold voltage vtz2, which is determined by the Zener voltage vzd2 of the constant voltage diode 822 and the resistance value of the resistor 823. That is, the upper limit voltage value of the voltage signal VMV3 is determined based on the sum of the voltage vmv2, which is the voltage value of the voltage signal VMV2, and the value of the threshold voltage vtz2. The value of the threshold voltage vtz2, which determines the upper limit voltage value of the voltage signal VMV3, is set within an allowable range for fluctuation in the voltage value of the voltage signal VMV3 when the voltage value of the first amplified modulation signal AMS1 is the voltage vmv1, which is the voltage value of the voltage signal VMV1. For example, the upper limit voltage value of the voltage signal VMV3 is set to a value equal to or less than 120% of the sum of the voltage vmv2, which is the voltage value of the voltage signal VMV2, and the voltage vmv1, which is the voltage value of the voltage signal VMV1.

[0106] In this case, the value of the threshold voltage vtz2, which is determined by the Zener voltage vzd2 of the constant voltage diode 822 and the resistance value of the resistor 823, is preferably set so that the sum of the voltage vmv2 and the threshold voltage vtz2 is smaller than the voltage vhv of the voltage signal VHV. This causes the voltage increase limiting circuit 820 to limit the voltage of the voltage signal VMV3 to a value lower than the voltage vhv of the voltage signal VHV. As a result, the risk of excessive voltage being applied to circuit elements provided in the propagation path of the drive signal COM based on the voltage signal VMV3 is further reduced, thereby further improving the reliability of the liquid ejection device 1 including the drive circuit 50.

[0107] As described above, the boost voltage limiting circuit 800 includes the voltage drop limiting circuit 810 and the voltage increase limiting circuit 820.

[0108] The voltage drop limiting circuit 810 includes a zener diode 812, a resistor 813, and a transistor 811. The zener diode 812 has a cathode terminal electrically connected to the wiring Wvm2 and an anode terminal electrically connected to one end of the resistor 813. The other end of the resistor 813 is electrically connected to the wiring Wbst. The transistor 811 has a base terminal electrically connected to the anode terminal of the zener diode 812 and one end of the resistor 813, a collector terminal electrically connected to the wiring Wvm2, and an emitter terminal electrically connected to the wiring Wbst. The voltage drop limiting circuit 810 establishes conduction between the wiring Wvm2 and the wiring Wbst when the potential of the wiring Wvm2 is greater than the potential of the wiring Wbst and the potential difference between the wiring Wvm2 and the wiring Wbst is greater than the threshold voltage vtz1.

[0109] The voltage rise limiting circuit 820 also includes a zener diode 822, a resistor 823, and a transistor 821. The zener diode 822 has a cathode terminal electrically connected to the wiring Wbst and an anode terminal electrically connected to one end of the resistor 823. The resistor 823 has another end electrically connected to the wiring Wvm2. The transistor 821 has a base terminal electrically connected to the anode terminal of the zener diode 822 and one end of the resistor 823, a collector terminal electrically connected to the wiring Wbst, and an emitter terminal electrically connected to the wiring Wvm2. The voltage rise limiting circuit 820 establishes conduction between the wiring Wvm2 and the wiring Wbst when the potential of the wiring Wvm2 is lower than the potential of the wiring Wbst and the potential difference between the wiring Wvm2 and the wiring Wbst is greater than a threshold voltage vtz2.

[0110] That is, the boost voltage limiting circuit 800 included in the drive circuit 50 of the liquid ejection device 1 of this embodiment is electrically connected to the wiring Wvm2 and the wiring Wbst. The boost voltage limiting circuit 800 switches the conduction state between the wiring Wvm2 and the wiring Wbst according to the potential differences ΔVlow, ΔVhi between the voltage values ​​of the wiring Wvm2 and the wiring Wbst.

[0111] The piezoelectric element 60 is an example of a capacitive load, and the drive circuit 50 that outputs the drive signal COM that drives the piezoelectric element 60 corresponds to a capacitive load drive circuit. The D / A conversion circuit 510 is an example of a DA conversion circuit, the pulse modulation circuit 520 is an example of a modulation circuit, the amplifier circuit 550 is an example of a first digital amplifier circuit, the demodulation circuit 560 is an example of a smoothing circuit, the level shift circuit 750 is an example of a second digital amplifier circuit, the boost circuit 760 is an example of a bootstrap circuit, and the boost voltage limiting circuit 800 is an example of a voltage limiting circuit. The capacitor C13 is an example of a capacitor element, the diode D13 is an example of a diode element, the voltage regulator diode 812 is an example of a first Zener diode, the voltage regulator diode 822 is an example of a second Zener diode, the resistor 813 is an example of a first resistor element, the resistor 823 is an example of a second resistor element, the transistor 811 is an example of a first transistor, and the transistor 821 is an example of a second transistor. Furthermore, the ground signal GND is an example of a first voltage signal, the ground potential gnd is an example of a first potential, the voltage signal VMV1 is an example of a second voltage signal, the voltage vmv1 is an example of a second potential, the voltage signal VMV2 is an example of a third voltage signal, and the voltage vmv3 is an example of a third potential. Furthermore, the first amplified modulation signal AMS1 is an example of a first amplified signal, the second amplified modulation signal AMS2 is an example of a second amplified signal, the voltage signal VMV3 is an example of a boot voltage signal, and the reference drive signal aA is an example of an analog reference drive signal. Furthermore, the wiring Wgnd is an example of a first propagation node, the wiring Wvm1 is an example of a second propagation node, the wiring Wvm2 is an example of a third propagation node, the wiring Wam1 is an example of a first output node, the wiring Wbst is an example of a second output node, and the wiring Wam2 is an example of a third output node. Furthermore, the threshold voltage vtz1 is an example of a first threshold, and the threshold voltage vtz2 is an example of a second threshold.

[0112] 4. Effects As described above, in the liquid ejection device 1 of this embodiment, the amplifier circuit 550 in the drive circuit 50 generates the first amplified modulated signal AMS1 by amplifying the modulated signal MS through the switching operation of transistors M1 and M2. The level shift circuit 750 outputs the first amplified modulated signal AMS1 or a signal obtained by shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 via transistors M3 and M4 in accordance with the potential of the level switching signal LS. The demodulation circuit 560 demodulates the second amplified modulated signal AMS2 to output the drive signal COM. This reduces the voltage values ​​of the voltage signals VMV1 and VMV2 relative to the voltage value of the drive signal COM output by the drive circuit 50. As a result, the on-resistance of the transistors M1, M2, M3, and M4 can be reduced, thereby reducing the switching loss occurring in each of the transistors M1, M2, M3, and M4. As a result, the power consumption of the drive circuit 50 can be reduced.

[0113] Furthermore, in the liquid ejection device 1 of this embodiment, the boost voltage limiting circuit 800 included in the drive circuit 50 is electrically connected to the wiring Wvm2 and the wiring Wbst and switches the conduction state between the wiring Wvm2 and the wiring Wbst in response to the potential differences ΔVlow and ΔVhi between the voltage values ​​of the wiring Wvm2 and the wiring Wbst. This allows the voltage value across the capacitor C13 included in the boost circuit 760 electrically connected to the wiring Wbst to be limited based on the voltage vmv2, which is the voltage value of the voltage signal VMV2 propagating through the wiring Wvm2, even if the voltage value across the capacitor C13 fluctuates due to unintended charge accumulation or discharge. As a result, the signal accuracy of the second amplified modulation signal AMS2 output from the level shift circuit 750 electrically connected to the wiring Wbst is improved. This improvement in the signal accuracy of the second amplified modulation signal AMS2 also improves the signal accuracy of the drive signal COM, which is obtained by smoothing the second amplified modulation signal AMS2. That is, the risk of distortion occurring in the signal waveform of the drive signal COM output by the drive circuit 50 is reduced.

[0114] Furthermore, in the drive circuit 50 of the liquid ejection device 1 of this embodiment, the boost voltage limiting circuit 800 has a voltage drop limiting circuit 810 that brings the lines Wvm2 and Wbst into conduction when the potential of the line Wvm2 is greater than the potential of the line Wbst and the potential difference between the lines Wvm2 and Wbst is greater than the threshold voltage vtz1, and a voltage rise limiting circuit 820 that brings the lines Wvm2 and Wbst into conduction when the potential of the line Wvm2 is less than the potential of the line Wbst and the potential difference between the lines Wvm2 and Wbst is greater than the threshold voltage vtz2. As a result, the voltage value across the capacitor C13 is limited to a predetermined voltage range by the voltage drop limiting circuit 810 and the voltage rise limiting circuit 820. As a result, the signal accuracy of the second amplified modulated signal AMS2 output from the level shift circuit 750 electrically connected to the wiring Wbst is further improved, and with this further improvement in the signal accuracy of the second amplified modulated signal AMS2, the signal accuracy of the drive signal COM obtained by smoothing the second amplified modulated signal AMS2 is also further improved. In other words, the risk of distortion occurring in the signal waveform of the drive signal COM output by the drive circuit 50 is further reduced.

[0115] 5. Variations In the liquid ejection device 1 described above, the boost voltage limiting circuit 800 possessed by the drive circuit 50 has been described as having a voltage drop limiting circuit 810, a voltage rise limiting circuit 820, and a voltage rise protection circuit 830, but the boost voltage limiting circuit 800 possessed by the drive circuit 50 only needs to have at least one of the voltage drop limiting circuit 810 and the voltage rise limiting circuit 820, and even in this case, the risk of distortion occurring in the signal waveform of the drive signal COM output by the drive circuit 50 can be reduced.

[0116] Furthermore, in the liquid ejection device 1 described above, the boost voltage limiting circuit 800 included in the drive circuit 50 may include a voltage rise protection circuit 840 instead of the voltage rise protection circuit 830, as shown in Fig. 13. Fig. 13 is a diagram showing an example of the configuration of a modified boost voltage limiting circuit 800.

[0117] The voltage rise protection circuit 840 includes a constant voltage diode 841 and a resistor 842. The cathode terminal of the constant voltage diode 841 is electrically connected to the wiring Wbst, and the anode terminal of the constant voltage diode 841 is electrically connected to one end of the resistor 842. The other end of the resistor 842 is electrically connected to the wiring Wam1.

[0118] In the voltage rise protection circuit 840 configured as described above, when the potential difference ΔVbst between the voltage value of the line Wbst and the voltage value of the line Wam1, and the voltage value across the capacitor C13, exceeds a threshold voltage vtz3 defined by the Zener voltage vzd3 of the voltage regulator diode 841 and the resistance value of the resistor 842, a current corresponding to the difference between the potential difference ΔVbst and the threshold voltage vtz3 flows through the line Wam1 via the voltage regulator diode 841 and the resistor 842. This causes the charge stored in the capacitor C13 electrically connected to the line Wbst to be released to the line Wam1. As a result, the voltage value of the voltage signal VMV3 on the line Wbst is limited based on the voltage value of the first amplified modulation signal AMS1 propagating through the line Wam1 and the threshold voltage vtz3.

[0119] In this case, the value of the threshold voltage vtz3, which is determined by the Zener voltage vzd3 of the constant voltage diode 841 and the resistance value of the resistor 842, is preferably set so that the sum of the voltage vmv1 and the threshold voltage vtz2 is smaller than the voltage vhv of the voltage signal VHV. This causes the voltage increase limiting circuit 820 to limit the voltage of the voltage signal VMV3 to a value lower than the voltage vhv of the voltage signal VHV. As a result, the risk of excessive voltage being applied to circuit elements provided in the propagation path of the drive signal COM based on the voltage signal VMV3 is further reduced, thereby further improving the reliability of the liquid ejection device 1 including the drive circuit 50.

[0120] Even if the boost voltage limiting circuit 800 of the drive circuit 50 has a voltage rise protection circuit 840 as shown in FIG. 13 instead of or in addition to the voltage rise protection circuit 830 shown in FIG. 12, the same effects as those of the above-described embodiment can be achieved.

[0121] Although the embodiments have been described above, the present invention is not limited to these embodiments and can be embodied in various forms without departing from the spirit of the present invention. For example, the above embodiments and modifications can be combined as appropriate.

[0122] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0123] The following can be derived from the above-described embodiment.

[0124] One aspect of the capacitive load drive circuit is A capacitive load drive circuit that outputs a drive signal for driving a capacitive load, a first digital amplifier circuit electrically connected to a first propagation node through which a first voltage signal of a first potential propagates and a second propagation node through which a second voltage signal of a second potential propagates, and which outputs a first amplified signal to a first output node; a bootstrap circuit electrically connected to a third propagation node through which a third voltage signal of a third potential propagates and the first output node, and configured to output a boot voltage signal to a second output node; a second digital amplifier circuit connected to the first output node and the second output node and outputting a second amplified signal to a third output node; a smoothing circuit that smoothes the second amplified signal and outputs the smoothed signal as the drive signal; a voltage limiting circuit electrically connected to the third propagation node and the second output node, and configured to switch a conduction state between the third propagation node and the second output node; Equipped with the bootstrap circuit includes a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node, and a diode element having an anode terminal electrically connected to the third propagation node and a cathode terminal electrically connected to the second output node; The voltage limiting circuit switches the conduction state between the third propagation node and the second output node in accordance with the potential difference between the third propagation node and the second output node.

[0125] In this capacitive load drive circuit, the voltage limiting circuit switches the conduction state between the third propagation node and the second output node in accordance with the potential difference between the third propagation node and the second output node. Even if the voltage value of the boot voltage signal output from the bootstrap circuit to the second output node increases or decreases, the voltage value of the boot voltage signal is limited by the third voltage signal at the third potential propagating through the third propagation node. This improves the signal accuracy of the second amplified signal output to the third output node by the second digital amplifier circuit connected to the first output node and the second output node. As a result, the smoothing circuit smooths the second amplified signal, reducing the risk of distortion in the waveform of the drive signal to be output.

[0126] In one aspect of the capacitive load drive circuit, When the potential of the third propagation node is greater than the potential of the second output node and the potential difference between the third propagation node and the second output node is greater than a first threshold, the voltage limiting circuit may establish conduction between the third propagation node and the second output node.

[0127] In this capacitive load drive circuit, even if the voltage value of the boot voltage signal output from the bootstrap circuit to the second output node drops, the voltage limiting circuit limits the voltage value of the boot voltage signal by the third voltage signal at the third potential propagating through the third propagation node. This improves the signal accuracy of the second amplified signal output from the second digital amplifier circuit connected to the first output node and the second output node, and reduces the risk of distortion in the signal waveform of the drive signal output by the smoothing circuit after smoothing the second amplified signal.

[0128] In one aspect of the capacitive load drive circuit, the voltage limiting circuit includes a first Zener diode, a first resistor, and a first transistor; the first Zener diode has a cathode terminal electrically connected to the third propagation node and an anode terminal electrically connected to one end of the first resistor element; the other end of the first resistor element is electrically connected to the second output node; The first transistor may have a base terminal electrically connected to an anode terminal of the first Zener diode and one end of the first resistor element, a collector terminal electrically connected to the third propagation node, and an emitter terminal electrically connected to the second output node.

[0129] In one aspect of the capacitive load drive circuit, the potential of the third propagation node is lower than the potential of the second output node; When a potential difference between the third propagation node and the second output node is greater than a second threshold, the voltage limiting circuit may bring the third propagation node and the second output node into conduction.

[0130] In this capacitive load drive circuit, even if the voltage value of the boot voltage signal output from the bootstrap circuit to the second output node rises, the voltage limiting circuit limits the voltage value of the boot voltage signal by the third voltage signal at the third potential propagating through the third propagation node. This improves the signal accuracy of the second amplified signal output from the second digital amplifier circuit connected to the first output node and the second output node, and reduces the risk of distortion in the signal waveform of the drive signal output by the smoothing circuit after smoothing the second amplified signal.

[0131] In one aspect of the capacitive load drive circuit, the voltage limiting circuit includes a second Zener diode, a second resistor, and a second transistor; the second Zener diode has a cathode terminal electrically connected to the second output node and an anode terminal electrically connected to one end of the second resistor element; the second resistor element has the other end electrically connected to the third propagation node; The second transistor may have a base terminal electrically connected to an anode terminal of the second Zener diode and one end of the second resistive element, a collector terminal electrically connected to the second output node, and an emitter terminal electrically connected to the third propagation node.

[0132] In one aspect of the capacitive load drive circuit, a DA conversion circuit that converts a base drive signal that is the basis of the drive signal into an analog base drive signal; a modulation circuit that modulates the analog base drive signal and outputs a modulated signal; a level switching signal output circuit that outputs a level switching signal based on the basic drive signal; Equipped with the first digital amplifier circuit amplifies the modulated signal based on the first potential and the second potential and outputs the first amplified signal; The second digital amplifier circuit may select, in response to the level switching signal, a signal in which the reference potential of the first amplified signal is shifted based on the third potential, or a signal in which the reference potential of the first amplified signal is not shifted, and output the selected signal as the second amplified signal.

[0133] In this capacitive load drive circuit, the first digital amplifier circuit outputs a first amplified signal obtained by amplifying a modulated signal based on a first potential and a second potential, and the second digital amplifier circuit selects, in response to a level switching signal, either a signal obtained by shifting the reference potential of the first amplified signal based on a third potential or a signal obtained by not shifting the reference potential of the first amplified signal, and outputs the selected signal as the second amplified signal. This reduces the withstand voltage of the transistor elements included in the first digital amplifier circuit and the second digital amplifier circuit, thereby reducing the on-resistance of the transistor elements included in the first digital amplifier circuit and the second digital amplifier circuit and reducing losses in the transistor elements. As a result, power consumption in the capacitive load drive circuit is reduced.

[0134] One aspect of the liquid ejection device is a discharge unit that discharges liquid by driving a capacitive load; a capacitive load drive circuit that outputs a drive signal for driving the capacitive load; Equipped with The capacitive load drive circuit comprises: a first digital amplifier circuit electrically connected to a first propagation node through which a first voltage signal of a first potential propagates and a second propagation node through which a second voltage signal of a second potential propagates, and which outputs a first amplified signal to a first output node; a bootstrap circuit electrically connected to a third propagation node through which a third voltage signal of a third potential propagates and the first output node, and configured to output a boot voltage signal to a second output node; a second digital amplifier circuit connected to the first output node and the second output node and outputting a second amplified signal to a third output node; a smoothing circuit that smoothes the second amplified signal and outputs the smoothed signal as the drive signal; a voltage limiting circuit electrically connected to the third propagation node and the second output node, and configured to switch a conduction state between the third propagation node and the second output node; and the bootstrap circuit includes a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node, and a diode element having an anode terminal electrically connected to the third propagation node and a cathode terminal electrically connected to the second output node; The voltage limiting circuit switches the conduction state between the third propagation node and the second output node in accordance with the potential difference between the third propagation node and the second output node.

[0135] In this liquid ejection device, the voltage limiting circuit of the capacitive load drive circuit switches the conduction state between the third propagation node and the second output node in accordance with the potential difference between the third propagation node and the second output node. Even if the voltage value of the boot voltage signal output from the bootstrap circuit to the second output node increases or decreases, the voltage value of the boot voltage signal is limited by the third voltage signal at the third potential propagating through the third propagation node. This improves the signal accuracy of the second amplified signal output to the third output node by the second digital amplifier circuit connected to the first output node and the second output node. As a result, the smoothing circuit smooths the second amplified signal, reducing the risk of distortion in the waveform of the drive signal to be output.

[0136] In one aspect of the liquid ejection device, When the potential of the third propagation node is greater than the potential of the second output node and the potential difference between the third propagation node and the second output node is greater than a first threshold, the voltage limiting circuit may establish conduction between the third propagation node and the second output node.

[0137] In this liquid ejection device, even if the voltage value of the boot voltage signal output from the bootstrap circuit of the capacitive load drive circuit to the second output node drops, the voltage limiting circuit limits the voltage value of the boot voltage signal by the third voltage signal at the third potential propagating through the third propagation node. Therefore, the signal accuracy of the second amplified signal output from the second digital amplifier circuit connected to the first output node and the second output node is improved, and the smoothing circuit smooths the second amplified signal, reducing the risk of distortion in the signal waveform of the drive signal to be output.

[0138] In one aspect of the liquid ejection device, the voltage limiting circuit includes a first Zener diode, a first resistor, and a first transistor; the first Zener diode has a cathode terminal electrically connected to the third propagation node and an anode terminal electrically connected to one end of the first resistor element; the other end of the first resistor element is electrically connected to the second output node; The first transistor may have a base terminal electrically connected to an anode terminal of the first Zener diode and one end of the first resistor element, a collector terminal electrically connected to the third propagation node, and an emitter terminal electrically connected to the second output node.

[0139] In one aspect of the liquid ejection device, the potential of the third propagation node is lower than the potential of the second output node; When a potential difference between the third propagation node and the second output node is greater than a second threshold, the voltage limiting circuit may bring the third propagation node and the second output node into conduction.

[0140] In this liquid ejection device, even if the voltage value of the boot voltage signal output from the bootstrap circuit of the capacitive load drive circuit to the second output node rises, the voltage limiting circuit limits the voltage value of the boot voltage signal by the third voltage signal at the third potential propagating through the third propagation node. Therefore, the signal accuracy of the second amplified signal output from the second digital amplifier circuit connected to the first output node and the second output node is improved, and the smoothing circuit smooths the second amplified signal, reducing the risk of distortion in the signal waveform of the drive signal to be output.

[0141] In one aspect of the liquid ejection device, the voltage limiting circuit includes a second Zener diode, a second resistor, and a second transistor; the second Zener diode has a cathode terminal electrically connected to the second output node and an anode terminal electrically connected to one end of the second resistor element; the second resistor element has the other end electrically connected to the third propagation node; The second transistor may have a base terminal electrically connected to an anode terminal of the second Zener diode and one end of the second resistive element, a collector terminal electrically connected to the second output node, and an emitter terminal electrically connected to the third propagation node.

[0142] In one aspect of the liquid ejection device, a DA conversion circuit that converts a base drive signal that is the basis of the drive signal into an analog base drive signal; a modulation circuit that modulates the analog base drive signal and outputs a modulated signal; a level switching signal output circuit that outputs a level switching signal based on the basic drive signal; Equipped with the first digital amplifier circuit amplifies the modulated signal based on the first potential and the second potential and outputs the first amplified signal; The second digital amplifier circuit may select, in response to the level switching signal, a signal in which the reference potential of the first amplified signal is shifted based on the third potential, or a signal in which the reference potential of the first amplified signal is not shifted, and output the selected signal as the second amplified signal.

[0143] In this liquid ejection device, the first digital amplifier circuit included in the capacitive load drive circuit outputs a first amplified signal obtained by amplifying a modulated signal based on a first potential and a second potential, and the second digital amplifier circuit selects, in response to a level switching signal, either a signal obtained by shifting the reference potential of the first amplified signal based on a third potential or a signal obtained by not shifting the reference potential of the first amplified signal, and outputs the selected signal as the second amplified signal. This reduces the withstand voltage of the transistor elements included in the first digital amplifier circuit and the second digital amplifier circuit, thereby reducing the on-resistance of the transistor elements included in the first digital amplifier circuit and the second digital amplifier circuit and reducing losses in the transistor elements. As a result, power consumption in the capacitive load drive circuit and therefore power consumption of the liquid ejection device are reduced. [Explanation of symbols]

[0144] 1...liquid ejection device, 2...moving body, 3...moving unit, 4...transport unit, 10...control unit, 11...power supply circuit, 13...capacitor, 20...head unit, 21...liquid ejection head, 24...carriage, 31...carriage motor, 32...carriage guide shaft, 33...timing belt, 40...platen, 41...transport motor, 42...transport roller, 50...drive circuit, 60...piezoelectric element, 100...control circuit, 190...cable, 2 10...Selection control unit, 230...Selection unit, 510...D / A conversion circuit, 511...Adder, 520...Pulse modulation circuit, 521...Inverter, 530...Gate drive circuit, 531, 532...Gate driver, 550...Amplification circuit, 560...Demodulation circuit, 561...Inductor, 562...Capacitor, 570...Feedback circuit, 600...Discharge unit, 601...Piezoelectric body, 611, 612...Electrode, 621...Vibration plate, 631...Cavity, 632...Nozzle plug Rate, 641... reservoir, 651... nozzle, 710... level switching signal output circuit, 721... inverter, 730... gate drive circuit, 731, 732... gate driver, 750... level shift circuit, 760... boost circuit, 800... boost voltage limiting circuit, 810... voltage drop limiting circuit, 811... transistor, 812... constant voltage diode, 813... resistor, 820... voltage rise limiting circuit, 821... transistor, 822... constant Voltage diode, 823...resistor, 830...voltage rise protection circuit, 831...diode, 840...voltage rise protection circuit, 841...regulator diode, 842...resistor, C1, C11 to C13...capacitors, D1, D11 to D13...diodes, L...nozzle array, M1 to M4...transistors, OP1...first output point, OP2...second output point, P...medium, Wam1, Wam2, Wbst, Wcom, Wgnd, Wvgd, Wvm1, Wvm2...wiring

Claims

1. A capacitive load drive circuit that outputs a drive signal for driving a capacitive load, a first digital amplifier circuit electrically connected to a first propagation node through which a first voltage signal of a first potential propagates and a second propagation node through which a second voltage signal of a second potential propagates, and which outputs a first amplified signal to a first output node; a bootstrap circuit electrically connected to a third propagation node through which a third voltage signal of a third potential propagates and the first output node, and configured to output a boot voltage signal to a second output node; a second digital amplifier circuit connected to the first output node and the second output node and outputting a second amplified signal to a third output node; a smoothing circuit that smoothes the second amplified signal and outputs the smoothed signal as the drive signal; a voltage limiting circuit electrically connected to the third propagation node and the second output node, and configured to switch a conduction state between the third propagation node and the second output node; Equipped with the bootstrap circuit includes a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node, and a diode element having an anode terminal electrically connected to the third propagation node and a cathode terminal electrically connected to the second output node, the voltage limiting circuit switches the conduction state between the third propagation node and the second output node in accordance with a potential difference between the third propagation node and the second output node; A capacitive load driving circuit comprising:

2. when a potential of the third propagation node is greater than a potential of the second output node and a potential difference between the third propagation node and the second output node is greater than a first threshold, the voltage limiting circuit brings the third propagation node and the second output node into conduction; 2. The capacitive load driving circuit according to claim 1, wherein:

3. the voltage limiting circuit includes a first Zener diode, a first resistor, and a first transistor; a cathode terminal of the first Zener diode electrically connected to the third propagation node and an anode terminal of the first Zener diode electrically connected to one end of the first resistor element; the other end of the first resistor element is electrically connected to the second output node; the first transistor has a base terminal electrically connected to an anode terminal of the first Zener diode and one end of the first resistor element, a collector terminal electrically connected to the third propagation node, and an emitter terminal electrically connected to the second output node; 3. The capacitive load driving circuit according to claim 2, wherein:

4. the potential of the third propagation node is lower than the potential of the second output node; When a potential difference between the third propagation node and the second output node is greater than a second threshold, the voltage limiting circuit brings the third propagation node and the second output node into conduction.

4. The capacitive load driving circuit according to claim 1, wherein the capacitive load driving circuit comprises: a first input terminal for inputting a voltage to the first capacitive load;

5. the voltage limiting circuit includes a second Zener diode, a second resistor, and a second transistor; the second Zener diode has a cathode terminal electrically connected to the second output node and an anode terminal electrically connected to one end of the second resistor element; the second resistance element has the other end electrically connected to the third propagation node; the second transistor has a base terminal electrically connected to an anode terminal of the second Zener diode and one end of the second resistor element, a collector terminal electrically connected to the second output node, and an emitter terminal electrically connected to the third propagation node; 5. The capacitive load driving circuit according to claim 4.

6. a DA conversion circuit that converts a base drive signal that is the basis of the drive signal into an analog base drive signal; a modulation circuit that modulates the analog base drive signal and outputs a modulated signal; a level switching signal output circuit that outputs a level switching signal based on the basic drive signal; Equipped with the first digital amplifier circuit amplifies the modulated signal based on the first potential and the second potential and outputs the first amplified signal; the second digital amplifier circuit selects, in response to the level switching signal, a signal in which the reference potential of the first amplified signal is shifted based on the third potential, or a signal in which the reference potential of the first amplified signal is not shifted, and outputs the selected signal as the second amplified signal.

2. The capacitive load driving circuit according to claim 1, wherein:

7. a discharge unit that discharges liquid by driving a capacitive load; a capacitive load drive circuit that outputs a drive signal for driving the capacitive load; Equipped with The capacitive load drive circuit comprises: a first digital amplifier circuit electrically connected to a first propagation node through which a first voltage signal of a first potential propagates and a second propagation node through which a second voltage signal of a second potential propagates, and which outputs a first amplified signal to a first output node; a bootstrap circuit electrically connected to a third propagation node through which a third voltage signal of a third potential propagates and the first output node, and configured to output a boot voltage signal to a second output node; a second digital amplifier circuit connected to the first output node and the second output node and outputting a second amplified signal to a third output node; a smoothing circuit that smoothes the second amplified signal and outputs the smoothed signal as the drive signal; a voltage limiting circuit electrically connected to the third propagation node and the second output node, and configured to switch a conduction state between the third propagation node and the second output node; and the bootstrap circuit includes a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node, and a diode element having an anode terminal electrically connected to the third propagation node and a cathode terminal electrically connected to the second output node, the voltage limiting circuit switches the conduction state between the third propagation node and the second output node in accordance with a potential difference between the third propagation node and the second output node; A liquid ejection device characterized by:

8. when a potential of the third propagation node is greater than a potential of the second output node and a potential difference between the third propagation node and the second output node is greater than a first threshold, the voltage limiting circuit brings the third propagation node and the second output node into conduction; 8. The liquid ejection device according to claim 7.

9. the voltage limiting circuit includes a first Zener diode, a first resistor, and a first transistor; a cathode terminal of the first Zener diode electrically connected to the third propagation node and an anode terminal of the first Zener diode electrically connected to one end of the first resistor element; the other end of the first resistor element is electrically connected to the second output node; the first transistor has a base terminal electrically connected to an anode terminal of the first Zener diode and one end of the first resistor element, a collector terminal electrically connected to the third propagation node, and an emitter terminal electrically connected to the second output node; 9. The liquid ejection device according to claim 8.

10. the potential of the third propagation node is lower than the potential of the second output node; When a potential difference between the third propagation node and the second output node is greater than a second threshold, the voltage limiting circuit brings the third propagation node and the second output node into conduction.

10. The liquid ejection device according to claim 7, wherein the ejection head is a nozzle.

11. the voltage limiting circuit includes a second Zener diode, a second resistor, and a second transistor; the second Zener diode has a cathode terminal electrically connected to the second output node and an anode terminal electrically connected to one end of the second resistor element; the second resistance element has the other end electrically connected to the third propagation node; the second transistor has a base terminal electrically connected to an anode terminal of the second Zener diode and one end of the second resistor element, a collector terminal electrically connected to the second output node, and an emitter terminal electrically connected to the third propagation node; The liquid ejection device according to claim 10 .

12. a DA conversion circuit that converts a base drive signal that is the basis of the drive signal into an analog base drive signal; a modulation circuit that modulates the analog base drive signal and outputs a modulated signal; a level switching signal output circuit that outputs a level switching signal based on the basic drive signal; Equipped with the first digital amplifier circuit amplifies the modulated signal based on the first potential and the second potential and outputs the first amplified signal; the second digital amplifier circuit selects, in response to the level switching signal, a signal in which the reference potential of the first amplified signal is shifted based on the third potential, or a signal in which the reference potential of the first amplified signal is not shifted, and outputs the selected signal as the second amplified signal.

8. The liquid ejection device according to claim 7.

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