Testing and measuring instrument, method therefor, interface trap capacitance deriving method, and testing and measuring system

Abstract

To derive a quasistatic (DC) capacitance of high power devices.SOLUTION: A source measure unit 102 includes: a current source 108 for outputting a constant current to a device under test (DUT) 104; and a voltmeter 110 for detecting a voltage of the DUT 104. The voltmeter 110 measures a first set of voltages over time while the current source 108 outputs a first current to the DUT 104, measures a second set of voltages over time while the current source 108 outputs to the DUT 104 a second current having a different polarity from the first current, and measures a third set of voltages over time while the current source 108 outputs to the DUT 104 a third current having the same polarity as the first current. In addition, the source measure unit 102 includes a controller 106 for deriving an electrostatic capacitance of the DUT 104 based on the second and the third current.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to test and measurement techniques, and more particularly to test and measurement techniques for power devices. [Background technology]

[0002] Capacitance-voltage (CV) measurements are used in the analysis of semiconductor materials and the fabrication of semiconductor devices. CV is particularly useful for characterizing metal-oxide-semiconductor (MOS) devices. Many MOS device characteristics can be derived from CV data, including oxide mobile charge, oxide capacitance, interface traps, doping profile, flat-band voltage, doping concentration, minority carrier lifetime, and input / output capacitance.

[0003] For most semiconductor CV measurements, high frequencies (typically 100 kHz to 1 MHz) are used. However, some CV measurements require low-frequency or quasi-static techniques. This is the case for interface trap density (DIT) measurements on MOS capacitors (MOScap), where quasi-static CV allows for the detection of interface traps. At high frequencies, interface traps cannot change state quickly enough to contribute to the capacitance of the device. As a result, both high- and low-frequency measurements are required to determine the number of trapped charges. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-134403 [Patent Document 2] Japanese Patent Application Laid-Open No. 2023-138490 [Non-patent literature]

[0005] [Non-Patent Document 1] "Keithley Source Measure Unit," Tektronix / Keithley, [Online], [Retrieved March 5, 2025], Internet<https: / / www.tek.com / ja / products / keithley / source-measure-units> Summary of the Invention [Problem to be solved by the invention]

[0006] Available quasi-static CV solutions typically involve forcing a voltage and measuring a current using a source measure unit (SMU). For example, the ramp rate technique or very low-frequency capacitance-voltage technique used by SMUs for CV measurements uses current measurements to obtain the capacitance of the device under test (DUT). These techniques are effective for conventional silicon MOS devices. However, for high-power devices such as SiC MOS devices, large capacitances can make these techniques difficult to use, potentially resulting in unstable results. The stability of the SMU's feedback ammeter is often specified based on the load capacitance or source impedance. Depending on the SMU model, the SMU's ammeter may not stabilize even with capacitances of several hundred picofarads.

[0007] Therefore, what is needed is a way to obtain the quasi-static (DC) capacitance of high-power devices using an SMU. [Means for solving the problem]

[0008] This disclosure describes a process for deriving quasistatic capacitance using a source measure unit (SMU) by measuring voltage instead of current, because voltage measurements are stable with capacitive loads. This disclosure describes a quasistatic capacitance-voltage (QSCV) measurement technique that involves forcing a constant current through the gate terminal of a device under test (DUT), such as a power device or metal-oxide semiconductor field-effect transistor (MOSFET), and measuring the voltage as a function of time to derive capacitance. Some advantages of using the technique described in this application with power devices include: requiring only one SMU with a preamplifier, as opposed to two SMUs for other methods; forcing current is faster than forcing voltage; forcing a constant DC current through the DUT allows for steady state, unlike stepping a voltage; avoiding instability issues by measuring voltage when deriving capacitance using the device in low output impedance mode; performing open circuit compensation; and correcting for leakage current. Operates with large capacitances above 20pF.

[0009] The present disclosure includes processes forcing a positive current to preset and charge the DUT, reversing the current to negative, and then reversing the current to positive. After collecting CV data (capacitance-voltage measurements over time), the leakage current measurements are used to improve charge calculations for high-leakage devices.

[0010] The foregoing brief summary will now be particularly described to provide a detailed understanding of the above-described features by reference to exemplary implementations, some of which are illustrated in the accompanying drawings, which illustrate, with the understanding that the accompanying drawings depict only examples of typical implementations and are not intended to limit the scope of the claims.

[0011] To facilitate understanding, the same reference numerals have been used, whenever possible, to designate identical elements that are common to multiple figures, and it is contemplated that elements of one embodiment may be advantageously incorporated into other embodiments. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 illustrates a device under test (DUT) coupled to a source measure unit (SMU) for deriving quasi-static capacitance-voltage (CV) characteristics, according to some embodiments. [Figure 2] FIG. 2 illustrates a graph of current versus time generated by an SMU and voltage versus time across the terminals of the SMU, according to some embodiments. [Figure 3] FIG. 3 illustrates a leakage current measurement circuit with circuitry representing an SMU and a DUT, according to some embodiments. [Figure 4A] FIG. 4A is a graph showing voltage versus time for a DUT using the quasi-static capacitance-voltage technique described herein, according to some embodiments. [Figure 4B] FIG. 4B is a graph showing forward and reverse CV curves obtained from the quasi-static capacitance-voltage technique described herein, according to some embodiments. [Figure 5] FIG. 5 is a flowchart of the operation of an SMU to determine the capacitance of a DUT, according to some embodiments. [Figure 6] FIG. 6 illustrates an SMU connected to a silicon carbide (SiC) MOS (metal oxide semiconductor) DUT, showing the circuit potentials, according to some embodiments. [Figure 7] FIG. 7 is a graph of forward and reverse capacitance curves as a function of surface potential using a quasi-static capacitance-voltage technique according to some embodiments. [Figure 8] FIG. 8 is a graph illustrating forward and reverse capacitance curves with oxide capacitance removed as a function of surface potential based on a quasi-static capacitance-voltage technique according to some embodiments. [Figure 9]FIG. 9 shows a plot of interface trap density (DIT) as a function of surface potential (Vs) based on the use of quasi-static capacitance-voltage techniques according to some embodiments. [Figure 10] FIG. 10 is a flow chart for deriving interface trap capacitance using a quasi-static capacitance-voltage technique according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0013] FIG. 1 illustrates a circuit diagram of a DUT coupled to an SMU for deriving quasi-static CV characteristics of the DUT, according to some embodiments. As shown in FIG. 1, circuit 100 includes an SMU 102 coupled to a DUT 104. Specifically, DUT 104 is a power MOSFET having a gate terminal, a drain terminal, and a source terminal, as illustrated in FIG. 1. Thus, in the example shown in FIG. 1, the Force HI terminal of SMU 102 is connected to the gate of DUT 104, and the Force LO terminal of SMU 102 is connected to the drain and source terminals of DUT 104, which are shorted together. In some embodiments, a single SMU can derive the quasi-static CV characteristics of a power MOSFET or capacitor. In the examples described herein, the SMU can source and measure current and voltage.

[0014] As shown in FIG. 1 , the SMU 102 includes a controller 106. The controller 106 of the SMU 102 includes firmware that controls the SMU 102. The SMU 102 includes a current source 108 and a voltmeter 110, and the controller 106 of the SMU 102 is configured to control the current source 108 and the voltmeter 110. In some embodiments, the controller 106 commands the current source 108 to generate a specific current to the DUT 104 and commands the voltmeter 110 to measure a voltage between the force HI terminal of the SMU 102 and the force LO terminal of the SMU 102 at a specific time. As used herein, the term “controller” refers to programmable circuitry. In this description, a controller may be referred to as a processor or programmable circuitry, which may include a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or any other type of controller capable of performing these functions.

[0015] In some embodiments, the circuit 100 includes a computing device 112 coupled to the SMU 102. In such examples, the SMU 102 provides voltage measurements to the computing device 112, which performs quasi-static CV calculations to determine the capacitance of the DUT 104. The computing device 112 transmits the capacitance of the DUT 104 to the SMU 102, allowing the SMU 102 to compensate for leakage current in the DUT 104. In other embodiments, the SMU 102 performs quasi-static CV calculations to determine the capacitance of the DUT 104. As used herein, the term "computing device" refers to programmable circuitry. In this description, a computing device may be referred to as a processor, controller, or programmable circuit, which may include a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or any other type of controller capable of performing these functions as described herein.

[0016] As described herein, the controller 106 of the SMU 102 derives the forward and reverse capacitance of the DUT 104 as a function of voltage and compensates for leakage current. To derive the capacitance, the SMU 102 is configured to force a current through the DUT 104 and measure the voltage across the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102 at a specific time. Forcing a constant current allows for precise control of the total charge delivered to the device (Q=I*dt). Using a constant current allows for a steady state of the device, unlike voltage steps, which can cause dynamic changes in the measurement equipment.

[0017] 2 includes a graph of current versus time generated by the current source 108 of the SMU 102 and a graph of the voltage of the DUT 104 measured by the voltmeter 110, as described herein. As shown, during time period T1, the SMU 102 forces a constant positive current (+I) using the current source 108 and measures the voltage (V) between the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102 versus time using the voltmeter 110 until the SMU 102 determines that the voltage measured by the voltmeter 110 has reached a first predetermined voltage level, VHigh. In some embodiments, the first predetermined voltage is a user-defined maximum voltage for the DUT 104. In some embodiments, the voltage measurements made during time period T1 are not used to measure capacitance.

[0018] After the SMU 102 determines that the voltage read by the voltmeter 110 has reached a first predetermined voltage level, during time period T2, the SMU 102 changes the polarity of the current source 108 so that the current source 108 forces a constant negative current (-I) through the DUT 104. During time period T2, the SMU 102 measures the voltage between the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102 using the voltmeter 110 until the SMU 102 determines that the voltage measured by the voltmeter has reached a second predetermined voltage level (VLow). In some embodiments, the second predetermined voltage is a user-defined minimum voltage for the DUT 104. The voltage measurement during time period T2 may be referred to as a reverse sweep.

[0019] After the SMU 102 determines that the voltage read by the voltmeter 110 has reached the first predetermined voltage level, during time period T3, the SMU 102 again changes the polarity of the current source 108 so that the current source 108 forces a constant positive current (+I) through the DUT 104. During time period T3, the SMU 102 uses the voltmeter 110 to measure the voltage (V) between the Force HI terminal of the voltmeter 102 and the Force LO terminal of the SMU 102 until the SMU 102 determines that the voltage measured by the voltmeter 110 has reached a third predetermined voltage level. In some embodiments, this predetermined voltage is a user-defined maximum voltage for the DUT 104. In a further example, the third predetermined voltage level may be the same as the first predetermined voltage level, VHigh. The voltage measurement during time period T3 may be referred to as a forward sweep.

[0020] In some embodiments, the SMU 102 may use a negative, positive, negative current sequence depending on the polarity of the force current, instead of the positive, negative, positive current sequence described above.

[0021] After the SMU 102 has sent various currents to the DUT 104 as described above, the SMU 102 collects voltage measurements from the DUT 104 and generates a voltage vs. capacitance curve. Because the SMU 102 has supplied both positive and negative currents to the DUT 104 and measured the voltages corresponding to both positive and negative currents, both forward and reverse CV curves can be obtained. The SMU 102 calculates the capacitance (Cm) of the DUT as follows:

number

number

[0022] FIG. 3 illustrates a leakage measurement circuit with an RC device representing the DUT, including all currents (within the dotted line) provided by the SMU's current sources, according to some embodiments of the present application. When performing direct current (DC) measurements as described herein, such as quasi-static CV derivations, the leakage resistance of the DUT 304 itself and the parasitic capacitance of the cables can contribute significant errors if not compensated for. The capacitance of the gate of the DUT 304, such as a power MOSFET or other capacitive device, can be modeled as a parallel RC circuit representing the DUT 304, as shown in FIG. 3. In this example, resistor R represents the leakage resistance of capacitor Cd. Additionally, capacitor Cp represents the parasitic capacitance of the cables and within circuit 300.

[0023] In some embodiments, the SMU 302 may include an ammeter 312 (controlled by the controller 306) used to measure current and a voltage source (not shown in FIG. 3 ) to generate voltage for the DUT 304. Thus, when measuring the leakage current of the DUT 304, the SMU 302 forces a voltage and measures the current because the leakage current is a function of the applied voltage. As shown in FIG. 3 , IR is the leakage current of the DUT 304, Id is the current due to the capacitance Cd of the DUT 304, which can be expressed as Id = Cd(dV / dt), and Ip is the current due to the parasitic capacitance Cp of the system / circuit 300, which can be expressed as Ip = Cp(dV / dt).

[0024] In this disclosure, the SMU 302 can measure and correct for unwanted currents (IR and Ip) by performing an IV sweep on the DUT 304 and subtracting out the unwanted currents. This voltage sweep uses actual measured voltage points based on constant forward and reverse current forcing. From this test, the forced current is:

number

[0025] The force current can also be written as:

number

number

[0026] So, combining these terms we get:

number

number

number

number

[0027] In the unprobed or other open circuit situation where the DUT is not coupled to the circuit and Cd is not present, what is measured is the parasitic capacitance (Cp), which is then subtracted from (Cp + Cd) to obtain a highly accurate leakage and parasitic corrected device capacitance.

[0028] FIG. 4A is a graph showing the voltage versus time between the Force HI terminal of SMU 102 and the Force LO terminal of SMU 102, and FIG. 4B is a graph showing the resulting forward and reverse CV curves corresponding to the voltage between the Force HI terminal of SMU 102 and the Force LO terminal of SMU 102, obtained from the quasi-static capacitance-voltage technique described herein. Specifically, the graph in FIG. 4B shows the resulting QSCV voltage versus forward and reverse capacitance measurements for a SiC power MOSFET. From these two curves, SMU 302 may enable other parameters, such as trapped charge, to be obtained.

[0029] 5 is a flowchart of the operation of an SMU to obtain the capacitance of a DUT as described herein. Process 500 is described with reference to circuit 100 of FIG. 1, but may also be implemented using circuit 300 of FIG. 3. In some embodiments, process 500 may be performed when DUT 104 is coupled to SMU 102.

[0030] Process 500 begins at step 502, which instructs a voltage sensor of the test and measurement instrument, such as the voltmeter of FIG. 1, to measure a first set of voltages over time while a current source of the SMU outputs a first constant current to the DUT. In some embodiments, the current source of the SMU outputs the first constant current to the DUT until the voltage sensor of the SMU determines that the voltage between the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102 reaches a first predetermined voltage threshold. In some embodiments, the first constant current to the DUT is a constant positive current, and by sending a constant positive current to the DUT, the SMU charges the DUT to the first predetermined voltage threshold. In further embodiments, the SMU tracks the time it takes for the DUT to reach the first predetermined voltage threshold. The first predetermined voltage threshold may be a user-defined maximum voltage for the DUT. In another embodiment, the first constant current to the DUT is a constant negative current, so that the SMU monitors (tracks) the time it takes for the DUT to reach a first predetermined voltage threshold (which may be a user-defined minimum voltage for the DUT).

[0031] In some embodiments, a controller of the SMU sends a command to a current source of the SMU to output a first positive current to the DUT.

[0032] Step 500 then proceeds to step 504, where the SMU's current source outputs a second constant current to the DUT while instructing the voltage sensor, e.g., voltmeter 110 of FIG. 1, to measure a second set of voltages over time. The second constant current has a different polarity than the first constant current to the DUT. For example, if the first constant current was a positive constant current, the second constant current is negative. Similarly, if the first constant current was a negative constant current, the second constant current is positive. In some embodiments, the SMU's current source outputs the second constant current to the DUT until the SMU's voltage sensor determines that the voltage between the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102 reaches a second predetermined voltage threshold. In some embodiments, the second constant current to the DUT is a constant negative current. By sending a negative current to the DUT, the SMU discharges the DUT, which is reflected in the voltage between the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102. In a further embodiment, the SMU monitors (tracks) the time it takes for the DUT to reach a second predetermined voltage threshold, which may be a user-defined minimum voltage for the DUT. In another embodiment, the second constant current to the DUT is a constant positive current, and therefore the SMU monitors (tracks) the time it takes for the DUT to reach a first predetermined voltage threshold (a user-defined maximum voltage for the DUT).

[0033] Next, process 500 proceeds to process 506, where the SMU's current source directs a voltage sensor to measure a third set of voltages over time while outputting a third constant current to the DUT. The third constant current has the same polarity as the first constant current to the DUT. For example, if the first constant current was a positive constant current, the third constant current will also be positive. Similarly, if the first constant current was a negative constant current, the third constant current will also be negative. In some embodiments, the SMU's current source outputs the third constant current to the DUT until the SMU's voltage sensor determines that the voltage between the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102 reaches a third predetermined voltage threshold. As described above, in some embodiments, the third constant current to the DUT is a constant positive current. By sending a positive current to the DUT, the SMU charges the DUT, which is reflected in the voltage between the Force HI terminal of the SMU 102 and the Force LO terminal of the SMU 102. In a further embodiment, the SMU monitors (tracks) the time it takes for the DUT to reach a third predetermined voltage threshold, which may be a user-defined maximum voltage and, in some embodiments, may be the same as the first predetermined voltage threshold. In other embodiments, the third constant current to the DUT is a constant negative current, and thus the SMU monitors (tracks) the time it takes for the DUT to reach a third predetermined voltage threshold, which may be a user-defined minimum voltage for the DUT.

[0034] Next, process 500 proceeds to step 508, where the capacitance of the DUT is derived based on the second and third constant currents and the second and third sets of voltages as a function of time. Step 508 includes determining the quasi-static voltage versus capacitance of the DUT based on the second and third sets of voltages over time. In some embodiments, step 508 includes collecting the voltage measurements collected in steps 504 and 506 and calculating the DUT capacitance (Cm) as follows:

number

number

[0035] Step 500 then proceeds to step 510, where device parameters of the DUT are determined based on the quasi-static capacitance of the DUT. The capacitance of the DUT allows the SMU to determine other parameters of the DUT, such as oxide mobile charge, oxide capacitance, and interface traps.

[0036] Process 500 then proceeds to process 512, where the SMU and computing device correct for unwanted leakage currents and parasitic capacitances in the DUT. As described above, the SMU can measure and correct for these unwanted currents by performing an IV sweep on the DUT and subtracting the unwanted currents (IR and Ip). The voltage sweep uses the actual measured voltage points resulting from constant forward and reverse current force testing, thereby deriving the capacitance as described. Additionally, the SMU can determine the system's parasitic capacitances, including cable parasitic capacitances and probe parasitic capacitances, and correct for the unwanted currents based on the previous calculations.

[0037] The quasi-static CV technique described here has several advantages over other methods. Measuring voltage is faster than measuring low currents, allowing more data points to be collected with greater accuracy. Feedback ammeters are often unstable with capacitive loads, so measuring voltage avoids noisy measurements. The method described here requires only one SMU, whereas other methods require two. The technique described here incorporates leakage current measurement and compensation, making the quasi-static technique applicable to leaky MOS devices. Quasi-static CV measurements in both the forward and reverse directions in a single run enable characterization of charge trapping.

[0038] The present disclosure includes measuring voltage instead of current, which results in faster, more accurate, and less noisy results. The present disclosure includes using only one SMU instead of two. The present disclosure includes providing compensation for leakage current at specific measurement voltage points without using differential methods, which can result in noisy results.

[0039] This disclosure further describes how to determine interface trapped charge and other internal charges in SiC MOS devices using the force current QSCV measurement technique. Because SiC devices have significantly more internal charge than conventional Si devices, the trapped charge can be calculated by multiplying the measured capacitance by the gate voltage (V g ) but the surface potential (V s ) and the interface trap charges in silicon MOS devices are plotted again at low frequency (quasi-static) CV g The capacitance difference between the CV curve and the high frequency (AC) curve is obtained. To observe the internal charge of a SiC MOSFET, forward and reverse quasi-static CV sweeps can be used to obtain this charge.

[0040] The method for deriving this interface trap capacitance can be described in five steps. First, the gate voltage (V g ) versus the surface potential (V s ) array is derived. Third, at each surface potential point, the forward capacitance (CfDut) and reverse capacitance (CrDut) are interpolated. Fourth, the oxide capacitance (C ox ) is subtracted. Fifth, the capacitance due to trapped charges (CIT) and density of interface traps (DIT) are calculated from the difference between the forward and reverse curves as a function of surface potential. These five steps are further explained in this application.

[0041] Although this disclosure refers to MOSFETs, the disclosure is potentially applicable to other devices. Additionally, although this disclosure refers to interface charges, the disclosure is potentially applicable to other types of charges, including, but not limited to, oxide charges or mobile ionic charges.

[0042] The present disclosure works by generating forward and reverse CV data using a force current quasi-static method and then obtaining the interface trap density as a function of surface potential.

[0043] As mentioned above, the derivation of interface trap capacitance (CIT) involves generating forward and reverse quasi-static CV curves. Specifically, to derive this interface trap capacitance, a forced current quasi-static CV technique is used to measure the gate voltage (V g ) versus forward quasi-static capacitance (Cf) and reverse quasi-static capacitance (Cr) curves must be generated. The forced current QSCV technique uses an SMU to derive quasi-static CV of a DUT such as a SiC MOSFET or MOS capacitor. In this test, the SMU forces a current and measures the voltage and time. A constant current precisely controls the total charge delivered to the DUT (Q=ΣI*dt). As a constant current is forced through the DUT, both forward and reverse CV sweeps are derived from the forced current, voltage, and time. The capacitance (C) is calculated as follows:

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[0044] At this point in the test, voltage and time are being measured. To accurately represent the data, the data should be spread out across the reverse and forward CV sweeps. The reverse sweep outputs reverse voltage (Vr), reverse sweep time (timeR), and reverse capacitance (Cr). The forward sweep outputs reverse voltage (Vf), forward sweep time (timeF), and forward capacitance (Cf).

[0045] From the forward and reverse CV sweeps, it is observed that there is both a voltage shift between the two curves, as well as "peaks" and smaller features in the curves. Both the voltage shift and the "peaks" are the result of internal charges in the device, such as trapped charges, mobile ionic charges, or charges associated with the device structure. However, during the high frequency (AC) sweep, the voltage shift and peaks may not be observed.

[0046] As mentioned above, to derive this interface trap capacitance, the surface potential (V s ) array must be derived. The capacitance of the DUT for forward and reverse voltage sweeps is usually measured at the same gate voltage (V g ) are compared. Because SiC MOSFETs have a large internal charge, the forward and reverse QSCV curves are compared based on the surface potential (V s ) are compared instead as a function of V s Using V corrects for the "shift" in gate voltage between the forward and reverse curves, making them comparable. By accurately measuring the charge, we can correct for the voltage drop across the gate oxide and s can be obtained.

[0047] 6 shows a circuit with an SMU connected to a SiC MOS DUT and illustrates the potentials of the circuit. As shown in FIG. 6, circuit 600 includes an SMU 102 coupled to a DUT 604 having a gate layer 614, an oxide layer 616, and a SiC layer 618. SMU 102 includes a current source 108 and a voltmeter 110. As shown in FIG. 6, in addition to applying a constant current to DUT 604, SMU 102 also applies a voltage V g and V s The voltage at the gate layer 614 of the DUT 604 is V g The voltage at the SiC / SiO2 interface is the surface potential (V s ) and is expressed by the following formula: [Number 14] V s =V g -V ox

[0048] Therefore, the surface potential (V s To derive the Cf array, the computing device 112 analyzes the reverse and forward capacitance arrays (Cr and Cf) to find the maximum value from either array. The maximum capacitance is Cf ox (i.e., oxide capacitance). Next, for each gate voltage V g Therefore, the SMU102 has an oxide film capacitance C ox Using the calculated charge (Q), the surface potential V is calculated as follows: s Calculate.

number

[0049] The surface potential is spread across two separate arrays for both sweeps. The output parameter V s R represents the reverse sweep surface potential, and V s F represents the forward sweep surface potential.

[0050] As mentioned above, to derive this interface trap capacitance, the surface potential V sAt each point, the forward capacitance (CfDut) and reverse capacitance (CrDut) must be interpolated. s The process of interpolating the forward capacitance (CfDut) and reverse capacitance (CrDut) at a point involves V g Although they are different, they are the same V s The process involves comparing two sets of data collected at 112. To do this, the computing device 112 uses linear interpolation as follows: (1) Determine the number of voltage step points using the following formula:

number

[0051] As mentioned above, the process of deriving this interface trap capacitance involves calculating the oxide capacitance (CfDut) from forward (CfDut) and reverse (CrDut) measurements. ox Specifically, the maximum capacity (C ox ) is subtracted from all CrDut and CfDut values. To do this, the SMU 102 calculates the reverse and forward surface potential values, V s R and V s Linear interpolation is used for F. The computing device 112 calculates the forward and reverse interpolated capacitance arrays (CrDut and CfDut), and for each function, the computing device 112 calculates C at each point using the following two equations: ox Remove a value.

number

number

[0052] Figure 7 shows the Vs 7 is a graph of the forward and reverse capacitance curves as a function of . Specifically, FIG. 7 shows both the forward and reverse capacitance curves CfDut and CrDut plotted as a function of interface voltage instead of gate voltage.

[0053] Figure 8 shows the C ox The Cf and Cr curves with V removed are s Specifically, in Figure 8, C ox With σ removed, CrOnly and CfOnly are plotted as a function of interfacial voltage, here on a logarithmic scale.

[0054] As described above, deriving the interface trap capacitance involves calculating the interface trap capacitance (CIT) and interface trap density (DIT) due to trapped charge from the difference between the corrected forward and reverse curves as a function of surface potential. In some embodiments, the computing device 112 uses the following equation to determine the interface trap capacitance due to trapped charge of the DUT 604:

number

[0055] In some embodiments, the computing device uses the following equation to determine the interface trap density (DIT) due to trapped charge in the DUT 604:

number

[0056] Figure 9 shows a plot of the interface trap density (DIT) versus the surface potential (V s ) as a function of the interfacial voltage (V s 1 shows a plot of the difference between the interpolated forward and reverse capacitances versus the capacitance of the capacitor.

[0057] 10 is a flowchart of the operation of an SMU and a computing device to derive interface trap capacitance using the quasi-static capacitance-voltage technique as described herein. Process 1000 is described with reference to circuit 100 of FIG. 1, but may also be implemented using circuit 600 of FIG. 6.

[0058] Process 1000 begins with process 1002, in which an SMU generates curves of forward and reverse quasi-static capacitance versus gate voltage for a DUT. The DUT may be a SiC MOSFET. In some embodiments, process 1002 includes a portion of process 500 of FIG. 5 to generate curves of gate voltage versus forward and reverse quasi-static capacitance for the DUT.

[0059] Next, process 1000 proceeds to step 1004, where the computing device derives surface potential arrays for the forward and reverse sweeps. The surface potentials for both the forward and reverse sweeps (V s To derive the Cr and Cf arrays, the SMU analyzes the reverse and forward capacitance arrays (Cr and Cf) to find the maximum value from either array. Then, for each gate voltage V g From this, the computing device has an oxide capacitance C ox Using the calculated charge (Q), the surface potential V s The surface potential is spilled into two separate arrays in both sweeps. The output parameter V s R represents the reverse sweep surface potential, and V s F represents the forward sweep surface potential.

[0060] Step 1000 then proceeds to step 1006, where the computing device interpolates the forward capacitance and the reverse capacitance at each surface potential point in the surface potential array. g are different, but the same surface potential V s To do this, the computing device uses linear interpolation as follows: (1) The computing device determines the number of voltage step points using the following formula:

number

[0061] Next, process 1000 proceeds to step 1008, where the computing device subtracts the oxide capacitance from the forward and reverse measurements. The computing device has reverse and forward surface potential values ​​V s R and V s Using linear interpolation of F, the maximum capacitance (C ox The computing device calculates the forward and reverse interpolated capacitance arrays (CrDut and CfDut), and for each function, the computing device calculates the capacitance at each point, C, using the following two equations: ox Remove a value.

number

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[0062] Step 1000 then proceeds to step 1010, where the computing device calculates the interface trap capacitance (CIT) and interface trap density (DIT) due to trapped charge as a function of surface potential from the difference between the corrected forward and reverse curves. Fonly Points and C RonlyThe interface trap capacitance due to the trapped charge of the DUT is calculated using the points. Similarly, the computing device is calculated using the gate area of ​​the DUT, the charge of the DUT, and C Fonly Points and C Ronly The points are used to determine the interface trap density (DIT) due to trapped charges in the DUT.

[0063] The present disclosure for calculating traps in SiC MOS devices from forward and reverse sweeps offers advantages over other solutions. For example, quasi-static CV measurements in both the forward and reverse directions can be performed in a single run, enabling characterization of charge traps. Another advantage is that the present disclosure enables measurement of capacitance as a function of interface potential, not just gate voltage. Yet another advantage is that the present disclosure includes capturing the internal charge of the device, which cannot be detected by high-frequency methods. Furthermore, the present disclosure requires only one SMU, rather than two as required by other methods. Furthermore, requiring only one SMU avoids disconnecting the measurement circuitry when two instruments need to be switched to the device.

[0064] In this disclosure, the difference between forward and reverse quasi-static (low frequency) capacitance measurements versus voltage is used to calculate internal traps. Other approaches use the difference between high and low frequency CV sweeps to derive interface trap density.

[0065] Because the charge is measured, the interfacial potential can be calculated, which allows for the characterization of capacitance as a function of interfacial potential. With other techniques, the interfacial potential is difficult to obtain because it is difficult or impossible to measure oxide charge at high frequencies. Therefore, comparisons are typically made as a function of gate voltage, rather than interfacial potential. Using this technique, high-frequency CV measurements are not required.

[0066] In this disclosure, the singular forms "a," "an," and "the" include plural referents unless the context dictates otherwise. The term "or" is inclusive and means either any, some, or all of the listed items. The terms "comprises," "comprising," "includes," "including," or other variations are intended to cover a non-exclusive inclusion, such that a process, method, article, or product consisting of a list of elements does not necessarily include only those elements, but may include other elements not expressly listed or inherent in such process, method, article, or device. Relative terms, such as "about," "approximately," "substantially," and "generally," are used to indicate a possible variation of ±10% of the stated or understood value.

[0067] The embodiments of the present disclosure are susceptible to various modifications and alternative forms. Specific embodiments have been shown and described in detail herein by way of example. However, these examples disclosed herein are presented for clarity of explanation and are not intended to limit the broad concepts disclosed in the specific embodiments described herein, unless expressly limited thereto. Accordingly, the present disclosure is intended to cover all modifications, equivalents, and alternatives of the described embodiments in light of the accompanying drawings and claims.

[0068] References to aspects, examples, etc. in the specification indicate that the described items may include particular features, structures, or characteristics. However, each disclosed aspect may or may not necessarily include such particular features, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same aspect unless specifically stated otherwise. Furthermore, when a particular feature, structure, or characteristic is described in connection with a particular aspect, such feature, structure, or characteristic may also be used in connection with any other disclosed aspect, regardless of whether such feature is explicitly described in connection with such other disclosed aspect.

[0069] Aspects of the disclosed technology may operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers, including processors that operate according to programmed instructions. The terms "controller" or "processor" herein contemplate microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the disclosed technology may be implemented with computer-usable data and computer-executable instructions, such as one or more program modules, executed by one or more computers (including a monitoring module) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform particular tasks or implement particular abstract data types. Computer-executable instructions may be stored in computer-readable storage media, such as hard disks, optical disks, removable storage media, solid-state memory, RAM, etc. Those skilled in the art will appreciate that the functionality of the program modules may be combined or distributed as desired in various embodiments. Furthermore, such functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, field programmable gate arrays (FPGAs), etc. Certain data structures may be used to more effectively implement one or more aspects of the disclosed technology, and such data structures are considered within the scope of the computer-executable instructions and computer-usable data described herein.

[0070] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As used herein, computer-readable media refers to any medium that can be accessed by a computing device. By way of example, and not limitation, computer-readable media may include computer storage media and communication media.

[0071] "Computer storage media" means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) and other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage and other magnetic storage devices, and any other volatile or nonvolatile, removable or non-removable medium implemented in any technology. "Computer storage media" excludes signals themselves and transitory forms of signal transmission.

[0072] A communication medium means any medium usable for communicating computer-readable information. By way of example, and not limitation, communication media may include coaxial cable, fiber optic cable, air, or any other medium suitable for communicating electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0073] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As used herein, computer-readable media refers to any medium that can be accessed by a computing device. By way of example, and not limitation, computer-readable media may include computer storage media and communication media.

[0074] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, unless the circumstances do not preclude this possibility.

[0075] While specific embodiments of the disclosed technology have been illustrated and described for purposes of illustration, it will be appreciated that various modifications can be made therein without departing from the spirit and scope of the invention. Accordingly, the disclosed technology should not be limited, except as by the appended claims. Example

[0076] The following examples are provided to aid in understanding the technology disclosed in this application. Embodiments of the technology may include one or more of the examples described below, and any combination thereof.

[0077] Example 1 is a test and measurement apparatus comprising: a current source configured to output a constant current to a connected device under test (DUT); a voltage sensor configured to detect a voltage of the DUT, the voltage sensor being configured to be used when the current source is outputting a first constant current to the DUT to measure a first set of voltages over time, to be used when the current source is outputting a second constant current to the DUT having a different polarity from the first constant current to measure a second set of voltages over time, and to be used when the current source is outputting a third constant current to the DUT having the same polarity as the first constant current to measure a third set of voltages over time; and one or more processors, the one or more processors configured to execute a program that causes the one or more processors to perform a process of deriving a capacitance of the DUT based on the first, second, and third constant currents and the sets of first, second, and third voltages as a function of time.

[0078] A second embodiment is the test and measurement apparatus of the first embodiment, wherein the DUT is a power device or a MOS (metal oxide semiconductor) device.

[0079] Example 3 is the test and measurement apparatus of Example 1 or Example 2, wherein the voltage sensor is configured to measure the second voltage when the current source outputs the second constant current to the DUT after the first voltage reaches a predetermined threshold.

[0080] Example 4 is the test and measurement instrument of any of Examples 1 to 3, wherein the voltage sensor is configured to measure the third voltage when the current source outputs the third constant current to the DUT after the second set of voltages reaches a predetermined threshold.

[0081] Example 5 is the test and measurement device of any of Examples 1 to 4, wherein the voltage sensor is configured to measure the first set of voltages until the first set of voltages reaches a predetermined threshold.

[0082] Example 6 is the test and measurement instrument of any of Examples 1 to 5, wherein the one or more processors are further configured to determine device parameters of the DUT based on the capacitance of the DUT.

[0083] Example 7 is the test and measurement apparatus of any of Examples 1 to 6, wherein the capacitance is a quasi-static capacitance of the DUT.

[0084] Example 8 is the test and measurement instrument of any of Examples 1 to 7, wherein the one or more processors are further configured to compensate for one or more unwanted currents based on a leakage current of the DUT and capacitance of a test fixture and cabling.

[0085] Example 9 is the test and measurement device of any of Examples 1 to 8, wherein the program that causes the one or more processors to perform a process to derive the capacitance of the DUT includes a program that causes the one or more processors to perform a process using the equation Cm=I / (dV / dt).

[0086] Example 10 is a method for a test and measurement apparatus, comprising: directing a voltage sensor of the test and measurement apparatus to measure a first set of voltages over time when a current source of the test and measurement apparatus outputs a first constant current to a device under test (DUT) coupled to the test and measurement apparatus; directing the voltage sensor of the test and measurement apparatus to measure a second set of voltages over time when a second constant current having a different polarity than the first constant current is output to the DUT; directing the voltage sensor of the test and measurement apparatus to measure a third set of voltages over time when a third constant current having the same polarity as the first constant current is output to the DUT; and deriving a quasi-static capacitance of the DUT based on the second and third constant currents and the sets of second and third voltages as a function of time.

[0087] Example 11 is the method of example 10, wherein the DUT is a power device or a MOS (metal oxide semiconductor) device.

[0088] A twelfth embodiment is the method of the tenth or eleventh embodiment, wherein the process of deriving the capacitance of the DUT includes a process of using an equation of Cm=I / (dV / dt).

[0089] Example 13 is the method of any of Examples 10 to 12, wherein instructing the voltage sensor of the test and measurement instrument to measure the second set of voltages over time may include instructing the voltage sensor of the test and measurement instrument to measure the second set of voltages over time while the current source is outputting the second constant current to the DUT after the first set of voltages reaches a user-defined threshold.

[0090] Example 14 is the method of any of Examples 10 to 13, wherein instructing the voltage sensor of the test and measurement instrument to measure the third set of voltages over time may include instructing the voltage sensor of the test and measurement instrument to measure the third set of voltages over time while the current source is outputting the third constant current to the DUT after the second set of voltages reaches a user-defined threshold.

[0091] Example 15 is the method of any of Examples 10 to 14, wherein the process of instructing the voltage sensors of the test and measurement device to measure may include a process of instructing the voltage sensors of the test and measurement device to measure the first set of voltages over time until the first set of voltages reaches a user-defined threshold.

[0092] Example 16 is the method of any of Examples 10 to 15, further comprising determining a device parameter of the DUT based on the capacitance of the DUT.

[0093] Example 17 is the method of any of examples 10 to 16, wherein the capacitance of the DUT is a quasi-static capacitance of the DUT.

[0094] Example 18 is the method of any of Examples 10 to 17, further comprising compensating for unwanted leakage current of the DUT and capacitance of a test fixture and cabling.

[0095] Example 19 is a test measurement system, comprising: a current source configured to output a constant current to a connected device under test (DUT); a voltage sensor configured to detect a voltage of the DUT; a test and measurement device having One or more processors Equipped with the one or more processors: instructing the voltage sensor to measure a first set of voltages over time while the current source outputs a first constant current to the DUT; instructing the voltage sensor to measure a second set of voltages over time while the current source outputs a second constant current to the DUT, the second constant current having a different polarity than the first constant current; instructing the voltage sensor to measure a third set of voltages over time while the current source outputs a third constant current to the DUT, the third constant current having the same polarity as the first constant current; deriving a quasi-static capacitance of the DUT based on the second and third constant currents and the second and third voltages as a function of time; The one or more processors are configured to execute a program that causes the one or more processors to perform the steps of:

[0096] Example 20 is the test and measurement system of Example 19, wherein the one or more processors configured to perform processing to derive the capacitance of the DUT include processing using the formula Cm=I / (dV / dt).

[0097] Example 21 is a method for deriving interface trap capacitance using a test measurement device, comprising: generating a forward quasi-static capacitance sweep and a reverse quasi-static capacitance sweep using a voltage sensor and a current source of the test and measurement equipment configured to detect a voltage of a connected device under test (DUT); deriving an array of surface potential voltages for the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; interpolating the forward capacitance and the reverse capacitance of the DUT at each of the surface potential voltages based on the arrays of surface potential voltages of the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; subtracting the oxide capacitance from each of the interpolated forward capacitances and each of the interpolated reverse capacitances to generate a forward-only quasi-static capacitance sweep and a reverse-only quasi-static capacitance sweep; calculating the capacitance and interface trap density of the DUT from the difference between the forward-only quasi-static capacitance sweep and the reverse-only quasi-static capacitance sweep as a function of the surface potential voltage; It is equipped with.

[0098] Example 22 is the method of example 21, wherein generating the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep comprises: deriving a first array of voltage and time measurements using a voltage sensor while a current source is outputting a first constant current to the DUT; deriving a second array of voltage and time measurements using the voltage sensor while a current source is outputting a second constant current to the DUT; deriving a third array of voltage and time measurements using the voltage sensor while a current source is outputting a third constant current to the DUT; determining the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep based on the second and third arrays of voltage and time measurements and the second and third constant currents; It may also include:

[0099] Example 23 is the method of example 21 or example 22, wherein the DUT is a power device or a MOS (metal oxide semiconductor) device.

[0100] Example 24 is the method of any of Examples 21 to 23, wherein the step of deriving the array of surface potential voltages comprises: determining oxide capacitance for the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; calculating an array of surface potential voltages based on the total charge and the oxide capacitance; It may have the following structure.

[0101] Example 25 is the method of any of examples 21 to 24, wherein the step of deriving the array of surface potential voltages comprises: V s =V g -Q / C ox Using the formula:

[0102] Example 26 is the method of any of Examples 21 to 25, wherein the process of interpolating the forward capacitance and the reverse capacitance of the DUT at each of the surface potential voltages may include a process of determining a number of voltage steps, and a process of linearly interpolating the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep to obtain interpolated capacitance points.

[0103] Example 27 is the method of any one of Examples 21 to 26, wherein the process of subtracting the oxide film capacitance is CfOnly=1 / (1 / CfDut-1 / C ox ) and CrOnly=1 / (1 / CrDut-1 / C ox ) formula is used.

[0104] Example 28 is the method of any of Examples 21 to 27, wherein the process of calculating the capacitance and the interface trap density of the DUT may include a process of calculating a capacitance due to trapped charge based on a gate area.

[0105] Example 29 is the method of any of Examples 21 to 28, wherein the process of calculating the capacitance and interface trap density of the DUT can include calculating the interface trap density based on a gate area and a total charge.

[0106] Example 30 is a test measurement system, comprising: a current source configured to output a current; a voltage sensor configured to detect a voltage of a connected device under test (DUT); One or more processors Equipped with the one or more processors: generating a forward quasi-static capacitance sweep and a reverse quasi-static capacitance sweep using the current source and the voltage sensor; deriving an array of surface potential voltages for the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; interpolating the forward capacitance and the reverse capacitance of the DUT at each of the surface potential voltages based on the arrays of surface potential voltages of the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; subtracting the oxide capacitance from each of the interpolated forward capacitances and each of the interpolated reverse capacitances; Calculating the capacitance and interface trap density of the DUT from the difference between the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep as a function of the surface potential voltage; The one or more processors are configured to execute a program that causes the one or more processors to perform the steps of:

[0107] Example 31 is the test and measurement system of Example 30, in which the current source is a DC current source.

[0108] Example 32 is the test and measurement system of Example 30 or Example 31, wherein the DUT is a power device or a MOS (metal oxide semiconductor) device.

[0109] Example 33 is the test and measurement system of any of Examples 30 to 32, wherein the program causing the one or more processors to process to derive the array of surface potential voltages comprises: determining oxide capacitance for the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; calculating said array of surface potential voltages based on the total charge and said oxide capacitance; The method further includes a program that causes the one or more processors to perform the steps of:

[0110] Example 34 is the test and measurement system of any of Examples 30 to 33, wherein the program causing the one or more processors to perform a process of interpolating the forward capacitance and the reverse capacitance of the DUT at each of the surface potential voltages comprises: determining a number of voltage steps; performing linear interpolation on the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep to obtain interpolated capacitance points; The method further includes a program that causes the one or more processors to perform the steps of:

[0111] Example 35 is a test and measurement system of any of Examples 30 to 34, wherein the program that causes the one or more processors to perform a process of calculating the capacitance and interface trap density of the DUT further includes a program that causes the one or more processors to perform a process of calculating the capacitance due to trapped charge based on a gate area.

[0112] Example 36 is a test and measurement system of any of Examples 30 to 35, wherein the program that causes the one or more processors to perform a process of calculating the capacitance and interface trap density of the DUT further includes a program that causes the one or more processors to perform a process of calculating the interface trap density based on a gate area and a total charge.

[0113] Although the above-described versions of the presently disclosed subject matter have many advantages that have been described or that will be apparent to those skilled in the art, not all of these advantages or features are required in every version of the disclosed devices, systems, or methods.

[0114] Additionally, the description of this application refers to specific features. It should be understood that the disclosure herein includes all possible combinations of these specific features. When a specific feature is disclosed in connection with a particular aspect or example, that feature can also be used in connection with other aspects and examples, to the extent possible.

[0115] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, unless the circumstances do not preclude this possibility.

[0116] Although specific embodiments of the invention have been illustrated and described for purposes of illustration, it will be appreciated that various modifications can be made therein without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited except as by the appended claims. [Explanation of symbols]

[0117] 100 circuits 102 Source Measure Units (SMUs) 104 Device Under Test (DUT) 106 Controller 108 Current source 110 Voltmeter 112 Computing Devices 300 circuits 302 Source Measure Unit (SMU) 304 Device Under Test (DUT) 306 Controller 312 Ammeter 600 circuits 604 Device Under Test (DUT) 614 Gate Layer 616 Acidification film 618 SiC layer

Claims

1. 1. A test and measurement device comprising: a current source configured to output a constant current to a connected device under test (DUT); a voltage sensor configured to detect a voltage of the DUT, measuring a first set of voltages over time used while the current source is outputting a first constant current to the DUT; measuring a second set of voltages over time when the current source is outputting a second constant current to the DUT, the second constant current having a different polarity than the first constant current; a third set of voltages over time that are used when the current source is outputting a third constant current to the DUT, the third constant current having the same polarity as the first constant current; The voltage sensor configured as follows: one or more processors Equipped with The test and measurement instrument is configured to execute a program that causes the one or more processors to perform a process of deriving the capacitance of the DUT based on the first, second, and third constant currents and the set of first, second, and third voltages as a function of time.

2. 2. The test and measurement instrument of claim 1, wherein the voltage sensor is configured to measure the second voltage when the current source is outputting the second constant current to the DUT after the first voltage reaches a predetermined threshold.

3. 2. The test and measurement instrument of claim 1, wherein the voltage sensor is configured to measure the third set of voltages when the current source is outputting the third constant current to the DUT after the second voltage reaches a predetermined threshold.

4. 2. The test and measurement instrument of claim 1, wherein the voltage sensor is configured to measure the first set of voltages until the first set of voltages reaches a predetermined threshold.

5. 2. The test and measurement instrument of claim 1, wherein the program that causes the one or more processors to perform processing to derive the capacitance of the DUT includes a program that causes the one or more processors to perform processing using the equation Cm=I / (dV / dt).

6. 1. A method for a test and measurement device, comprising: instructing a voltage sensor of the test and measurement instrument to measure a first set of voltage measurements over time while a current source of the test and measurement instrument outputs a first constant current to a device under test (DUT) coupled to the test and measurement instrument; instructing the voltage sensor of the test and measurement instrument to measure a second set of voltage measurements over time while outputting a second constant current to the DUT, the second constant current having a different polarity than the first constant current; instructing the voltage sensor of the test and measurement instrument to measure a third set of voltage measurements over time while outputting a third constant current to the DUT, the third constant current having the same polarity as the first constant current; deriving a quasi-static capacitance of the DUT based on the second and third constant currents and the second and third voltages as a function of time; A method for a test and measurement device comprising:

7. 7. The method for a test and measurement instrument of claim 6, wherein the step of instructing the voltage sensor of the test and measurement instrument to measure the second set of voltages over time includes the step of instructing the voltage sensor of the test and measurement instrument to measure the second set of voltages over time while the current source is outputting the second constant current to the DUT after the first voltage reaches a user-defined threshold.

8. 7. The method for a test and measurement instrument of claim 6, wherein the step of instructing the voltage sensor of the test and measurement instrument to measure the third set of voltages over time includes the step of instructing the voltage sensor of the test and measurement instrument to measure the third set of voltages over time while the current source is outputting the third constant current to the DUT after the second set of voltages reaches a user-defined threshold.

9. 7. The method for a test and measurement instrument of claim 6, wherein the step of instructing the voltage sensor of the test and measurement instrument to measure includes the step of instructing the voltage sensor of the test and measurement instrument to measure the first set of voltages over time until the first voltages reach a user-defined threshold.

10. 1. A method for deriving interface trap capacitance using a test and measurement device, comprising: generating a forward quasi-static capacitance sweep and a reverse quasi-static capacitance sweep using a voltage sensor and a current source of the test and measurement instrument configured to detect a voltage of a connected device under test (DUT); deriving an array of surface potential voltages for the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; interpolating the forward capacitance and the reverse capacitance of the DUT at each of the surface potential voltages based on the arrays of surface potential voltages of the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; subtracting the oxide capacitance from each of the interpolated forward capacitances and each of the interpolated reverse capacitances to generate a forward-only quasi-static capacitance sweep and a reverse-only quasi-static capacitance sweep; calculating the capacitance and interface trap density of the DUT from the difference between the forward-only quasi-static capacitance sweep and the reverse-only quasi-static capacitance sweep as a function of the surface potential voltage; A method for deriving interface trap capacitance comprising:

11. generating the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep, deriving a first array of voltage and time measurements using a voltage sensor while a current source is outputting a first constant current to the DUT; deriving a second array of voltage and time measurements using the voltage sensor while a current source is outputting a second constant current to the DUT; deriving a third array of voltage and time measurements using the voltage sensor while a current source is outputting a third constant current to the DUT; determining the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep based on the second and third arrays of voltage and time measurements and the second and third constant currents; The method for deriving interface trap capacitance according to claim 10, comprising:

12. deriving the array of surface potential voltages, determining oxide capacitance for the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; calculating an array of surface potential voltages based on the total charge and the oxide capacitance; The method for deriving interface trap capacitance according to claim 10 or 11, comprising:

13. a process of interpolating a forward capacitance and a reverse capacitance of the DUT at each of the surface potential voltages, determining a number of voltage steps; performing linear interpolation on the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep to obtain interpolated capacitance points; The method for deriving interface trap capacitance according to claim 10 or 11, comprising:

14. 12. The method for deriving interface trap capacitance according to claim 10, wherein the process of calculating the capacitance and the interface trap density of the DUT includes a process of calculating a capacitance due to trapped charges based on a gate area.

15. 12. The method for deriving interface trap capacitance according to claim 10, wherein the step of calculating the capacitance and interface trap density of the DUT includes the step of calculating the interface trap density based on a gate area and a total charge.

16. 1. A test and measurement system comprising: a current source configured to output a current; a voltage sensor configured to detect a voltage of a connected device under test (DUT); one or more processors Equipped with the one or more processors generating a forward quasi-static capacitance sweep and a reverse quasi-static capacitance sweep using the current source and the voltage sensor; deriving an array of surface potential voltages for the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; interpolating the forward capacitance and the reverse capacitance of the DUT at each of the surface potential voltages based on the arrays of surface potential voltages of the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; subtracting the oxide capacitance from each of the interpolated forward capacitances and each of the interpolated reverse capacitances; calculating the capacitance and interface trap density of the DUT from the difference between the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep as a function of surface potential voltage; a test and measurement system configured to execute a program that causes the one or more processors to perform the steps of:

17. The program causing the one or more processors to perform a process of deriving an array of surface potential voltages comprises: determining oxide capacitance for the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep; calculating said array of surface potential voltages based on the total charge and said oxide capacitance; 17. The test and measurement system of claim 16, further comprising a program that causes the one or more processors to:

18. The program causing the one or more processors to perform a process of interpolating a forward capacitance and a reverse capacitance of the DUT at each of the surface potential voltages comprises: determining a number of voltage steps; performing linear interpolation on the forward quasi-static capacitance sweep and the reverse quasi-static capacitance sweep to obtain interpolated capacitance points; 17. The test and measurement system of claim 16, further comprising a program that causes the one or more processors to:

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