Cleaved semiconductor wafer camera system and method

Abstract

To provide a method and a system for imaging a semiconductor substrate, and in particular, imaging a cleaved wafer.SOLUTION: A semiconductor wafer imaging system 110 for imaging a semiconductor wafer includes a shroud panel defining a dark box 118, a camera for imaging the semiconductor wafer, and an illumination panel for directing diffused light toward the semiconductor wafer, both disposed in the dark box. A portion of the diffused light is reflected from the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 62 / 706894, filed September 16, 2020, U.S. Provisional Patent Application No. 62 / 706895, filed September 16, 2020, and U.S. Provisional Patent Application No. 62 / 706897, filed September 16, 2020. The entire disclosures of the priority applications are incorporated herein by reference in their entirety.

[0002] The field of the disclosure relates to methods and systems for imaging semiconductor substrates, and in particular, imaging cleaved wafers. [Background technology]

[0003] Semiconductor wafers are typically used to manufacture integrated circuit (IC) chips, on which circuits are printed. Miniaturized circuits are first printed on the surface of the wafer, and then the wafer is divided into circuit chips. During the manufacturing process, the wafers are treated and polished so that the front and back surfaces of each wafer have mirror-like reflective surfaces. To reduce manufacturing costs, wafers are imaged during the manufacturing process to detect defects on the wafer's surface before the wafer is further processed.

[0004] Some imaging systems used in quality control systems image manufactured items by reflecting light off the manufactured item and detecting the reflected light with a camera. The camera typically images the non-specular surface of the manufactured item. However, because the surface of a wafer is specular, the light directed at the wafer must be uniformly diffused. Otherwise, the image captured by the imaging system will be a reflection of the light source rather than the wafer's features.

[0005] Additionally, imaging systems that image the reflective surface of a wafer are also available. However, these systems typically include large parabolic mirrors, which increase the size of the imaging system and limit where it can be placed within the manufacturing process. Specifically, the parabolic mirrors significantly increase the height and width of the imaging system. Imaging systems can only be placed in locations with sufficient space to accommodate the large volume of the system. A suitable location for the system may interfere with the manufacturing process.

[0006] This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to better understand the various aspects of the present disclosure. As such, it should be understood that these statements are to be read in this light, and not as admissions of prior art. Summary of the Invention

[0007] One aspect of the present disclosure relates to a semiconductor wafer imaging system for imaging a semiconductor wafer, the system including a shroud panel defining a dark box, a camera disposed in the dark box for imaging the semiconductor wafer, and an illumination panel for directing diffused light toward the semiconductor wafer, a portion of the diffused light being reflected by the semiconductor wafer, and the camera detecting the reflected diffused light to image the semiconductor wafer.

[0008] Another aspect of the present disclosure relates to a dark box for imaging a semiconductor wafer. The dark box includes a shroud panel defining an upper chamber and a lower chamber. A support plate separates the upper chamber from the lower chamber. A bottom shroud panel at least partially defines the lower chamber and defines a wafer opening. The support plate defines a camera opening. The dark box further includes a camera disposed in the upper chamber for imaging the semiconductor wafer and an illumination panel for directing diffused light toward the semiconductor wafer. The diffused light is transmitted to the semiconductor wafer through the wafer opening, and a portion of the diffused light is reflected off the semiconductor wafer through the wafer opening and the camera opening. The camera images the semiconductor wafer by detecting the reflected diffused light.

[0009] Yet another aspect of the present disclosure relates to a semiconductor wafer processing system for processing semiconductor wafers. The system includes a semiconductor wafer processing station for processing the semiconductor wafers and a semiconductor wafer imaging system for imaging the semiconductor wafers after the semiconductor wafer processing station has processed the semiconductor wafers. The semiconductor wafer imaging system includes a shroud panel defining a dark box, a camera disposed in the dark box for imaging the semiconductor wafers, and an illumination panel for directing diffused light toward the semiconductor wafers. A portion of the diffused light is reflected by the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light.

[0010] Yet another aspect of the present disclosure relates to a semiconductor wafer processing system for processing semiconductor wafers. The system includes a first manufacturing line for processing a first semiconductor wafer, the first manufacturing line including a first semiconductor wafer processing station for processing the first semiconductor wafer. The system further includes a second manufacturing line for processing a second semiconductor wafer, the second manufacturing line including a second semiconductor wafer processing station for processing the second semiconductor wafer. The second manufacturing line intersects with the first manufacturing line at a common location. The system further includes a semiconductor wafer imaging system for imaging the first semiconductor wafer and the second semiconductor wafer, disposed within the common location where the first manufacturing line and the second manufacturing line intersect. The semiconductor wafer imaging system images the first semiconductor wafer and the second semiconductor wafer after the first semiconductor wafer processing station and the second semiconductor wafer processing station have processed the first semiconductor wafer and the second semiconductor wafer. The semiconductor wafer imaging system includes a shroud panel defining a dark box, a camera disposed in the dark box for imaging the semiconductor wafer, and an illumination panel for directing diffused light toward the semiconductor wafer. A portion of the diffused light is reflected by the semiconductor wafer, and the camera captures an image of the semiconductor wafer by detecting the reflected diffused light.

[0011] Yet another aspect of the present disclosure relates to a semiconductor wafer imaging station of a semiconductor wafer processing system for imaging a semiconductor wafer. The station includes a frame, a positioning plate attached to the frame, and a dark box movably attached to the positioning plate. The dark box includes a shroud panel defining the dark box, a camera for imaging the semiconductor wafer, and an illumination panel disposed in the dark box for directing diffused light toward the semiconductor wafer. A portion of the diffused light is reflected by the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light. The station further includes an end effector for positioning the semiconductor wafer within a field of view of the camera.

[0012] Yet another aspect of the present disclosure relates to a method for detecting defects in a semiconductor wafer, the method including directing diffused light at the semiconductor wafer and reflecting the diffused light off the semiconductor wafer, the method further including detecting the diffused light with a camera, generating an image of the semiconductor wafer, and analyzing the image to detect defects in the semiconductor wafer.

[0013] Yet another aspect of the present disclosure relates to a method for processing a semiconductor wafer, the method including cleaving the semiconductor wafer at a cleaving station, positioning the semiconductor wafer within a field of view of a camera, and directing diffused light at the semiconductor wafer, the method further including reflecting the diffused light off the semiconductor wafer, detecting the diffused light with a camera, generating an image of the semiconductor wafer, and analyzing the image to detect defects in the semiconductor wafer.

[0014] Yet another aspect of the present disclosure relates to a method for processing semiconductor wafers using a semiconductor wafer processing system, the semiconductor wafer processing system including a processing station and a semiconductor wafer imaging station, the method including processing the semiconductor wafer in the processing station, positioning the semiconductor wafer within a field of view of a camera of the semiconductor wafer imaging station, and directing diffused light at the semiconductor wafer, the method further including reflecting the diffused light off the semiconductor wafer, detecting the diffused light with the camera, generating an image of the semiconductor wafer, and analyzing the image to detect defects in the semiconductor wafer.

[0015] Yet another aspect of the present disclosure relates to a method for processing semiconductor wafers using a semiconductor wafer processing system, the semiconductor wafer processing system including a first manufacturing line, a second manufacturing line, and a semiconductor wafer imaging station disposed within a common location where the first manufacturing line and the second manufacturing line intersect. The first manufacturing line and the second manufacturing line each include a processing station for processing semiconductor wafers. The method includes: i) processing a first semiconductor wafer at the processing station of the first manufacturing line; ii) positioning the first semiconductor wafer within a field of view of a camera of the semiconductor wafer imaging station; and iii) directing diffused light at the first semiconductor wafer. The method further includes: iv) reflecting the diffused light off the first semiconductor wafer; v) detecting the diffused light with the camera to generate an image of the first semiconductor wafer; and vi) analyzing the image to detect defects in the semiconductor wafer. The method further includes vii) processing a second semiconductor wafer at the processing station of the second manufacturing line; and viiii) repeating steps ii through vi to image the second semiconductor wafer.

[0016] Various refinements exist to the features described in connection with the above-described aspects. Likewise, additional features may be incorporated into the above-described aspects. These refinements and additional features may exist individually or in any combination. For example, various features described below in connection with any of the illustrated embodiments may be incorporated into any of the above-described aspects, alone or in any combination. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a schematic diagram of a semiconductor wafer processing system. [Figure 2] FIG. 2 is a schematic diagram of an alternative semiconductor wafer processing system. [Figure 3] FIG. 3 is a perspective view of a semiconductor wafer imaging system located at a common location within the semiconductor wafer processing systems of FIGS. [Figure 4]FIG. 4 is another perspective view of the semiconductor wafer imaging systems co-located within the semiconductor wafer processing systems of FIGS. [Figure 5] FIG. 5 is a perspective view of the semiconductor wafer imaging system shown in FIGS. 3 and 4 with the shroud shown in transparency. [Figure 6] FIG. 6 is a cross-sectional view of the lighting panel shown in FIG. [Figure 7] FIG. 7 is a perspective view of the semiconductor wafer imaging system illustrated in FIG. 5 with the shroud removed. [Figure 8] FIG. 8 is another perspective view of the semiconductor wafer imaging system illustrated in FIG. 5 with the shroud and structural members removed. [Figure 9] FIG. 9 is a cross-sectional view of the semiconductor wafer imaging system shown in FIG. [Figure 10] FIG. 10 is another perspective view of the semiconductor wafer imaging system shown in FIG. 5 with the shroud and structural members removed and the filter illustrated. [Figure 11] FIG. 11 is another perspective view of the semiconductor wafer imaging system shown in FIGS. 3 and 4 with an end effector positioner attached. [Figure 12] FIG. 12 is another perspective view of the semiconductor wafer imaging system shown in FIGS. 3 and 4 with the end effector positioner and the end effector attached. [Figure 13] FIG. 13 is a schematic diagram of an image of a semiconductor wafer captured by the semiconductor wafer imaging system shown in FIGS. [Figure 14] FIG. 14 is an image of a semiconductor wafer captured by the semiconductor wafer imaging system shown in FIGS. [Figure 15] FIG. 15 is a raw Fast Fourier Transform (FFT) image of a semiconductor wafer generated by the controller. [Figure 16] FIG. 16 is a schematic diagram of an output image of a semiconductor wafer generated by the controller. [Figure 17]FIG. 17 is an output image of a semiconductor wafer generated by the controller. [Figure 18] FIG. 18 is a diagram of a computer program for imaging and analyzing a semiconductor wafer. [Figure 19] FIG. 19 is a flow diagram of a method for imaging and analyzing a semiconductor wafer. [Figure 20] FIG. 20 is a flow diagram of a method for imaging and analyzing a semiconductor wafer. [Figure 21] FIG. 21 is a flow diagram of a method for imaging and analyzing a semiconductor wafer. [Figure 22] FIG. 22 shows the display used for wafer position calibration by the image analysis process.

[0018] Although particular features of the various examples may be shown in some drawings and not in others, this is for convenience only, and any feature of any drawing may be referenced and / or claimed in combination with any feature of any other drawing.

[0019] Unless otherwise indicated, the drawings are intended to illustrate features of examples of the present disclosure. These features may be applicable in a variety of systems having one or more examples of the present disclosure. The drawings are not intended to include all conventional features known to those skilled in the art that may be required to practice the disclosed examples. DETAILED DESCRIPTION OF THE INVENTION

[0020] Semiconductor wafers (sometimes referred to as semiconductor or silicon "wafers" or "substrates") are typically prepared from a single crystal ingot (e.g., a silicon ingot) that is formed by a crystal growth process and sliced ​​into individual wafers. Suitable crystal growth processes include the Czochralski process, the float-zone process, the hydrothermal process, the Bridgman process, the Kyropoulos process, and / or any other crystal growth process. While reference is made herein to semiconductor wafers composed of silicon, other materials may be used to prepare semiconductor wafers, such as germanium, silicon carbide, silicon germanium, germanium arsenide, and other alloys of Group III and Group IV elements, such as gallium nitride or indium phosphide, or alloys of Group II and Group VI elements, such as cadmium sulfide or zinc oxide. Each semiconductor wafer includes a central axis, a front surface, and a rear surface parallel to the front surface. The front and rear surfaces are generally perpendicular to the central axis. The front and rear surfaces are joined by a periphery.

[0021] Semiconductor wafers may be used to prepare composite layer structures. Composite layer structures (e.g., semiconductor-on-insulator, more specifically, silicon-on-insulator (SOI) structures) generally comprise a handle layer or handle layer, a device layer, and an insulating (e.g., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Composite layer structures, such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz, are typically fabricated by placing two wafers in close contact, bonding them via van der Waals forces, and then strengthening the bond through a thermal treatment. Annealing converts terminal silanol groups between the two interfaces into siloxane bonds, strengthening the bond.

[0022] After thermal annealing, the bonded structure undergoes further processing to remove a substantial portion of the donor wafer to achieve layer transfer. For example, a common method for achieving layer transfer utilizes hydrogen implantation followed by thermally induced layer separation. Particles (atoms or ionized atoms, e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted to a predetermined depth below the front surface of the donor wafer. The implanted particles form a cleave plane in the donor wafer at the predetermined depth where the particles are embedded. The surface of the donor wafer is cleaned to remove organic compounds or other contaminants, such as boron compounds, that may have been deposited on the wafer during the implantation process.

[0023] The front side of the donor wafer is then bonded to the handle wafer via a hydrophilic bonding process to form a bonded wafer. Prior to bonding, the donor wafer and / or handle wafer are activated by exposing the wafer surfaces to a plasma containing, for example, oxygen or nitrogen. The plasma exposure changes the surface structure in a process often referred to as surface activation. The activation process renders one or both surfaces of the donor and handle wafers hydrophilic. The wafer surfaces may be further chemically activated by a wet treatment, such as SC1 cleaning or hydrofluoric acid. The wet treatment and plasma activation may be performed in either order, or the wafers may undergo only one treatment. The wafers are then pressed together to form a bond between them. This bond is relatively weak due to van der Waals forces and must be strengthened before further processing can occur.

[0024] In some processes, the hydrophilic bond between the donor wafer and the handle wafer (i.e., the bonded wafer) is strengthened by heating or annealing the bonded wafer pair. In some processes, wafer bonding may occur at low temperatures, such as about 300°C to 500°C. In some processes, wafer bonding may occur at high temperatures, such as about 800°C to 1100°C. The elevated temperature forms covalent bonds between the adjacent surfaces of the donor and handle wafers, thereby solidifying the bond between the donor and handle wafers. Upon heating or annealing the bonded wafers, particles previously implanted in the donor wafer weaken the cleavage plane.

[0025] The donor wafer portion is then separated (i.e., cleaved) from the bonded wafer along the cleavage plane to form the SOI wafer. Cleaving may be accomplished by placing the bonded wafer in a fixture and applying a mechanical force perpendicular to both sides of the bonded wafer to pull the donor wafer portion away from the bonded wafer. According to some methods, a suction cup is used to apply the mechanical force. Separation of the donor wafer portion is initiated by applying a mechanical wedge to the edge of the bonded wafer at the cleavage plane to cause a crack to propagate along the cleavage plane. The mechanical force applied by the suction cup then pulls the donor wafer portion away from the bonded wafer, thereby forming the SOI wafer.

[0026] In one example, a semiconductor wafer imaging system images a wafer to detect defects in the wafer during the manufacturing process. The imaging system images the wafer after the wafer is cleaved to detect defects in the wafer formed during any upstream manufacturing processes, including the cleaving process. If the semiconductor wafer imaging system detects defects in the wafer, the wafer is removed from the manufacturing process, thereby reducing wafer manufacturing costs. The wafer has a specular reflective surface, and the semiconductor wafer imaging system images the wafer without imaging a light source reflected by the reflective surface. Specifically, the semiconductor wafer imaging system includes a dark box surrounding a camera and an illumination panel. The dark box minimizes reflections in the semiconductor wafer imaging system, and the illumination panel directs diffuse light toward the wafer. The diffuse light is reflected by the wafer toward the camera. Because the light generated by the illumination panel is scattered, the camera detects the reflected diffuse light but does not image the illumination panel. In this way, the camera images the wafer but does not image the light source, thereby enabling a controller to analyze the wafer for defects and reducing manufacturing costs.

[0027] Referring to FIG. 1 , a semiconductor wafer processing system 100 includes a manufacturing line 102 for manufacturing semiconductor wafers 104. The manufacturing line 102 includes a semiconductor wafer processing station 106 for processing the wafers 104. The semiconductor wafer processing station 106 includes a cleaving station 108 and a semiconductor wafer imaging station or system 110 for imaging the wafers 104. In the illustrated embodiment, the imaging system 110 is positioned above the cleaving station 108 and images the wafers 104 after they are cleaved by the cleaving station. The imaging system 110 images each wafer 104, and a controller 112 analyzes the images to detect defects in the wafer. If a wafer 104 contains defects, the wafer is discarded before further processing, thereby reducing wafer manufacturing costs.

[0028] Referring to FIG. 2 , an alternative semiconductor wafer processing system 114 includes two or more manufacturing lines 102 for producing wafers 104. Similar to processing system 100, each manufacturing line 102 includes a processing station 106, including a cleaving station 108. The manufacturing lines 102 include a common location 116 where the manufacturing lines intersect. An imaging system 110 is disposed within the common location 116 and images the wafers 104 produced by all manufacturing lines 102 that intersect at the common location. In the illustrated embodiment, the processing system 114 includes two manufacturing lines 102. However, in alternative embodiments, the processing system 114 may include any number of manufacturing lines 102 that enables the processing system 114 to operate as described herein. Also, in the embodiment illustrated in FIGS. 1 and 2 , the imaging system 110 is disposed above or immediately downstream of the cleaving station 108. In alternative embodiments, imaging system 110 may be located anywhere within processing system 100, 114 that enables the processing system to operate as described herein.

[0029] 3 and 4, the imaging system 110 includes a dark box 118, an end effector 120, and a positioning plate 122. As described below, the dark box 118 includes a camera for imaging the wafer 104. The positioning plate 122 positions the dark box 118 at the common position 116, and the end effector 120 positions the wafer 104 below the dark box 118 for imaging. The positioning plate 122 is attached to a frame 124, and the dark box 118 is movably attached to the positioning plate. The position of the dark box 118 can be adjusted by adjusting the position of the dark box 118 on the positioning plate 122. The end effector 120 is also movable relative to the dark box 118 so that the position of the wafer 104 can be adjusted during imaging.

[0030] 5 , the shroud panel 126 defines the dark box 118. Specifically, the shroud panel 126 defines an upper chamber 128 and a lower chamber 130. A support plate 132 is disposed within the dark box 118 and separates the upper chamber 128 from the lower chamber 130. A bottom shroud 134 defines a bottom 136 of the dark box 118. The support plate 132 defines a support plate opening 138, and the bottom shroud 134 defines a bottom shroud opening 140. In the illustrated embodiment, both the support plate opening 138 and the bottom shroud opening 140 are circular in shape to correspond to the size and shape of the wafer 104. However, in alternative embodiments, the support plate opening 138 and the bottom shroud opening 140 may be any shape that enables the imaging system 110 to operate as described herein. Additionally, support plate opening 138 is aligned with bottom shroud opening 140 so that when a wafer is placed in bottom shroud opening 140, it is visible through a direct, unobstructed line of sight 142 from the wafer to upper chamber 128. Shroud panel 126 is preferably made of a black anodized aluminum panel to minimize reflections in dark box 118. In alternative embodiments, shroud panel 126 may be made of any material that enables dark box 118 to operate as described herein.

[0031] The dark box 118 includes an illumination panel 144 for directing diffused light toward the wafer 104. The illumination panel 144 is disposed in the lower chamber 130 and directs the diffused light through the bottom shroud opening 140 toward the wafer 104, which is located in the bottom shroud opening. The diffused light then reflects from the wafer 104 back into the upper chamber 128 through the support plate opening 138 and the bottom shroud opening 140. In the illustrated embodiment, the illumination panel 144 is rectangular, and the shape of the lower chamber 130 matches the shape of the illumination panel. In alternative embodiments, the illumination panel 144 may have any shape, including a circular and / or polygonal shape, that enables the semiconductor wafer imaging system 110 to operate as described herein.

[0032] 6 , the lighting panel 144 includes a frame 186, a light 188, and a transparent plate 190. The frame 186 is rectangular and conforms to the shape of the lower chamber 130. In the illustrated embodiment, the light 188 is a light-emitting diode (LED) light. In alternative embodiments, the light 188 may be any type of light that enables the semiconductor wafer imaging system 110 to operate as described herein. The light 188 is mounted to the frame 186 such that the light directs visible light in the horizontal direction 152 through the transparent plate 190. The transparent plate 190 includes a first edge 192, a second edge 194, a top surface 196, a bottom surface 198, and a reflector 200.

[0033] A light 188 directs light onto a first edge 192 of a transparent plate 190, where the light exits a second edge 194 or is directed by a reflector 200 through a bottom surface 198. The light 188 substantially surrounds the transparent plate 190 such that visible light emitted by the light is scattered throughout the transparent plate, traveling and reflecting in all directions parallel to the top surface 196 and bottom surface 198. The visible light remains within the transparent plate 190 until it is directed downward by a reflector 200. The top surface 196 is textured with a regular geometric array of reflectors 200 to direct a portion of the visible light emitted by the light 188 downward through the bottom surface 198. In the illustrated embodiment, the reflector 200 is formed in the transparent plate 190 and includes raised and / or recessed features, including holes and / or protrusions, that reflect, diffuse, and / or scatter visible light downward. For example, the raised features formed in the transparent plate 190 may include pyramidal or cone-shaped protrusions extending from the transparent plate, and the recessed features formed in the transparent plate 190 may include holes that allow some of the reflected light to pass through. The raised and recessed features are misaligned so that reflections from the features do not interfere with each other. When visible light strikes one of the reflectors 200, the visible light is scattered or reflected downward, intersects the bottom surface 198 at substantially normal incidence to avoid internal reflection, and exits the transparent plate 190. The reflector 200 scatters the visible light so that it is directed downward toward the wafer 104 as diffuse light.

[0034] The diffused light is reflected off the wafer 104 and returns upward through the transparent plate 190. Some of the reflected diffused light passes through the transparent plate 190 without hitting the reflector 200 and is imaged by the camera as described below. However, the reflected diffused light that hits the reflector 200 is scattered or refracted in a way that prevents the camera from imaging the scattered diffused light, producing an array of dark spots on the image of the wafer 104.

[0035] The dark box 118 includes a camera 146 for imaging the wafer 104. The camera 146 includes a monochrome digital camera for taking black-and-white digital photographs of the wafer 104. The camera 146 is disposed in the upper chamber 128 and images the wafer 104 through the support plate opening 138 and the bottom shroud opening 140. In the illustrated embodiment, the camera 146 is disposed proximate to a mirror 148 that reflects light reflected from the wafer 104 back to the camera, as described below. In an alternative embodiment, the dark box 118 may not include the mirror 148, and the camera 146 may be disposed in the upper chamber 128 so that it can directly image the wafer 104.

[0036] The dark box 118 is attached to the camera 146 and includes a slide lock 150 for positioning the camera in the upper chamber 128. The camera 146 is movably attached to the slide lock 150 to position and reposition the camera in the upper chamber 128. Specifically, as shown in FIGS. 5 and 7-10 , the slide lock 150 is oriented in a horizontal direction 152, and the camera 146 is slid horizontally to focus the camera on the wafer 104. In an alternative embodiment, the dark box 118 may not include the mirror 148 and slide lock 150, and the camera 146 may be oriented in a vertical direction 154. The slide lock 150 slides the camera 146 in the vertical direction 154 to focus the camera on the wafer 104. In an alternative embodiment, the camera 146 may have an adjustable focus, and the dark box 118 may not include the slide lock 150.

[0037] The mirror 148 includes a flat mirror 156 mounted on a mirror positioning system 158. The flat mirror 156 reflects the diffuse light reflected by the wafer 104 toward the camera 146, which positions the flat mirror 156 in the upper chamber 128. The mirror 148 redirects the diffuse light reflected by the wafer 104 from a vertical direction 154 to a horizontal direction 152, thereby allowing the camera 146 to be oriented horizontally and reducing the height 160 of the dark box 118. The mirror 148 therefore allows the semiconductor wafer imaging system 110 to be compact and located within the semiconductor wafer processing system 100.

[0038] The mirror positioning system 158 includes a base 162, a mirror holder 164, and a plurality of mirror screws 166. The mirror holder 164 is rotatably mounted to the base 162, and the screws 166 mount the flat mirror 156 to the mirror holder. Rotating the screws 166 adjusts the angle α of the flat mirror 156 relative to the camera 146. Rotating the screws 166 allows for fine adjustment of the angle α. In an alternative embodiment, the mirror positioning system 158 may include a slide similar to the slide lock 150.

[0039] The dark box 118 may optionally include a filter 168 disposed in the upper chamber 128. The filter 168 may be a polarizing filter, a color filter, a high-pass filter, and / or any other type of filter that enables the imaging system 110 to operate as described herein. The filter 168 is disposed either at a first position 170 on the camera 146 or at a second position 172 above the support plate opening 138. The filter 168 creates contrast between the wafer 104 and the surrounding environment, allowing the camera 146 to image the wafer. Specifically, the filter 168 reduces or eliminates reflections, allowing the camera 146 to image the wafer 104 rather than light or objects reflected by the wafer.

[0040] For example, when filter 168 is a polarizing filter, the filter uses polarization to create contrast between wafer 104 and the surrounding environment. As described above, light emitted from illumination panel 144 is diffuse light that reflects off the specular surface of wafer 104 and passes back through the light emitted from the illumination panel. Light reflected from other surfaces is reflected and scattered. Because scattered diffuse light is unpolarized and reflected light is polarized, filter 168 only allows transmission of the diffuse light reflected from wafer 104. Reflections from surrounding surfaces are reduced or not transmitted to camera 146. Reducing or eliminating reflections allows camera 146 to image wafer 104, rather than light or objects reflected from the wafer.

[0041] Similarly, when filter 168 is a color filter, the filter creates contrast between wafer 104 and the surrounding environment based on the wavelength of light reflected from the specular surface of wafer 104. Filter 168 selectively transmits different wavelengths of light. For example, filter 168 may transmit only long wavelengths (long pass), only short wavelengths (short pass), or a bandpass that blocks both longer and shorter wavelengths. Reflections from surrounding surfaces may have a predetermined wavelength, and filter 168 reduces or eliminates the reflections by absorbing light within the predetermined wavelengths. Reducing or eliminating the reflections allows camera 146 to image wafer 104 rather than light or objects reflected from the wafer.

[0042] Additionally, when filter 168 is a high-pass filter, filter 168 creates contrast between wafer 104 and the surrounding environment based on the wavelength of light reflected from the specular surface of wafer 104. Specifically, filter 168 transmits light having wavelengths of 600 nanometers (nm) or greater while absorbing light having wavelengths less than 600 nm. Reflections from surrounding surfaces may have wavelengths less than 600 nm, and filter 168 reduces or eliminates the reflections by absorbing light having wavelengths less than 600 nm. Reducing or eliminating the reflections allows camera 146 to image wafer 104 rather than light or objects reflected from the wafer.

[0043] The imaging system 110 includes an end effector positioner 174 that is attached to a dark box 118 and that calibrates (adjusts) a position 176 of the end effector 120. The end effector positioner 174 is removed from the dark box 118 after the position 176 of the end effector 120 has been calibrated. The end effector positioner 174 includes a dark box brace 178, an arm 180, and a puck 182. The end effector positioner 174 is attached to the dark box 118 before the imaging system 110 images the wafer 104. The puck 182 is attached to the arm 180, the arm and puck are attached to the dark box brace 178, and the arm, puck, and dark box brace are attached to the dark box 118. The dark box brace 178 and arm 180 are sized and shaped to position the puck 182 below the bottom shroud opening 140 within the field of view 184 of the camera 146. The end effector 120 is positioned so that the end effector is attached to the puck 182, and the controller 112 records and calibrates the position 176 so that the end effector positions the wafer 104 at the position 176 for each image. The end effector positioner 174 is removed from the dark box 118 after the position 176 has been calibrated.

[0044] Prior to manufacturing the wafer 104, the imaging system 110 is placed and calibrated in the processing system 100. Specifically, a positioning plate 122 is attached to a frame 124, and the imaging system 110 is attached to the positioning plate 122. More specifically, the dark box 118 is attached to the positioning plate 122.

[0045] The camera 146 and mirror 148 are positioned and calibrated in the dark box 118 when the imaging system 110 is positioned and calibrated in the processing system 100. Specifically, an operator positions the mirror 148 in the upper chamber 128 of the dark box 118 using the mirror positioning system 158. More specifically, the operator attaches the flat mirror 148 to the mirror holder 164 and attaches the mirror holder and flat mirror to the base 162. The operator also attaches the camera 146 to the slide lock 150 and positions the camera and slide lock in the upper chamber 128 of the dark box 118. The operator simultaneously adjusts the slide lock 150, the camera 146, and the flat mirror 156 to ensure that the camera's field of view 184 is centered in the bottom shroud opening 140. More specifically, the operator simultaneously adjusts the screw 166, rotates the mirror holder 164, and slides the camera 146 on the slide lock 150 to ensure that the camera's field of view 184 is centered within the bottom shroud opening 140.

[0046] The operator attaches the end effector positioner 174 to the dark box 118 by attaching the puck 182 to the arm 180, attaching the puck and arm to the dark box brace 178, and attaching the puck, arm, and dark box brace to the dark box. The end effector positioner 174 is attached to the dark box 118 so that the puck 182 is centered in the bottom shroud opening 140. The operator positions the end effector 120 so that the end effector is directly or indirectly attached to the puck 182. The controller 112 records and calibrates the position 176 of the end effector 120 so that the end effector positions the wafer at position 176 for each imaging. The operator removes the end effector positioner 174 from the dark box 118.

[0047] During operation, wafer processing system 100 at least partially produces wafers 104. Specifically, in the illustrated embodiment, cleaving station 108 cleaves wafer 104 and sends the wafer to imaging system 110 for imaging. More specifically, after cleaving station 108 cleaves wafer 104, end effector 120 positions wafer 104 below bottom shroud opening 140, and camera 146 generates an image 202 of wafer 104 (shown in FIG. 14; a schematic representation 203 of image 202 is shown in FIG. 13). Image 202 of wafer 104 is sent to controller 112 for analysis, as described below.

[0048] 13 and 14 , as shown in image 202 and schematic representation 203 of image 202, wafer 104 includes base 204 and transfer layer 206 deposited on the base. Base 204 has wafer boundary 208, and transfer layer 206 has transfer layer boundary 210. Wafer boundary 208 and transfer layer boundary 210 define terrace width 212 between wafer boundary 208 and transfer layer boundary 210. Wafer 104 also includes notch 222. Controller 112 detects base 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212 in image 202 and analyzes the detected areas for defects in wafer 104. Also, as described above, the placement of reflector 200 on top surface 196 of transparent plate 190 produces a regular geometric array of periodic artifacts (as shown by the crease pattern in image 202) in image 202. Specifically, reflector 200 produces a grid pattern of periodic artifacts 214 in image 202. The grid pattern of periodic artifacts 214 may include a regularly spaced periodic array of out-of-focus points, slight in-focus points, and / or dark spots.

[0049] The controller 112 includes a computer program 300 for imaging and analyzing wafers 104. FIG. 18 is a diagram of the computer program 300 for imaging and analyzing wafers 104. The computer program 300 includes an image capture module 302, a data management module 304, and a data analysis module 306. The image capture module 302 controls the semiconductor wafer imaging system 110 to position the wafer 104 within the bottom shroud opening 140, capture images 202 of the wafer, and return the wafer to the semiconductor wafer processing system 100 for further processing. The data management module 304 records identification information for each wafer 104, stores the images 202 for analysis, and notifies the data analysis module 306 when the images 202 are ready for analysis. The data analysis module 306 analyzes the images 202, determines whether the wafer is acceptable for further processing, and, if necessary, removes the wafer from the manufacturing process by controlling the semiconductor wafer processing system 100.

[0050] The computer program 300 may be a single program that includes all three modules, or it may be multiple programs that interact with each other. For example, in a first embodiment, the computer program 300 is a single program that includes all three modules. In this embodiment, the computer program 300 images and analyzes a wafer 104 before another wafer is imaged and analyzed. Modules 302-306 are executed sequentially before another wafer 104 is imaged and analyzed.

[0051] In a second embodiment, the computer program 300 includes a single program that executes the modules 302-306 discontinuously. For example, in this embodiment, the computer program 300 may execute the image capture module 302 and the data management module 304 sequentially, but may not execute the data analysis module 306 until multiple wafers 104 have been imaged, allowing the controller 112 to analyze the wafers in bulk. When there is an error in the data analysis module 306, the images 202 are saved by the data management module 304 for later analysis.

[0052] In a third embodiment, the computer program 300 includes multiple programs, each including one or more modules 302-306. In this embodiment, the modules 302-306 are separated into separate programs so that the modules 302-306 can be executed discontinuously. For example, a first computer program may include the image capture module 302 and the data management module 304, and a second computer program may include the data analysis module 306. The first and second computer programs may also execute on different controllers 112 or computing devices, allowing the controllers to execute the image capture module 302 and the data management module 304 without simultaneously analyzing the images 202. According to the third embodiment, the manufacturing process can continue even if the data analysis module 306 and / or the controller or computing device executing the data analysis module are temporarily unable to perform the analysis.

[0053] 19-21 are flow diagrams of a method for imaging and analyzing a wafer 104. Each module 302-306 performs a specific step of the method 400, and the modules may be performed discontinuously. The method 400 includes imaging 402 the wafer 104 using the semiconductor wafer imaging system 110, as described above. Specifically, imaging 402 the wafer 104 using the semiconductor wafer imaging system 110 includes positioning 404 the wafer 104 in the bottom shroud opening 140 using the end effector 120, directing 406 diffused light toward the wafer 104 using the illumination panel 144, reflecting 408 the diffused light off the wafer, and detecting 410 the diffused light with the camera 146 to generate an image 202 of the wafer.

[0054] The method 400 includes storing and transmitting 412 the images. The images 202 are transmitted to the controller 112, which analyzes the images before other wafers 104 are imaged. The controller 112 analyzes the images as soon as they are received from the camera 146. However, the controller 112 and / or the analysis may create a bottleneck in the manufacturing process. To reduce manufacturing time, the camera 146 may transmit the images along with the wafer identification number to the controller 112, and the controller may analyze the images as the wafers 104 progress through the manufacturing process.

[0055] The method 400 further includes analyzing 414 the wafer 104 using the controller 112 to detect defects in the wafer. The defects include voids (missing portions in the transfer layer 206 that do not intersect the transfer layer boundary 210), edge voids (missing portions of the transfer layer 206 that intersect the transfer layer boundary 210), asymmetric terrace widths 212, notch terrace widths that are too large or too small, alignment of the transfer layer 206 within the wafer 104, various metrics of terrace width area and symmetry, contamination (dark and / or light areas), and / or any other defects in at least one of the base 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212. As described above, the placement of the reflector 200 on the top surface 196 of the transparent plate 190 can cause a regular geometric array of periodic artifacts 214 in the image 202. Analyzing 414 the wafer 104 using the controller 112 to detect defects on the wafer to remove or reduce the periodic artifacts 214 may include applying 416 a software filter to the image 202 to remove or reduce the periodic artifacts 214.

[0056] The software filter may include a Fast Fourier Transform (FFT) to identify and remove periodic artifacts 214 from image 202. Specifically, because the grid pattern of periodic artifacts 214 is a regularly spaced, periodic array, the FFT decomposes image 202 into sine and cosine components, generating an output image 216 (shown in FIG. 17 ) in the Fourier or frequency domain while image 202 is in its spatial domain equivalent. The regular spacing of the grid pattern of periodic artifacts 214 allows the FFT to identify periodic artifacts 214 from image 202. In output image 216, each point represents a specific frequency contained in the spatial domain image or image 202. Specifically, the controller 112 generates 418 a raw FFT image 218 (shown in FIG. 15 ), detects 420 periodic artifacts 214 in the image 202, removes or reduces 422 the periodic artifacts 214 from the image, and converts 424 the image to an output image 216 (shown in FIG. 17 , with a schematic representation 217 of the image 216 shown in FIG. 16 ). Because the software filter is insensitive to translational position variations of the wafer, diffuser plate, and / or camera, and is essentially self-correcting to rotational position variations of the wafer, diffuser plate, or camera, the software filter improves the image 202 prior to its analysis to detect defects on the wafer 104.

[0057] At high magnification, periodic artifacts 214 are visible, caused by the placement of reflector 200 on top surface 196 of transparent plate 190. The grid pattern of periodic artifacts 214 can reduce the accuracy of the results of analysis 414. When image 202 is transformed into the frequency domain, periodic artifacts 214 appear as bright spots 228 on raw FFT image 218. By removing bright spots 228 in raw FFT image 218 and transforming raw FFT image 218 back to a spatial domain image, the grid pattern of periodic artifacts 214 can be removed from image 202.

[0058] The raw FFT image 218 is generated to enable visualization of the FFT analysis, and aspects of the raw FFT image 218 enable visualization of specific aspects of the FFT analysis. For example, the raw FFT image 218 is generated using a conventional FFT method and includes a central spot 224 and a pair of vertical axes 226. The size of the central spot 224 visually represents the period or distance between the periodic artifacts 214 in the image 202. The raw FFT image 218 also includes high-intensity spots 228, and the vertical axes 226 are aligned with the high-intensity spots 228. As shown in FIG. 14 , the grid pattern of the periodic artifacts 214 is diagonally oriented. The high-intensity spots 228 are oriented at the same angle as the orientation angle of the grid pattern of the periodic artifacts 214, and the pair of vertical axes 226 are oriented at the same angle as the high-intensity spots 228 and the grid pattern of the periodic artifacts 214. Thus, the raw FFT image 218 enables visualization of the FFT analysis.

[0059] Once output image 216 is generated, controller 112 analyzes the output image to detect defects in wafer 104. Specifically, controller 112 detects 426 base 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, terrace width 212, and notch 222 in output image 216. More specifically, controller 112 detects 428 wafer boundary 208 by segmenting and separating the wafer boundary in output image 216 and detects 430 transfer layer boundary 210 by segmenting and separating the transfer layer boundary in output image 216. Boundaries of transfer layer 206, notch 222, and voids in the transfer layer are segmented using various image processing techniques, including image blurring, gradient calculation, high-gradient edge detection, and contour calculation from edge detection. When boundaries are fuzzy or blurred, further processing is performed to enhance edge locations, and in some embodiments where output image 216 has incomplete or missing edges, an estimate of boundary closure is performed if possible. For example, when small edge segments are missing, edge boundary extrapolation may be used, and the detected edges may be smoothed to reduce noise introduced by the edge detection technique. If the controller 112 cannot estimate occlusion, the output image 216 is flagged for manual inspection.

[0060] After the base 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212 are detected in the output image 216, the controller 112 analyzes 432 the detected regions for defects. More specifically, the controller 112 analyzes 432 at least one of the base 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212 for defects. For example, the controller 112 detects 434 features of the at least one of the base 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212 and quantifies the detected features into quantified metrics. The controller 112 then compares 438 the quantified metrics to predetermined metrics and detects 440 defects in at least one of the base 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212 based on the comparison.

[0061] Specifically, detecting 434 characteristics of at least one of base 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212 and quantifying 436 the detected characteristics into quantified metrics includes detecting terrace width 212 and quantifying the detected characteristics of terrace width 212 into various global and local terrace width statistics. For example, in some embodiments, terrace width 212 is divided into twelve 30° segments around the edge of wafer 104, and the detected characteristics of terrace width 212 are quantified into local terrace width statistics based on each segment.

[0062] FIG. 22 illustrates a graphical user interface display 500 for use in calibrating the position of the end effector 120 (shown in FIG. 12) and / or wafer 104 relative to the camera 146 (shown in FIG. 9) through an image analysis process. The user interface display 500 displays a captured image 502 of the wafer 104 and centering meters 504-508. To calibrate the position of the end effector 120 and / or wafer 104 through image analysis, the end effector 120 is positioned below the bottom shroud opening 140 (shown in FIG. 5) and at least partially within the field of view 184 (shown in FIG. 9) of the camera 146. The camera 146 captures an image 502 of the wafer 104, which is transmitted to the controller 112. The controller 112 then analyzes the captured image 502 of the wafer 104 to determine whether the wafer 104 is within a predetermined positioning range and is properly centered within the field of view 184. When the controller 112 determines that the wafer 104 is not properly centered within the field of view 184, the wafer 104 and / or the end effector 120 are adjusted based on that determination. After the adjustment, a new image is captured and the controller 112 again determines whether the detected position of the wafer 104 is within the predetermined positioning range. The image analysis process may be used in conjunction with, or as an alternative to, the end effector positioner 174 described above with respect to FIG. 12 .

[0063] In operation, to determine whether the wafer 104 is properly centered within the field of view 184, the controller 112 captures an image 502 of the wafer 104 and detects the boundary 208 of the wafer 104, as described above with respect to Figures 14-21. The controller 112 then measures the distance on the captured image 502 between the edges 510-516 of the image 502 and the wafer boundary 208.

[0064] For example, for positioning along the X-axis, the controller 112 measures a first horizontal distance X1 from a first side edge 510 of the captured image 502 to the wafer boundary 208 and a second horizontal distance X2 from a second side edge 512 of the image 502 to the wafer boundary 208. The controller 112 then determines a delta X value corresponding to the difference between the first horizontal distance X1 and the second horizontal distance X2. For positioning along the Y-axis, the controller 112 measures a first vertical distance Y1 from a bottom wall 514 of the image 502 to the wafer boundary 208 and a second vertical distance Y2 from a top edge 516 of the image 502 to the wafer boundary 208. The controller 112 then determines a delta Y value corresponding to the difference between the first vertical distance Y1 and the second vertical distance Y2. For positioning along the Z-axis, the controller determines the smallest distance among X1, X2, Y1, and Y2 to determine the minimum gap of the wafer 104 from the edges 510-516 of the image 502. The controller 112 then compares the determined delta X, delta Y, and minimum gap values ​​with predetermined tolerances (e.g., as indicated by centering meters 504-508) to determine whether further adjustments of the wafer 104 and / or end effector 120 in the X, Y, or Z directions are necessary. Color-coded indicators 520 are provided on or near the image 502 on the user interface 500 to show the technician whether the wafer 104 is centered within its respective range along the X, Y, and Z axes. For example, the indicators 520 change color based on whether the delta X, delta Y, or minimum gap value, respectively, falls within its corresponding ideal, acceptable, or out-of-range range.

[0065] In the embodiment of FIG. 22, the centering meters 504-508 include an X-axis centering meter 504, a Y-axis centering meter 506, and a Z-axis or zoom centering meter 508. Each of the centering meters 504-508 indicates an ideal range, an acceptable range, and an out-of-range. The controller 112 projects the determined delta X value, delta Y value, and minimum gap value onto the X-axis centering meter 504, the Y-axis centering meter 506, and the Z-axis centering meter 508, respectively. As shown in FIG. 22, the delta Y value of the image 502 is equal to −20, which is within the ideal range of −20 to 20 on the Y-axis centering meter 506. The minimum gap value is equal to 25, which is within the ideal range of 20 to 40 on the Z-axis centering meter 508. The delta X value is equal to 130, which is outside the ideal and acceptable ranges on the X-axis centering meter 504. The positioning of the wafer 104 and / or end effector 120 is then adjusted (e.g., by a technician or by an automated positioning system in communication with the controller 112). In particular, the wafer positioning is adjusted based on the determined values ​​displayed on the centering meters 504-508. As an example, as shown in FIG. 22, based on the displayed results from the centering meters 504-508, the technician may move the wafer 104 to the left side of the page as shown in FIG. 22 to decrease the displayed delta X value. After the adjustment, an image is captured again, and the process is repeated until each of the delta X value, delta Y value, and minimum gap value are all within the acceptable and / or ideal ranges.

[0066] The semiconductor wafer imaging system described herein images a wafer to detect defects in the wafer during the manufacturing process. The imaging system images the wafer after the wafer is cleaved to detect defects in the wafer formed during the cleaving process. If the semiconductor wafer imaging system detects defects in the wafer, the wafer is removed from the manufacturing process, thereby reducing wafer manufacturing costs. The wafer has a specular reflective surface, and the semiconductor wafer imaging system images the wafer without imaging a light source reflected by the reflective surface. Specifically, the semiconductor wafer imaging system includes a dark box surrounding a camera and a light panel. The dark box minimizes reflections in the semiconductor wafer imaging system, and the light panel directs diffuse light toward the wafer. The diffuse light is reflected off the wafer toward the camera. Because the light generated by the light panel is diffuse, the camera detects the reflected diffuse light and does not image the light panel. Thus, the camera images the wafer, not the light source, which allows a controller to analyze the wafer for defects and reduces wafer manufacturing costs.

[0067] As used herein, the terms "about," "substantially," "essentially," and "approximately," when used in connection with a range of a dimension, density, temperature, or other physical or chemical property or characteristic, are meant to encompass variations that may exist at the upper and / or lower limits of the property or characteristic, including variations that result, for example, from rounding, measurement methods, or other statistical variations.

[0068] When introducing elements of the present disclosure or embodiments of the present disclosure, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," "containing," and "having" are intended to be inclusive and mean that additional elements may be present other than the listed elements. The use of specific orientation terms (e.g., "top," "bottom," "side") is for convenience of description and does not require a specific orientation of the described article.

[0069] Because various changes may be made in the structure and methods described above without departing from the scope of the present disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawings be interpreted as illustrative and not in a limiting sense.

Claims

1. 1. A semiconductor wafer imaging system for imaging a semiconductor wafer, comprising: a shroud panel defining a dark box; a camera disposed in the dark box for capturing an image of the semiconductor wafer; an illumination panel for directing diffused light onto the semiconductor wafer; Equipped with A portion of the diffused light is reflected by the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light.

2. a controller for analyzing images generated by the camera; The system of claim 1 , wherein the controller detects defects in the semiconductor wafer.

3. The system of claim 1 , further comprising a flat mirror that reflects the diffused light to the camera.

4. The system of claim 3 , wherein the shroud panel comprises a black anodized aluminum panel to minimize reflections within the dark box.

5. the shroud panel defines an upper chamber and a lower chamber; a support plate separating the upper chamber from the lower chamber; a bottom shroud panel at least partially defining the lower chamber and defining a wafer opening; the support plate defines a camera aperture; the diffused light is transmitted to the semiconductor wafer through the wafer opening; The system of claim 3 , wherein the reflected diffuse light is transmitted from the semiconductor wafer through the wafer aperture and the camera aperture to the camera.

6. The system of claim 5 , wherein the lighting panel is disposed in the lower chamber.

7. The system of claim 5 further comprising an end effector for placing the semiconductor wafer in the wafer opening.

8. an end effector positioner attached to the dark box and configured to calibrate the position of the end effector; The system of claim 7 , wherein the end effector positioner is removable from the dark box after the position of the end effector has been calibrated.

9. The system of claim 5 , wherein the camera and the plane mirror are disposed in the upper chamber.

10. The system of claim 9 further comprising a slide lock attached to the camera for positioning the camera in the upper chamber.

11. 10. The system of claim 9, further comprising a mirror positioning system attached to the flat mirror for positioning the flat mirror in the upper chamber.

12. The system of claim 9 , wherein a filter is disposed in the upper chamber, the filter covering the camera opening.

13. The system of claim 9 , wherein the camera has a filter attached thereto, the filter covering a lens of the camera.

14. The system of claim 1 , further comprising a positioning plate attached to the dark box for positioning the dark box.

15. 1. A dark box for imaging a semiconductor wafer, comprising: a shroud panel defining an upper chamber and a lower chamber, wherein a support plate separates the upper chamber from the lower chamber, a bottom shroud panel at least partially defines the lower chamber and defines a wafer opening, and the support plate defines a camera opening; a camera disposed in the upper chamber for imaging the semiconductor wafer; an illumination panel for directing diffused light onto the semiconductor wafer; Equipped with the diffused light is transmitted to the semiconductor wafer through the wafer opening; a dark box, wherein a portion of the diffused light is reflected by the semiconductor wafer through the wafer opening and the camera opening, and the camera captures an image of the semiconductor wafer by detecting the reflected diffused light.

16. the diffused light is transmitted to the semiconductor wafer through the wafer opening; The dark box of claim 15 , wherein the reflected diffuse light is transmitted to the semiconductor wafer through the wafer aperture and the camera aperture.

17. The dark box of claim 15 , wherein the illumination panel is disposed in the lower chamber.

18. 16. The dark box of claim 15, wherein the camera and the plane mirror are disposed in the upper chamber.

19. 20. The dark box of claim 18, further comprising a slide lock attached to the camera for positioning the camera in the upper chamber.

20. 20. The dark box of claim 18, further comprising a mirror positioning system attached to the plane mirror for positioning the plane mirror in the upper chamber.

21. 1. A semiconductor wafer processing system for processing semiconductor wafers, comprising: a semiconductor wafer processing station for processing the semiconductor wafer; a semiconductor wafer imaging system for imaging the semiconductor wafer; Equipped with the semiconductor wafer imaging system images the semiconductor wafer after the semiconductor wafer processing station processes the semiconductor wafer; the semiconductor wafer imaging system, a shroud panel defining a dark box; a camera disposed in the dark box for capturing an image of the semiconductor wafer; an illumination panel for directing diffused light onto the semiconductor wafer; Equipped with A portion of the diffused light is reflected by the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light.

22. the semiconductor wafer processing station comprises a cleaving station; 22. The system of claim 21, wherein the semiconductor wafer imaging system is positioned above the cleaving station.

23. 23. The system of claim 22, wherein the cleaving station is located upstream of the semiconductor wafer imaging system.

24. the semiconductor wafer imaging station further comprising:

22. The system of claim 21, wherein the semiconductor wafer imaging system is located at the semiconductor wafer imaging station.

25. The frame and a positioning plate attached to the frame; Further provided with 22. The system of claim 21, wherein the semiconductor wafer imaging system is attached to the positioning plate.

26. the semiconductor wafer imaging system is movably mounted on the positioning plate; 26. The system of claim 25, wherein the position of the semiconductor wafer imaging system is adjusted by adjusting the position of the semiconductor wafer imaging system on the positioning plate.

27. 26. The system of claim 25, further comprising an end effector attached to the frame for positioning the semiconductor wafer within the field of view of the camera.

28. 30. The system of claim 27, wherein the end effector receives the semiconductor wafer from the semiconductor wafer processing station.

29. 1. A semiconductor wafer processing system for processing semiconductor wafers, comprising: a first manufacturing line for processing a first semiconductor wafer, the first manufacturing line including a first semiconductor wafer processing station for processing the first semiconductor wafer; a second manufacturing line for processing a second semiconductor wafer, the second manufacturing line including a second semiconductor wafer processing station for processing the second semiconductor wafer, wherein the second manufacturing line intersects with the first manufacturing line at a common location; a semiconductor wafer imaging system for imaging the first semiconductor wafer and the second semiconductor wafer, the semiconductor wafer imaging system being disposed within the common location where the first manufacturing line and the second manufacturing line intersect, wherein the semiconductor wafer imaging system images the first semiconductor wafer and the second semiconductor wafer after the first semiconductor wafer processing station and the second semiconductor wafer processing station have processed the first semiconductor wafer and the second semiconductor wafer; Equipped with the semiconductor wafer imaging system, a shroud panel defining a dark box; a camera disposed in the dark box for capturing an image of the semiconductor wafer; an illumination panel for directing diffused light onto the semiconductor wafer; Equipped with A portion of the diffused light is reflected by the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light.

30. 30. The system of claim 29, wherein at least one of the first semiconductor wafer processing station and the second semiconductor wafer processing station comprises a cleaving station.

31. 31. The system of claim 30, wherein the cleaving station is located upstream of the semiconductor wafer imaging system.

32. a semiconductor wafer imaging station located within the common location where the first manufacturing line and the second manufacturing line intersect; 30. The system of claim 29, wherein the semiconductor wafer imaging system is located at the semiconductor wafer imaging station.

33. The frame and a positioning plate attached to the frame; Further provided with 30. The system of claim 29, wherein the semiconductor wafer imaging system is attached to the positioning plate.

34. the semiconductor wafer imaging system is movably mounted on the positioning plate; 34. The system of claim 33, wherein the position of the semiconductor wafer imaging system is adjusted by adjusting the position of the semiconductor wafer imaging system on the positioning plate.

35. 34. The system of claim 33, further comprising an end effector attached to the frame for positioning the first semiconductor wafer and the second semiconductor wafer within the field of view of the camera.

36. 36. The system of claim 35, wherein the end effector receives the semiconductor wafer from at least one of the first semiconductor wafer processing station and the second semiconductor wafer processing station.

37. 30. The system of claim 29, wherein the semiconductor wafer imaging system is positioned downstream of the first semiconductor wafer processing station and the second semiconductor wafer processing station and alternately images the first semiconductor wafer and the second semiconductor wafer from the first manufacturing line and the second manufacturing line.

38. 1. A semiconductor wafer imaging station of a semiconductor wafer processing system for imaging a semiconductor wafer, comprising: The frame and a positioning plate attached to the frame; a dark box movably attached to the positioning plate; End effector and Equipped with The dark box is a shroud panel defining the dark box; a camera disposed in the dark box for capturing an image of the semiconductor wafer; an illumination panel for directing diffused light onto the semiconductor wafer; Equipped with a part of the diffused light is reflected by the semiconductor wafer, and the camera captures an image of the semiconductor wafer by detecting the reflected diffused light; The end effector positions the semiconductor wafer within the field of view of the camera.

39. 39. The station of claim 38, wherein the position of the dark box is adjusted by adjusting the position of the dark box on the positioning plate.

40. 39. The station of claim 38, wherein the end effector is mounted to the frame and positions the semiconductor wafer within the field of view of the camera.

41. 1. A method for detecting defects in a semiconductor wafer, comprising: directing diffused light at the semiconductor wafer; reflecting the diffused light off the semiconductor wafer; detecting the diffused light with a camera to generate an image of the semiconductor wafer; Analyzing the image to detect defects in the semiconductor wafer. A method comprising:

42. Analyzing the image to detect defects on the semiconductor wafer includes: detecting a wafer boundary of the semiconductor wafer by segmenting and isolating the wafer boundary in the image; detecting a transfer layer boundary on the semiconductor wafer by dividing and separating the transfer layer boundary in the image; 42. The method of claim 41, comprising:

43. Analyzing the image to detect defects on the semiconductor wafer includes: analyzing the transferred layer of the semiconductor wafer in the image; Detecting defects in the transfer layer of the semiconductor wafer 43. The method of claim 42, comprising:

44. the wafer boundary and the transfer layer boundary define a terrace width between the wafer boundary and the transfer layer boundary; 43. The method of claim 42, wherein analyzing the image to detect defects in the semiconductor wafer further comprises analyzing the terrace widths to generate the terrace width statistics.

45. 43. The method of claim 42, wherein analyzing the images to detect defects in the semiconductor wafer further comprises quantifying the detected defects into quantified metrics.

46. 1. A method for processing a semiconductor wafer, comprising: cleaving the semiconductor wafer at a cleaving station; positioning the semiconductor wafer within a field of view of a camera; directing diffused light at the semiconductor wafer; reflecting the diffused light off the semiconductor wafer; detecting the diffused light with a camera to generate an image of the semiconductor wafer; Analyzing the image to detect defects in the semiconductor wafer. A method comprising:

47. Analyzing the image to detect defects on the semiconductor wafer includes: detecting a wafer boundary of the semiconductor wafer by segmenting and isolating the wafer boundary in the image; detecting a transfer layer boundary on the semiconductor wafer by dividing and separating the transfer layer boundary in the image; 47. The method of claim 46, comprising:

48. Analyzing the image to detect defects on the semiconductor wafer includes: analyzing the transferred layer of the semiconductor wafer in the image; Detecting defects in the transfer layer of the semiconductor wafer 48. The method of claim 47, comprising:

49. the wafer boundary and the transfer layer boundary define a terrace width between the wafer boundary and the transfer layer boundary; 48. The method of claim 47, wherein analyzing the image to detect defects in the semiconductor wafer further comprises analyzing the terrace widths to generate the terrace width statistics.

50. 48. The method of claim 47, wherein analyzing the images to detect defects in the semiconductor wafer further comprises quantifying the detected defects into quantified metrics.

51. 1. A method for processing a semiconductor wafer using a semiconductor wafer processing system including a processing station and a semiconductor wafer imaging station, comprising: processing the semiconductor wafer in the processing station; positioning the semiconductor wafer within a field of view of a camera of the semiconductor wafer imaging station; directing diffused light at the semiconductor wafer; reflecting the diffused light off the semiconductor wafer; detecting the diffused light with the camera to generate an image of the semiconductor wafer; Analyzing the image to detect defects in the semiconductor wafer. A method comprising:

52. Analyzing the image to detect defects on the semiconductor wafer includes: detecting a wafer boundary of the semiconductor wafer by segmenting and isolating the wafer boundary in the image; detecting a transfer layer boundary on the semiconductor wafer by dividing and separating the transfer layer boundary in the image; 52. The method of claim 51, comprising:

53. Analyzing the image to detect defects on the semiconductor wafer includes: analyzing the transferred layer of the semiconductor wafer in the image; Detecting defects in the transfer layer of the semiconductor wafer 53. The method of claim 52, comprising:

54. the wafer boundary and the transfer layer boundary define a terrace width between the wafer boundary and the transfer layer boundary; 53. The method of claim 52, wherein analyzing the image to detect defects in the semiconductor wafer further comprises analyzing the terrace widths to generate the terrace width statistics.

55. 53. The method of claim 52, wherein analyzing the images to detect defects in the semiconductor wafer further comprises quantifying the detected defects into quantified metrics.

56. 1. A method for processing semiconductor wafers using a semiconductor wafer processing system including a first manufacturing line and a second manufacturing line each including a processing station for processing semiconductor wafers, and a semiconductor wafer imaging station located within a common location where the first manufacturing line and the second manufacturing line intersect, comprising: i) processing a first semiconductor wafer at the processing station of the first manufacturing line; ii) positioning the first semiconductor wafer within a field of view of a camera of the semiconductor wafer imaging station; iii) directing diffused light at the first semiconductor wafer; iv) reflecting the diffused light off the first semiconductor wafer; v) detecting the diffused light with the camera to generate an image of the first semiconductor wafer; vi) analyzing the image to detect defects in the semiconductor wafer; vii) processing the second semiconductor wafer at the processing station of the second manufacturing line; viii) Repeating steps ii through vi to image the second semiconductor wafer. A method comprising:

57. Analyzing the image to detect defects on the semiconductor wafer includes: detecting a wafer boundary of the semiconductor wafer by segmenting and isolating the wafer boundary in the image; detecting a transfer layer boundary on the semiconductor wafer by dividing and separating the transfer layer boundary in the image; 57. The method of claim 56, comprising:

58. Analyzing the image to detect defects on the semiconductor wafer includes: analyzing the transferred layer of the semiconductor wafer in the image; Detecting defects in the transfer layer of the semiconductor wafer 58. The method of claim 57, comprising:

59. the wafer boundary and the transfer layer boundary define a terrace width between the wafer boundary and the transfer layer boundary; 58. The method of claim 57, wherein analyzing the image to detect defects in the semiconductor wafer further comprises analyzing the terrace widths to generate the terrace width statistics.

60. 58. The method of claim 57, wherein analyzing the images to detect defects in the semiconductor wafer further comprises quantifying the detected defects into quantified metrics.

Images