Interface, electronic device, and communication system

Abstract

To provide an interface, an electronic device, and a communication system that fully utilize the performance of an optical module.SOLUTION: An interface includes a general-purpose functional unit and one or more specialized functional units, the general-purpose functional unit includes one or more general-purpose functional modules and performs processing dependent on a media access control (MAC) rate, and the specialized functional unit includes one or more specific functional modules and performs processing independent of the MAC rate.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This application is This is a divisional application of Patent Application No. 2024-081258 filed on March 17, 2024. Patent application No. 2022-581367 filed on December 28, 2022 issue This is a divisional application of is 2 This application claims priority to Chinese Patent Application No. 202010605324.3, filed June 29, 2020, and Chinese Patent Application No. 202110049548.5, filed January 14, 2021. All of the above-mentioned patent applications are incorporated herein by reference in their entirety.

[0002] The present application relates to interfaces, electronic devices, and communication systems. [Background technology]

[0003] In the current evolution process of Ethernet interfaces, new interface speeds need to be compatible with previous electrical and optical interfaces with multiple speeds, but the logical layer solutions of Ethernet interfaces result in low utilization of the performance of the transmission medium. Summary of the Invention

[0004] The embodiments of the present application provide an interface, an electronic device, and a communication system. The technical solutions in the embodiments of the present application can fully utilize the performance of an optical module. According to a first aspect, the interface includes a functional part 1 and a functional part 2. The functional part 1 is configured to perform processing dependent on a medium access control (MAC) rate, and the functional part 2 is configured to perform processing independent of the MAC rate.

[0005] In some embodiments, the interface is an Ethernet interface.

[0006] In some embodiments, functional portion 1 includes a media independent interface.

[0007] In some embodiments, functional portion 1 includes a MAC module, a reconciliation sublayer (RS) module, and a coding and rate matching module in the physical coding sublayer (PCS).

[0008] In some embodiments, the functional portion 2 includes one or more functional units, and the one or more functional units include a first functional unit, and the first functional unit includes a transcoding module, a scrambling module, an alignment marker insertion module, a forward error correction (FEC) module, a physical medium attachment sublayer (PMA) module, and a physical medium dependent (PMD) module.

[0009] In some embodiments, functional portion 2 includes one PMA / PMD module and one or more functional units, the one or more functional units including a second functional unit, the second functional unit including a transcoding module, a scrambling module, an alignment marker insertion module, and a forward error correction (FEC) module, and the second functional unit is coupled to the PMA / PMD module.

[0010] In some embodiments, functional portion 2 includes concatenated first-level functional units and second-level functional units. The first-level functional units include one or more first-level subunits, at least one of which includes a transcoding module, a scrambling module, an alignment marker insertion module, a forward error correction (FEC) module, and a PMA module. The second-level functional units include one or more second-level subunits, at least one of which includes a PCS / FEC / PMA module and a PMD module.

[0011] In some embodiments, the data output by the FECs of multiple functional portions 2 is interleaved at the PMA layer.

[0012] In some embodiments, the FEC module included in at least one first-level subunit in the first-level functional unit is configured to perform Reed-Solomon (RS) (544,514) FEC encoding and / or decoding, and the FEC module included in at least one second-level subunit in the second-level functional unit is configured to perform BCH FEC encoding and / or decoding, Reed-Solomon forward error correction (RS FEC) encoding and / or decoding, polar FEC encoding and / or decoding, low-density parity-check forward error correction (LDPC FEC) encoding and / or decoding, concatenated forward error correction (CFEC) encoding and / or decoding, open forward error correction (OFEC) encoding and / or decoding, or Turbo product code (TPC FEC) encoding and / or decoding. Optionally, the FEC module included in the first-level subunit is an outer code FEC module.

[0013] In some embodiments, the interface includes an optical digital signal processor (oDSP).

[0014] In some embodiments, the FEC module is a concatenated FEC module, and the second level functional unit further includes an inner code encoding module configured to perform concatenated inner-code encoding on data entering the second level functional unit. Optionally, the second level functional unit further includes a decoding module configured to perform concatenated FEC inner-code decoding on data entering the second level functional unit.

[0015] In some embodiments, functional portion 1 includes a MAC module, a conditioning sublayer (RS) module, a coding and rate matching module in the physical coding sublayer (PCS), and a transcoding module.

[0016] In some embodiments, functional portion 2 includes one or more functional units, and the one or more functional units include a third functional unit, and the third functional unit includes a scrambling module, an alignment marker insertion module, a forward error correction (FEC) module, and a physical medium attachment sublayer (PMA) / physical medium dependent (PMD) module.

[0017] In some embodiments, functional portion 2 includes one or more functional units, and the one or more functional units include a fourth functional unit, and the fourth functional unit includes a transcoding module, a scrambling module, an alignment marker insertion module, a forward error correction (FEC) module, a physical medium attachment sublayer (PMA) module, and a physical medium dependent (PMD) module.

[0018] In some embodiments, functional portion 1 includes a MAC module, a regulation sublayer (RS) module, a coding and rate matching module in the physical coding sublayer (PCS), a transcoding module, and a scrambling module.

[0019] In some embodiments, functional portion 2 includes one or more functional units, and the one or more functional units include a fifth functional unit, and the fifth functional unit includes an alignment marker insertion module, a forward error correction (FEC) module, and a physical medium attachment sublayer (PMA) / physical medium dependent (PMD) module.

[0020] In some embodiments, the interface is an Ethernet interface with a speed of 800 Gb / s or 1.6 Tb / s.

[0021] In some embodiments, the transcoding is IEEE 802.3-2018 compliant 64B / 66B to 256B / 257B transcoding.

[0022] In some embodiments, the number of functional units included in functional portion 2 is 1, 2, 3, 4, 5, 8, or 16.

[0023] In some embodiments, functional part 2 is coupled to functional part 1 via a data block distribution module.

[0024] According to another aspect, an electronic device includes an interface according to any one of the preceding embodiments.

[0025] According to another aspect, a communication system includes a sending device and a receiving device, wherein the sending device and / or the receiving device are electronic devices.

[0026] In some embodiments, the interface includes a general-purpose functional unit and one or more specialized functional units: the general-purpose functional unit includes one or more general-purpose functional modules; and the specialized functional unit includes one or more specific functional modules.

[0027] In some embodiments, the interface is an Ethernet interface.

[0028] In some embodiments, the general-purpose functional unit includes a functional module that is closely dependent on a medium access control (MAC) rate.

[0029] In some embodiments, the special function unit includes a speed-dependent functional portion.

[0030] In some embodiments, the general-purpose functional unit includes a media-independent interface.

[0031] In some embodiments, the general-purpose functional units include a medium access control (MAC) unit, a coordination sublayer (RS) unit, and a coding and rate matching module in the PCS layer.

[0032] In some embodiments, the special function units include a transcoding unit, a scrambling unit, an alignment locking unit, a forward error correction (FEC) encoding / decoding unit, and a physical medium attachment sublayer (PMA) / physical medium dependent (PMD) unit.

[0033] In some embodiments, the specialized function unit includes multiple functional subunits and one PMA / PMD unit, each of which includes a transcoding subunit, a scrambling subunit, an alignment lock processing subunit, and an FEC subunit, and the multiple functional subunits are coupled to the PMA / PMD unit.

[0034] In some embodiments, the special function unit includes a first level and a second level. The first level includes one or more first-level subunits, each including a transcoding subunit, a scrambling subunit, an alignment lock subunit, an FEC subunit, and a PMA subunit. The second level includes one or more second-level subunits, each including a PCS / FEC / PMA subunit and a PMD subunit.

[0035] In some embodiments, the data output by the FECs of multiple special function units is interleaved at the PMA layer.

[0036] In some embodiments, the first level FEC is configured to perform RS(544,514) FEC encoding, and the second level FEC is configured to perform BCH FEC, polar FEC, LDPC FEC, CFEC, OFEC, or TPC FEC encoding.

[0037] In some embodiments, the interface includes an optical digital signal processor (oDSP).

[0038] In some embodiments, the FEC is a concatenated FEC, and the second level further includes an inner code decoding unit configured to perform concatenated code inner code decoding on the data entering the second level (the decoding is primarily an error correction function, and the overhead comes from removing the inner code encoding after the decoding is complete).

[0039] In some embodiments, the second level PCS / FEC / PMA is PCS / CFEC / OFEC / PMA.

[0040] In some embodiments, the general-purpose functional units include coding and rate matching modules in the MAC, RS, and PCS layers, and a transcoding module.

[0041] In some embodiments, the special function units include scrambling, AM, FEC, and PMA / PMD.

[0042] In some embodiments, the specialized functional unit includes a plurality of functional subunits, each of which includes a scrambling subunit, an alignment locking subunit, an FEC subunit, a PMA subunit, and a PMD subunit.

[0043] In some embodiments, the general-purpose functional units include a MAC unit, an RS unit, a coding and rate matching module in the PCS layer, a transcoding module, and a scrambling module.

[0044] In some embodiments, the special function units include an alignment lock unit, an FEC unit, and a PMA / PMD unit.

[0045] In some embodiments, the FEC subunit is an 800 Gb / s Ethernet interface.

[0046] 21. The interface according to claim 1, wherein the transcoding is 64B / 66B to 256B / 257B transcoding conforming to IEEE802.3-2018.

[0047] In some embodiments, the number of special function units included in the interface is 1, 2, 4, 5, 8, or 16.

[0048] In some embodiments, the general-purpose functional units are coupled to the specialized functional units via data block distribution modules.

[0049] According to another aspect, an electronic device includes an interface according to any one of the preceding embodiments.

[0050] According to another aspect, a network system includes a sending device and a receiving device, wherein the sending device and / or the receiving device are electronic devices.

[0051] According to another aspect, a computer-readable storage medium includes a computer-readable program or instructions that, when executed, enable an apparatus to perform the functions of an interface according to any one of the preceding embodiments.

[0052] According to another aspect, a computer program product includes computer readable programs or instructions that, when executed, enable a device to perform the functionality of an interface according to any one of the preceding embodiments.

[0053] According to another aspect, a transmission method includes a functioning step of an interface according to any one of the previous embodiments. [Brief explanation of the drawings]

[0054] [Figure 1] FIG. 1 is a schematic diagram of an interface configuration and communication. [Figure 2A] FIG. 10 is a schematic diagram of another interface configuration and communication. [Figure 2B-1] FIG. 10 is a schematic diagram of another interface configuration and communication. [Figure 2B-2] FIG. 10 is a schematic diagram of another interface configuration and communication. [Figure 3] FIG. 2 is a schematic diagram of the architecture of an interface according to one embodiment. [Figure 4A] FIG. 10 is a schematic diagram of the architecture of an interface according to another embodiment. [Figure 4B] FIG. 10 is a schematic diagram of the architecture of an interface according to another embodiment. [Figure 4C] FIG. 4B is a schematic diagram of a communication system including the interface of FIG. 4A. [Figure 4D] FIG. 4C is a schematic diagram of a communication system including the interface of FIG. 4B. [Figure 4E] 4B is a schematic diagram of a communication system including a transmitter-side device having the interface of FIG. 4A and a receiver-side device having an IEEE 802.3 standard interface. [Figure 4F] 4C is a schematic diagram of a communication system including a transmitter-side device having the interface of FIG. 4B and a receiver-side device having an IEEE 802.3 standard interface. [Figure 4G] FIG. 10 is a schematic diagram of the architecture of an interface according to yet another embodiment. [Figure 5A] FIG. 10 is a schematic diagram of the architecture of an interface according to yet another embodiment. [Figure 5B] FIG. 5B is a schematic diagram of a communication system including the interface of FIG. 5A. [Figure 6A] FIG. 10 is a schematic diagram of the architecture of an interface according to yet another embodiment. [Figure 6B] FIG. 6B is a schematic diagram of a communication system including the interface of FIG. 6A. [Figure 6C]FIG. 10 is a schematic diagram of the architecture of an interface according to yet another embodiment. [Figure 6D] FIG. 6D is a schematic diagram of a communication system including the interface of FIG. 6C. [Figure 7A] FIG. 10 is a schematic diagram of the architecture of an interface according to yet another embodiment. [Figure 7B] FIG. 7B is a schematic diagram of a communication system including the interface of FIG. 7A. [Figure 7C] FIG. 10 is a schematic diagram of the architecture of an interface according to yet another embodiment. [Figure 8] FIG. 1 is a schematic diagram of the architecture of an interface according to embodiment 1. [Figure 9] FIG. 10 is a schematic diagram of the architecture of an interface according to embodiment 2. [Figure 10] FIG. 10 is a schematic diagram of the architecture of an interface according to embodiment 3. [Figure 11] FIG. 10 is a schematic diagram of the architecture of an interface according to embodiment 4. [Figure 12A] FIG. 10 is a schematic diagram of the architecture of an interface according to embodiment 5. [Figure 12B] 4B is a schematic diagram of a communication system including a receiver device having an interface corresponding to the interface of FIG. 4A and a transmitter device having an IEEE 802.3 standard interface. [Figure 12C] 4C is a schematic diagram of another communication system including a receiving device having an interface corresponding to the interface of FIG. 4B and a transmitting device having an IEEE 802.3 standard interface. [Figure 12D] 5B is a schematic diagram of another communication system including a receiver device having an interface corresponding to the interface of FIG. 5A and a transmitter device having an IEEE 802.3 standard interface. [Figure 12E] 6B is a schematic diagram of another communication system including a receiver device having an interface corresponding to the interface of FIG. 6A and a transmitter device having an IEEE 802.3 standard interface. [Figure 12F] 6D is a schematic diagram of another communication system including a receiving device having an interface corresponding to the interface of FIG. 6C and a transmitting device having an IEEE 802.3 standard interface. [Figure 12G] 7B is a schematic diagram of another communication system including a receiver device having an interface corresponding to the interface of FIG. 7A and a transmitter device having an IEEE 802.3 standard interface. [Figure 13] 1 is a schematic diagram of the structure of the device according to one embodiment. [Figure 14] 1 is a schematic diagram of the structure of the device according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0055] In the embodiment, "functional part 1" is also referred to as "general-purpose functional part" or "general-purpose functional unit", "functional part 2" is also referred to as "special functional part", and "functional unit 2" is also referred to as "special functional part". Multiple functional units in "functional part 2" are also referred to as "special functional units". For example, "functional part 2" includes N functional units: a first functional unit, a second functional unit, ..., an nth functional unit, and the ith functional unit is also referred to as the ith special functional unit, where i is a positive integer, n is a positive integer greater than 1, and 1<=i<=n.

[0056] In this application, the media independent interface (official English name: media independent interface) for 10 Mb / s operation and 100 Mb / s operation is referred to as MII, the media independent interface for 1000 Mb / s operation is referred to as GMII, and the media independent interface for 10 Gb / s operation is referred to as XGMII. In this application, xMII refers to RMII (reduced MII), serial MII (SMII), serial synchronous MII (SSMII), source synchronous SMII (S3MII), gigabit MII (GMII), RGMII (reduced GMII), serial GMII (SGMII), ten bit interface (TBI), RTBI (reduced TBI), 10 gigabit MII (10 Gigabit MII, XGMII), 25 gigabit MII (25 Gigabit MII), 40 gigabit MII, 50 gigabit MII, 100 Gb / s MII (100 GB / s MII, CGMII), 200 Gb / s MII (200 GB / s MII, It can include multiple types of Ethernet interfaces such as 200Gb / s MII, 400Gb / s MII, 800Gb / s MII, and 1.6 Terabit MII.

[0057] The 200GbE / 400GbE speed standards implement a new generation of Ethernet speed standards based on single-lane electrical interface 50G four-level pulse amplitude modulation (PAM4) technology. Consideration of the next-generation 800GbE / 1.6TbE standard increases the single-lane electrical interface speed to 100G PAM4 or 200G PAM-N (using N-level pulse amplitude modulation PAM-N, where N = 4, 6, or 8). These next-generation speeds may support electrical interface speeds that may require compatibility with the current generation 50Gb / s lane electrical interface. The optical interface evolution path offers many possibilities with different speeds per wavelength. For example, each wavelength can carry a rate of 50Gb / s, 100Gb / s, 200Gb / s, 400Gb / s, or 800Gb / s.

[0058] In current solutions for the logical layer of Ethernet interfaces, the logical layers of interfaces with different rates share certain common characteristics and distinct differences. These differences make it difficult to share hardware resources between different-rate interfaces or to combine multiple low-speed Ethernet interfaces into one high-speed interface module for interworking. For example, a 200GbE / 400GbE interface uses the logical layer architecture shown in Figure 1. In Figure 1, the device interface includes a medium access control (MAC) layer, a reconciliation sublayer (RS), a physical coding sublayer (PCS), a forward error correction (FEC), a physical medium attachment sublayer (PMA), and a physical medium dependent (PMD) layer. Data from the transmitting device is processed and then sent from the PMD to the PMD of the receiving device, where it is processed by multiple submodules before reaching the MAC layer. The PCS is configured to perform functions such as 64B / 66B encoding and decoding, transcoding, scrambling, alignment marker (AM) insertion, FEC encoding and decoding, etc. The PMA sublayer is configured to perform functions such as clock recovery, carrier detection, PAM4 modulation / demodulation, etc. The PMD sublayer is configured to perform parallel-to-serial / serial-to-parallel conversion on received data and modulate the digital signal onto the line for transmission.In the FEC sublayer of the PCS layer, the introduction of a new interleaving FEC (e.g., Reed-Solomon RS (544, 514) FEC) will require significant redevelopment work due to significant differences between the logical layer of the new interleaving FEC and 100GbE solutions. As another example, the logical layer specified in 400G-ZR uses the architecture shown in Figures 2A, 2B-1, and 2B-2. In this logical layer architecture, an optical module supporting 400G-ZR (80km) cannot support a 2*200GbE interface because the host-side interface is fixed at 400G AUI (Attachment Unit Interface).

[0059] Research has shown that the logical layer changes caused by cross-generation Ethernet speeds are primarily in the PCS function. Above the PCS, the data output by the RS is very similar. Distinguishing similar parts from dissimilar parts and modularizing the dissimilar parts parallel to the data flow direction can achieve a high degree of resource reuse, reduce development costs, and provide economic benefits. According to an embodiment of the present application, the current Ethernet architecture is divided into two parts, functional part 1 and functional part 2, based on a specific rate-dependent functional part and a subrate-dependent functional part corresponding to a specific PMD. See FIG. 3 . Functional part 1 is a general-purpose functional part and includes functional modules closely dependent on the MAC rate, such as the RS module and modules required for rate matching. In some embodiments, functional part 1 further includes an xMII interface that is directly dependent on the rate. Functional part 2 includes a rate-independent functional part. For example, functional part 2 includes one or more functional units: functional unit 1, functional unit 2, ..., and functional unit n. Functional portion 2 may include PCS / PMA layer functionality that performs processing based on data flow. It is contemplated that the PMD is media dependent and may be used as part of functional portion 2 based on the specific implementation, or the PMD may be protocol independent and may be used as a functional component independent of functional portions 1 and 2.

[0060] Here, the reference criteria for selecting the boundary point between the two functional parts may include one or more of the following: (1) To save costs by selecting downward as much as possible so that there are as many general-purpose functional parts as possible after the emergence of cross-generation rates; (2) To simplify the design of data distribution between the two functional parts as much as possible and use small units for distributing data blocks; (3) To ensure that the units of functional part 2 have as complete functions as possible, including the verification functions necessary to ensure reliability; (4) To achieve an optimal design by comprehensively considering the complexity of specific implementations and the control of chip resources. Regarding (4), in some scenarios, such as ultra-high-speed connection scenarios, it is not appropriate to use a traditional parallel media independent interface as a connection functional interface.

[0061] 4A , in one embodiment, the interface includes functional portion 1, functional portion 2, and a data block distribution module located between functional portion 1 and functional portion 2. Functional portion 1 includes a MAC module, an RS module, and an encoding and rate matching module in the PCS layer. Functional portion 2 includes one or more functional units. Each of the one or more functional units includes multiple functional sub-modules, such as a transcode module, a scramble module, an alignment marker insertion (AM Insertion) module, an FEC module, and a PMA / PMD module.

[0062] For example, assume that each functional unit of functional portion 2 can process a MAC data flow at a corresponding speed of 200 Gbps. In the case of an 800 Gb / s Ethernet (official English name: 800 Gigabit Ethernet) MAC, functional portion 2 may include four functional units, each capable of processing a MAC data flow at a corresponding speed of 200 Gbps. The four functional units may be integrated or located separately. In the case of a 1 Tbps speed MAC module, functional portion 2 may include five functional units, each capable of processing a MAC data flow at a corresponding speed of 200 Gbps. The five functional units may be integrated or located separately. In the case of a 1.6 Tbps speed MAC module, functional portion 2 may include eight functional units, each capable of processing a MAC data flow at a corresponding speed of 200 Gbps. The eight functional units may be integrated or located separately.

[0063] In some embodiments, each functional unit of functional portion 2 can process a corresponding MAC data flow at a different speed, for example, 5 Gbps, 10 Gbps, 20 Gbps, 25 Gbps, 100 Gbps, 400 Gbps, 800 Gbps, 1 Tbps, or 1.6 Tbps.

[0064] In some other embodiments, functional portion 2 includes M functional units, N of which are active and configured to transmit data from the current MAC module. The N functional units include a first functional unit and a second functional unit, and the rate at which the first functional unit can process a corresponding MAC data flow is the same as or different from the rate at which the second functional unit can process a corresponding MAC data flow. For example, for an 800 GbE / s Ethernet MAC, functional portion 2 may include eight functional units: a, b, c, d, e, f, g, and h. Functional units a, b, c, and d are activated, and each of functional units a, b, c, and d can process a corresponding MAC data flow at a rate of 200 Gbps. Alternatively, functional units a, b, c, d, g, and h may be in an inactive state while functional units d, e, and f may be in an active state, and functional units d, e, and f may process corresponding MAC data flows at speeds of 200 Gbps, 200 Gbps, and 400 Gbps, respectively, where M and N are positive integers and M=>N=>1.

[0065] Starting from the top, the data obtained by encoding (such as 64B / 66B or 256B / 257B encoding) and rate matching is the first appropriate demarcation point because the data distributed at the demarcation point is in units of data blocks. Unlike the xMII interface, which achieves synchronous transmission by using data and a clock, the data blocks themselves have a sync header. Furthermore, the transmission rate of the data blocks obtained by rate matching is fixed, and the encoded data blocks can be distributed regularly. After performing round-robin distribution, the processing speed of the activated functional units in Functional Part 2 can be guaranteed to be constant, so there is no need for rate matching operations in Functional Part 2. To perform rate matching on an Ethernet interface, it is necessary to identify the data flow format, find packet boundaries, and insert or remove idle code blocks into or from the MAC interframe gap (IFG, also known as inter-frame gap, IPG, or inter-packet gap) for rate adjustment. The rate matching function is moved to Functional Part 1. The part dependent on the MAC rate is distinguished from the part dependent only on the intermediate rate but independent of the MAC rate.

[0066] In the interface of Figure 4A, because the PMA / PMD does not identify the protocol or data format, the PMA / PMD can exist across functional portions. The interface is shown in Figure 4B. For example, functional units in functional portion 2 that are active and configured to process data flows from the current MAC module, e.g., N of the M functional units, share one PMA / PMD module. In some embodiments, some of the N functional units could share a first PMA / PMD module and some could share a second PMA / PMD module, or some of the N functional units could share a first PMA / PMD module and each of the other functional units could use a separate PMA / PMD module.

[0067] 4G corresponds to one embodiment. An oDSP (Optical Digital Signal Processor) is integrated and encapsulated in a host chip. The data flow or data frame flow output by the oDSP is sent to a PMD, processed by the PMD, and then enters a laser, or the data flow or data frame flow output by the oDSP is modulated and used as a driving signal for a laser. The modulation can be completed by the oDSP or a separate modulator.

[0068] Optionally, functional part 2 may further include a new FEC encoding function (FEC encode x) to encode the data processed by the oDSP. The FEC encoding is RS FEC encoding. Secondary FEC encoding is performed after processing by the oDSP. The secondary FEC encoding may be BCH FEC or RS FEC encoding. FEC encode x may be configured by the oDSP or independently.

[0069] In some embodiments, functional portion 1 and functional portion 2 of FIG. 4A, FIG. 4B, or FIG. 4G may be integrated into the same chip.

[0070] In some embodiments, a communication system includes a sending device and a receiving device, where the sending device includes the interface of FIG. 4G and the interface included in the receiving device is an interface of any architecture. For example, in some embodiments, a communication system includes a sending device and a receiving device, where the sending device includes the interface of FIG. 7C and the interface included in the receiving device is an interface of any architecture, such as the interface of FIG. 4A, 4B, 4G, 5A, 6A, 7A, 7C, 8, 9, 10, 11, or 12A, or an IEEE 802.3 standard Ethernet interface.

[0071] For example, the interface of the sending device is the architecture of Figure 4B, see Figure 4D. The communication system includes a sending device and a receiving device.

[0072] Packets received by the interface of the sending device enter functional part 1 of the interface of the sending device.

[0073] In this embodiment, the functional part 1 of the interface of the transmitting device includes a MAC module, an RS module, and an encoding and rate matching module. Packets are processed by the MAC module, the RS module, and the encoding and rate matching module, and then enter a data block distribution module. Specifically, the data frame obtained by processing by the MAC module is converted into data of the corresponding bit width by the RS module (the width varies depending on the rate), and the data is sent to the encoding and rate matching module via the media independent interface MII for processing. The encoding and rate matching module processes the data sent from the MII to generate 64B / 66B blocks.

[0074] In one embodiment, the input data of the 100GbE PCS is parallel data in the 100G Ethernet Media Independent Interface (CGMII) format in the Regulation Sublayer (RS). The 400G Ethernet (abbreviated as 400GbE) interface converts the input data into the corresponding CDGMII format. The data format of the CDGMII interface is specifically described as follows: The bit width of the CDGMII interface is (64+8+2). The format of the CDGMII interface is 64 data bits, 8 control information indicator bits, and two clocks corresponding to transmission and reception. The 8 control information bits indicate whether the 64-bit, i.e., 8-byte, data represents data or control information. The data from the CDGMII is sent to the 64B / 66B encoding module for encoding.

[0075] After receiving the processed data blocks from the encoding and rate matching module, the data block distribution module in the sending device distributes the data blocks to N functional units in the functional part 2 of the sending device.

[0076] In this embodiment, each of the N functional units includes one or more PCS lanes. In some embodiments, one or more of the N functional units each include one or more PCS lanes.

[0077] In this embodiment, the data block distribution module distributes 64B / 66B blocks generated by processing by the encoding and rate matching module to the N functional units. In some embodiments, the data block distribution module distributes the 64B / 66B blocks to the N functional units one by one in a round-robin mode. For example, the data block distribution module distributes the first received 64B / 66B block to a first functional unit of the N functional units, the second received 64B / 66B block to a second functional unit of the N functional units, ..., the Nth received 64B / 66B block to an Nth functional unit of the N functional units.

[0078] In this embodiment, each of the N functional units includes a transcoding module, a scrambling module, an AM module, an FEC encoding module, and a PMA / PMD module. The transcoding module, scrambling module, AM module, and FEC encoding module in each functional unit perform corresponding processing on data blocks entering the functional unit. For example, the i-th functional unit among the N functional units sequentially performs transcoding, scrambling, AM insertion, and FEC encoding on data received from the data block distribution module, and sends the processed data to a receiving device via a PMA / PMD and a medium (e.g., a backplane or optical fiber). For example, the i-th functional unit transcodes blocks obtained by performing 64B / 66B encoding on the data flow. Specific formats of data transcoded by the transcoding module include 256B / 257B, 512B / 513B, 256B / 258B, or 512B / 514B. The specific transcoding method is not limited by the present application.

[0079] Specifically, the scrambling module scrambles the transcoded data flow. In some embodiments, full or partial scrambling can be performed at a specific granularity. Self-synchronizing scrambling (also called multiplicative scrambling) can be performed on the entire aggregated data flow, or synchronous scrambling (also called additive scrambling) can be performed at the FEC granularity, or self-synchronizing or synchronous scrambling can be performed at the PCS lane granularity. In the case of synchronous scrambling, the initial values ​​of the scrambling module and descrambling module can be set to ensure the performance of the entire system.

[0080] After the alignment marker insertion module inserts an alignment marker (AM) into the scrambled data flow, the data flow enters the FEC encoding module for FEC encoding. In some embodiments, the FEC encoding module can process the received data flow based on one or more encoding schemes, including Reed-Solomon (RS) (544,514) FEC, Bose-Chaudhuri-Hocquenghem (BCH) FEC, polar FEC, LDPC FEC, CFEC FEC, OFEC FEC, or TPC FEC. The data processed by the FEC encoding module passes through a PMA module and a PMD module in order to reach the transmission medium. The PMA module and the PMD module may be integrated into one functional module or may be located separately. The PMA module performs serial-to-parallel conversion on the received data and sends the converted data to the PMD module. The PMD module then converts the received signal to a corresponding transmission medium.

[0081] As shown in Figure 4D, in one embodiment, the architecture of the interface of the receiving device corresponds to the structure of the interface shown in Figure 4A. In this case, N data flows processed by functional portion 2 of the sending device enter functional portion 2 of the interface of the receiving device via a medium, and the N functional units in functional portion 2 of the interface of the receiving device correspond one-to-one to the N functional units in functional portion 2 of the interface of the sending device. The N functional units in functional portion 2 of the interface of the receiving device respectively receive the data transmitted by the N functional units in functional portion 2. Each of the N functional units in functional portion 2 includes a reverse transcode module, a descrambling module, an alignment marker removal (AM) module, an FEC decoding module, and an alignment lock module. For example, the i-th functional unit among the N functional units sequentially performs alignment marker alignment lock, FEC decoding, alignment marker removal, descrambling, and reverse transcoding on the data received from the PMA / PMD module, and the processed N data flows enter the data block distribution module of the interface of the receiving device. The data block distribution module of the interface of the receiving device sends the N data flows to functional part 1 of the interface of the receiving device. Functional part 1 of the interface of the receiving device includes a MAC module, an RS module, and a decoding and rate matching module. The decoding and rate matching module of the interface of the receiving device decodes the N data flows distributed by the data block distribution module, performs rate matching, and sends the data obtained by rate matching to the RS module. The data is processed by the RS module and reaches the MAC module of the interface of the receiving device.Optionally, the decoding and rate matching module of the receiving device interface performs rate matching on the N data flows, and the data resulting from the rate matching reaches the RS module of the receiving device interface via the xMII.

[0082] Please refer to Figure 4C. The communication system includes a sending device and a receiving device. The interface architecture of the sending device is shown in Figure 4A. The interface architecture of the receiving device corresponds to the interface architecture of Figure 4A. The process in which the interface of the sending device processes data and then sends the processed data to the interface of the receiving device, and the process in which the interface of the receiving device processes the received data are similar to the processes of the interface of the sending device and the interface of the receiving device in the communication system of Figure 4D. The details will not be described again here.

[0083] See FIG. 4E. The communication system includes a transmitting device and a receiving device. The transmitting device includes the interface shown in FIG. 4A, and the interface of the receiving device is an IEEE 802.3 standard Ethernet interface. The process by which the interface of the transmitting device processes data to be transmitted is similar to the operation of the interface of the transmitting device in FIG. 4C. Details will not be described again here. After the interface of the transmitting device processes the data, the N data flows processed by functional part 2 of the transmitting device enter the interface of the receiving device through the medium. The interface of the receiving device is an IEEE 802.3 Ethernet interface and includes a MAC module, an RS module, a decoding and rate matching module, a data block distribution module, a detranscoding module, a descrambling module, an alignment marker removal module, an FEC decoding module, and a PMA / PMD module. After the interface of the receiving device receives the data flow from the transmitting device through the medium, the data flow undergoes PMD / PMA processing, alignment marker alignment lock, FEC decoding, alignment marker removal, descrambling, and reverse transcoding in sequence, and then the processed data flow reaches the data block distribution module. The data block distribution module processes the received data flow. The data flow undergoes decoding, rate matching, and RS processing in sequence, and then the processed data flow reaches the MAC module. The MAC module processes the data flow and generates Ethernet frames.

[0084] Please refer to Figure 4F. The communication system includes a sending device and a receiving device. The sending device includes the interface shown in Figure 4B, and the interface of the receiving device is an Ethernet interface of the IEEE802.3 standard. The process by which the interface of the sending device processes data to be transmitted is similar to the operation of the interface of the sending device in Figure 4D. Details will not be described again here. The process by which the interface of the receiving device processes received data is similar to the processing process of the interface of the receiving device in Figure 4E. Details will not be described again here.

[0085] As shown in FIG. 5A , in one embodiment, the Ethernet interface includes functional portion 1, functional portion 2, and a data block distribution module located between functional portion 1 and functional portion 2. Functional portion 1 includes a MAC module, a conditioning module, and a coding and rate matching module. Functional portion 2 includes multiple functional units. For example, each functional unit includes multiple flows of PCS functions. The data block distribution module is included between functional portion 1 and functional portion 2. The data block distribution module accesses the multiple functional units in functional portion 2. The multiple functional units in functional portion 2 output through a PMA / PMD. In some embodiments, the multiple functional units in functional portion 2 may connect to a shared PMA / PMD.

[0086] Please refer to FIG. 5B. The communication system includes a transmitting device and a receiving device. The transmitting device includes an interface shown in FIG. 5A, and the receiving device includes an interface corresponding to the interface shown in FIG. 5A. The processing method of each module in functional part 1 of the interface shown in FIG. 5A is the same as that of functional part 1 of FIG. 4A. Details will not be described again here. Functional part 2 of FIG. 5A includes m flows of PCS functions, where m is an integer greater than or equal to 1. Each flow of the PCS functions includes a transcoding module, a scrambling module, an alignment marker insertion module, and an FEC encoding module. The processing method of these modules is the same as that of the corresponding module in FIG. 4A. The data block distribution module distributes data blocks from the encoding and rate matching module to the m flows of the PCS functions. After performing corresponding processing, the m flows of the PCS functions send the data of the m flows of the PCS functions to one PMA module. The data processed by the PMA module is distributed to one or more PMD modules, processed by the PMD module, and then sent to the transmission medium. In the solution of FIG. 5A , functional part 2 only has a transcoding module, a scrambling module, an alignment marker insertion module, and an FEC encoding module separately arranged, and the data output by the m flows of the PCS function is processed by a separate PMA module, thereby enabling more flexible data processing. The m data flows processed by functional part 2 of the transmitting device enter functional part 2 of the receiving device via a medium. Functional part 2 of the receiving device includes the m flows of the PCS function and a PMA and PMD shared by the m flows of the PCS function. The m data flows processed by functional part 2 of the transmitting device enter functional part 2 via a medium, are processed by the PMA and PMD of the receiving device, and then enter each of the m flows of the PCS function of the receiving device.The m flows of the PCS function in functional section 2 of the receiving device correspond one-to-one to the m flows of the functional units in functional section 2 of the transmitting device, and each flow of the functional unit includes a detranscoding module, a descrambling module, an alignment marker removal module, an FEC decoding module, and an alignment lock module. The m flows of the PCS function in functional section 2 of the receiving device each receive data transmitted by the m flows of the PCS function in functional section 2 of the transmitting device. For example, the ith flow of the PCS function among the m flows of the PCS function performs PCS processing on data received from the PMA. The data output after processing by the m flows of the PCS function in functional section 2 of the receiving device is processed by a data block distribution module and then enters functional section 1 of the receiving device. Functional section 1 of the receiving device sequentially performs decoding, rate matching, adjustment, and MAC processing on the data from the data block distribution module to obtain an Ethernet frame.

[0087] In some embodiments, the data distribution location within the interface may be different, as shown in Figures 6A and 6B. The transcoded data is used as the distribution boundary. In this case, the data is distributed at a post-transcoding granularity (e.g., 257 bits), and functional portion 2 processes the data flow at 257-bit granularity. In Figure 6A, the interface includes functional portion 1, functional portion 2, and a data block distribution module located between functional portion 1 and functional portion 2. Functional portion 1 includes a MAC module, an RS module, a PCS layer encoding and rate matching module, and a transcoding module. Functional portion 2 includes multiple functional units, each of which includes a scramble module, an alignment marker insertion module, an FEC encoding module, and a PMA / PMD module. Functional portion 1 is coupled to functional portion 2 via the data block distribution module and communicates with functional portion 2. The structure of the Ethernet interface in Figure 6A can be applied to a transmitting device. The functions of the functional modules in FIG. 6A, i.e., the MAC module, RS module, encoding and rate matching module, transcoding module, data block distribution module, scrambling module, FEC module, PMA module, and PMD module, are similar to those of the corresponding modules in FIG. 4A. Details will not be described again here. In FIG. 6A, functional section 1 includes a MAC module, RS module, and transcoding module. In the case of a transmitting device, after the transmitting device receives a packet, the packet enters functional section 1 of the transmitting device. The MAC module in functional section 1 processes the packet to form a data frame. The RS module converts the data frame into data of the corresponding bit width and sends the data to the encoding and rate matching module. The encoding and rate matching module processes the received data to generate a 64B / 66B block. The 64B / 66B block is transferred to the transcoding module.The transcoding module transcodes received data blocks, for example, transcoding blocks obtained by performing 64B / 66B encoding on a data flow. Specific formats of data transcoded by the transcoding module include 256B / 257B, 512B / 513B, 256B / 258B, or 512B / 514B. The specific transcoding method is not limited by this application.

[0088] The data block distribution module distributes the transcoded data flow to m flows of functional units included in the functional part 2, and each of the m flows of functional units includes a scrambling module, an alignment marker insertion module, an FEC encoding module, a PMA module, and a PMD module. The functions and operations of the scrambling module, alignment marker insertion module, FEC encoding module, PMA module, and PMD module in this specification are similar to the functions of the corresponding functional modules in FIG. 4A. The details will not be described again here. The data block distribution module distributing the transcoded data flow to the m flows of functional units included in the functional part 2 particularly includes the data block distribution module distributing the transcoded data flow to the m flows of functional units included in the functional part 2 in a round robin mode.

[0089] In some embodiments, in functional portion 2 of Figure 6A, each of the m flows of functional units includes a scrambling module, an alignment locking module, and an FEC encoding module. The FEC encoding modules in the m flows of functional units send FEC-processed data to one or more PMA modules. The data is processed by the one or more PMA modules and then sent to one or more PMD modules for processing. The one or more PMD modules send the processed data over a transmission medium to a receiving device.

[0090] As shown in FIG. 6B, the communication system includes a transmitting device and a receiving device. The transmitting device includes the interface shown in FIG. 6A, and the receiving device includes an interface corresponding to the interface shown in FIG. 6A. The interface of the receiving device includes functional portion 1, functional portion 2, and a data block distribution module located between functional portion 1 and functional portion 2. Functional portion 1 includes a MAC module, an RS module, a PCS layer decoding and rate matching module, and a transcoding module. Functional portion 2 includes multiple functional units, each of which includes a descrambling module, an alignment marker removal module, an FEC decoding module, an alignment lock module, and a PMA / PMD module. Functional portion 1 is coupled to functional portion 2 via the data block distribution module and communicates with functional portion 2. The functions of the functional modules of the interface module of the receiving device in Figure 6B, i.e., the MAC module, RS module, decoding and rate matching module, reverse transcode module, data block distribution module, descrambling module, alignment marker removal (AM Removal) module, FEC decoding module, alignment lock module, PMA module, and PMD module, are similar to the functions of the corresponding modules in Figure 4C, and the details will not be described again here.

[0091] In some embodiments, functional portion 1 and functional portion 2 of FIG. 6A can be integrated into the same chip.

[0092] See Figure 6C. In another interface structure, when scrambling is used as the distribution boundary, data may be distributed at multiple granularities, such as 1 bit and 10 bits. The interface includes functional part 1, functional part 2, and a data block distribution module located between functional part 1 and functional part 2. Functional part 1 is coupled to functional part 2 and communicates with it via data block distribution. Functional part 1 includes a MAC module, an RS module, a PCS layer encoding and rate matching module, a transcoding module, and a scrambling module. Functional part 2 includes an AM insertion module, an FEC encoding module, and a PMA / PMD module. Functional part 2 includes m flows of functional units, each of which includes an alignment marker insertion module, an FEC module, and a PMA / PMD module.

[0093] As shown in FIG. 6D, the communication system includes a transmitting device and a receiving device. The transmitting device includes an interface shown in FIG. 6C, and the receiving device includes an interface corresponding to the interface shown in FIG. 6C. The interface of the receiving device includes functional portion 1, functional portion 2, and a data block distribution module located between functional portion 1 and functional portion 2. Functional portion 1 includes a MAC module, an RS module, a PCS layer decoding and rate matching module, a detranscoding module, and a descrambling module. Functional portion 2 includes multiple functional units, each of which includes an alignment marker removal module, an FEC decoding module, an alignment lock module, and a PMA / PMD module. Functional portion 1 is coupled to functional portion 2 via the data block distribution module and communicates with functional portion 2. The functional modules of the receiving device in FIG. 6D, namely, the MAC module, RS module, decoding and rate matching module, detranscoding module, data block distribution module, descrambling module, alignment marker removal (AM removal) module, FEC decoding module, alignment lock module, PMA module, and PMD module, have the same functions as the corresponding modules in FIG. 4C. Details will not be described again here. In the transmitting device, the MAC module processes the received packets to obtain data frames and forwards the data frames to the RS module. The RS module converts the received data frames into data of the corresponding bit width and sends the converted data to the encoding and rate matching module. The encoding and rate matching module processes the data to generate 64B / 66B blocks. The transcoding module receives the data blocks processed by the encoding and rate matching module and transcodes the data blocks.Specific formats of data transcoded by the transcoding module include 256B / 257B, 512B / 513B, 256B / 258B, or 512B / 514B. The specific transcoding method is not limited in this application. The data flow transcoded by the transcoding module is scrambled by the scrambling module and then sent to the data block distribution module. The data block distribution module distributes the received data flow to m flows of functional units in the functional part 2 of the sending device, where m is an integer greater than or equal to 1. An alignment marker insertion (AM Insertion) module of each of the m flows of functional units adds an alignment marker (AM) to the received data flow and then sends the data flow to the FEC encoding module. The FEC encoding module performs FEC encoding processing on the received data flow and then sends the processed data flow to the PMA module. The data flow is sent to the transmission medium via the PMA module and the PMD module. The processing performed on the data flow by the alignment marker insertion module of the sending device is the insertion of an alignment marker called AM insertion. The data block distribution module distributing the received data flow to m flows of functional units in the functional part 2 of the sending device particularly includes the data block distribution module distributing the received data flow to m flows of functional units in the functional part 2 of the sending device by performing round robin distribution on the data flow scrambled at a specific granularity (e.g., 1 bit, 2 bits, 8 bits, or 10 bits).

[0094] In the receiving device, the receiving device receives, via a transmission medium, data flows transmitted by a transmitting device including the interface shown in FIG. 6C. The m data flows transmitted from the transmitting device enter m flows of functional units in functional part 2 of the receiving device, respectively. For each of the m flows of the functional units of the receiving device, a PMD module converts the received data, which conforms to the transmission format of the transmission medium, into data conforming to the format of the receiving device and sends the data to a PMA module. The PMA module performs parallel-to-serial conversion on the received data and sends the converted data to an alignment lock module. The aligned data enters an FEC decoding module. The FEC decoding module performs FEC decoding on the data and removes the alignment marker, and the data is then sent to a data block distribution module. The data block distribution module sends the received m data flows to a descrambling module in functional part 1 of the interface of the receiving device. The descrambling module descrambles the received data and then sends the data to a transcoding module. The transcoding module performs inverse transcoding on the received data, transcoding data in formats such as 256B / 257B, 512B / 513B, 256B / 258B, and 512B / 514B into 64B / 66B code blocks. The inverse transcoding module sends the generated 64B / 66B code blocks to the decoding and rate matching module. The decoding and rate matching module processes the 64B / 66B blocks to obtain data of the corresponding bit width and sends the corresponding bit width data to the RS module. The RS module processes the corresponding bit width data to obtain data frames and sends the data frames to the MAC module for processing. The MAC module processes the data frames to obtain packets sent by the transmitting device.The process of removing alignment markers from the received data flow by the alignment marker removal (AM Removal) module of the receiving device is also called AM removal, the process performed by the RS module of the receiving device on data of the corresponding bit width is called reconciliation, and the process of FEC decoding performed by the FEC decoding module of the receiving device on the data flow is called FEC decoding.

[0095] In some embodiments, the transmitter device includes the interface shown in FIG. 6A or 6C, and the receiver device includes an IEEE 802.3 standard interface. The m data flows processed by the transmitter device enter the receiver device via a medium. The PMA of the interface of the receiver device converts the m received data flows into data. The PMA module performs serial-to-parallel / parallel-to-serial conversion on the data, and then sends the data to the alignment marker removal module. The aligned data enters the FEC decoding module. The FEC decoding module performs FEC decoding on the received data and sends the data to the descrambling module. The descrambling module descrambles the received data and sends the data to the transcoding module. The transcoding module transcodes the received data. Specific formats of the data transcoded by the transcoding module include 256B / 257B, 512B / 513B, 256B / 258B, or 512B / 514B formats. The specific transcoding format is not limited by this application. The blocks resulting from the inverse transcoding are processed sequentially by a data block distribution module, a decoding and rate matching module, and an RS module, before reaching a MAC module. In some embodiments, the RS module is connected to the decoding and rate matching module via an M1I.

[0096] In some embodiments, in the m flows of functional units in functional portion 2 of Figures 6A to 6D, each flow of functional units may not include a PMA module or a PMD module, and the m flows of functional units share one PMA module and one PMD module.

[0097] In some embodiments, the functional portion 2 of the interface in the embodiments of the present application can be expanded, and the functional portion 2 can include two or more levels of functional portion 2. For example, in FIG. 7A, two levels of functional portion 2 are used to realize FEC concatenation and extend the transmission distance. Functional portion 1 includes encoding and rate matching functional units in the MAC, RS, and PCS layers. Functional portion 2 includes two levels. The first level includes multiple first-level functional units. Each first-level functional unit includes a transcoding module, a scrambling module, an alignment marker insertion module, an FEC encoding module, and a PMA module. The second level includes multiple second-level functional units, and the second-level functional units correspond one-to-one to the first-level functional units. Each second-level functional unit includes a PCS / FEC / PMA module and a PMD module. Functional portion 1 is coupled to and communicates with functional portion 2 via a data block distribution module.

[0098] The interface shown in FIG. 7A includes functional portion 1, functional portion 2, and a data block distribution module. Functional portion 2 includes m flows of first-level functional units and m flows of second-level functional units, with the m flows of the second-level functional units corresponding one-to-one to the m flows of the first-level functional units. Functional portion 1 includes a MAC module, an RS module, and an encoding and rate matching module. Each first-level functional unit includes a transcoding module, a scrambling module, an alignment lock module, an FEC encoding module, and a PMA module. Each second-level functional unit includes a PCS module, an FEC module, and a PMA / PMD module.

[0099] As shown in FIG. 7B, the communication system includes a transmitting device and a receiving device. The transmitting device includes an interface shown in FIG. 7A, and the receiving device includes an interface corresponding to the interface in FIG. 7A. In the transmitting device, a MAC module processes a received packet flow to obtain a data frame and forwards the data frame to an RS module. The RS module converts the received data frame into data of a corresponding bit width and sends the converted data to an encoding and rate matching module. The encoding and rate matching module processes the data to generate a data block, e.g., a 64B / 66B block, and sends the data block to a data block distribution module. The data block distribution module receives the data block processed by the encoding and rate matching module and distributes the data block to m flows of first-level functional units in functional part 2 of the transmitting device, where m is a positive integer greater than or equal to 1. The method by which the data block distribution module distributes the data block to m flows of first-level functional units in functional part 2 and the functions of each module of each flow of the first-level functional units is the same as that in the previous embodiment. The details will not be described again here. The m data flows processed by the transmitting device enter the receiving device via a medium. The second-level functional units, first-level functional units, data block distribution module, decoding and rate matching module, RS module, and MAC module of the interface of the receiving device sequentially process the m received data flows to obtain Ethernet frames. Specifically, the m flows of data processed by the transmitting device travel via a medium to m flows of second-level functional units corresponding to the interface of the transmitting device in the second-level functional units. The PMD module and PCS / FEC / PMA module in each flow of the functional units convert the received data into data. The data enters each flow of the corresponding first-level functional units in the first-level functional units.The PMA module in each flow of the first-level functional unit performs serial-to-parallel / parallel-to-serial conversion on the received data and sends the converted data to the FEC decoding module. The FEC decoding module performs FEC decoding on the received data. The data obtained by FEC decoding is sequentially processed by an alignment marker removal (AM removal) module, a descrambling module, and a transcoding module, and then reaches the data block distribution module. The alignment marker removal module removes alignment markers from the data. The descrambling module descrambles the data with the alignment markers removed. The descrambled data reaches the detranscoding module. The detranscoding module performs detranscoding on the received data. Specific formats of the data transcoded by the transcoding module include 256B / 257B, 512B / 513B, 256B / 258B, or 512B / 514B. The specific transcoding method is not limited in this application. The transcoded blocks are processed sequentially by a data block distribution module, a decoding and rate matching module, and an RS module, and then reach a MAC module. In some embodiments, the RS module is connected to the decoding and rate matching module via an M1I.

[0100] See Figure 7C. The second-level functional unit further includes an integrated package oDSP (Optical Digital Signal Processor). The output of the PMA of the second-level functional unit enters the oDSP. The data flow or data frame flow output after processing by the oDSP is sent to the PMD, processed by the PMD, and then enters the laser. Alternatively, the data flow or data frame flow output by the oDSP is modulated and used as the driving signal for the laser without the need to pass through the PMD module. The modulation can be completed by the oDSP or a separate modulator.

[0101] Optionally, the oDSP may further include a new FEC encoding function (FEC encode x) to encode data processed by the oDSP. The FEC encoding at the first level functional unit is RS FEC encoding. The secondary FEC encoding is performed after processing by the oDSP. The secondary FEC encoding may be BCH FEC or RS FEC encoding.

[0102] Optionally, the second-level functional unit may further include an FEC decoding module. The FEC decoding module decodes the data flow or data frame flow encoded by the FEC encoding module in the first-level functional unit, and the decoded data flow enters the FEC encoding x of the oDSP in the second-level functional unit for secondary FEC encoding. The FEC decoding module may be located in the first-level functional unit or the second-level functional unit. The FEC encoding x may be configured by the oDSP or independently.

[0103] In some embodiments, a communication system includes a sending device and a receiving device, where the sending device includes the interface of Figure 7C and the interface included in the receiving device is an interface of any architecture, for example, the interface of Figure 4A, Figure 4B, Figure 7A, or Figure 7B, or an Ethernet interface of the IEEE 802.3 standard.

[0104] In some embodiments, a communication system includes a sending device and a receiving device, where the sending device includes the interface of Figure 7C and the interface included in the receiving device is an interface of any architecture, for example an Ethernet interface of Figure 4A, 4B, 4G, 5A, 6A, 7A, 7C, 8, 9, 10, 11, or 12A, or an IEEE 802.3 standard.

[0105] 3 to 7, in the diagrams of each group of functional units in the functional section 2, each block diagram represents only the function, not the number of circuits and modules that perform the function. For example, an FEC function may include multiple FEC encoders / decoders. Data obtained by FEC encoding is not necessarily output via a single lane, but is output via multiple virtual lanes (or PCS lanes).

[0106] The following describes in detail the technical solutions in the embodiments of the present application based on a specific MAC rate.

[0107] Embodiment 1: Functional part 2 includes a group of functional units that support a MAC rate of 800 Gb / s.

[0108] Figure 8 is a schematic diagram of a possible 800GE interface structure. The interface includes functional part 1, functional part 2, and a data block distribution module located between functional part 1 and functional part 2. Functional part 1 includes a MAC module, an RS module, and an encoding and rate matching module. Functional part 2 includes a transcoding module, a scrambling module, an alignment lock module, an FEC encoding module, a PMA module, and a PMD module. The FEC encoding module is configured to perform FEC encoding on the data flow. 64B / 66B-encoded 66-bit data blocks are output. These data blocks enter functional part 2 in their original order via data block distribution, and undergo the processing steps of functional part 2 one by one. Functional part 2 includes one or more groups of functional units. Each group of functional units includes a transcoding module, a scrambling module, an AM insertion module, an 800G FEC module, a PMA module, and a PMD module. The transcoding in this specification may be 64B / 66B to 256B / 257B transcoding, the same as IEEE802.3-2018. AM insertion may be the same AM insertion method as in 200GE / 400GE interfaces. FEC coding may be Reed-Solomon RS-FEC, which encodes and interleaves multiple code blocks. After encoding, data is interleaved based on FEC symbols (10-bit symbols) and distributed to multiple PCS lanes. Then, bit-muxing (bit multiplexing) is performed in the PMA layer to enable adaptation to multiple types of PMD.

[0109] In some embodiments, the functional part 2 may include multiple functional units, each of which includes a transcoding module, a scrambling module, an alignment marker insertion module, an FEC encoding module, a PMA module, and a PMD module. For specific implementations, please refer to the previous embodiments. The interface shown in FIG. 8 can be applied to a transmitting device. For data processing methods of the transmitting device, please refer to the previous embodiments.

[0110] Embodiment 2: Functional part 2 includes two groups of functional units, and the 1.6TbE interface is realized using the technology of embodiment 1.

[0111] Based on the interface architecture shown in FIG. 8, a 1.6 Tb / s Ethernet MAC can be supported by implementing functional units in two groups in functional part 2, as shown in FIG. 9. The MAC module, RS module, and encoding and rate matching module are located in functional part 1 and are similar in function to embodiment 1, but at double the rate. The data block distribution module distributes encoded 66-bit data blocks to the two groups of functional units in functional part 2 in round-robin mode. Therefore, the execution rate and execution method of each group of functional units are the same as those in embodiment 1. The PMA layer can perform simple bit-level operations across functional units, i.e., bit-muxing two portions of data to support multiple types of PMD.

[0112] Embodiment 3: Functional part 2 is concatenated to perform FEC concatenation.

[0113] In Figure 10, functional section 1 includes a MAC function, an RS function, and encoding and rate matching functions. 66-bit data blocks encoded based on 64B / 66B are output. These data blocks enter functional section 2 in their original order via data block distribution, and the processing steps of functional section 2 are performed one by one. Functional section 2 includes a first level and a second level, and the functional units in the two levels are different. For example, the first level of "functional section 2" includes multiple groups of functional units, each of which includes multiple functional submodules, such as a transcoding submodule, a scrambling submodule, an alignment marker insertion submodule, an FEC encoding submodule, and a PMA submodule. Data processed by the first level enters the second level. In the "concatenated functional section 2," i.e., the second level, a second-level FEC encoding operation can be performed on the output data flow from the upper layer. The second level includes functional units that correspond one-to-one to those in the first level, each of which includes a PCS / FEC / PMA and a PMD. The function of the second level of the functional unit 2 is to process data transmitted from the two upper layers without needing to understand the protocol of the MAC data in the first level of the functional unit 1. A typical scenario of this application may be a scenario in which a host chip (host ASIC) is externally connected to an optical digital signal processor (oDSP). The second level of the functional unit 2 does not terminate the FEC of the upper layer, but can directly perform FEC encoding at the second level. For example, the first level of the FEC may be RS (544,514) FEC encoding, and the second level of the FEC may be one or more of BCH code (Bose-Chaudhuri-Hocquenghem code) FEC, polar FEC, low density parity check (LDPC) FEC, concatenated FEC (CFEC), open FEC (OFEC), turbo product code (TPC) FEC, and source coding FEC (SCFEC).

[0114] Embodiment 4: Functional part 2 is concatenated to perform FEC concatenation.

[0115] As shown in Figure 11, similar to embodiment 3, in some scenarios, stronger FEC protection may be required between two functional parts 2. As shown in Figure 11, the upper layer functional part 2 already includes a concatenated FEC, and RS+BCH concatenation is used. However, in the concatenated functional part 2, due to data overhead limitations and SerDes rate limitations, the inner code of the concatenated FEC may need to be removed first, and then encapsulation is performed by a stronger FEC frame in the oDSP. In this case, the concatenated functional part 2 does not need to perform operations on the data flow corresponding to the MAC rate of functional part 1, and only processes the data flow corresponding to the rate of one functional unit in the upper layer functional part 2.

[0116] According to the technical solution of the present application, the multi-flow parallel processing of the functional part 2 can replicate one flow of the functional unit into multiple flows of the functional unit, and any rate can be realized by the combination of the functional units, which ultimately realizes the reuse of the investment of the functional units and greatly reduces the cost of the Ethernet interface.

[0117] In some embodiments, the Ethernet interface is divided from a logical layer architecture into two layers of functional parts: functional part 1, which performs processing based on the total data rate of a particular interface, and functional part 2, which performs processing based on a subset (portion of the total data rate) of the particular interface speed. Functional part 2 includes at least one functional unit. In some embodiments, functional part 2 includes two or more functional units.

[0118] In some embodiments, functional part 1 completes data processing based on a specific total data rate and includes a 64 / 66B encoding / decoding sublayer that is subordinate to the MAC sublayer, RS sublayer, and PCS sublayer in the current Ethernet standard. Functional part 1 may further include a transcoding sublayer, a scrambling / descrambling sublayer, or a complete PCS / FEC / PMA sublayer for a specific total data rate, according to different embodiments.

[0119] In some embodiments, functional portion 1 distributes data to functional units subordinate to functional portion 2 in a round-robin mode based on a specific rule or sequence, and data blocks that do not reflect the contents of a packet format for a specific interface speed are obtained by distribution. The granularity of the data blocks can be bits, 64 / 66B, 256 / 257B after transcoding, another different transcoded data format, FEC symbols, or a combination thereof.

[0120] In some embodiments, each functional unit of functional portion 2 performs PCS / FEC / PMA layer processing on data blocks from functional portion 1, as required for further data transmission. However, the specific interface speed information of functional portion 1 does not need to be known for processing. Briefly, it is understood that each functional unit only considers information about the data received from that functional unit, re-interleaves and re-combines it to form data blocks, and then performs PCS / FEC / PMA layer processing based on the data blocks. Content information that can be reflected only by sensing the total data rate data of functional portion 1 does not need to be processed in complex processing, and processing is performed without the need to recover or sense specific information (Idle and Preamble / SFD) of the Ethernet data frame of functional portion 1. Furthermore, only bit-level data re-combination or interleaving and distribution is optionally performed between different functional units at the PMA layer; interaction based on sensing information obtained through multi-bit combinations does not need to occur between multiple functional units.

[0121] In some embodiments, each functional unit of functional portion 2 operates independently and no longer needs to restore some or all of the functionality of functional portion 1 for a particular interface speed, for example, functional portion 2 no longer performs unified coordination of Idle insertion or deletion with functional portion 1, or no longer performs AM identification with functional portion 1, or no longer restores the corresponding data after realignment.

[0122] In some embodiments, each functional unit of functional portion 2 corresponds to a PMD physical layer subordinate to that functional unit. In this way, theoretically, any number of functional units can be combined to form a physical layer solution required by an Ethernet interface matching a particular rate, realizing a rate-independent Ethernet architecture.

[0123] In some embodiments, the interface in the present application is a separate chip or functional module located on another device.

[0124] In some embodiments, the interface in the embodiments of the present application is located on a network device, a workstation, a storage device, or a server.

[0125] In some embodiments, a workstation may be various types of devices, such as a host, a terminal, a server, or a virtual machine. A network device may be a device configured to forward packets in a communication network, such as a switch or a router. Also, network devices within the same communication network may be the same network device or different network devices. For example, all network devices within the same communication network may be routers, some network devices may be routers, and other network devices may be switches.

[0126] For the non-breakout scenarios of Figures 1 to 11 in the present application, the process of inserting alignment markers requires collaborative insertion among multiple functional units (e.g., insertion based on bit intervals or code block intervals), so that the receiving side can perform data block recovery operations based on the distribution sequence of the distribution unit on the transmitting side.

[0127] Example 5: Breakout Scenario

[0128] In a breakout scenario, a high-capacity port is split via a physical channel to support multiple lower-speed ports or interfaces. For example, a 400 GbE port supporting breakout on a switch can support four 100 GbE ports or eight 50 GbE ports via breakout cables, fanout cables, or modules. In this application, functional part 2 naturally supports multi-flow parallelism, which provides an inherent advantage in supporting breakout scenarios. For example, if functional part 1 already has a 1.6 TbE MAC and functional part 2 has eight functional unit flows, each supporting 200 Gb / s of data throughput, a 2*800 GbE breakout can be implemented in the architecture with minor changes, as shown in FIG. 12A. In this case, functional part 1 includes a 1.6 TbE functional unit that is split into two 800 GbE functional units, each of which is a standard 800 GbE MAC. The eight functional units in functional part 2 remain unchanged. Only the final data aggregation mode is changed: one output flow is changed to two output flows, each of which is a standard 800GbE physical port.

[0129] In a breakout scenario, each unit carries its own Ethernet data flow. The alignment marker insertion process is adaptive; there is no need for joint insertion between multiple functional units. In other words, the data block recovery operation can be performed at the receiver side based on the distribution sequence of the distribution unit at the transmitter side.

[0130] See FIG. 12B. In some embodiments, the communication system includes a receiving device and multiple transmitting devices. The interface of the transmitting device is an IEEE 802.3 standard Ethernet interface. The receiving device includes an interface corresponding to the interface shown in FIG. 4A, but further includes an alignment lock module between the PMA module and the FEC module. The scrambling module of FIG. 4A is replaced with a descrambling module, and the alignment marker insertion (AM Insertion) module of FIG. 4A is replaced with an alignment marker removal (AM Removal) module. The interface of the transmitting device processes data to be transmitted in the manner of the IEEE 802.3 Ethernet interface and then transmits the processed data to the receiving device over a medium. The interface of the receiving device receives data from the transmitting device. In a breakout scenario, the interface of the receiving device distributes data from the multiple transmitting device interfaces to one or more functional units within the receiving device interface and corresponding to the speed of the transmitting device interface. For example, four IEEE 802.3 standard Ethernet interfaces with a rate of 200 Gbps send data to the interface shown in Fig. 4A. The interface shown in Fig. 4A receives four data flows at a rate of 200 Gbps, and in functional part 2 of the interface, maps the four data flows at a rate of 200 Gbps to four functional units at a rate of 200 Gbps respectively, performs processing in functional part 2, and then performs processing in functional part 1 to obtain the data sent by the four sending devices.

[0131] Please refer to Figure 12C. The communication system includes a receiving device and multiple transmitting devices. The interface of the transmitting device is an Ethernet interface of the IEEE 802.3 standard. The receiving device includes an interface corresponding to the interface shown in Figure 4B, but further includes an alignment lock module between the PMA module and the FEC module. The scrambling module in Figure 4B is replaced with a descrambling module, and the alignment marker insertion (AM Insertion) module in Figure 4B is replaced with an alignment marker removal (AM Removal) module. The process by which the interface of the transmitting device processes data to be transmitted is similar to the operation of the interface of the transmitting device in Figure 12B. The details will not be described again here.

[0132] See Figure 12D. The communication system includes a receiving device and multiple transmitting devices. The interface of the transmitting device is an Ethernet interface conforming to the IEEE 802.3 standard. The receiving device includes an interface corresponding to the interface shown in Figure 5A, but further includes an alignment lock module between the PMA module and the FEC module. The scrambling module in Figure 5A is replaced with a descrambling module, and the alignment marker insertion (AM Insertion) module in Figure 5A is replaced with an alignment marker removal (AM Removal) module. The process by which the interface of the transmitting device processes data to be transmitted is similar to the operation of the interface of the transmitting device in Figure 12B. The details will not be described again here.

[0133] See Figure 12E. The communication system includes a receiving device and multiple transmitting devices. The interface of the transmitting device is an Ethernet interface conforming to the IEEE 802.3 standard. The receiving device includes an interface corresponding to the interface shown in Figure 6A, but further includes an alignment lock module between the PMA module and the FEC module. The scrambling module in Figure 6A is replaced with a descrambling module, and the alignment marker insertion (AM Insertion) module in Figure 6A is replaced with an alignment marker removal (AM Removal) module. The process by which the interface of the transmitting device processes data to be transmitted is similar to the operation of the interface of the transmitting device in Figure 12B. The details will not be described again here.

[0134] See Figure 12F. The communication system includes a receiving device and multiple transmitting devices. The interface of the transmitting device is an Ethernet interface conforming to the IEEE 802.3 standard. The receiving device includes an interface corresponding to the interface shown in Figure 6C, but further includes an alignment lock module between the PMA module and the FEC module. The scrambling module in Figure 6C is replaced with a descrambling module, and the alignment marker insertion (AM Insertion) module in Figure 6C is replaced with an alignment marker removal (AM Removal) module. The process by which the interface of the transmitting device processes data to be transmitted is similar to the operation of the interface of the transmitting device in Figure 12B. The details will not be described again here.

[0135] See Figure 12G. The communication system includes a receiving device and multiple transmitting devices. The interface of the transmitting device is an Ethernet interface conforming to the IEEE 802.3 standard. The receiving device includes an interface corresponding to the interface shown in Figure 7A, but further includes an alignment lock module between the PMA module and the FEC module. The scrambling module in Figure 7A is replaced with a descrambling module, and the alignment marker insertion (AM Insertion) module in Figure 7A is replaced with an alignment marker removal (AM Removal) module. The process by which the interface of the transmitting device processes data to be transmitted is similar to the operation of the interface of the transmitting device in Figure 12B. The details will not be described again here.

[0136] For functional units in functional portion 2 of the interface of a receiving device in an embodiment of the present application, if there is only a single PCS lane, alignment lock only needs to be performed, or if there are multiple PCS lanes, lane deskew between the lanes needs to be performed after alignment lock.

[0137] In some embodiments, the FEC decoding module may be shared for functional units of functional portion 2 of the receiving device interface, specifically, multiple or all functional units in functional portion 2 share the same FEC decoding module, and the same FEC decoding module performs FEC decoding on data from other modules in multiple or all functional units.

[0138] 13 is a schematic diagram of the structure of a device 2100 according to an exemplary embodiment of the present application. The device 2100 is, for example, a switch or a router, and the device 2100 may be implemented using a bus architecture.

[0139] 13, the device 2100 includes a main control board 2110 and an interface board 2130. The interface board 2130 includes any of the interfaces shown in FIGS.

[0140] The main control board 2110 is also called a main processing unit (MPU) or a route processor card. The main control board 2110 is configured to control and manage components within the device 2100, including route calculation, device management, device maintenance, and protocol-based processing. The main control board 2110 includes a central processing unit 2111 and a memory 2112.

[0141] The interface board 2130 is also called a line processing unit (LPU), line card, or service board. The interface board 2130 is configured to provide various service interfaces and transfer data packets. The service interfaces include, but are not limited to, an Ethernet interface and a Packet over SONET / SDH (POS) interface. An example of the Ethernet interface is a flexible Ethernet service interface (Flexible Ethernet Client, FlexE Client). The interface board 2130 includes a central processing unit 2131, a network processor 2132, a forwarding entry memory 2134, and a physical interface card (PIC) 2133.

[0142] A central processing unit 2131 on the interface board 2130 is configured to control and manage the interface board 2130 and to communicate with a central processing unit 2111 on the main control board 2110 .

[0143] The network processor 2132 is configured to forward packets. The network processor 2132 may take the form of a forwarding chip. The forwarding chip may be a network processor (NP). In some embodiments, the forwarding chip may be implemented using an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 2132 is configured to forward received packets based on a forwarding table stored in a forwarding entry memory 2134. If the destination address of the packet is the address of the device 2100, the network processor 2132 sends the packet to a CPU (e.g., central processing unit 2131) for processing. If the destination address of the packet is not the address of the device 2100, the network processor 2132 searches the forwarding table for a next hop and an outbound interface corresponding to the destination address based on the destination address, and forwards the packet to the outbound interface corresponding to the destination address. The processing for uplink packets may include processing at the packet ingress interface and forwarding table lookup, and the processing for downlink packets may include forwarding table lookup, etc. In some embodiments, the central processing unit may also perform the functions of a forwarding chip, for example, software forwarding may be implemented based on a general-purpose CPU. Therefore, a forwarding chip is not required on the interface board.

[0144] The physical interface card 2133 is configured to implement physical layer interconnection functions. Original traffic enters the interface board 2130 from the physical interface card 2133, and processed packets are sent out from the physical interface card 2133. The physical interface card 2133, also called a subcard, may be attached to the interface board 2130 and is responsible for converting optical / electrical signals into packets, validating the packets, and forwarding the packets to the network processor 2132 for processing. In some embodiments, the central processing unit 2131 can also perform the functions of the network processor 2132, for example, by implementing software forwarding based on a general-purpose CPU. Therefore, the network processor 2132 is not required for the physical interface card 2133.

[0145] Optionally, the device 2100 includes multiple interface boards. For example, the device 2100 further includes an interface board 2140, which includes a central processing unit 2141, a network processor 2142, a forwarding entry memory 2144, and a physical interface card 2143. The functions and implementations of the components of the interface board 2140 are the same as or similar to those of the interface board 2130, and the details will not be described again here. The interface board includes one or more interfaces described in the previous embodiments.

[0146] Optionally, the device 2100 further includes a switching board 2120. The switching board 2120 may also be referred to as a switch fabric unit (SFU). When the device has multiple interface boards, the switching board 2120 is configured to complete data exchange between the interface boards. For example, the interface board 2130 and the interface board 2140 can communicate with each other via the switching board 2120.

[0147] The main control board 2110 is coupled to the interface boards. For example, the main control board 2110, the interface boards 2130, the interface boards 2140, and the switching board 2120 are connected to a system backplane via a system bus to achieve interworking. In a possible embodiment, inter-process communication (IPC) channels are established between the main control board 2110 and the interface boards 2130 and between the main control board 2110 and the interface boards 2140, and the main control board 2110 communicates with the interface boards 2130 and 2140 via the IPC channels.

[0148] Logically, device 2100 includes a control plane and a forwarding plane. The control plane includes main control board 2110 and central processing unit 2111. The forwarding plane includes components used for forwarding, such as forwarding entry memory 2134, physical interface cards 2133, and network processors 2132. The control plane performs functions such as routing, generating forwarding tables, processing signaling and protocol packets, and configuring and maintaining device status. The control plane distributes the generated forwarding tables to the forwarding plane. In the forwarding plane, network processors 2132 look up the forwarding tables distributed by the control plane to forward packets received by physical interface cards 2133. The forwarding tables distributed by the control plane may be stored in forwarding entry memory 2134. In some embodiments, the control plane and forwarding plane may be completely separate and not on the same device.

[0149] It should be noted that there may be one or more main control boards, and if there are multiple main control boards, the main control board may include a primary main control board and a secondary main control board. There may be one or more interface boards, and the more interface boards provided, the more powerful the data processing capabilities of the equipment. The interface board may include one or more physical interface cards. There may be no switching board or one or more switching boards. When there are multiple switching boards, the multiple switching boards can jointly perform load balancing and redundant backup. In a centralized forwarding architecture, a switching board is not required in the equipment, and the interface board provides the function of processing service data for the entire system. In a distributed forwarding architecture, the equipment may have at least one switching board, and data exchange between multiple interface boards is performed using the switching board, providing large-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of equipment with a distributed architecture are superior to those of equipment with a centralized architecture. Optionally, the equipment may alternatively have a single card. Specifically, there is no switching board, and the functions of the interface board and the main control board are integrated into a card. In this case, the central processing unit on the interface board and the central processing unit on the main control board can be combined to form one central processing unit on the card, which can execute the functions obtained by combining the two central processing units. This type of equipment (e.g., equipment such as a low-end switch or router) has weak data exchange and processing capabilities. The specific architecture to be used depends on the specific network deployment scenario, which is not limited in this specification.

[0150] It is understood that the processor may be a Central Processing Unit (CPU), or may be another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is noted that the processor is a processor that supports the advanced reduced instruction set computing machine (ARM) architecture.

[0151] Additionally, in optional embodiments, the memory may include read-only memory and random access memory to provide instructions and data to the processor. The memory may further include non-volatile random access memory. For example, the memory may further store information regarding device type.

[0152] The memory may be volatile, non-volatile, or include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM) used as an external cache. Many forms of RAM may be used, such as, for example and without limitation, static random access memory (static RAM, SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synchlink DRAM, SLDRAM), and direct Rambus random access memory (direct Rambus RAM, DR RAM).

[0153] Fig. 14 is a schematic diagram of the structure of a device 4000 according to an exemplary embodiment of the present application. The device 4000 shown in Fig. 14 is configured to perform operations related to the functions of the interfaces shown in any one of Figs. 3 to 12. The device 4000 may be, for example, a switch, a router, a controller, a server, a storage device, a network device, or the like. The device 4000 may be implemented using a bus architecture.

[0154] 14, the device 4000 includes at least one processor 4001 and at least one communication interface 4004. In some embodiments, the processor 4001 is coupled to a memory 4003.

[0155] The processor 4001 may be, for example, a general-purpose central processing unit (CPU), digital signal processor (DSP), network processor (NP), graphics processing unit (GPU), neural network processing unit (NPU), data processing unit (DPU), microprocessor, or one or more integrated circuits configured to implement the solutions of the present application. For example, the processor 4001 may include an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or another programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The PLD may be, for example, a complex programmable logic device (CPLD), a field programmable gate array (FPGA), generic array logic (GAL), or any combination thereof. The processor 4001 may implement or execute various logic block modules and circuits described with reference to the contents disclosed in the embodiments of the present invention. Alternatively, the processor may be a combination of processors that perform computing functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0156] Optionally, device 4000 further includes a bus. The bus is configured to transmit information between components within device 4000. The bus may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. Buses may be classified into address buses, data buses, control buses, and the like. For ease of representation, only one thick line is used to represent the bus in FIG. 14, but this does not imply that there is only one bus or only one type of bus.

[0157] The memory 4003 may be, for example, but is not limited to, read-only memory (ROM) or another type of static storage device capable of storing static information and instructions, random access memory (RAM) or another type of dynamic storage device capable of storing information and instructions, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or another type of compact disc storage device, optical disc storage device (including compact disc, laser disc, optical disc, digital versatile disc, or Blu-ray disc, etc.), magnetic disk storage medium or another magnetic storage device, or any other medium that can be used to carry or store the expected program code in the form of instructions or data structures and that can be accessed by a computer. For example, the memory 4003 may exist independently and be connected to the processor 4001 via a bus. Alternatively, the memory 4003 may be integrated with the processor 4001.

[0158] The communication interface 4004 is any device, such as a transceiver, configured to communicate with another device or a communication network. The communication network may be an Ethernet, a radio access network (RAN), a wireless local area network (WAN), or the like. The communication interface 4004 may include a wired communication interface and may further include a wireless communication interface. Specifically, the communication interface 4004 may be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an Asynchronous Transfer Mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. In this embodiment of the present application, the communication interface 4004 may be used by the device 4000 to communicate with another device.

[0159] In a particular implementation, in one embodiment, processor 4001 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 14. Each processor may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. A processor herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0160] In certain implementations, in one embodiment, device 4000 may include multiple processors, such as processor 4001 and processor 4005 shown in Figure 14. Each processor may be a single-core processor (single CPU) or a multi-core processor (multiple CPUs). A processor herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0161] In certain implementations, in one embodiment, the device 4000 may further include an output device and an input device. The output device communicates with the processor 4001 and can display information in multiple ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display, a cathode ray tube (CRT) display, a projector, or the like. The input device communicates with the processor 4001 and can receive input from a user in multiple ways. For example, the input device may be a mouse, a keyboard, a touchscreen device, or a sensor device.

[0162] In some embodiments, the memory 4003 is configured to store program code 4010 for executing the solution of the present application, and the processor 4001 can execute the program code 4010 stored in the memory 4003. In other words, the device 4000 can realize the functionality of the interfaces shown in any one of Figures 3 to 12 using the processor 4001 and the program code 4010 in the memory 4003. The program code 4010 can include one or more software modules. Optionally, the processor 4001 can alternatively store program code or instructions for executing the solution of the present application.

[0163] In some embodiments, the communications interface 4004 is configured to perform operations related to the functionality of the interfaces shown in any one of FIGS.

[0164] An embodiment of the present application further provides a computer-readable storage medium, which stores at least one instruction, which is loaded and executed by a processor to implement the functionality of the interface shown in any one of Figures 3 to 12.

[0165] One embodiment of the present application provides a computer program (product), which, when executed by a computer, may enable a processor or a computer to perform the functions of the interfaces shown in any one of Figures 3 to 12.

[0166] One embodiment of the present application provides a chip including a processor configured to call instructions stored in the memory from the memory and execute the instructions, and a communication device in which the chip is installed performs the functions of the interface shown in any one of Figures 3 to 12.

[0167] An embodiment of the present application further provides another chip including an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected to each other via an internal connection path. The processor is configured to execute code in the memory. When the code is executed, the processor is configured to perform the functions of the interfaces shown in any one of Figures 3 to 12.

[0168] In the above embodiment, if functional portion 2 includes m flows of functional units, and the rate of the corresponding MAC data flow that can be processed by each functional unit is R, then the maximum rate of functional portion 1 that can be supported by functional portion 2 is m*R. Typically, the value of m is an integer power of 2, for example, m=2 kwhere k=0, 1, 2, etc. The value of R is typically 5 Gbps, 10 Gbps, 25 Gbps, 50 Gbps, 100 Gbps, 200 Gbps, or 400 Gbps.

[0169] In some embodiments, the actual output rates may be higher than the nominal 100 Gbps and 200 Gbps due to the introduction of functions such as encoding, transcoding, and FEC into each functional unit. For example, for a 100 Gbps MAC data flow, if 64B / 66B encoding and 256B / 257B transcoding are used and RS(544,514) FEC encoding is added, the data flow rate becomes 106.25 Gbps. Alternatively, if the FEC is RS(528,514), the rate after encoding is 103.125 Gbps. Generally, the rate is referred to in the industry as 100G. Similar explanations apply to other rates.

[0170] If the number of functional units in functional part 1 is n, then the corresponding n*2 k The functional unit 2 can be used for support.

[0171] All or part of the above-described embodiments can be implemented by software, hardware, firmware, or any combination thereof. When an embodiment is implemented using software, all or part of the embodiment can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded into a computer and executed, all or part of the procedures or functions of the present application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or another programmable device. The computer instructions may be stored on a computer-readable storage medium or transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, or digital subscriber line) or wireless (infrared, radio wave, microwave, etc.) transmission. The computer-readable storage medium may be any available medium accessible by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, or magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0172] The above specific embodiments further describe the objectives, technical solutions, and beneficial effects of the present application. It should be understood that the above descriptions are only specific embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made based on the technical solutions of the present application shall fall within the protection scope of the present application.

[0173] Those skilled in the art can recognize that the method steps and modules described with reference to the embodiments disclosed herein can be implemented by software, hardware, firmware, or a combination thereof. In order to clearly explain the compatibility between hardware and software, the steps and configurations of each embodiment are generally described above according to their functions. Whether a function is executed by hardware or software depends on a specific application and the design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be deemed to go beyond the scope of the present application.

[0174] Those skilled in the art will understand that all or part of the steps of the embodiments can be implemented by hardware or a program instructing related hardware. The program can be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a magnetic disk, an optical disk, etc.

[0175] When implementing embodiments using software, all or a portion of the embodiments may be realized in the form of a computer program product. A computer program product includes one or more computer program instructions. For example, methods in embodiments of the present application may be described in the context of machine-executable instructions. Machine-executable instructions are included in program modules that, for example, execute on components on a target real or virtual processor. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc., that perform particular tasks or implement particular abstract data structures. In various embodiments, the functionality of a program module may be combined or divided among the described program modules. The machine-executable instructions of a program module may be executed locally or in a distributed system. In a distributed system, program modules may be located in both local and remote storage media.

[0176] The computer program code used to implement the methods in the embodiments of the present application may be written in one or more programming languages. The computer program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or another programmable data processing device, and when the program code is executed by the computer or another programmable data processing device, the functions / acts specified in the flowcharts and / or block diagrams are performed. All of the program code may be executed on the computer, or part of it may be executed on the computer as a stand-alone software package, or part of it may be executed on the computer and part of it may be executed on a remote computer, or all of the program code may be executed on a remote computer or server.

[0177] In the context of the embodiments of the present application, the computer program code or associated data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of the carrier include signals, computer-readable media, etc.

[0178] Examples of signals may include electrical signals, optical signals, radio signals, audio signals, or other forms of propagated signals such as carrier waves and infrared signals.

[0179] A machine-readable medium may be any tangible medium that contains or stores a program used in or associated with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More specific examples of machine-readable storage media include an electrical connection using one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0180] For the sake of convenience and conciseness, it will be clearly understood by those skilled in the art that the detailed operation processes of the aforementioned systems, devices and modules may be referred to the corresponding processes in the aforementioned method embodiments, and the details will not be described herein.

[0181] In some embodiments provided herein, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the described device embodiments are merely examples. For example, the modular division is merely a logical functional division, and in actual implementation, other divisions may be used. For example, multiple modules or components may be combined or integrated into another system, or some functions may be ignored or not performed. Furthermore, the shown or discussed mutual couplings or direct couplings or communication connections may be realized through some interfaces. Indirect couplings or communication connections between devices or modules may be electrical, mechanical, or other types of connections.

[0182] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, and may be located in one location or distributed across multiple network modules. To achieve the objectives of the solutions in the embodiments of the present application, some or all of the modules may be selected according to actual requirements.

[0183] Furthermore, the functional modules in the embodiments of the present application may be integrated into one processing module, or each module may exist physically independently, or two or more modules may be integrated into one module. The integrated module may be realized in the form of hardware or in the form of a software functional module.

[0184] When the integrated module is realized in the form of a software function module and sold or used as an independent product, the integrated unit may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, i.e., the portion contributing to the prior art, or all or part of the technical solution, can be realized in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes any medium capable of storing program code, such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0185] In this application, terms such as "first" and "second" are used to distinguish between identical or similar items that are essentially the same in effect and function. It should be understood that there is no logical or chronological dependency between "first," "second," and "nth" and that there are no limitations on quantity or execution order. Terms such as "first" and "second" are used in the following description to describe various elements, but it should be further understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first image can be referred to as a second image, and similarly, a second image can be referred to as a first image, without departing from the scope of various examples. Both the first image and the second image may be images, and in some cases, may be separate and distinct images.

[0186] It should be further understood that the sequence numbers of the processes do not imply an execution sequence in various embodiments of the present application, and the execution sequence of the processes should be determined based on the functions and internal logic of the processes, and should not be construed as any limitation on the implementation process of the embodiments of the present application.

[0187] As used herein, the term "at least one" means one or more, and the term "plurality" means two or more. For example, a plurality of second packets means two or more second packets. The terms "system" and "network" may be used interchangeably herein.

[0188] It should be understood that the terminology used in the description of the various examples herein is intended merely to describe particular examples and is not intended to constitute a limitation. As used in the description of the various examples and in the appended claims, the singular terms "a" and "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise.

[0189] It is to be further understood that the term "include" as used herein (also referred to as "includes," "including," "comprises," and / or "comprising") specifies the presence of stated features, integer steps, operations, elements, and / or components in addition to and / or to the exclusion of one or more other features, integers, steps, operations, elements, components.

[0190] It should be further understood that the term "if" may be interpreted as meaning "when" ("when" or "upon"), "upon determining," or "upon detecting." Similarly, depending on the context, the phrase "when it is determined" or "when (a stated condition or event) is detected" may be interpreted as meaning "when it is determined" or "upon determining that," or "when (a stated condition or event) is detected" or "in response to detecting (a stated condition or event)."

[0191] It should be understood that determining B based on A does not mean that B is determined based only on A; alternatively, B may be determined based on A and / or other information.

[0192] It should be further understood that references throughout this specification to "one embodiment," "an embodiment," or "a possible implementation" mean that the particular feature, structure, or characteristic associated with the embodiment or implementation is included in at least one embodiment of the present application. Thus, the appearances of "one embodiment," "an embodiment," or "a possible implementation" throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0193] The foregoing description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, or improvement made without departing from the principle of the present application should fall within the protection scope of the present application.

Claims

1. A transmitting device including a coding and rate matching module, a data block distribution module, a first group of modules, a second group of modules, and a physical medium attachment (PMA) layer, the encoding and rate matching module is coupled to the data block distribution module, the data block distribution module is coupled to the first module group and the second module group; the first module group is coupled to the PMA layer, and the second module group is coupled to the PMA layer, the PMA layer configured to perform bit-mux across the first module group and the second module group; the first group of modules includes a first transcoding module, a first scrambling module, a first alignment marker insertion module, and a first forward error correction (FEC) encoding module; the second group of modules includes a second transcoding module, a second scrambling module, a second alignment marker insertion module, and a second FEC encoding module; Transmitting device.

2. 2. The transmitting device of claim 1, comprising: a Physical Coding Sublayer (PCS) configured to perform interleaving on first data based on FEC symbols to obtain first symbol-interleaved data, and configured to perform interleaving on second data based on the FEC symbols to obtain second symbol-interleaved data, wherein the first data is output by the first FEC encoding module and the second data is output by the second FEC encoding module.

3. the PMA layer configured to perform the bit multiplexing across the first module group and the second module group, 3. The transmitting apparatus of claim 2, wherein the PMA layer performs the bit multiplexing of the first symbol-interleaved data and the second symbol-interleaved data across the first module group and the second module group.

4. The transmitting device of claim 1 , wherein the first FEC encoding module is a first-level FEC encoding module in a concatenated FEC encoding module.

5. The transmitting device of claim 4 , wherein the first level FEC encoding module is configured to perform Reed-Solomon (RS) FEC.

6. The transmitting device of claim 1 , further comprising a Coordination Sublayer (RS) module, the RS module being coupled to the coding and rate matching module via a Media Independent Interface (MII).

7. The transmitting device of claim 1 , wherein the data block distribution module is configured to distribute data to the first module group and the second module group with a granularity of 66 bits.

8. 6. The transmitting device according to claim 1, wherein the sum of the rate of the first module group and the rate of the second module group matches a medium access control (MAC) rate of the encoding and rate matching module.

9. 9. The transmitter of claim 8, wherein the MAC rate is 800 Gb / s, the rate of the first module group is 400 Gb / s, and the rate of the second module group is 400 Gb / s.

10. 6. The transmitting device of claim 1, wherein the first FEC encoding module has a rate of 400 Gb / s and the second FEC encoding module has a rate of 400 Gb / s.

11. 6. The transmitting device of claim 1, wherein the first transcoding module is configured to perform 64B / 66B to 256B / 257B transcoding.

12. A receiving device including a decoding and rate matching module, a data block distribution module, a first group of modules, a second group of modules, and a physical medium attachment (PMA) layer, the decoding and rate matching module is coupled to the data block distribution module, the data block distribution module is coupled to the first module group and the second module group; the first module group is coupled to the PMA layer, the second module group is coupled to the PMA layer, the PMA layer is configured to perform bit-demux across the first module group and the second module group; the first group of modules includes a first de-transcoding module, a first descrambling module, a first alignment marker removal module, and a first forward error correction (FEC) decoding module; the second group of modules includes a second de-transcoding module, a second descrambling module, a second alignment marker removal module, and a second FEC decoding module; Receiving device.

13. The receiving device of claim 12 , wherein the first FEC decoding module is a first-level FEC decoding module in a concatenated FEC decoding module.

14. 13. The receiving device of claim 12, further comprising a Reconciliation Sublayer (RS) module, the RS module being coupled to the decoding and rate matching module via a Media Independent Interface (MII).

15. 15. The receiving device according to claim 12, wherein the sum of the rate of the first module group and the rate of the second module group matches a medium access control (MAC) rate of the decoding and rate matching module.

16. 16. The receiving device of claim 15, wherein the MAC rate is 800 Gb / s, the rate of the first module group is 400 Gb / s, and the rate of the second module group is 400 Gb / s.

17. 15. The receiving device of claim 12, wherein the first FEC decoding module has a rate of 400 Gb / s and the second FEC decoding module has a rate of 400 Gb / s.

18. 15. The receiving device according to claim 12, wherein the first inverse transcoding module is configured to perform inverse transcoding from 256B / 257B to 64B / 66B, and the second inverse transcoding module is configured to perform inverse transcoding from 256B / 257B to 64B / 66B.

19. 1. A method of transmission, the method comprising: performing encoding and rate matching on the first data to obtain second data; a first group of modules transcoding a first portion of the second data to obtain first transcoded data; the first group of modules scrambling the first transcoded data to obtain first scrambled data; the first module group inserting a first alignment mark into the first scrambled data to obtain first alignment data; the first module group encoding the first alignment data according to a forward error correction (FEC) code to obtain first processed data; a second group of modules transcoding a second portion of the second data to obtain second transcoded data; the second group of modules scrambling the second transcoded data to obtain second scrambled data; the second module group inserting second alignment marks into the second scrambled data to obtain second alignment data; the second module group encoding the second alignment data according to the FEC code to obtain second processed data; performing bit multiplexing on the first processed data and the second processed data across the first module group and the second module group at a physical medium attachment (PMA) layer; method.

20. The step of the first module group encoding the first alignment data according to a forward error correction (FEC) code to obtain first processed data includes: the first module group encoding the first alignment data according to the FEC code to obtain first encoded data; The first module group specifically includes: performing interleaving on the first coded data in a physical coding sublayer (PCS) based on FEC symbols to obtain the first processed data; The step of the second module group encoding the second alignment data according to the FEC code to obtain second processed data includes: the second module group encoding the second alignment data according to the FEC code to obtain second encoded data; 20. The method of claim 19, particularly comprising: the second module group performing interleaving on the second coded data in the PCS based on the FEC symbols to obtain the second processed data.

21. 20. The method of claim 19, wherein the first FEC encoding process is a first level FEC encoding process in a concatenated FEC encoding process.

22. 22. The method of claim 21, wherein the first level FEC encoding process is configured to perform Reed-Solomon (RS) FEC.

23. 23. The method of claim 19, wherein the sum of the rate of the first module group and the rate of the second module group matches a medium access control (MAC) rate of the encoding and rate matching module.

24. 24. The method of claim 23, wherein the MAC rate is 800 Gb / s, the rate of the first module group is 400 Gb / s, and the rate of the second module group is 400 Gb / s.

25. 23. The method of any one of claims 19 to 22, wherein the transcoding step is configured to perform a 64B / 66B to 256B / 257B transcoding.

26. 1. A method of transmission, the method comprising: performing bit demultiplexing on third data across the first module group and the second module group at a physical medium attachment (PMA) layer to obtain first processed data and second processed data, the third data being data from a physical medium dependent (PMD) layer; the first group of modules decoding the first processed data according to a forward error correction (FEC) code to obtain first decoded data; the first module group removing the first alignment mark from the first decoded data to obtain first alignment-removed data; the first module group descrambling the first alignment-removed data to obtain first descrambled data; the first group of modules inverse transcoding the first descrambled data to obtain a first portion of second data; the second group of modules decoding the second processed data according to the FEC code to obtain second decoded data; the second module group removing the second alignment marks from the second decoded data to obtain second alignment-removed data; the second group of modules descrambling the second alignment-removed data to obtain second descrambled data; the second group of modules inverse transcoding the second descrambled data to obtain a second portion of the second data; performing decoding and rate matching on the first portion of the second data and the second portion of the second data to obtain first data; method.

27. The step of the first module group decoding the first processed data according to a forward error correction (FEC) code to obtain first decoded data includes: the first module group performing deinterleaving on the first processed data in a physical coding sublayer (PCS) based on FEC symbols to obtain first de-symbol-interleaved data; the first module group decoding the first de-symbol interleaved data according to the FEC code to obtain the first decoded data; The second module group decoding the second processed data according to the FEC code to obtain second decoded data includes: the second module group performing deinterleaving on the second processed data in the PCS based on the FEC symbols to obtain second de-symbol-interleaved data; 27. The method of claim 26, particularly comprising the step of: the second group of modules decoding the second de-symbol-interleaved data according to the FEC code to obtain the second decoded data.

28. 27. The method of claim 26, wherein the first FEC decoding process is a first level FEC decoding process in a concatenated FEC decoding process.

29. 29. The method of claim 26, wherein the sum of the rate of the first module group and the rate of the second module group matches a Medium Access Control (MAC) rate of the decoding and rate matching module.

30. 30. The method of claim 29, wherein the MAC rate is 800 Gb / s, the rate of the first module group is 400 Gb / s, and the rate of the second module group is 400 Gb / s.

31. 29. The method of any one of claims 26 to 28, wherein the inverse transcoding step is configured to perform an inverse transcoding from 256B / 257B to 64B / 66B.

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