Liquid crystal display device

Abstract

To solve the problem of a display defect or a production decrease that occurs because, in a case where TFTs that control subpixels are formed in matrix at certain intervals in a display part, it is difficult to arrange all the TFTs while avoiding the joint between adjacent SOI layers formed when a large SOI substrate is manufactured.SOLUTION: A plurality of TFTs that control subpixels are arranged collectively so as to surround an intersecting part between scan lines and signal lines. Thus, a gap between regions where the TFTs exist is expanded. Compared to a conventional arrangement in which the TFTs are disposed at certain intervals in a display part, it is possible to avoid the TFTs overlapping with the joint between SOI layers because a gap between the regions where the TFTs exist is expanded.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a so-called SOI (Silicon on Insulator) device in which a semiconductor layer is provided on an insulating surface. This relates to a display device having a rectifier structure. [Background technology]

[0002] Instead of silicon wafers, which are made by thinly slicing single-crystal semiconductor ingots, Silicon-on-insulator (SOI) is a semiconductor device with a thin single-crystal semiconductor layer on its surface. Integrated circuits using semiconductor substrates called SOI substrates are being developed. The integrated circuit reduces the parasitic capacitance between the drain and substrate of the transistor, It is attracting attention as a means of improving circuit performance.

[0003] There are various methods for manufacturing SOI substrates, but the quality of the SOI layer and ease of production (high throughput) are the most important factors. A method called SmartCut (registered trademark) is known as a method that combines the two. This SOI substrate is made by implanting hydrogen ions into the base wafer that forms the base of the silicon layer. Then, the base wafer is bonded to another wafer (bond wafer) at room temperature. Van der Waals forces act on the bonding, forming a strong bond even at room temperature. The silicon layer bonded to the bond wafer can be heat treated at a temperature of about 500°C. The hydrogen ion implanted layer is then separated from the base wafer at the boundary.

[0004] A single crystal silicon obtained by using the Smart Cut method on glass-ceramic, which is a highly heat-resistant glass. A method for forming a silicon thin film, proposed by the present applicant, is known (see Patent Document 1). ).

[0005] In addition, thin-film transistors that make up the drive circuits and control circuits of displays such as liquid crystal and organic EL displays The star is made of amorphous silicon film, polycrystalline silicon film, etc., deposited on a glass substrate. In recent years, there has been an increasing demand for higher resolution and faster driving of such displays. Attempts have been made to form single-crystal silicon films with higher carrier mobility on glass substrates. is being actively carried out.

[0006] With the recent trend toward larger screen sizes and increased productivity due to an increase in the number of pieces per board, For example, mother glass has not yet been put to practical use. However, the largest motherboard is 2850mm x 3050mm (the so-called 10th generation). Glass is known.

[0007] On the other hand, even the largest silicon wafers have a diameter of 300 mm, and the entire surface of a large glass substrate To form an SOI layer, multiple silicon wafers must be bonded together. On a large glass substrate, a large SOI layer can be fabricated without creating a seam (gap) between adjacent SOI layers. Fabricating an OI substrate is not easy. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 11-163363 Summary of the Invention [Problem to be solved by the invention]

[0009] Hereinafter, in this specification, a point that emits light or transmits light is defined as a sub-pixel. A pixel is defined as a group of sub-pixels that are made up of multiple sub-pixels that emit different colors. Each of R (red), G (green), and B (blue) is a sub-pixel, and a group of these sub-pixels is a pixel. It is possible.

[0010] In a conventional example, one pixel is divided into sub-pixels a (also called the first sub-pixel), b (also called the second sub-pixel), ), c (also called the third subpixel), and each subpixel has a switching element. An active matrix in which thin film transistors (hereinafter referred to as TFTs) are provided An example of the pixel configuration of a display device is shown in Figure 2. As shown in Figure 2, the pixel configuration of the simplest display unit is The pixel arrangement is a stripe arrangement of three sub-pixels. Each sub-pixel is surrounded by scanning lines and signal lines. The layout of the TFT and pixel electrodes is the same for all sub-pixels. (The storage capacitor is not shown in the figure to simplify the drawing.) The interval between the FTs is equal to the pitch of the sub-pixels.

[0011] In many active matrix display devices, the distance between adjacent TFTs is narrow. , formed by bonding a plurality of single crystal semiconductor substrates to a large glass substrate; When manufacturing a display device using a large SOI substrate, all TFTs in the display area are It is difficult to avoid the joints between the SOI layers. It is possible that T cannot be formed, or even if it can be formed, it does not function properly. This causes a problem that display defects such as point defects and line defects are likely to occur. The margin for alignment during SOI layer formation is small, and the alignment of the SOI layer is difficult. , high accuracy is required.

[0012] In addition, many liquid crystal display devices have a function to improve contrast and prevent leakage current caused by light irradiation. For the purpose of preventing the TFT from being broken, a substrate ( A black matrix (hereinafter referred to as BM) is provided on the counter substrate. Normally, BM is used to compensate for misalignment that occurs when bonding the TFT substrate and the opposing substrate. It is formed wide to provide a margin, which increases the positional deviation of the BM. As a result, the pixel area blocked by the BM becomes larger, and the aperture ratio decreases.

[0013] The present invention has been made in consideration of such problems, and aims to improve alignment during SOI layer formation. The margin for the alignment is wide, or the opening is small when the TFT substrate and the opposing substrate are misaligned when they are bonded together. This paper proposes a TFT layout that suppresses the decrease in the display efficiency. The present invention provides a display device. [Means for solving the problem]

[0014] The present invention relates to a display device, which has a display section including a plurality of pixels arranged in a matrix, A pixel has a plurality of sub-pixels, and a plurality of scanning lines or a plurality of signal lines are adjacent to the pixel. Alternatively, a plurality of scanning lines and a plurality of signal lines are provided between adjacent pixels. The TFTs provided in each of the plurality of sub-pixels are arranged adjacent to the intersections of the scanning lines and the signal lines. The gist of the matter is that they are arranged in a manner that is consistent with the above.

[0015] In addition, the arrangement of the plurality of TFTs at this time is such that adjacent TFTs are connected to each other as scanning lines or signal lines. An arrangement in which the two sensors are placed directly opposite each other with a gap therebetween is also applicable.

[0016] That is, in the present invention, the TFTs for controlling the sub-pixels are arranged in a plurality of positions so as to surround the intersections of the scanning lines and the signal lines. By arranging several TFTs together, the spacing between the areas where multiple TFTs are located can be expanded, and the above problem can be solved. Compared to when TFTs are arranged at regular intervals within the display area, The large spacing between the regions where the FTs are located prevents the TFTs from reaching the seams between the SOI layers. In addition, the margin of the BM that is provided so as to overlap with the scanning lines and signal lines can be reduced. By reducing the area, the decrease in aperture ratio when the TFT substrate and the opposing substrate are misaligned is suppressed. It is possible to do so. [Effects of the Invention]

[0017] According to the present invention, the margin for alignment during SOI layer formation is increased, or T The reduction in aperture ratio caused by misalignment when bonding the FT substrate and the opposing substrate is suppressed. This makes it possible to improve productivity and reduce display defects. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 2 is a schematic diagram showing an example of a pixel arrangement in a display unit according to the present invention. [Figure 2] FIG. 1 is a schematic diagram showing an example of a conventional pixel arrangement in a display unit. [Figure 3] FIG. 2 is a schematic diagram showing an example of a pixel arrangement in a display unit according to the present invention. [Figure 4] FIG. 1 is a schematic diagram showing an example of a conventional pixel arrangement in a display unit. [Figure 5] FIG. 2 is a schematic diagram showing an example of a pixel arrangement in a display unit according to the present invention. [Figure 6] FIG. 2 is a schematic diagram showing an example of a pixel arrangement in a display unit according to the present invention. [Figure 7] FIG. 2 is a schematic diagram showing an example of a pixel arrangement in a display unit according to the present invention. [Figure 8] FIG. 2 is a schematic diagram showing an example of a pixel arrangement in a display unit according to the present invention. [Figure 9] FIG. 1 is a schematic diagram showing an example of a conventional pixel arrangement in a display unit. [Figure 10] FIG. 2 is a schematic diagram showing an example of a pixel arrangement in a display unit according to the present invention. [Figure 11] FIG. 1 is a schematic diagram showing an example of a conventional pixel arrangement in a display unit. [Figure 12] FIG. 1 is a schematic diagram showing an example of the arrangement relationship between conventional pixels and BMs in a display unit. [Figure 13] FIG. 2 is a schematic diagram showing an example of the arrangement relationship between pixels of a display unit and a BM according to the present invention. [Figure 14] 1A to 1C are cross-sectional views showing an example of a manufacturing process of a display device according to the present invention. [Figure 15] 1 is a diagram showing an example of a cross-sectional structure of a display device according to the present invention. [Figure 16] 1 is a diagram showing a configuration of an example of a display device according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention will be described below with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the present invention. The present invention described below should not be construed as being limited to the description of the embodiments. In the configuration, reference numerals indicating the same or corresponding elements may be commonly used among different drawings. Let's say.

[0020] (Embodiment 1) FIG. 1 is a schematic diagram showing an example of the configuration of an active matrix display device according to one embodiment of the present invention. The pixel in this embodiment is divided into a (also called a first sub-pixel), b (a second sub-pixel), and c (also called the third sub-pixel), and three rectangular or quasi-rectangular sub-pixels. The pixels are arranged in stripes with their long sides parallel to the signal lines, and there is a gap between adjacent pixels. It consists of three signal lines.

[0021] The specific configuration of the sub-pixels a, b, and c is not limited. For example, R (red), G (green), B (blue) can be applied to three sub-pixels.

[0022] Scanning lines G(i), G(i+1) and signal lines S(j+3) to S(j+5), S(j+6) to A TFT provided in the first sub-pixel of the first pixel arranged in the region surrounded by S(j+8) is Tr1 (also called the first thin film transistor), and the scanning lines G(i+1), G(i+2) and in the area surrounded by signal lines S(j+3) to S(j+5), S(j+6) to S(j+8) The TFT provided in the second sub-pixel of the second pixel is referred to as Tr2 (second thin film transistor). The scanning lines G(i+1), G(i+2) and the signal lines S(j) to S(j+ 3), the third sub-pixel of the third pixel located in the area surrounded by S(j+4) to S(j+5) The TFT provided in the element is called Tr3 (also called the third thin film transistor). Tr1 is connected to the scan line G(i+1) and the signal line S(j+5), and Tr2 is connected to the scan line G(i+1) and the signal line S(j+5). Tr3 is connected to the scanning line G(i+1) and the signal line S(j+3). The same is true for other pixels, and they are connected to the intersections of the scanning lines and the three signal lines. Arrange a group of three TFTs so that

[0023] The configuration of this embodiment can be described in other ways as follows: The pixel shown in this embodiment has first to third sub-pixels arranged parallel to each other, and the first to third sub-pixels arranged parallel to each other The first to third signal lines (for example, S(j+1) to S(j+3)) and the first and second parallel signal lines The second subpixel has two scan lines (for example, G(i) and G(i+1)). the first to third signal lines are orthogonal to the first and second scanning lines; The second signal line is provided between the first and third signal lines, and the first to third sub-pixels are connected to the second signal line. The signal line and the third signal line, and the first scanning line and the second scanning line are provided in an area surrounded by the signal line and the third signal line. Each sub-pixel has a TFT, and the TFT of the first sub-pixel is connected to the second scanning line and the second signal line. The TFT of the second subpixel is driven by the first scanning line and the first signal line. The TFT of the third subpixel is driven by the first scanning line and the third signal line. The TFT of the first subpixel is disposed closer to the second signal line than to the third signal line, and The TFT of the second subpixel is arranged closer to the second scan line than the first scan line. The second signal line is arranged closer to the first scanning line than the third signal line, and the first scanning line is arranged closer to the second scanning line than the second scanning line. The TFT of the third subpixel is arranged closer to the third signal line than the second signal line. The first scan line is located closer to the second scan line, and the second scan line is located closer to the first scan line. According to the embodiment, unlike the conventional arrangement in which all TFTs are arranged at equal intervals, The three TFTs included in each pixel are located near the intersection of three signal lines and one scanning line. In this TFT group, as shown in Figure 1, each TFT The Ts are arranged facing each other with the scanning line or signal line in between, which is similar to the conventional Compared with the TFT arrangement in (1), the spacing between the TFTs can be expanded by approximately two times. That is, a TFT group including three TFTs in different pixels, as shown in Figures 1 and 2. The distance X1 between adjacent TFTs is larger than the distance X2 between adjacent TFTs in the conventional TFT arrangement shown in FIG. Therefore, the alignment margin during SOI layer formation is increased.

[0024] Next, the arrangement of pixels and BM will be explained with reference to Figs. 12 and 13. Fig. 12 shows a conventional table. 13 shows the layout relationship between the BM and pixels of the display device, and FIG. 13 shows the layout relationship between the BM and pixels of the display device formed by using this embodiment. In other words, FIG. 12 corresponds to a part of FIG. 2, and 13 corresponds to a part of FIG.

[0025] In FIG. 12, a BM10 is provided on each signal line, so many BM10s with relatively narrow widths are provided. In contrast, in Figure 13, BM11 is provided on the three collected signal lines. Therefore, a small number of relatively wide BM11s are provided. In this case, the margins provided for each signal line can be shared, so the BM is The area formed can be made smaller than that of FIG.

[0026] That is, in a pixel in which a plurality of signal lines are gathered as in this embodiment, the scanning lines and the signal lines When a BM is formed that overlaps with the TFT substrate, a BM is formed that takes into consideration the positional deviation between the TFT substrate and the opposing substrate. Therefore, it is possible to suppress the decrease in aperture ratio when the position is misaligned. come.

[0027] By applying the above-mentioned TFT arrangement, the thin film transistors provided in each sub-pixel Each of these can be provided close to the intersection of the scanning line and the signal line. Increase the alignment margin when forming the I layer, or improve the bonding between the TFT substrate and the opposing substrate. This can prevent a decrease in aperture ratio when misalignment occurs during the installation.

[0028] (Embodiment 2) FIG. 3 is a schematic diagram showing an example of the configuration of an active matrix display device according to one embodiment of the present invention. The pixel in this embodiment is divided into a (also called a first sub-pixel), b (a second sub-pixel), and c (also called the third sub-pixel), and three rectangular or quasi-rectangular sub-pixels. The pixels are arranged in stripes with their long sides parallel to the scanning lines, and there is a gap between adjacent pixels. It consists of three scanning lines.

[0029] The specific configuration of the sub-pixels a, b, and c is not limited. For example, R (red), G (green), B (blue) can be applied to three sub-pixels.

[0030] Scanning lines G(i) to G(i+2), G(i+3) to G(i+5) and signal line S(j+1), A TFT provided in the first sub-pixel of the first pixel arranged in the region surrounded by S(j+2) is Tr1 (also called the first thin film transistor), and the scanning lines G(i+3) to G(i+5) , G(i+6) to G(i+8) and signal lines S(j+1), S(j+2) The TFT provided in the second sub-pixel of the second pixel is referred to as Tr2 (second thin film transistor). The scan lines are G(i+3) to G(i+5), G(i+6) to G(i+8) and a third sub-pixel of a third pixel disposed in an area surrounded by signal lines S(j) and S(j+1). The TFT provided in the element is called Tr3 (also called the third thin film transistor). Tr1 is connected to the scan line G(i+3) and the signal line S(j+1), and Tr2 is connected to the scan line G(i+5) and Tr3 is connected to the scanning line G(i+4) and the signal line S(j+1). The same is true for other pixels, and they are connected to the intersections of three scanning lines and signal lines. Arrange a group of three TFTs so that

[0031] The configuration of this embodiment can be described in other ways as follows: The pixel shown in this embodiment has first to third sub-pixels arranged parallel to each other, and the first to third sub-pixels arranged parallel to each other The first and second signal lines (for example, S(j) and S(j+1)) and the first to third running lines parallel to each other. The third subpixel has a scan line (e.g., G(i+1) to G(i+3)). the first and second signal lines are orthogonal to the first to third scanning lines; The second scanning line is provided between the first and third scanning lines, and the first to third sub-pixels are connected to the first signal line. The second signal line and the third scanning line are provided in an area surrounded by the first signal line and the second scanning line. Each sub-pixel has a TFT, and the TFT of the first sub-pixel is connected to the third scanning line and the first signal line. The TFT of the second subpixel is driven by the second scanning line and the first signal line. The TFT of the third subpixel is driven by the first scanning line and the second signal line. The TFT of the first subpixel is disposed closer to the first signal line than to the second signal line, and The TFT of the second subpixel is located closer to the third scan line than the second scan line. The first signal line is arranged closer to the first scanning line than the second signal line, and the second scanning line is arranged closer to the third scanning line than the third scanning line. The TFT of the third subpixel is arranged closer to the second signal line than to the first signal line. The second scan line is located closer to the first scan line than the third scan line, and is located closer to the second scan line than the third scan line. According to the embodiment, unlike the conventional arrangement in which all TFTs are arranged at equal intervals, The three TFTs contained in each pixel are located near the intersection of one signal line and three scanning lines. In this TFT group, as shown in FIG. The Ts are arranged facing each other with the scanning line or signal line in between, which is similar to the conventional Compared with the TFT arrangement in (1), the spacing between the TFTs can be expanded by approximately two times. That is, as shown in Figures 3 and 4, a TFT group including three TFTs in different pixels The distance X1 between the TFTs is greater than the distance X2 between the TFTs in the conventional TFT arrangement shown in FIG. Therefore, the alignment margin during the formation of the SOI layer is increased.

[0032] In addition, in a pixel in which a plurality of scanning lines are collected as in the present invention, the scanning lines and the signal lines overlap. When the BM is formed, the total margin provided to take into account the misalignment between the TFT substrate and the opposing substrate is The area can be reduced, which makes it possible to suppress the decrease in aperture ratio when misalignment occurs.

[0033] By applying the above-mentioned TFT arrangement, the thin film transistors provided in each sub-pixel Each of these can be provided close to the intersection of the scanning line and the signal line. Increase the alignment margin when forming the I layer, or improve the bonding between the TFT substrate and the opposing substrate. This can prevent a decrease in aperture ratio when misalignment occurs during the installation.

[0034] (Embodiment 3) FIG. 5 shows an active matrix display device in which four pixels are arranged around the intersection of the scanning lines and the signal lines. FIG. 1 is a diagram showing an example of a configuration in which two TFTs are arranged. a (also called pixel), b (also called second sub-pixel), c (also called third sub-pixel), and three long Sub-pixels with a square or rectangular shape are arranged in stripes with their long sides parallel to the signal lines. The signal lines are arranged in a row and four signal lines are collected together.

[0035] In addition, the pixel in this embodiment is divided into sub-pixels a (also called the first sub-pixel), b (also called the second sub-pixel), and (also called the third subpixel), c (also called the fourth subpixel (α=a, b, c) ) and four rectangular or quasi-rectangular sub-pixels are arranged so that the long sides are parallel to the signal lines. The display is arranged in stripes, with four signal lines gathered between adjacent pixels. This can be rephrased as, ``to be.''

[0036] The specific configuration of the sub-pixels a, b, and c is not limited. For example, R (red), G (green), B (blue) can be applied to three sub-pixels.

[0037] Four sub-pixels are arranged inside the grid formed by the scanning lines and signal lines. For example, for an arbitrary row (row i), three consecutive grids are arranged in the row direction as a unit, and four pixels are The elemental sub-pixels (12 sub-pixels) are arranged.

[0038] Scanning lines G(i), G(i+1) and signal lines S(j) to S(j+3), S(j+4) to S( j+7) is defined as a TFT provided in the first sub-pixel of the first pixel. r1 (also called the first thin film transistor), and the scanning lines G(i+1), G(i+2) and It is installed in the area surrounded by signal lines S(j) to S(j+3) and S(j+4) to S(j+7). The TFT provided in the second sub-pixel of the second pixel is referred to as Tr2 (also referred to as the second thin film transistor). The scanning lines G(i), G(i+1) and the signal lines S(j+4) to S(j+7), S The third sub-pixel of the third pixel located in the area surrounded by (j+8) to (j+11) is The TFT that is connected to the scanning line G(i+1) is designated as Tr3 (also called the third thin film transistor). , G(i+2) and signal lines S(j+4) to S(j+7), S(j+8) to S(j+11) The TFT provided in the fourth sub-pixel of the fourth pixel provided in the region surrounded by is designated as Tr4 (the fourth sub-pixel). Tr1 is connected to the scanning line G(i+1) and the signal line S(j Tr1 is connected to the scanning line G(i+1) and the signal line S(j+5), and T r3 is connected to the scanning line G(i+1) and the signal line S(j+7), and Tr4 is connected to the scanning line G(i+ 1) and signal line S(j+6). The same applies to other pixels, and the scanning line A group consisting of four TFTs is placed close to the intersection of the four signal lines. .

[0039] In this embodiment, the sub-pixels are arranged in stripes so that the long sides of the sub-pixels are parallel to the signal lines. Although the configuration in which four signal lines are gathered is shown, the long side of the sub-pixel is parallel to the scanning line. Even in a configuration in which the four scanning lines are arranged in stripes, the four TFTs The resulting groups can be placed at the intersections of scan lines and signal lines (not shown).

[0040] The configuration of this embodiment can be described in other ways as follows: The pixel shown in this embodiment has first to fourth sub-pixels arranged parallel to each other, and the first to fourth sub-pixels arranged parallel to each other The first to fourth signal lines (e.g., S(j+2) to S(j+5)) and the first and second parallel signal lines The first and third sub-pixels are the second and the fourth subpixel, and the third subpixel is closer to the second subpixel than the fourth subpixel. The first subpixel is closer to the fourth subpixel than the second subpixel. The first and second scanning lines are perpendicular to each other, and the second and third signal lines are provided between the first and fourth signal lines. The second signal line is closer to the first signal line than the fourth signal line, and the third signal line is closer to the first signal line than the fourth signal line. The first to fourth subpixels are closer to the fourth signal line than the second and third signal lines. The sub-pixels are arranged in the area surrounded by the first and second scanning lines. the TFT of the first subpixel is driven by the second scanning line and the third signal line; The TFT of the second subpixel is driven by the second scanning line and the second signal line, and the TFT of the third subpixel is driven by the second scanning line and the second signal line. The TFT is driven by the first scanning line and the first signal line, and the TFT of the fourth sub-pixel is driven by the first The TFT of the first subpixel is driven by the second signal line and the fourth signal line. the first scanning line and the second scanning line. The TFT of the second subpixel is arranged closer to the second signal line than to the third signal line. The third scan line is arranged close to the first scan line, and is arranged closer to the second scan line than to the first scan line. The TFT of the sub-pixel is arranged closer to the second signal line than to the third signal line, and The TFT of the fourth subpixel is located closer to the first scan line than the second signal line. The third signal line is arranged closer to the first scanning line than the second scanning line, and the third signal line is arranged closer to the first scanning line than the second scanning line. According to this embodiment, all the TFTs are arranged at equal intervals, unlike the conventional arrangement. The four TFTs in different pixels are located near the intersection of four signal lines and one scanning line. In this TFT group, as shown in Figure 5, The TFTs are arranged facing each other with the scanning or signal lines in between, Compared to the conventional TFT arrangement shown in 2, the spacing between the TFTs is expanded by approximately three times. That is, as shown in FIG. 5, a pixel including four TFTs in different pixels can be formed. The distance X1 between the TFT groups is larger than the distance between TFTs in a conventional TFT arrangement. This increases the alignment margin when forming the SOI layer.

[0041] In addition, in a pixel in which a plurality of scanning lines or signal lines are collected as in the present invention, When a BM that overlaps with the line is formed, the mark that is provided taking into consideration the positional deviation between the TFT substrate and the opposing substrate This reduces the total area of ​​the gin, thereby preventing a decrease in aperture ratio when the gin is misaligned. It can be controlled.

[0042] By applying the above-mentioned TFT arrangement, the thin film transistors provided in each sub-pixel Each of these can be provided close to the intersection of the scanning line and the signal line. Increase the alignment margin when forming the I layer, or improve the bonding between the TFT substrate and the opposing substrate. This can prevent a decrease in aperture ratio when misalignment occurs during the installation.

[0043] (Fourth embodiment) FIG. 6 shows an active matrix display device in which four pixels are arranged around the intersection of the scanning lines and the signal lines. FIG. 1 is a diagram showing an example of a configuration in which two TFTs are arranged. pixel), b (also called the second sub-pixel), c (also called the third sub-pixel), d (also called the fourth sub-pixel) The four rectangular or quasi-rectangular sub-pixels are arranged such that the long sides are connected to the signal lines. The stripes are arranged parallel to each other, and four signal lines are gathered between adjacent pixels. It is structured as follows.

[0044] The specific configuration of the sub-pixels a, b, c, and d is not limited. For example, R (red), G (green), ), B (blue), and W (white) can be applied to the four sub-pixels.

[0045] Scanning lines G(i), G(i+1) and signal lines S(j) to S(j+3), S(j+4) to S( j+7) is defined as a TFT provided in the first sub-pixel of the first pixel. r1 (also called the first thin film transistor), and the scanning lines G(i+1), G(i+2) and It is installed in the area surrounded by signal lines S(j) to S(j+3) and S(j+4) to S(j+7). The TFT provided in the second sub-pixel of the second pixel is referred to as Tr2 (also referred to as the second thin film transistor). The scanning lines G(i), G(i+1) and the signal lines S(j+4) to S(j+7), S The third sub-pixel of the third pixel located in the area surrounded by (j+8) to (j+11) is The TFT that is connected to the scanning line G(i+1) is designated as Tr3 (also called the third thin film transistor). , G(i+2) and signal lines S(j+4) to S(j+7), S(j+8) to S(j+11) The TFT provided in the fourth sub-pixel of the fourth pixel provided in the region surrounded by is designated as Tr4 (the fourth sub-pixel). Tr1 is connected to the scanning line G(i+1) and the signal line S(j Tr1 is connected to the scanning line G(i+1) and the signal line S(j+5), and T r3 is connected to the scanning line G(i+1) and the signal line S(j+7), and Tr4 is connected to the scanning line G(i+ 1) and signal line S(j+6). The same applies to other pixels, and the scanning line A group consisting of four TFTs is arranged close to the intersection of the signal line and the pixel.

[0046] In this embodiment, the sub-pixels are arranged in stripes so that the long sides of the sub-pixels are parallel to the signal lines. Although the configuration in which four signal lines are gathered is shown, the long side of the sub-pixel is parallel to the scanning line. Even in a configuration in which the four scanning lines are arranged in stripes, the four TFTs The resulting groups can be placed at the intersections of scan lines and signal lines (not shown).

[0047] The configuration of this embodiment can be described in other ways as follows: The pixel shown in this embodiment has first to fourth sub-pixels arranged parallel to each other, and the first to fourth sub-pixels arranged parallel to each other The first to fourth signal lines (e.g., S(j+2) to S(j+5)) and the first and second parallel signal lines The first and fourth sub-pixels are the second and the third subpixel, and the first subpixel is closer to the second subpixel than the third subpixel. The fourth subpixel is closer to the third subpixel than the second subpixel. The first to fourth signal lines are connected to the first The first and second scanning lines are perpendicular to each other, and the second and third signal lines are provided between the first and fourth signal lines. The second signal line is closer to the first signal line than the fourth signal line, and the third signal line is closer to the first signal line than the fourth signal line. The first to fourth subpixels are closer to the fourth signal line than the second and third signal lines. The sub-pixels are arranged in the area surrounded by the first and second scanning lines. The TFT of the first subpixel is driven by the second scanning line and the third signal line, The TFT of the second subpixel is driven by the first scanning line and the fourth signal line, and the TFT of the third subpixel is driven by the The TFT is driven by the second scanning line and the second signal line, and the TFT of the fourth sub-pixel is driven by the first The TFT of the first subpixel is driven by the scanning line and the first signal line. the first scanning line and the second scanning line. The TFT of the second subpixel is arranged closer to the third signal line than to the second signal line. The third scan line is arranged close to the first scan line and closer to the second scan line than the first scan line. The TFT of the sub-pixel is arranged closer to the second signal line than to the third signal line, and the TFT of the first scanning The TFT of the fourth subpixel is located closer to the second scan line than the third signal line. The first signal line is arranged closer to the second signal line, and the second scan line is arranged closer to the first scan line. According to this embodiment, all the TFTs are arranged at equal intervals, unlike the conventional arrangement. The four TFTs in different pixels are located near the intersection of four signal lines and one scanning line. In this TFT group, as shown in Figure 6, The TFTs are arranged so that they face each other across the scanning or signal lines. Compared to the conventional TFT arrangement, the spacing between the TFTs can be expanded by approximately three times. That is, as shown in FIG. 6, the TFT groups each including four TFTs included in different pixels are The distance X1 is larger than the distance between TFTs in a conventional TFT arrangement. The alignment margin during the formation of the I layer is increased.

[0048] In addition, as in the present invention, a plurality of scanning lines or signal lines, or a plurality of scanning lines and signal lines, may be collected. In this element, when a BM overlapping the scanning lines and signal lines is formed, the position of the TFT substrate and the counter substrate is The total area of ​​the margins provided to take into account misalignment is reduced. Therefore, it is possible to suppress the decrease in the aperture ratio.

[0049] By applying the above-mentioned TFT arrangement, the thin film transistors provided in each sub-pixel Each of these can be provided close to the intersection of the scanning line and the signal line. Increase the alignment margin when forming the I layer, or improve the bonding between the TFT substrate and the opposing substrate. This can prevent a decrease in aperture ratio when misalignment occurs during the installation.

[0050] (Embodiment 5) FIG. 7 shows an active matrix display device in which four pixels are arranged around the intersection of the scanning lines and the signal lines. FIG. 1 is a diagram showing an example of a configuration in which two TFTs are arranged. pixel), b (also called the second sub-pixel), c (also called the third sub-pixel), d (also called the fourth sub-pixel) The pixel is a mosaic array of four square or quasi-square sub-pixels. In addition, four signal lines are gathered between adjacent pixels.

[0051] The specific configuration of the sub-pixels a, b, c, and d is not limited. For example, R (red), G (green), ), B (blue), and W (white) can be applied to the four sub-pixels.

[0052] Scanning lines G(i), G(i+1) and signal lines S(j) to S(j+3), S(j+4) to S( j+7) is defined as a TFT provided in the first sub-pixel of the first pixel. r1 (also called the first thin film transistor), and the scanning lines G(i+1), G(i+2) and It is installed in the area surrounded by signal lines S(j) to S(j+3), S(j+4) to S(j+7). The TFT provided in the second sub-pixel of the second pixel is referred to as Tr2 (also referred to as the second thin film transistor). The scanning lines G(i), G(i+1) and the signal lines S(j+4) to S(j+7), S The third sub-pixel of the third pixel located in the area surrounded by (j+8) to (j+11) is The TFT that is connected to the scanning line G(i+1) is designated as Tr3 (also called the third thin film transistor). , G(i+2) and signal lines S(j+4) to S(j+7), S(j+8) to S(j+11) The TFT provided in the fourth sub-pixel of the fourth pixel provided in the region surrounded by is designated as Tr4 (the fourth sub-pixel). Tr1 is connected to the scanning line G(i+1) and the signal line S(j Tr1 is connected to the scanning line G(i+1) and the signal line S(j+5), and T r3 is connected to the scanning line G(i+1) and the signal line S(j+7), and Tr4 is connected to the scanning line G(i+ 1) and signal line S(j+6). The same applies to other pixels, and the scanning line A group consisting of four TFTs is placed close to the intersection of the four signal lines. .

[0053] In this embodiment, four signal lines are collected together, but four scanning lines are collected together. Even in this structure, a group of four TFTs is arranged at the intersection of the scanning line and the signal line. As shown in FIG. 8, the scanning lines and the signal lines can be arranged in the same area (not shown). A similar TFT arrangement can also be achieved by gathering two of each.

[0054] As shown below, the configuration of this embodiment shown in FIG. 7 can be expressed in another way. The pixel shown in this embodiment in FIG. 7 has first to fourth sub-pixels arranged in a mosaic pattern. , the first to fourth signal lines (e.g., S(j+2) to S(j+5)) arranged parallel to each other. ) and first and second scan lines (e.g., G(i) and G(i+1)) that are parallel to each other. The first subpixel is closer to the second scanning line than to the first scanning line, and is closer to the third scanning line than to the second scanning line. The second subpixel is closer to the first scan line than the second scan line, and is also closer to the second signal line. The third subpixel is closer to the second signal line than the first scan line. The fourth subpixel is closer to the first scan line than the second scan line. The first to fourth signal lines are closer to the scanning line 1 and closer to the second signal line than the third signal line. The first and second scanning lines are perpendicular to each other, and the second and third signal lines are set between the first and fourth signal lines. The second signal line is closer to the first signal line than the fourth signal line, and the third signal line is closer to the first signal line than the fourth signal line. The first to fourth subpixels are closer to the second signal line than the third signal line. Each sub-pixel is arranged in an area surrounded by the first scanning line, the second scanning line, and the first scanning line. The TFT of the first subpixel is driven by the second scanning line and the third signal line. The TFT of the second sub-pixel is driven by the first scanning line and the fourth signal line, and the TFT of the third sub-pixel is driven by the The TFT of the fourth sub-pixel is driven by the second scanning line and the second signal line. The TFT of the first subpixel is driven by the first scanning line and the first signal line. The third signal line is arranged closer to the second scanning line than the first signal line, and the second scanning line is arranged closer to the third signal line than the first scanning line. The TFT of the second subpixel is arranged closer to the third signal line than to the second signal line. The first scan line is positioned closer to the second scan line than the second scan line. The TFT of the third subpixel is disposed closer to the second signal line than to the third signal line, and The TFT of the fourth sub-pixel is arranged closer to the second scan line than to the third scan line. The first scanning line is disposed closer to the second signal line than the second scanning line. Similarly, as shown below, the configuration of this embodiment shown in FIG. The pixel has first to fourth sub-pixels arranged in a mosaic arrangement, First and second signal lines (e.g., S(j+1) and S(j+2)) arranged parallel to each other; It has first and second scan lines (for example, G(i+1) and G(i+2)) that are parallel to each other. The first subpixel is closer to the first scanning line than the second scanning line, and is closer to the first scanning line than the second scanning line. The second subpixel is closer to the first scan line than the second scan line, and the first signal line is closer to the second subpixel than the second scan line. The third subpixel is closer to the second signal line than the first scan line. The fourth subpixel is closer to the second scan line than the first scan line. The first and second signal lines are closer to the scanning lines and closer to the second signal lines than the first signal lines. The first to fourth subpixels are perpendicular to the first and second scanning lines. Each sub-pixel is located in the area surrounded by the first and second scanning lines. The TFT of the first subpixel is driven by the first scanning line and the first signal line. , the TFT of the second subpixel is driven by the first scanning line and the second signal line, and the TFT of the third subpixel is driven by the first scanning line and the second signal line. The TFT of the fourth sub-pixel is driven by the second scanning line and the first signal line, and the TFT of the fourth sub-pixel is driven by the second scanning line and the first signal line. The TFT of the first subpixel is driven by the first scanning line and the second signal line. The first scanning line is arranged closer to the first signal line than the second scanning line, and the second scanning line is arranged closer to the first signal line than the second scanning line. The TFT of the second subpixel is arranged closer to the second signal line than to the first signal line. The first scan line is arranged closer to the second scan line than the second scan line. The TFT of the third sub-pixel is disposed closer to the first signal line than to the second signal line, and the first The TFT of the fourth sub-pixel is located closer to the first scan line than to the second scan line, and the TFT of the fourth sub-pixel is located closer to the second scan line than to the first signal line. The first signal line is arranged closer to the second signal line than the second scan line, and closer to the second scan line than the first scan line. According to this embodiment, all the TFTs are arranged at equal intervals in the conventional arrangement. Unlike the conventional method, four TFTs in different pixels are arranged near the intersection of four signal lines and one scanning line. It is placed near the intersection of two signal lines and two scanning lines to form a group of TFTs. In this TFT group, as shown in FIGS. By arranging the TFTs facing each other with the signal line in between, the TFTs are arranged in a way that is different from the conventional TFT arrangement shown in Figure 9. In comparison, the spacing between the TFTs can be expanded by approximately two times. As shown in 7 and 8, the distance X1 between the TFT groups including four TFTs included in different pixels is This is larger than the distance X2 between the TFTs in the TFT arrangement shown in FIG. In addition, the sub-pixels are arranged as shown in Figs. The mosaic arrangement also has the secondary effect of improving visibility.

[0055] Furthermore, in the top view of FIG. 8, the wiring of the TFT does not overlap with the scanning lines and signal lines. In the normal manufacturing process, an insulating layer is formed to avoid connection with the scanning line or signal line. Then, contact holes are formed and a conductive layer is formed, whereby the TFT and the desired scanning However, in the embodiment shown in FIG. process is not required.

[0056] In addition, as in the present invention, a plurality of scanning lines or signal lines, or a plurality of scanning lines and signal lines, may be collected. In this element, when a BM overlapping the scanning lines and signal lines is formed, the position of the TFT substrate and the counter substrate is The total area of ​​the margins provided to take into account misalignment is reduced. Therefore, it is possible to suppress the decrease in the aperture ratio.

[0057] By applying the above-mentioned TFT arrangement, the thin film transistors provided in each sub-pixel Each of these can be provided close to the intersection of the scanning line and the signal line. Increase the alignment margin when forming the I layer, or improve the bonding between the TFT substrate and the opposing substrate. This can prevent a decrease in aperture ratio when misalignment occurs during the installation.

[0058] (Embodiment 6) FIG. 10 shows the structure of an active matrix display device, in which a pixel is formed around the intersection of a scanning line and a signal line. FIG. 1 is a diagram showing an example of a configuration in which two TFTs are arranged. subpixel), b (also called the second subpixel), c (also called the third subpixel), Sub-pixels having a rectangular shape or a shape similar to a rectangle are arranged in a delta array, and a pixel is formed between adjacent pixels. It consists of two scanning lines.

[0059] The specific configuration of the sub-pixels a, b, and c is not limited. For example, R (red), G (green), B (blue) can be applied to three sub-pixels.

[0060] Scanning lines G(i) and G(i+1), G(i+2) and G(i+3), and signal lines S(j The first pixel is disposed in the area surrounded by S(j+1), S(j+2), and S(j+3). The TFT is designated as Tr1 (also called the first thin film transistor), and the scanning lines G(i+2) and G (i+3), G(i+4) and G(i+5), and signal lines S(j) and S(j+1). The TFT provided in the second sub-pixel of the second pixel provided in the enclosed area is designated as Tr2 (second Tr1 is connected to the scanning line G(i+2) and the signal line S(j+1 ), and Tr2 is connected to the scanning line G(i+3) and the signal line S(j+1). The same applies to other pixels, and two lines are arranged close to the intersections of two scanning lines and signal lines. Place a group consisting of TFT.

[0061] In this embodiment, a configuration in which two scanning lines are gathered together has been shown, but it is also possible to use a configuration in which two signal lines are gathered together. Even in this structure, two TFTs can be placed near the intersection of the scanning line and the signal line. (Not shown) In addition, by collecting two scanning lines and two signal lines, The four TFTs are arranged near the intersections of the scanning lines and signal lines. This is also possible (not shown).

[0062] According to this embodiment, the TFTs constituting the sub-pixels of the display section are arranged as shown in FIG. By using this arrangement, it is possible to achieve the same results as in the conventional TFTs, where all TFTs are arranged at regular intervals, as shown in Figure 11. Compared with the FT arrangement, the spacing between the regions where the TFTs are located can be expanded by about two times. That is, as shown in FIG. 10, the distance between the TFT groups including two TFTs in different pixels is The distance X1 is larger than the distance X2 between the TFTs in the TFT arrangement shown in FIG. This increases the alignment margin when forming the SOI layer.

[0063] In addition, as in the present invention, a plurality of scanning lines or signal lines, or a plurality of scanning lines and signal lines, may be collected. In this element, when a BM overlapping the scanning lines and signal lines is formed, the position of the TFT substrate and the counter substrate is The total area of ​​the margins provided to take into account misalignment is reduced. Therefore, it is possible to suppress the decrease in the aperture ratio.

[0064] Furthermore, in the top view of Figure 10, the TFT wiring and the scanning and signal lines overlap each other. In the normal manufacturing process, in order to avoid connection with the scanning line or the signal line, By forming a layer, forming a contact hole, and forming a conductive layer, the TFT and the desired However, in this embodiment, Such a process is no longer necessary.

[0065] By applying the above-mentioned TFT arrangement, the thin film transistors provided in each sub-pixel Each of these can be provided close to the intersection of the scanning line and the signal line. Increase the alignment margin when forming the I layer, or improve the bonding between the TFT substrate and the opposing substrate. This can prevent a decrease in aperture ratio when misalignment occurs during the installation.

[0066] (Embodiment 7) In this embodiment, a transmissive liquid crystal display having a TFT arrangement as shown in the first to sixth embodiments is used. A method for fabricating the device will be described.

[0067] First, a process of forming a single crystal semiconductor thin film on a base substrate will be described with reference to FIG. A silicon oxide film or a silicon oxynitride film is formed on a rectangular single crystal semiconductor substrate 100. A silicon nitride film or a silicon nitride oxide film is formed thereon. 01 and a silicon nitride oxide film 102 are formed in this order. It is preferable to form the silicon nitride oxide film to a thickness of about 10 nm or more and 150 nm or less. It is preferable to form the film with a thickness of about 10 nm to 200 nm.

[0068] The silicon oxynitride film 101 and the silicon nitride oxide film 102 are formed by disposing sodium from the base substrate 106. This is provided to prevent impurities such as ions from diffusing and contaminating the single crystal semiconductor layer. Here, the silicon nitride oxide film has a composition containing more nitrogen than oxygen. The concentration ranges are 15 to 30 atomic % for oxygen, 20 to 35 atomic % for nitrogen, and 25 to 3 5 atomic % and hydrogen in the range of 15 to 25 atomic %, so that the total is 100 atomic %. The silicon oxynitride film is a film containing silicon dioxide at a certain concentration. The oxygen content is higher than that of the other metals, and the concentration range is 55 to 65 atomic % for oxygen and 100 to 150 atomic % for nitrogen. 1 to 20 atomic %, Si is 25 to 35 atomic %, and hydrogen is 0.1 to 10 atomic %. It refers to a material that contains each element at an arbitrary concentration so that the total is 100 atomic %. Alternatively, silicon oxynitride film 101 or nitride film may be used. The silicon oxide film 102 is not necessarily provided, and may be formed by ion implantation into the single crystal semiconductor substrate, as will be described later. Alternatively, a substrate on which only an ion-implanted layer is formed by ion implantation may be used.

[0069] Next, hydrogen ions 103 are implanted into the single crystal semiconductor substrate 100 to form an ion-implanted layer 104. (FIG. 14(A)). The hydrogen ion implantation here is performed on the single-crystal semiconductor The thickness of the single crystal semiconductor layer is preferably 10 nm to 200 nm. The thickness is preferably 10 nm to 50 nm. The acceleration voltage when implanting hydrogen ions is The thickness is set in consideration of the above. An ion-implanted layer 104 is formed in a region at a certain depth. Not only the element but also a rare gas may be used, or a mixture of the two may be used.

[0070] Next, a chemical vapor deposition process is performed on the silicon nitride oxide film 102 using a mixed gas of TEOS gas and oxygen gas. Chemical Vapor Deposition (CVD) or Plasma Silicon oxide film 105 formed by plasma chemical vapor deposition (plasma CVD) The silicon oxide film 105 is formed by ion implantation into the single crystal semiconductor substrate 100. It is also possible to form the CVD method using a mixture of TEOS gas and oxygen gas. When forming a silicon oxide film by the D method or plasma CVD method, 10 nm or more It is preferable to form the film to a thickness of 800 nm or less.

[0071] Here, TEOS gas is Tetra Ethyl Ortho Silica TEOS gas and oxygen gas are used in the CVD method or plasma CVD method. The silicon oxide film thus formed is provided at the bonding interface between the single crystal semiconductor substrate and the support substrate. This can further improve the adhesion of the substrate.

[0072] When the silicon oxynitride film 101 or the silicon nitride oxide film 102 is not formed, a single crystal semiconductor The surface of the substrate 100 is covered with a natural oxide film, a chemically formed oxide film, or an oxide film formed in an oxygen-containing atmosphere. It is preferable to form an ultra-thin oxide film by irradiating it with UV light. Before forming the silicon oxynitride film 101 or the silicon nitride oxide film 102 on the single crystal semiconductor substrate, In addition, it is preferable to form the above-described ultrathin oxide film on the surface of the single crystal semiconductor substrate 100 . Here, the chemically formed oxide film is oxidized by ozone water, hydrogen peroxide water, sulfuric acid, or other oxidizing agents. The thin film can be formed by treating the surface of a crystalline semiconductor substrate.

[0073] Next, a plurality of single crystal semiconductor substrates 100 that have been subjected to the steps of FIGS. 14(A) and 14(B) are prepared. As shown in FIG. 4(C), a silicon oxide film 105 and a base film 106 formed on a single crystal semiconductor substrate 100 are For simplicity of the drawing, two single crystal semiconductor substrates 106 are bonded to each other. 10. In this case, the surface of the base substrate 106 is The base film 107 is formed using a mixed gas of TEOS gas and oxygen gas. Examples of the silicon oxide film include a silicon oxide film formed by a CVD method or a plasma CVD method. The film 105 and the base film 107 are bonded to each other, so that the single crystal semiconductor substrate 100 and the base substrate The base film 107 such as a silicon oxide film may not necessarily be used. Although it is not necessary to form a film, it is preferable to provide the film in order to improve the adhesion of the substrate.

[0074] Here, the base substrate 106 may be a substrate having transparency, and therefore may be made of glass, quartz, or the like. In this embodiment, a glass substrate is used. Let's say.

[0075] In this embodiment, the bonding is performed between the silicon oxide film 105 on the single crystal semiconductor substrate 100 side and the base substrate. The bonding is formed by intimate contact with the base film 107 on the plate side. This bonding occurs at the atomic level and is achieved by van der Waals forces at room temperature. A strong bond is formed.

[0076] After the bond between the single crystal semiconductor substrate 100 and the base substrate 106 is formed, heat treatment is performed to form a single crystal. A part of the single crystal semiconductor substrate 100 (i.e., the single crystal semiconductor layer 108) is peeled off (FIG. 14(D)). Heating causes a volume change in the minute cavities formed in the ion-implanted layer 104. A fracture surface is generated along the ion-implanted layer 104, and the single-crystal semiconductor layer 108 is broken along the fracture surface. After that, to further strengthen the bond, It is preferable to perform heat treatment at a temperature of 700° C. to 700° C. A single crystal semiconductor layer 109 is formed. After that, a chemical reaction is performed to flatten the surface. Chemical Mechanical Polishing (CMP) It is preferable to do so.

[0077] As shown in FIG. 14(D), a plurality of single-crystal semiconductor layers 10 formed on a base substrate 106 9, a joint 110 (gap) is formed between adjacent single crystal semiconductor layers. 2. When using the conventional TFT arrangement shown in Figures 4, 9, and 11, the distance between each TFT is narrow. Therefore, it is very difficult to form all the TFTs while avoiding the joints 110. However, by using the TFT arrangements shown in the first to sixth embodiments, the joints 110 can be avoided and the display can be efficiently displayed. This makes it possible to place TFTs on the

[0078] Next, a resist is selectively formed on the single crystal semiconductor layer 109, and a single crystal semiconductor layer is formed using the resist as a mask. The crystalline semiconductor layer 109 is etched to form an island-shaped single-crystalline semiconductor layer 201. (Figure 14(E)).

[0079] Hereinafter, the process of forming a TFT and manufacturing a liquid crystal display device will be described with reference to FIG.

[0080] A first insulating layer 202 is formed to cover the island-shaped single-crystal semiconductor layer 201. The silicon is deposited to a thickness of 10 to 150 nm using a plasma CVD method or a sputtering method. The first insulating layer 202 is formed of an insulating film containing silicon nitride, silicon oxide, silicon oxynitride, or the like. The insulating layer 10 may be formed of a material such as silicon oxide or nitride, typified by silicon nitride oxide. The insulating layer may be a three-layer laminate of a silicon nitride film, a silicon oxide film, and a silicon nitride film. A single layer or a two-layer laminate of silicon oxynitride films may be used. Preferably, a nitride film having a dense film quality is used. A silicon film is preferably used. Furthermore, between the island-shaped single crystal semiconductor layer 201 and the first insulating layer 202, , a film having a thickness of 1 to 100 nm, preferably 1 to 10 nm, and more preferably 2 to 5 nm. A thin silicon oxide film may be formed. The thin silicon oxide film may be formed by the GRTA method. , a method of oxidizing the surface of a semiconductor region using the LRTA method or the like to form a thermal oxide film, It is possible to form a thin silicon oxide film. To form a dense insulating film with little cracking, a rare gas element such as argon is added to the reaction gas, It is preferable to mix the first insulating layer 202 with the gate insulating layer. It functions as such.

[0081] Next, a first conductive layer 202 is formed on the first insulating layer 202, which functions as a gate electrode layer and a connection electrode. Here, an example in which the first conductive layer 203 is formed as a single layer is shown. The first conductive layer 20 may have a structure in which two or more conductive layers are laminated. 3 is formed by selectively etching the conductive layer formed over the first insulating layer 202. It is formed more.

[0082] The first conductive layer 203 is made of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), or the like. Buten (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb) It is made of an element selected from the above, or an alloy or compound containing these elements as the main component. In addition, semiconductors such as polycrystalline silicon doped with impurity elements such as phosphorus can be used. For example, when the first conductive layer 203 has a laminated structure, The first layer is preferably made of tantalum nitride, and the second layer is preferably made of tungsten. However, the combination is not limited to this, and the above materials can be freely combined. .

[0083] Subsequently, an impurity element is introduced into the island-shaped single-crystal semiconductor layer 201 using the first conductive layer 203 as a mask. By introducing the impurity atoms, the island-shaped single crystal semiconductor layer 201 is provided with impurity regions 201b, 201c and 201d. The channel region 201a is formed by doping the first impurity element. After the conductive layer 203 is formed so as to cross the island-shaped single-crystal semiconductor layer 201, an impurity element is added. In order to do this, the impurity is introduced into the region not covered by the first conductive layer 203 to form the impurity region. The regions 201b and 201c are formed, and the region covered with the first conductive layer 203 contains impurity elements. An unimplanted channel region 201a is formed.

[0084] Here, the impurity element is an impurity element that imparts n-type conductivity or an impurity element that imparts p-type conductivity. Impurity elements that exhibit n-type include phosphorus (P) and arsenic (As). Impurity elements that exhibit p-type conductivity include boron (B) and aluminum (A For example, phosphorus (P) or gallium (Ga) can be used as an impurity element. ) to 1×10 18 ~1×10 21 atoms / cm 3 The concentration of the island-like single bond The impurity regions 201b and 201c are introduced into the crystalline semiconductor layer 201 to exhibit n-type. In addition, a low concentration of impurities is formed between the channel region 201a and the source region or the drain region. A low concentration impurity region (LDD region) may be formed by adding .

[0085] Next, a second insulating layer 204 is formed to cover the first conductive layer 203 and the first insulating layer 202. Here, the second insulating layer 204 is formed by an oxide film formed by a CVD method, a sputtering method, or the like. Silicon oxide nitride (SiOxNy) (x>y>0), silicon oxide nitride (S iNxOy) (x>y>0), etc. can also be used. , polyvinylphenol, benzocyclobutene resin, acrylic, epoxy and other organic materials or a single layer made of a siloxane material such as a siloxane resin, an oxazole resin, or the like; It can be provided in a laminated structure. Note that the siloxane material is a material containing Si-O-Si bonds. Siloxane has a skeletal structure made up of bonds between silicon (Si) and oxygen (O). The substituents include organic groups (e.g., alkyl groups, aromatic hydrocarbons) and fluoro groups. The organic group may contain a fluoro group. The oxazole resin may be, for example, a photosensitive resin. Photosensitive polybenzoxazole has a low dielectric constant. (Relative dielectric constant 2.9 at room temperature and 1MHz), high heat resistance (differential thermal and thermogravimetric simultaneous measurement (TG / DT A:Thermogravimetry-Differential Thermal Analysis) with a temperature rise of 5℃ / min, the thermal decomposition temperature is 550℃, and the water absorption rate is low (2 0.3% in 4 hours. Oxazole resin is a material with a relative dielectric constant (3.2 Compared to silicon dioxide, the dielectric constant is low (approximately 2.9) and the occurrence of parasitic capacitance is suppressed. Here, the second insulating layer 204 is formed by the CVD method. Formed silicon oxide, silicon oxynitride (SiOxNy) (x>y>0) or oxynitride Silicon (SiNxOy) (x>y>0) is formed as a single layer or a multilayer. Polyimide, polyamide, polyvinylphenol, benzocyclobutene resin, acrylic , an organic material such as epoxy, a siloxane material such as siloxane resin, or an oxazole resin Next, a resist is selectively formed on the second insulating layer 204. As the resist, a positive photoresist or a negative photoresist can be selected appropriately. It can be used.

[0086] Next, the second insulating layer 204 and the first insulating layer 202 are dried using the resist as a mask. Contact holes reaching the island-shaped single-crystal semiconductor layer 201 are formed by etching. The etching gas used in dry etching is selected so that the semiconductor layer is not etched. As described above, there is no particular limitation as long as the selectivity between the second insulating layer 204 and the first insulating layer 202 can be obtained. Although not specified, examples of suitable gases include fluorine-based gases such as CF4, NF3, SF6, CHF3, and CF4. Or, a mixture of the fluorine-based gas with an appropriate amount of inert gas such as O2 gas, H2 gas, He, or Ar. A mixed gas of CHF3 and He, or a mixed gas of CF4 and H2 is preferably used. or a mixed gas of CHF3, He, and H2 may be used.

[0087] Next, a conductive layer is inserted into the contact holes formed in the second insulating layer 204 and the first insulating layer 202. The surfaces of the impurity regions 201b and 201c of the island-shaped single-crystal semiconductor layer 201 are filled with an impurity material. The second conductive layer 205 is formed to electrically connect the second The conductive layer formed on the insulating layer 204 is selectively etched. It is possible.

[0088] Next, a third insulating layer 206 is formed to cover the second insulating layer 204 and the second conductive layer 205. The third insulating layer 206 is formed of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. , aluminum nitride, aluminum oxynitride (AlON), where the nitrogen content is higher than the oxygen content Also commonly used is aluminum oxide nitride (AlNO) or aluminum oxide, a diamond-like Carbon (DLC), nitrogen-containing carbon film (CN), PSG (phosphor glass), BPSG (phosphor Select from materials including boron glass, alumina film, polysilazane, and other inorganic insulating materials. The material can be a siloxane resin. An insulating material may be used, and the organic material may be either photosensitive or non-photosensitive, and may be poly. Imide, acrylic, polyamide, polyimideamide, resist or benzocyclobutene Resins can be used.

[0089] In this embodiment, the third insulating layer 206 is formed by spin coating or the like. This is preferable.

[0090] Next, a resist is selectively formed on the third insulating layer 206, and etching is performed using the resist as a mask. By performing etching, contact holes reaching the second conductive layer 205 are formed. A pixel electrode 207 electrically connected to the second conductive layer 205 is formed on the third insulating layer 206. Further, an alignment film 208 is formed on the third insulating layer 206 and the pixel electrode 207 .

[0091] Next, the opposing substrate 802 is prepared. The opposing substrate 802 is made of a glass substrate 300 and a transparent conductive film. The liquid crystal display device is composed of a counter electrode 301 and an alignment film 302.

[0092] Next, the TFT substrate 801 and the counter substrate 802 obtained in the above process are attached via a sealant. Here, in order to keep the distance between the two substrates constant, the alignment film 208 and the alignment film 302 are aligned. A spacer may be provided between the two substrates. After that, a liquid crystal 803 is injected between the two substrates, and the liquid crystal 803 is sealed with a sealing material. By sealing the device, a transmission type liquid crystal display device as shown in FIG. 15 is completed.

[0093] By using the present invention, the alignment margin during SOI layer formation is increased, and In other words, it is possible to improve productivity and reduce display defects. It is possible to create the following.

[0094] In this embodiment, a transmissive liquid crystal display device has been described. For example, the display device may be a display device having a reflective electrode as the pixel electrode 207. By using a layer or providing a reflective film on the upper or lower surface of the pixel electrode 207, a reflective liquid crystal display can be realized. It can also be applied to a display device having an electroluminescence element ( It can also be applied to EL display devices.

[0095] (Embodiment 8) FIG. 16 shows an example of the configuration of a mobile phone 1000 to which the present invention is applied, and FIG. 16(A) is a front view. 16(B) is a rear view, and FIG. 16(C) is a development view. The mobile phone 1000 is a It has the functions of both a mobile information terminal and a computer, and can perform various functions in addition to voice calls. It is a so-called smartphone capable of data processing.

[0096] The mobile phone 1000 is composed of two housings, housings 1001 and 1002. Housing 1 001 includes a display unit 1101, a speaker 1102, a microphone 1103, and operation keys. 1104, pointing device 1105, camera lens 1106, external connection terminal 1 107, etc., and the housing 1002 includes a keyboard 1201, an external memory slot 1202, It is equipped with a camera lens 1203, a light 1204, an earphone jack 1108, etc. In addition, the antenna is built into the housing 1001 .

[0097] In addition to the above configuration, a contactless IC chip, a small recording device, etc. may be built in.

[0098] The display device shown in the above embodiment can be incorporated into the display unit 1101. The display direction changes appropriately depending on the form. The camera lens 1101 is on the same surface as the display unit 1101. 106, it is possible to make a video call. It is possible to take still images and videos using the camera lens 1203 and light 1204. The speaker 1102 and microphone 1103 are not limited to voice calls, but can also be used for video calls, recording, etc. The operation keys 1104 are used for simple operations such as making and receiving calls and sending e-mails. It is possible to input information, scroll the screen, move the cursor, etc. Furthermore, the overlapping housings 1 The casing 1001 and the housing 1002 (Fig. 16(A)) slide and unfold as shown in Fig. 16(C), and the In this case, the keyboard 1201 and the pointing device The external connection terminal 1107 can be used with an AC adapter or a US It can be connected to various cables such as B cable, and can be used for charging and connecting to a personal computer, etc. Data communication is possible. In addition, a recording medium can be inserted into the external memory slot 1202 to enable larger It can handle large amounts of data storage and movement.

[0099] In addition to the above functions, it may also have infrared communication functions, television reception functions, etc. stomach.

[0100] By using the present invention, a highly reliable display device with reduced display defects can be manufactured. This becomes possible. [Explanation of symbols]

[0101] 10 BM 11 BM 100 Single crystal semiconductor substrate 101 Silicon oxynitride film 102 Silicon oxynitride film 103 Hydrogen ions 104 Ion implantation layer 105 Silicon oxide film 106 Base board 107 Base film 108 Single crystal semiconductor layer 109 Single crystal semiconductor layer 110 Seam 201 Island-shaped single crystal semiconductor layer 201a channel region 201b Impurity region 201c Impurity region 202 First insulating layer 203 First conductive layer 204 Second insulating layer 205 Second conductive layer 206 Third insulating layer 207 Pixel electrode 208 Alignment Film 300 glass substrate 301 Counter electrode 302 Alignment film 801 TFT substrate 802 Opposing substrate 803 LCD 1000 mobile phones 1001 Case 1002 Case 1101 Display section 1102 Speaker 1103 Microphone 1104 Operation key 1105 Pointing Device 1106 Camera Lens 1107 External connection terminal 1108 Earphone jack 1201 keyboard 1202 external memory slot 1203 Camera Lens 1204 Light

Claims

1. a pixel portion including a first scanning line, a second scanning line, a third scanning line, a signal line, a first transistor, a second transistor, a third transistor, a first pixel electrode, a second pixel electrode, a third pixel electrode, and a black matrix; the first transistor has one of a source and a drain electrically connected to the signal line, the other of the source and the drain electrically connected to the first pixel electrode, and a gate electrically connected to the first scanning line; the second transistor has one of a source and a drain electrically connected to the signal line, the other of the source and the drain electrically connected to the second pixel electrode, and a gate electrically connected to the second scanning line; the third transistor has one of a source and a drain electrically connected to the signal line, the other of the source and the drain electrically connected to the third pixel electrode, and a gate electrically connected to the third scanning line; In a plan view of the pixel unit, the first scanning line, the second scanning line, and the third scanning line extend in a first direction, the second scanning line is disposed adjacent to the first scanning line and adjacent to the third scanning line in a plan view of the pixel unit; In a plan view of the pixel unit, the signal line has a region disposed between the first transistor and the second transistor and a region disposed between the second transistor and the third transistor; a region where the second pixel electrode is disposed and a region where the third pixel electrode is disposed are provided between the second transistor and the third transistor in a plan view of the pixel unit; In a plan view of the pixel unit, the signal line has a first region extending in a second direction intersecting the first direction, and a second region extending in a third direction intersecting the first direction and intersecting the second direction; the second region has a region that is disposed between the first scanning line and the second scanning line and between the first pixel electrode and the second pixel electrode in a plan view of the pixel unit, a liquid crystal display device, wherein, in a planar view of the pixel portion, the black matrix has a region overlapping with the first scanning line, a region overlapping with the second scanning line, a region overlapping between the first scanning line and the second scanning line, and a region overlapping with the signal line.

2. a pixel portion including a first scanning line, a second scanning line, a third scanning line, a signal line, a first transistor, a second transistor, a third transistor, a first pixel electrode, a second pixel electrode, a third pixel electrode, and a black matrix; the first transistor has one of a source and a drain electrically connected to the signal line, the other of the source and the drain electrically connected to the first pixel electrode, and a gate electrically connected to the first scanning line; the second transistor has one of a source and a drain electrically connected to the signal line, the other of the source and the drain electrically connected to the second pixel electrode, and a gate electrically connected to the second scanning line; the third transistor has one of a source and a drain electrically connected to the signal line, the other of the source and the drain electrically connected to the third pixel electrode, and a gate electrically connected to the third scanning line; In a plan view of the pixel unit, the first scanning line, the second scanning line, and the third scanning line extend in a first direction, the second scanning line is disposed adjacent to the first scanning line and adjacent to the third scanning line in a plan view of the pixel unit; In a plan view of the pixel unit, the signal line has a region disposed between the first transistor and the second transistor and a region disposed between the second transistor and the third transistor; a region where the second pixel electrode is disposed and a region where the third pixel electrode is disposed are provided between the second transistor and the third transistor in a plan view of the pixel unit; In a plan view of the pixel unit, the second pixel electrode has a region disposed between the first pixel electrode and the third pixel electrode, In a plan view of the pixel unit, the signal line has a first region extending in a second direction intersecting the first direction, and a second region extending in a third direction intersecting the first direction and intersecting the second direction; the second region has a region that is disposed between the first scanning line and the second scanning line and between the first pixel electrode and the second pixel electrode in a plan view of the pixel unit, a liquid crystal display device, wherein, in a planar view of the pixel portion, the black matrix has a region overlapping with the first scanning line, a region overlapping with the second scanning line, a region overlapping between the first scanning line and the second scanning line, and a region overlapping with the signal line.

Images