Information processing device and information processing method

Abstract

To provide an information processing device which can detect an attack inserting a failure of the same value at the same timing into two arithmetic circuits having the same constitution as projection objects, when the attack is performed.SOLUTION: An information processing device includes: a first arithmetic circuit to which first data is input, executing first arithmetic by a first algorithm on the basis of the input first data, and outputting second data indicating the arithmetic result of the first arithmetic; a second arithmetic circuit to which the first data is input, executing second arithmetic by a second algorithm that has the same arithmetic result though being different in the arithmetic procedure from that of the first algorithm, on the basis of the input first data, and outputting third data indicating the arithmetic result of the second arithmetic; and a comparison circuit for comparing the second data with the third data, and detecting receiving of a failure utilization attack when the second data and the third data are different.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an information processing device and an information processing method. [Background technology]

[0002] With the recent development of IoT technology, various information processing devices are now connected to networks, which increases the threat of secret information being stolen from information processing devices through physical attacks. Physical attacks include timing attacks, power analysis attacks, and fault attacks (FA). Timing attacks steal secret information by analyzing processing time. Power analysis attacks steal secret information by analyzing the power consumption generated when an information processing device processes secret information. Power analysis attacks include simple power analysis (SPA) and differential power analysis (DPA). FA attacks intentionally induce calculation errors by applying physical stimuli to an information processing device while it is processing secret information, and then analyze its behavior to steal secret information.

[0003] Public key cryptography is one type of cryptographic method. Among the various operations used in public key cryptography, scalar multiplication and modular exponentiation are the two that have the most significant and critical computational costs. The binary algorithm is widely implemented as a method for accelerating scalar multiplication and modular exponentiation. However, the binary algorithm has a characteristic processing time or waveform depending on the value of the input secret information, making it vulnerable to attacks such as timing attacks and SPA. Countermeasures against timing attacks and SPA include the Always algorithm, BRIP, and Montgomery ladder algorithm. In these algorithms, the processing time or waveform is constant regardless of the value of the secret information.

[0004] On the other hand, FA is susceptible to attacks that identify secret information by analyzing erroneous calculation results obtained by rewriting part of the value during the calculation. One countermeasure against such attacks is to duplicate the calculation circuit to be protected and compare the calculation results of the two calculation circuits. Since the two calculation circuits have the same circuit configuration, the same result is obtained when the same value is input. When one of the calculation circuits is attacked by FA, ​​a calculation error occurs in the attacked calculation circuit. Therefore, by comparing the calculation results of the two calculation circuits and finding that the two calculation results are different, it is possible to detect an FA attack. If the two calculation results match, the information processing device outputs the correct calculation result; on the other hand, if the two calculation results do not match, the information processing device does not output the calculation result or outputs an unrelated value.

[0005] Incidentally, Patent Document 1 discloses a semiconductor device according to the background art, in which a plurality of IC chips are stacked and are capable of executing data processing including cryptographic calculations, the plurality of IC chips execute the same cryptographic calculations in parallel to calculate respective calculation results, one of the plurality of IC chips has an element surface covered by another IC chip, and the plurality of calculation results corresponding to the plurality of IC chips are compared with each other, and the content of subsequent data processing is controlled based on the comparison result. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-58777 Summary of the Invention [Problem to be solved by the invention]

[0007] According to the method of duplicating the arithmetic circuit to be protected as a countermeasure against FA, two arithmetic circuits with the same circuit configuration perform the same calculation at the same time. Therefore, if a fault with the same value is inserted at the same time into both arithmetic circuits during the calculation, the two arithmetic circuits will generate the same calculation error. This type of attack, in which a fault with the same value is inserted at the same time into two arithmetic circuits, is hereafter referred to as "double FA." As a result, the calculation results of the two arithmetic circuits will be the same, making it impossible to detect FA.

[0008] The present invention has been made in consideration of the above circumstances, and aims to provide an information processing device and an information processing method that are capable of detecting an attack even when double FA is performed on two arithmetic circuits that are the target of protection. [Means for solving the problem]

[0009] An information processing device according to a first aspect of the present invention includes a first arithmetic circuit that receives first data, executes a first operation according to a first algorithm based on the input first data, and outputs second data indicating a result of the first operation; a second arithmetic circuit that receives the first data, executes a second operation according to a second algorithm that has a different operation procedure from the first algorithm but produces the same result as the first algorithm, and outputs third data indicating a result of the second operation; and a comparison circuit that compares the second data with the third data and detects that a fault exploitation attack has been performed if the second data and the third data are different.

[0010] According to the first aspect, the first arithmetic circuit performs a first operation using a first algorithm based on input first data and outputs second data. The second arithmetic circuit performs a second operation using a second algorithm based on the input first data, the second algorithm having a different operation procedure from the first algorithm but producing the same operation result, and outputs third data. The comparison circuit detects that a fault exploitation attack has been performed when the second data and the third data are different. Therefore, even if double FA is performed on the first arithmetic circuit and the second arithmetic circuit, the attack can be detected.

[0011] An information processing device according to a second aspect of the present invention is an information processing device according to the first aspect, wherein the first arithmetic circuit and the second arithmetic circuit are scalar multiplication circuits, the first arithmetic circuit has a first adder circuit and a first doubling circuit, the second arithmetic circuit has a second adder circuit and a second doubling circuit, and the first arithmetic circuit performs, in order from the most significant bit of the first data, a doubling by the first doubling circuit and an addition by the first adder circuit when the logic of the bit to be processed is "1". The first operation is performed by the first doubling circuit, and if the logic of the bit to be processed is "0", the first operation is doubling by the first doubling circuit. The second operation circuit, starting from the least significant bit of the first data, performs addition by the second adding circuit and doubling by the second doubling circuit as the second operation if the logic of the bit to be processed is "1", and if the logic of the bit to be processed is "0", performs doubling by the second doubling circuit as the second operation.

[0012] According to the second aspect, even if double FA is performed on a first arithmetic circuit constituting a scalar multiplication circuit that performs scalar multiplication using the right-hand binary method and a second arithmetic circuit constituting a scalar multiplication circuit that performs scalar multiplication using the left-hand binary method, the attack can be detected.

[0013] An information processing device according to a third aspect of the present invention is, in the first aspect, such that when the logic of the bit to be processed is "0", the first arithmetic circuit and the second arithmetic circuit further perform waiting processing equivalent to the processing time of addition.

[0014] According to the third aspect, it is possible to further impart resistance to attacks such as timing attacks.

[0015] An information processing device according to a fourth aspect of the present invention is, in the second aspect, such that the first arithmetic circuit further performs addition by the first adder circuit when the logic of the bit to be processed is "0", and the second arithmetic circuit further performs addition by the second adder circuit when the logic of the bit to be processed is "0".

[0016] According to the fourth aspect, it is possible to further provide resistance to attacks such as timing attacks and simple power analysis.

[0017] An information processing device according to a fifth aspect of the present invention is the information processing device of the third or fourth aspect, wherein the processing time for addition is longer than the processing time for doubling, the execution period of the doubling by the first doubling circuit and the execution period of the doubling by the second doubling circuit do not overlap with each other, and the first doubling circuit and the second doubling circuit are configured to share a single doubling circuit.

[0018] According to the fifth aspect, the first doubling circuit and the second doubling circuit are configured by sharing one doubling circuit, thereby making it possible to reduce the circuit size.

[0019] An information processing device according to a sixth aspect of the present invention is the information processing device of the fifth aspect, wherein the first addition circuit and the second addition circuit are further configured to share a single addition circuit, and the first arithmetic circuit and the second arithmetic circuit further perform a wait process corresponding to the processing time difference between the addition and the doubling after performing the doubling.

[0020] According to the sixth aspect, the first adder circuit and the second adder circuit are configured by sharing one adder circuit, thereby making it possible to further reduce the circuit size.

[0021] An information processing device according to a seventh aspect of the present invention is an information processing device according to the first aspect, wherein the first arithmetic circuit and the second arithmetic circuit are modular exponentiation arithmetic circuits, the first arithmetic circuit has a first multiplier circuit and a first squaring circuit, the second arithmetic circuit has a second multiplier circuit and a second squaring circuit, and the first arithmetic circuit, starting from the most significant bit of the first data, executes squaring by the first squaring circuit and multiplication by the first multiplier circuit as the first operation when the logic of the bit to be processed is "1", and executes squaring by the first squaring circuit as the first operation when the logic of the bit to be processed is "0", and the second arithmetic circuit, starting from the least significant bit of the first data, executes multiplication by the second multiplier circuit and squaring by the second squaring circuit as the second operation when the logic of the bit to be processed is "1", and executes squaring by the second squaring circuit as the second operation when the logic of the bit to be processed is "0".

[0022] According to the seventh aspect, even if a double FA is performed on a first arithmetic circuit constituting a modular exponentiation circuit that performs modular exponentiation using the right-hand binary method and a second arithmetic circuit constituting a modular exponentiation circuit that performs modular exponentiation using the left-hand binary method, the attack can be detected.

[0023] An information processing device according to an eighth aspect of the present invention is the seventh aspect, wherein when the logic of the bit to be processed is "0", the first arithmetic circuit and the second arithmetic circuit further perform waiting processing equivalent to the processing time of multiplication.

[0024] According to the eighth aspect, it is possible to further impart resistance to attacks such as timing attacks.

[0025] An information processing device according to a ninth aspect of the present invention is the seventh aspect, wherein the first arithmetic circuit further performs multiplication by the first multiplier circuit when the logic of the bit to be processed is "0", and the second arithmetic circuit further performs multiplication by the second multiplier circuit when the logic of the bit to be processed is "0".

[0026] According to the ninth aspect, it is possible to further provide resistance to attacks such as timing attacks and simple power analysis.

[0027] An information processing device according to a tenth aspect of the present invention is, in the eighth or ninth aspect, an information processing device in which the processing time for multiplication is longer than the processing time for squaring, the period during which the first squaring circuit performs squaring and the period during which the second squaring circuit performs squaring do not overlap, and the first squaring circuit and the second squaring circuit are configured to share a single squaring circuit.

[0028] According to the tenth aspect, the first squaring circuit and the second squaring circuit are configured by sharing one squaring circuit, thereby making it possible to reduce the circuit size.

[0029] An information processing device according to an eleventh aspect of the present invention is the information processing device of the tenth aspect, wherein the first multiplication circuit and the second multiplication circuit are further configured to share one multiplication circuit, and the first arithmetic circuit and the second arithmetic circuit further execute a waiting process corresponding to the processing time difference between the multiplication and the squaring after executing the squaring.

[0030] According to the eleventh aspect, the first multiplication circuit and the second multiplication circuit are configured by sharing one multiplication circuit, thereby making it possible to further reduce the circuit size.

[0031] An information processing method according to a twelfth aspect of the present invention comprises an information processing device that performs a first operation using a first algorithm based on first data, performs a second operation using a second algorithm based on the first data, the second algorithm having a different operation procedure from the first algorithm but producing the same operation result, compares second data indicating the operation result of the first operation with third data indicating the operation result of the second operation, and detects that the information processing device has been subjected to a fault exploitation attack if the second data and the third data are different.

[0032] According to a twelfth aspect, an information processing device executes a first operation using a first algorithm based on first data. The information processing device also executes a second operation using a second algorithm based on the first data, the second algorithm having a different operation procedure from the first algorithm but producing the same operation result. Furthermore, the information processing device detects that it has been subjected to a fault exploitation attack when second data indicating the operation result of the first operation differs from third data indicating the operation result of the second operation. Therefore, even if double FA is performed during the execution of the first operation and the second operation, the attack can be detected. [Effects of the Invention]

[0033] According to the present invention, even if double FA is performed on two arithmetic circuits to be protected, the attack can be detected. [Brief explanation of the drawings]

[0034] [Figure 1] 1 is a diagram showing a simplified configuration of an information processing device according to the present invention; [Figure 2] 1 is a diagram showing a simplified first configuration example of an information processing device according to a first embodiment. [Figure 3] FIG. 10 is a diagram illustrating an example of a calculation procedure for scalar multiplication using the right binary method and the left binary method. [Figure 4] FIG. 2 is a diagram illustrating an example of processing executed by an information processing device according to a first configuration example of the first embodiment. [Figure 5] FIG. 2 is a diagram showing a simplified second configuration example of the information processing device according to the first embodiment. [Figure 6] FIG. 10 is a diagram illustrating an example of a calculation procedure for modular exponentiation using a rightward binary method and a leftward binary method. [Figure 7] FIG. 10 is a diagram illustrating an example of processing executed by an information processing device according to a second configuration example of the first embodiment. [Figure 8] FIG. 10 is a diagram illustrating an example of processing executed by an information processing device according to a first configuration example of the second embodiment. [Figure 9] FIG. 10 is a diagram illustrating an example of processing executed by an information processing device according to a second configuration example of the second embodiment. [Figure 10] FIG. 13 is a diagram illustrating an example of processing executed by an information processing device according to a first configuration example of the third embodiment. [Figure 11] FIG. 13 is a diagram illustrating an example of processing executed by an information processing device according to a second configuration example of the third embodiment. [Figure 12] FIG. 10 is a diagram showing an example of a calculation procedure for scalar multiplication using a right-hand Montgomery ladder and a left-hand Montgomery ladder. [Figure 13] FIG. 10 is a diagram illustrating an example of a procedure for scalar multiplication using right-direction BRIP and left-direction BRIP. [Figure 14] FIG. 10 is a diagram showing a simplified first configuration example of an information processing device according to a fourth embodiment. [Figure 15] FIG. 10 is a diagram showing a simplified second configuration example of an information processing device according to a fourth embodiment. [Figure 16] FIG. 10 is a diagram showing a simplified first configuration example of an information processing device according to a fifth embodiment. [Figure 17] FIG. 13 is a diagram illustrating an example of processing executed by an information processing device according to a first configuration example of the fifth embodiment. [Figure 18] FIG. 10 is a diagram showing a simplified second configuration example of an information processing device according to a fifth embodiment. [Figure 19] FIG. 13 is a diagram illustrating an example of processing executed by an information processing device according to a second configuration example of the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Elements with the same reference numerals in different drawings indicate the same or corresponding elements. In addition, multiple embodiments described below can be applied in any combination.

[0036] FIG. 1 is a simplified diagram showing the configuration of an information processing device 1 according to the present invention. The information processing device 1 includes a first arithmetic circuit 11, a second arithmetic circuit 12, and a comparison circuit 13. First data D1 is input to the first arithmetic circuit 11. The first arithmetic circuit 11 performs a first operation according to a first algorithm based on the input first data D1 and outputs second data D2 indicating the operation result of the first operation. The first data D1 is input to the second arithmetic circuit 12 in parallel with the first arithmetic circuit 11. The second arithmetic circuit 12 performs a second operation according to a second algorithm based on the input first data D1 and outputs third data D3 indicating the operation result of the second operation. The second algorithm is an algorithm that has a different operation procedure from the first algorithm but produces the same operation result. Details of the first and second algorithms will be described later. The comparison circuit 13 receives the second data D2 from the first arithmetic circuit 11 and the third data D3 from the second arithmetic circuit 12. The comparison circuit 13 compares the second data D2 and the third data D3. If the second data D2 and the third data D3 are identical, the comparison circuit 13 detects that the first arithmetic circuit 11 and the second arithmetic circuit 12 have not been subjected to a fault attack. If the second data D2 and the third data D3 are different, the comparison circuit 13 detects that at least one of the first arithmetic circuit 11 and the second arithmetic circuit 12 has been subjected to a fault attack. The comparison circuit 13 outputs data D4 indicating the detection result of the fault attack. Furthermore, fifth data D5 is input to the first arithmetic circuit 11 and the second arithmetic circuit 12. The first arithmetic circuit 11 performs a first operation on the fifth data D5 based on the first data D1. The second arithmetic circuit 12 performs a second operation on the fifth data D5 based on the first data D1. The first data D1 may be confidential information. The confidential information is information that affects the processing of the first operation or the second operation on the fifth data D5. The secret information may be, for example, a scalar value in a scalar multiplication, which will be described later, or an exponent in a modular exponentiation, which will be described later.

[0037] According to the present invention, the first arithmetic circuit 11 executes a first operation according to a first algorithm based on the input first data D1 and outputs second data D2. The second arithmetic circuit 12 executes a second operation according to a second algorithm, which has a different operation procedure from the first algorithm but produces the same operation result, based on the input first data D1, and outputs third data D3. The comparison circuit 13 detects that a fault exploitation attack has been performed when the second data D2 and the third data D3 are different. Therefore, even if a double FA is performed on the first arithmetic circuit 11 and the second arithmetic circuit 12, the attack can be detected.

[0038] (First embodiment) In the first embodiment, an example will be described in which the first algorithm is the right-hand binary method and the second algorithm is the left-hand binary method.

[0039] 2 is a simplified diagram showing a first configuration example of an information processing device 1A according to Embodiment 1. In the first configuration example, the first operation and the second operation are scalar multiplications.

[0040] The information processing device 1A is an application of elliptic curve cryptography, which is included in public key cryptography, to the information processing device 1. The information processing device 1A includes a scalar multiplication circuit 11A corresponding to the first arithmetic circuit 11, a scalar multiplication circuit 12A corresponding to the second arithmetic circuit 12, and a comparison circuit 13.

[0041] The scalar multiplication circuit 11A has a point addition circuit 21A (first point addition circuit) that performs point addition and a point doubling circuit 31A (first point doubling circuit) that performs point doubling. The scalar multiplication circuit 12A has a point addition circuit 22A (second point addition circuit) that performs point addition and a point doubling circuit 32A (second point doubling circuit) that performs point doubling. Point addition means adding different points on an elliptic curve. Point doubling means doubling a point on an elliptic curve.

[0042] In elliptic curve cryptography, the computational cost of scalar multiplication is dominant and critical. Scalar multiplication circuit 11A performs scalar multiplication at high speed using the right binary algorithm, and scalar multiplication circuit 12A performs scalar multiplication at high speed using the left binary algorithm.

[0043] The scalar multiplication circuit 11A performs, as the first operation, scalar multiplication defined on an elliptic curve on coordinate data D5A based on first data D1A. The first data D1A corresponds to the first data D1 and indicates an n-bit scalar value k. n is, for example, 256, but is not limited to this. The first data D1A may be secret information such as a secret key. The coordinate data D5A corresponds to the fifth data D5 and indicates the coordinates (X coordinate and Y coordinate) of an arbitrary rational point P on the elliptic curve. The coordinate data D5A may be public information such as a public key or public parameters. The scalar multiplication circuit 11A outputs second data D2A indicating a value kP obtained by scalar multiplication of the scalar value k and the rational point P. The second data D2A corresponds to the second data D2.

[0044] As the second operation, the scalar multiplication circuit 12A performs scalar multiplication defined on an elliptic curve on the coordinate data D5A based on the first data D1A. The scalar multiplication circuit 12A outputs third data D3A indicating a value kP obtained by scalar multiplication of the scalar value k and the rational point P. The third data D3A corresponds to the third data D3.

[0045] 3A and 3B are diagrams showing an example of the arithmetic procedure for scalar multiplication using the right binary method and the left binary method, where (A) shows the right binary method and (B) shows the left binary method.

[0046] 4A and 4B are diagrams showing an example of processing executed by the information processing device 1A according to the first configuration example of the first embodiment. (A) shows the rightward binary algorithm, and (B) shows the leftward binary algorithm. In this example, the scalar value k is "1101." D1 in (A) represents point doubling by the point doubling circuit 31A, and A1 in (A) represents point addition by the point addition circuit 21A. D2 in (B) represents point doubling by the point doubling circuit 32A, and A2 in (B) represents point addition by the point addition circuit 22A.

[0047] As shown in each of Figures 3 and 4 (A), the scalar multiplication circuit 11A performs point doubling by the point doubling circuit 31A and then point addition by the point addition circuit 21A when the logic of the bit to be processed is "1", starting from the most significant bit of the first data D1A, and when the logic of the bit to be processed is "0", only point doubling by the point doubling circuit 31A is performed.

[0048] As shown in each of Figures 3 and 4 (B), the scalar multiplication circuit 12A performs point addition by the point addition circuit 22A and then point doubling by the point doubling circuit 32A, starting from the least significant bit of the first data D1A, if the logic of the bit to be processed is "1", and if the logic of the bit to be processed is "0", only point doubling by the point doubling circuit 32A is performed.

[0049] The comparator circuit 13 receives the second data D2A from the scalar multiplication circuit 11A and the third data D3A from the scalar multiplication circuit 12A. The comparator circuit 13 compares the second data D2A with the third data D3A.

[0050] When the scalar multiplication circuits 11A and 12A have not received FA, the second data D2A and the third data D3A match. When only one of the scalar multiplication circuits 11A and 12A has received FA, a calculation error occurs only in the attacked scalar multiplication circuit 11A or 12A, and the second data D2A and the third data D3A do not match. Furthermore, when the scalar multiplication circuits 11A and 12A have received double FA, the second data D2A and the third data D3A do not match because the rightward binary algorithm and the leftward binary algorithm have different calculation procedures. In other words, when the scalar multiplication circuits 11A and 12A have not received FA, the second data D2A and the third data D3A match, but when the scalar multiplication circuits 11A and 12A have received FA or double FA, the second data D2A and the third data D3A do not match.

[0051] The information processing device 1A outputs a correct calculation result (e.g., the second data D2A) when the second data D2A and the third data D3A match based on the data D4. The information processing device 1A does not output a correct calculation result or outputs an irrelevant value when the second data D2A and the third data D3A do not match based on the data D4.

[0052] The first configuration example may be applied not only to elliptic curve cryptography but also to any public key cryptography that uses a scalar multiplication circuit. In this case, the point addition circuit may be an addition circuit, the point doubling circuit may be a doubling circuit, and the fifth data may not be coordinate data.

[0053] 5 is a diagram showing a simplified second configuration example of the information processing device 1B according to the first embodiment. In the second configuration example, the first operation and the second operation are modular exponentiation operations.

[0054] The information processing device 1B is an application of the information processing device 1 to RSA encryption, which is included in public key encryption. However, it is not limited to RSA encryption, and any public key encryption using modular exponentiation may be used. The information processing device 1B includes a modular exponentiation circuit 11B corresponding to the first arithmetic circuit 11, a modular exponentiation circuit 12B corresponding to the second arithmetic circuit 12, and a comparison circuit 13.

[0055] The modular exponentiation circuit 11B has a multiplication circuit 21B (first multiplication circuit) that performs multiplication and a squaring circuit 31B (first squaring circuit) that performs squaring. The modular exponentiation circuit 12B has a multiplication circuit 22B (second multiplication circuit) that performs multiplication and a squaring circuit 32B (second squaring circuit) that performs squaring.

[0056] In RSA encryption, the computational cost of modular exponentiation is dominant and critical. The modular exponentiation circuit 11B performs modular exponentiation at high speed using the right-hand binary algorithm, while the modular exponentiation circuit 12B performs modular exponentiation at high speed using the left-hand binary algorithm.

[0057] The modular exponentiation circuit 11B performs modular exponentiation on value data D5B based on first data D1B as the first operation. The first data D1B corresponds to the first data D1 and indicates the value of an n-bit exponent k. n is, for example, 2048, but is not limited to this. The first data D1B may be secret information such as a secret key. The value data D5B corresponds to the fifth data D5 and indicates an arbitrary value of base g. The value data D5B may be public information such as a public parameter. The modular exponentiation circuit 11B calculates value g using the exponent k and base g. k The second data D2B corresponds to the second data D2.

[0058] The modular exponentiation circuit 12B performs a modular exponentiation operation on the value data D5B based on the first data D1B as the second operation. The modular exponentiation circuit 12B calculates a value g using an exponent k and a base g. kThe third data D3B corresponds to the third data D3.

[0059] 6A and 6B are diagrams showing an example of a procedure for modular exponentiation using the right binary method and the left binary method, where (A) shows the right binary method and (B) shows the left binary method.

[0060] 7A and 7B are diagrams showing an example of processing executed by an information processing device 1B according to a second configuration example of the first embodiment. (A) shows the rightward binary algorithm, and (B) shows the leftward binary algorithm. In this example, the exponent k is "1101." S1 in (A) means squaring by the squaring circuit 31B, and M1 in (A) means multiplication by the multiplication circuit 21B. S2 in (B) means squaring by the squaring circuit 32B, and M2 in (B) means multiplication by the multiplication circuit 22B.

[0061] As shown in each of Figures 6 and 7 (A), the modular exponentiation circuit 11B performs squaring by the squaring circuit 31B and then multiplication by the multiplication circuit 21B when the logic of the bit to be processed is "1", starting from the most significant bit of the first data D1A, and when the logic of the bit to be processed is "0", only squaring by the squaring circuit 31B is performed.

[0062] As shown in each of Figures 6 and 7 (B), the modular exponentiation circuit 12B performs multiplication by the multiplication circuit 22B and then squaring by the squaring circuit 32B, starting from the least significant bit of the first data D1A, if the logic of the bit to be processed is "1", and if the logic of the bit to be processed is "0", only squaring by the squaring circuit 32B.

[0063] The comparison circuit 13 receives the second data D2B from the modular exponentiation circuit 11B and the third data D3B from the modular exponentiation circuit 12B. The comparison circuit 13 compares the second data D2B with the third data D3B.

[0064] When the modular exponentiation circuits 11B and 12B have not received FA, the second data D2B and the third data D3B match. When only one of the modular exponentiation circuits 11B and 12B has received FA, a calculation error occurs only in the attacked modular exponentiation circuit 11B or 12B, and the second data D2B and the third data D3B do not match. Furthermore, when the modular exponentiation circuits 11B and 12B have received double FA, the second data D2B and the third data D3B do not match because the calculation procedures are different between the rightward binary algorithm and the leftward binary algorithm. In other words, when the modular exponentiation circuits 11B and 12B have not received FA, the second data D2B and the third data D3B match, but when the modular exponentiation circuits 11B and 12B have received FA or double FA, the second data D2B and the third data D3B do not match.

[0065] The information processing device 1B outputs a correct calculation result (e.g., the second data D2B) when the second data D2B and the third data D3B match based on the data D4. The information processing device 1B does not output a correct calculation result or outputs an irrelevant value when the second data D2B and the third data D3B do not match based on the data D4.

[0066] According to this embodiment, even if double FA is performed on a scalar multiplication circuit 11A that performs scalar multiplication using the right-hand binary method and a scalar multiplication circuit 12A that performs scalar multiplication using the left-hand binary method, the attack can be detected.

[0067] Furthermore, according to this embodiment, even if a double FA is performed on the modular exponentiation circuit 11B that performs modular exponentiation using the right-hand binary method and the modular exponentiation circuit 12B that performs modular exponentiation using the left-hand binary method, the attack can be detected.

[0068] (Second embodiment) In the second embodiment, an example will be described in which the first algorithm is a right-direction extended binary algorithm and the second algorithm is a left-direction extended binary algorithm. The extended binary algorithm refers to an algorithm that is an extension of the binary algorithm. In scalar multiplication using the extended binary algorithm, when the logic of the bit to be processed is "0", a wait process equivalent to the processing time of point addition is added. In modular exponentiation using the extended binary algorithm, when the logic of the bit to be processed is "0", a wait process equivalent to the processing time of multiplication is added.

[0069] A first configuration example of the information processing device 1A according to the second embodiment is similar to the configuration example shown in FIG.

[0070] 8A and 8B are diagrams showing an example of processing executed by an information processing device 1A according to a first configuration example of the second embodiment. (A) shows the rightward extended binary algorithm, and (B) shows the leftward extended binary algorithm. As shown in (A), when the logic of the bit to be processed is "0," the scalar multiplication circuit 11A executes a wait process 41A corresponding to the processing time for point addition. As shown in (B), when the logic of the bit to be processed is "0," the scalar multiplication circuit 12A executes a wait process 42A corresponding to the processing time for point addition.

[0071] The second configuration example of the information processing device 1B according to the second embodiment is similar to the configuration example shown in FIG.

[0072] 9A and 9B are diagrams illustrating an example of processing executed by an information processing device 1B according to a second configuration example of the second embodiment. (A) illustrates the rightward extended binary algorithm, and (B) illustrates the leftward extended binary algorithm. As shown in (A), when the logic of the bit to be processed is "0," the modular exponentiation circuit 11B executes a wait process 41B corresponding to the processing time of multiplication. As shown in (B), when the logic of the bit to be processed is "0," the modular exponentiation circuit 12B executes a wait process 42B corresponding to the processing time of multiplication.

[0073] According to this embodiment, the total calculation time is constant regardless of the number of bits with a logic value of "0", thereby providing further resistance to attacks such as timing attacks that analyze confidential information based on the total calculation time.

[0074] (Third embodiment) In the third embodiment, an example will be described in which the first algorithm is the right-facing Add and Double Always algorithm, the right-facing Montgomery ladder algorithm, or the right-facing BRIP (Binary Expansion with Random Initial Point), and the second algorithm is the left-facing Add and Double Always algorithm, the left-facing Montgomery ladder algorithm, or the left-facing BRIP.

[0075] A first configuration example of an information processing device 1A according to the third embodiment is similar to the configuration example shown in FIG.

[0076] 10A and 10B are diagrams illustrating an example of processing performed by an information processing device 1A according to a first configuration example of the third embodiment. (A) illustrates the rightward Add and Double Always algorithm, the rightward Montgomery ladder algorithm, or the rightward BRIP algorithm, and (B) illustrates the leftward Add and Double Always algorithm, the leftward Montgomery ladder algorithm, or the leftward BRIP algorithm. As illustrated in (A), when the logic of the bit to be processed is "0," the scalar multiplication circuit 11A additionally performs point addition 51A using the point addition circuit 21A. As illustrated in (B), when the logic of the bit to be processed is "0," the scalar multiplication circuit 12A additionally performs point addition 52A using the point addition circuit 22A. The scalar multiplication circuits 11A and 12A may discard the results of the additional point additions 51A and 52A or may propagate them to the operation of the next bit. The Add and Double Always algorithm discards the results of the point additions 51A and 52A. In the Montgomery ladder algorithm and BRIP, the results of the point additions 51A and 52A are propagated to the calculation of the next bit.

[0077] The second configuration example of the information processing device 1B according to the third embodiment is similar to the configuration example shown in FIG.

[0078] 11A and 11B are diagrams illustrating an example of processing performed by an information processing device 1B according to a second configuration example of the third embodiment. (A) illustrates the rightward Square and Multiply Always algorithm, the rightward Montgomery ladder algorithm, or the rightward BRIP algorithm, and (B) illustrates the leftward Square and Multiply Always algorithm, the leftward Montgomery ladder algorithm, or the leftward BRIP algorithm. As illustrated in (A), the modular exponentiation circuit 11B additionally performs multiplication 51B by the multiplier circuit 21B when the logic of the bit to be processed is "0." As illustrated in (B), the modular exponentiation circuit 12B additionally performs multiplication 52B by the multiplier circuit 22B when the logic of the bit to be processed is "0." The modular exponentiation circuits 11B and 12B may discard the results of the additional multiplications 51B and 52B or may propagate them to the calculation of the next bit. The Square and Multiply Always algorithm discards the results of the multiplications 51B and 52B. In the Montgomery ladder method and BRIP, the results of multiplications 51B and 52B are propagated to the calculation of the next bit.

[0079] 12A and 12B are diagrams showing an example of a scalar multiplication procedure using the rightward Montgomery ladder algorithm and the leftward Montgomery ladder algorithm. (A) shows the rightward Montgomery ladder algorithm, and (B) shows the leftward Montgomery ladder algorithm. Since the Montgomery ladder algorithm is a known algorithm, detailed explanation will be omitted.

[0080] 13A and 13B are diagrams showing an example of a scalar multiplication procedure using right-direction BRIP and left-direction BRIP. (A) shows right-direction BRIP, and (B) shows left-direction BRIP. BRIP is a known algorithm, so a detailed description will be omitted.

[0081] According to this embodiment, it is possible to further provide resistance to attacks such as timing attacks and simple power analysis.

[0082] Furthermore, according to the Montgomery ladder method or BRIP, the additionally executed point additions 51A and 52A or multiplications 51B and 52B are not dummy operations, so that FA due to fault injection at any timing can be detected.

[0083] Furthermore, BRIP can provide additional resistance to differential power analysis (DPA) attacks.

[0084] (Fourth embodiment) 14 is a simplified diagram showing a first configuration example of an information processing device 1C according to the fourth embodiment. Compared to the configuration example shown in FIG. 2, the point doubling circuit 31A is omitted from the scalar multiplication circuit 11A, and the point doubling circuit 32A is omitted from the scalar multiplication circuit 12A. Furthermore, a point doubling circuit 33A is added. The point doubling circuit 33A is shared by the scalar multiplication circuits 11A and 12A. In other words, the point doubling circuit 31A and the point doubling circuit 32A are configured by sharing the same point doubling circuit 33A.

[0085] Generally, the processing time for point addition is longer than the processing time for point doubling. Furthermore, the execution order of point addition and point doubling is reversed between the rightward and leftward algorithms. Therefore, as shown in FIGS. 8 and 10 , in the extended binary algorithm, the Add and Double Always algorithm, the Montgomery ladder algorithm, and BRIP, the point doubling by the point doubling circuit 31A and the point doubling by the point doubling circuit 32A are not executed simultaneously. In other words, the execution periods of the point doubling by the point doubling circuit 31A and the point doubling by the point doubling circuit 32A do not overlap with each other. Therefore, as shown in FIG. 14 , one point doubling circuit 33A can be shared by the scalar multiplication circuits 11A and 12A.

[0086] 15 is a simplified diagram showing a second configuration example of an information processing device 1D according to the fourth embodiment. Compared to the configuration example shown in FIG. 5, the squaring circuit 31B is omitted from the modular exponentiation circuit 11B, and the squaring circuit 32B is omitted from the modular exponentiation circuit 12B. In addition, a squaring circuit 33B is added. The squaring circuit 33B is shared by the modular exponentiation circuits 11B and 12B. In other words, the squaring circuit 31B and the squaring circuit 32B are configured by sharing the same squaring circuit 33B.

[0087] Generally, the processing time for multiplication is longer than the processing time for squaring. Furthermore, the execution order of multiplication and squaring is reversed between the rightward and leftward algorithms. Therefore, as shown in FIGS. 9 and 11 , in the extended binary algorithm, the Square and Multiply Always algorithm, the Montgomery ladder algorithm, and BRIP, the squaring by the squaring circuit 31B and the squaring by the squaring circuit 32B are not executed simultaneously. In other words, the execution period of the squaring by the squaring circuit 31B and the execution period of the squaring by the squaring circuit 32B do not overlap with each other. Therefore, as shown in FIG. 15 , one squaring circuit 33B can be shared by the modular exponentiation circuits 11B and 12B.

[0088] According to this embodiment, the point doubling circuit 31A and the point doubling circuit 32A are configured to share one point doubling circuit 33A, thereby making it possible to reduce the circuit scale.

[0089] Furthermore, according to this embodiment, the squaring circuit 31B and the squaring circuit 32B are configured to share one squaring circuit 33B, thereby making it possible to reduce the circuit scale.

[0090] (Fifth embodiment) FIG. 16 is a diagram showing a simplified first configuration example of an information processing device 1E according to the fifth embodiment.

[0091] FIG. 17 is a diagram showing an example of processing executed by an information processing device 1E according to the first configuration example of the fifth embodiment.

[0092] In the information processing device 1E, not only do the point doubling circuit 31A and the point doubling circuit 32A share one point doubling circuit 33A, but the point adding circuit 21A and the point adding circuit 22A share one point adding circuit 34A.

[0093] As described above, the processing time for point addition is longer than that for point doubling. Therefore, to avoid overlap between the execution period of point addition by scalar multiplication circuit 11A and the execution period of point addition by scalar multiplication circuit 12A, scalar multiplication circuit 11A executes a wait process 71A corresponding to the difference in processing time between point addition and point doubling after executing point doubling. Similarly, scalar multiplication circuit 12A executes a wait process 72A corresponding to the difference in processing time between point addition and point doubling after executing point doubling.

[0094] FIG. 18 is a simplified diagram showing a second configuration example of an information processing device 1F according to the fifth embodiment.

[0095] FIG. 19 is a diagram showing an example of processing executed by an information processing device 1F according to a second configuration example of the fifth embodiment.

[0096] In the information processing device 1F, not only do the squaring circuits 31B and 32B share one squaring circuit 33B, but the multiplication circuits 21B and 22B also share one multiplication circuit 34B.

[0097] As described above, the processing time for multiplication is longer than the processing time for squaring. Therefore, to avoid overlap between the period during which the modular exponentiation circuit 11B performs multiplication and the period during which the modular exponentiation circuit 12B performs multiplication, the modular exponentiation circuit 11B executes a wait process 71B corresponding to the difference in processing time between the multiplication and the squaring after executing the squaring. Similarly, the modular exponentiation circuit 12B executes a wait process 72B corresponding to the difference in processing time between the multiplication and the squaring after executing the squaring.

[0098] According to this embodiment, the point adding circuit 21A and the point adding circuit 22A are configured to share one point adding circuit 34A, which allows further reduction in circuit size.

[0099] Furthermore, according to this embodiment, the multiplication circuit 21B and the multiplication circuit 22B are configured to share one multiplication circuit 34B, which allows for a further reduction in circuit size.

[0100] The functions of the elements disclosed herein may be implemented using circuitry or processing circuitry, including general-purpose processors, special-purpose processors, integrated circuits, ASICs ("application-specific integrated circuits"), conventional circuitry, and / or combinations thereof, configured to perform the disclosed elements or programmed to perform the disclosed functions. A processor is considered to be processing circuitry or circuitry when it includes transistors and other circuitry therein. In this disclosure, a circuitry, unit, or means is hardware that performs the recited function or hardware programmed to perform the function. The hardware may be any hardware disclosed herein or other known hardware that is programmed to perform or configured to perform the recited function. When the hardware is a processor, which may be considered as a type of circuitry, the circuitry, means, or unit is a combination of hardware and software, software used to configure the hardware, and / or processor. [Explanation of symbols]

[0101] 1, 1A~1F Information processing equipment 11 First arithmetic circuit 12 Second arithmetic circuit 13 Comparison circuit 21A, 22A, 34A point adding circuit 21B, 22B, 34B multiplication circuit 31A, 32A, 33A point doubling circuit 31B, 32B, 33B squaring circuit

Claims

1. a first arithmetic circuit that receives first data, executes a first operation according to a first algorithm based on the input first data, and outputs second data indicating an operation result of the first operation; a second arithmetic circuit that receives the first data, executes a second operation based on the input first data by a second algorithm that has a different operation procedure from the first algorithm but produces the same operation result, and outputs third data that indicates the operation result of the second operation; a comparison circuit that compares the second data with the third data and detects a fault exploitation attack when the second data and the third data are different; Equipped with Information processing device.

2. the first arithmetic circuit and the second arithmetic circuit are scalar multiplication circuits, the first arithmetic circuit has a first adder circuit and a first doubling circuit; the second arithmetic circuit has a second adder circuit and a second doubling circuit; the first arithmetic circuit, in order from the most significant bit of the first data, when the logic of the bit to be processed is "1", executes a doubling by the first doubling circuit and an addition by the first adder circuit as the first arithmetic operation, and when the logic of the bit to be processed is "0", executes a doubling by the first doubling circuit as the first arithmetic operation; the second arithmetic circuit, in order from the least significant bit of the first data, executes, as the second operation, an addition by the second adding circuit and a doubling by the second doubling circuit when the logic of the bit to be processed is "1", and executes, as the second operation, a doubling by the second doubling circuit when the logic of the bit to be processed is "0". The information processing device according to claim 1 .

3. the first arithmetic circuit and the second arithmetic circuit further execute a waiting process corresponding to the processing time of the addition when the logic of the bit to be processed is "0". The information processing device according to claim 2 .

4. the first arithmetic circuit further executes addition by the first adder circuit when the logic of the processing target bit is "0"; the second arithmetic circuit further executes addition by the second adder circuit when the logic of the bit to be processed is "0". The information processing device according to claim 2 .

5. The processing time for addition is longer than that for doubling, a period during which the first doubling circuit performs doubling and a period during which the second doubling circuit performs doubling do not overlap each other; the first doubling circuit and the second doubling circuit are configured by sharing one doubling circuit; 5. The information processing device according to claim 3 or 4.

6. the first adder circuit and the second adder circuit are further configured to share one adder circuit; the first arithmetic circuit and the second arithmetic circuit further execute a standby process corresponding to a processing time difference between the addition and the doubling after executing the doubling. The information processing device according to claim 5 .

7. the first arithmetic circuit and the second arithmetic circuit are modular exponentiation circuits, the first arithmetic circuit has a first multiplication circuit and a first squaring circuit; the second arithmetic circuit has a second multiplication circuit and a second squaring circuit; the first arithmetic circuit, in order from the most significant bit of the first data, when the logic of the bit to be processed is "1", executes squaring by the first squaring circuit and multiplication by the first multiplier circuit as the first arithmetic operation, and when the logic of the bit to be processed is "0", executes squaring by the first squaring circuit as the first arithmetic operation; the second arithmetic circuit, in order from the least significant bit of the first data, executes, as the second operation, a multiplication by the second multiplier circuit and a squaring by the second squaring circuit when the logic of the bit to be processed is "1", and executes, as the second operation, a squaring by the second squaring circuit when the logic of the bit to be processed is "0". The information processing device according to claim 1 .

8. when the logic of the bit to be processed is "0", the first arithmetic circuit and the second arithmetic circuit further execute a waiting process equivalent to the processing time of the multiplication. The information processing device according to claim 7 .

9. the first arithmetic circuit further executes multiplication by the first multiplication circuit when the logic of the processing target bit is "0"; the second arithmetic circuit further executes multiplication by the second multiplication circuit when the logic of the bit to be processed is "0". The information processing device according to claim 7 .

10. The processing time for multiplication is longer than that for squaring, a period during which the first squaring circuit performs squaring and a period during which the second squaring circuit performs squaring do not overlap each other; the first squaring circuit and the second squaring circuit are configured by sharing one squaring circuit; The information processing device according to claim 8 or 9.

11. the first multiplication circuit and the second multiplication circuit are further configured to share one multiplication circuit; the first arithmetic circuit and the second arithmetic circuit further execute, after executing the squaring, a waiting process corresponding to a processing time difference between the multiplication and the squaring. The information processing device according to claim 10.

12. The information processing device performing a first calculation according to a first algorithm based on the first data; execute a second calculation based on the first data using a second algorithm that has a different calculation procedure from the first algorithm but produces the same calculation result; comparing second data indicating the result of the first operation with third data indicating the result of the second operation, and detecting that a fault exploitation attack has been performed if the second data and the third data are different; Information processing methods.

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