Multilayer ceramic electronic component

Abstract

To provide a multilayer ceramic electronic component which can suppress generation of interface separations.SOLUTION: A first lead-out portion 17A has a bent portion 20A in an LT cross section. A straight line tangent to a first end surface CA and extending parallel to a stacking direction T is defined as a first end-surface reference line LC1, and a straight line tangent to a first main surface AA and extending parallel to a length direction L is defined as a first main-surface reference line LA1. The distance between the bent portion 20A and the first end-surface reference line LC1 is defined as x, and the distance between the bent portion 20A and the first main-surface reference line LA1 is defined as y. Among regions obtained by dividing a laminate 2 into four by a straight line passing through the central portion of the laminate 2 in the stacking direction T and a straight line passing through the central portion of the laminate 2 in the length direction L, a region located on the first main surface AA side and the first end surface CA side is defined as a first reference region A1. A regression line derived on the basis of the x and y values relating to the bent portion 20A within the first reference region A1 is defined as a virtual connection line VL. The virtual connection line VL intersects an active layer portion 10.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic electronic component. [Background technology]

[0002] Multilayer ceramic capacitors have been known as multilayer ceramic electronic components. Generally, a multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes provided on both end surfaces of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure, in which the external electrodes include base electrode layers formed by baking. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-243249 Summary of the Invention [Problem to be solved by the invention]

[0004] In multilayer ceramic capacitors, for example, during the process of cutting laminated chips, a phenomenon called "interfacial peeling" can occur in which the internal electrodes peel off from the adjacent dielectric. This interfacial peeling reduces product yield.

[0005] An object of the present invention is to provide a multilayer ceramic electronic component that can suppress the occurrence of interfacial peeling. [Means for solving the problem]

[0006] In order to achieve the above object, a multilayer ceramic electronic component of the present invention is a multilayer ceramic electronic component comprising: a laminate having a first main surface and a second main surface, a first side surface and a second side surface opposing each other in a width direction that is a direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction that is a direction perpendicular to the stacking direction and the width direction; and external electrodes arranged in pairs on each end surface, wherein the internal electrodes have opposing portions opposing the internal electrodes adjacent in the stacking direction, and lead portions drawn from the opposing portions and connected to the external electrodes, the laminate has effective layer portions consisting of each of the opposing portions and a portion of each of the ceramic layers sandwiched between the adjacent opposing portions, and wherein a direction in the stacking direction when viewing each of the main surfaces from a center portion of the laminate in the stacking direction is defined as an outer side in the stacking direction, and a direction in the stacking direction when viewing the center portion of the laminate in the stacking direction from each of the main surfaces is defined as a center side in the stacking direction, and a cross section parallel to the stacking direction and the length direction is defined as an LT cross section, and a first inclined portion that is drawn out from the opposing portion and inclined toward the center in the stacking direction as it moves from the opposing portion side toward a side away from the opposing portion; a second inclined portion that extends from the first inclined portion toward the side away from the opposing portion and inclined outward in the stacking direction as it moves from the opposing portion side toward the side away from the opposing portion; and a bent portion that connects the first inclined portion and the second inclined portion; is defined as a main surface-side reference line, the distance between the bent portion and the end face-side reference line is defined as x, the distance between the bent portion and the main surface-side reference line is defined as y, the laminate is divided into four regions by a line passing through a center portion of the laminate in the stacking direction and a line passing through a center portion of the laminate in the length direction is defined as a reference region, and a regression line derived based on the values ​​of x and y for the bent portion in the reference region is defined as a virtual connecting line, the virtual connecting line intersects with the effective layer portion. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can suppress the occurrence of interfacial peeling. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic perspective view of a multilayer ceramic capacitor in accordance with a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Figure 3] FIG. 3 is an enlarged view of the first reference region and its vicinity in FIG. 2. [Figure 4] FIG. 4 is a diagram showing a multilayer ceramic capacitor according to a second embodiment, and corresponds to FIG. 2. [Figure 5] FIG. 10 is a diagram showing a multilayer ceramic capacitor according to a third embodiment, and corresponds to FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] First Embodiment A multilayer ceramic capacitor 1 according to a first embodiment of the present invention will now be described with reference to Figures 1 and 2. The multilayer ceramic capacitor 1 corresponds to a multilayer ceramic electronic component.

[0010] (Multilayer ceramic capacitor 1) As shown in Fig. 1, the multilayer ceramic capacitor 1 is a multilayer ceramic capacitor with a so-called two-terminal structure. The multilayer ceramic capacitor 1 includes a laminate 2 and a pair of external electrodes 3. The laminate 2 is substantially rectangular and has six outer surfaces. The laminate 2 includes an inner layer portion 11 in which a dielectric layer 14 and an internal electrode 15 are laminated.

[0011] In this specification, the direction in which the dielectric layers 14 and internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 is referred to as the stacking direction T. One of the directions perpendicular to the stacking direction T is referred to as the length direction L. The direction perpendicular to both the length direction L and the stacking direction T is referred to as the width direction W. Within the stacking direction T, the direction from the center of the stacking direction T of the laminate 2 toward each main surface A is referred to as the "stacking direction outer side T1," and within the stacking direction T, the direction from each main surface A toward the center of the stacking direction T of the laminate 2 is referred to as the "stacking direction center side T2."

[0012] A cross section parallel to the lamination direction T and the length direction L is referred to as an “LT cross section.” The cross section of FIG.

[0013] Of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides in the stacking direction T is referred to as the first main surface AA and the second main surface AB, a pair of outer surfaces extending in the stacking direction T and on both sides in the width direction W is referred to as the first side surface BA and the second side surface BB, and a pair of outer surfaces extending in the stacking direction T and on both sides in the length direction L is referred to as the first end surface CA and the second end surface CB. The first main surface AA and the second main surface AB may be collectively referred to as the "main surfaces A." The first side surface BA and the second side surface BB may be collectively referred to as the "side surfaces B." The first end surface CA and the second end surface CB may be collectively referred to as the "end surfaces C."

[0014] A pair of external electrodes 3 is provided on each end face C. The external electrodes 3 are aligned in the length direction L.

[0015] The length direction L dimension of the multilayer ceramic capacitor 1 is preferably 0.2 mm to 10 mm, more preferably 0.2 mm to 6 mm. The stacking direction T dimension of the multilayer ceramic capacitor 1 is preferably 0.05 mm to 10 mm, more preferably 0.1 mm to 5 mm. The width direction W dimension of the multilayer ceramic capacitor 1 is preferably 0.1 mm to 10 mm, more preferably 0.1 mm to 5 mm.

[0016] (Laminate 2) As shown in Figure 2, the laminate 2 has an inner layer portion 11 and a pair of outer layer portions 12 arranged on either side of the inner layer portion 11 in the stacking direction T. The corners and ridges of the laminate 2 are preferably rounded. Note that the corners are portions where three surfaces of the laminate intersect. The ridges are portions where two surfaces of the laminate intersect.

[0017] The length direction L dimension of the laminate 2 is preferably 0.2 mm to 10 mm, more preferably 0.2 mm to 6 mm. The stacking direction T dimension of the laminate 2 is preferably 0.05 mm to 10 mm, more preferably 0.1 mm to 5 mm. The width direction W dimension of the laminate 2 is preferably 0.1 mm to 10 mm, more preferably 0.1 mm to 5 mm.

[0018] (Inner layer 11) The inner layer portion 11 has a plurality of dielectric layers 14 as ceramic layers and a plurality of internal electrodes 15. The dielectric layers 14 and the internal electrodes 15 are alternately stacked.

[0019] The dielectric layer 14 is formed of a dielectric ceramic containing, for example, BaTiO3 as a main component. The dielectric ceramic may contain a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound as a secondary component. The dimension T of the dielectric layer 14 in the stacking direction is preferably 0.2 μm or more and 15 μm or less, and more preferably 0.5 μm or more and 2.0 μm or less.

[0020] The internal electrodes 15 are formed of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au. The internal electrodes 15 include a plurality of first internal electrodes 15A and a plurality of second internal electrodes 15B. The first internal electrodes 15A are exposed only at the first end face CA. The second internal electrodes 15B are exposed only at the second end face CB. The first internal electrodes 15A and the second internal electrodes 15B are arranged alternately.

[0021] The first internal electrode 15A has a first opposing portion 16A and a first lead portion 17A. The first opposing portion 16A is a portion of the first internal electrode 15A that faces the second internal electrode 15B adjacent to it in the stacking direction T. The first opposing portion 16A is located in the center between the end faces C. The first lead portion 17A is a portion of the first internal electrode 15A that is led out from the first opposing portion 16A toward the first end face CA. The first lead portion 17A is exposed at the first end face CA.

[0022] The second internal electrode 15B has a second opposing portion 16B and a second lead portion 17B. The second opposing portion 16B is a portion of the second internal electrode 15B that faces the adjacent first internal electrode 15A (first opposing portion 16A). The second opposing portion 16B is located in the center between the end faces C. The second lead portion 17B is a portion of the second internal electrode 15B that is led out from the second opposing portion 16B toward the second end face CB. The second lead portion 17B is exposed at the second end face CB.

[0023] The first internal electrode 15A and the second internal electrode 15B may be collectively referred to as "internal electrodes 15." The first opposing portion 16A and the second opposing portion 16B may be collectively referred to as "opposing portions 16."

[0024] The dimension T in the stacking direction of the internal electrode 15 is preferably 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrodes 15A and second internal electrodes 15B is preferably 10 or more and 700 or less, and more preferably 15 or more and 1000 or less.

[0025] The opposing portions 16 and the portions of the dielectric layers 14 sandwiched between adjacent opposing portions 16 are collectively referred to as the "effective layer portion 10." In other words, the laminate 2 has an effective layer portion 10, which is made up of each opposing portion 16 and the portions of each dielectric layer 14 sandwiched between adjacent opposing portions 16. The effective layer portion 10 is the portion where the capacitor capacitance is formed.

[0026] (Outer layer 12) The outer layer portion 12 is formed of the same material as the dielectric layer 14 of the inner layer portion 11. No internal electrode 15 is disposed in the outer layer portion 12. The total number of the dielectric layers 14 and the outer layer portions 12 is preferably 10 to 1200, and more preferably 15 to 700.

[0027] (External electrode 3) Each external electrode 3 is disposed on each end face C. Each external electrode 3 covers not only the end face C but also part of the main face A and part of the side face B. Either a first internal electrode 15A or a second internal electrode 15B is connected to each external electrode 3. The external electrode 3 includes a base electrode layer 31 formed in contact with the surface of the laminate 2, a first plating layer 32 disposed on the base electrode layer 31, and a second plating layer 33 disposed on the first plating layer 32.

[0028] The base electrode layer 31 is, for example, a baked layer containing a conductive metal such as Cu (copper) and glass. The first plating layer 32 is, for example, a Ni (nickel) plating layer. The second plating layer 33 is, for example, a Sn (tin) plating layer.

[0029] The thickness of the portion of the base electrode layer 31 located on the end face C is preferably 2 μm or more and 220 μm or less, and more preferably 3 μm or more and 200 μm or less. The thickness of the portion of the base electrode layer 31 located on either the main face A or the side face B is preferably 3 μm or more and 40 μm or less, and more preferably 4 μm or more and 25 μm or less. The thickness of the first plating layer 32 and the thickness of the second plating layer 33 are each preferably 1 μm or more and 15 μm or less, and more preferably 2 μm or more and 10 μm or less.

[0030] The external electrode 3 may have a conductive resin layer. In this case, the thickness of the conductive resin layer is preferably 10 μm or more and 150 μm or less. The base electrode layer 31 may be a thin film layer such as a sputtered electrode. The base electrode layer 31 is not an essential component, and for example, the first plating layer 32 may be disposed directly on the laminate 2.

[0031] Here, the laminate 2 is divided into four regions by a line passing through the center of the laminate 2 in the stacking direction T and a line passing through the center of the laminate 2 in the length direction L. Of these four regions, the region on the first main surface AA side and the first end face CA side is referred to as the "first reference region A1," the region on the first main surface AA side and the second end face CB side is referred to as the "second reference region A2," the region on the second main surface AB side and the first end face CA side is referred to as the "third reference region A3," and the region on the second main surface AB side and the second end face CB side is referred to as the "fourth reference region A4." The first reference region A1, the second reference region A2, the third reference region A3, and the fourth reference region A4 each correspond to a reference region.

[0032] The multilayer ceramic capacitor 1 has a generally symmetrical structure when viewed in the longitudinal direction L. Therefore, the first reference region A1 and the second reference region A2 have a generally symmetrical structure when viewed in the longitudinal direction L. The third reference region A3 and the fourth reference region A4 have a generally symmetrical structure when viewed in the longitudinal direction L.

[0033] As shown in Figure 3, in the LT cross section of the first reference area A1, the first pull-out portion 17A has a first inclined portion 18A that is pulled out from the first opposing portion 16A and inclined toward the center side T2 of the stacking direction as it moves from the first opposing portion 16A side toward the side away from the first opposing portion 16A, a second inclined portion 19A that extends from the first inclined portion 18A toward the side away from the first opposing portion 16A and inclined toward the outside side T1 of the stacking direction as it moves from the first opposing portion 16A side toward the side away from the first opposing portion 16A, and a bent portion 20A that connects the first inclined portion 18A and the second inclined portion 19A.

[0034] A line tangent to the first end face CA and extending parallel to the stacking direction T is referred to as the "first end face side reference line LC1." A line tangent to the first main face AA and extending parallel to the length direction L is referred to as the "first main face side reference line LA1." The distance from the first end face side reference line LC1 is referred to as "x." The distance from the first main face side reference line LA1 is referred to as "y." The position of the bent portion 20A can be expressed by x and y coordinates, respectively.

[0035] The regression line derived based on the values ​​of x and y for the bent portion 20A in the first reference region A1 is defined as the virtual connecting line VL. The regression line is derived by the least squares method.

[0036] The virtual connecting line VL intersects with the effective layer portion 10. Of the internal electrodes 15 adjacent to each other in the stacking direction T, the bent portion 20A of the internal electrode 15 located on the center side T2 in the stacking direction is closer to the effective layer portion 10 than the bent portion 20A of the internal electrode 15 located on the outer side T1 in the stacking direction.

[0037] The imaginary connecting line VL only needs to intersect with the effective layer portion 10 on the LT cross section, and does not need to intersect with the effective layer portion 10 within the first reference region A1. For example, the imaginary connecting line VL may intersect with the effective layer portion 10 within the third reference region A3. Furthermore, the imaginary connecting line VL does not need to actually connect all of the bend portions 20A within the first reference region A1.

[0038] The bending portion 20A located at the outermost side T1 in the stacking direction is referred to as the outermost bending portion 21A. The bending angle of the outermost bending portion 21A is smaller than the bending angle of the bending portion 20A located at the center side T2 in the stacking direction from the outermost bending portion 21A. In FIG. 3, the bending angle of the outermost bending portion 21A is indicated as "θ1," and the bending angle of the bending portion 20A located at the center side T2 in the stacking direction from the outermost bending portion 21A is indicated as "θt."

[0039] When measuring distances and angles inside the laminate 2, the laminate 2 is polished to expose a predetermined cross section at the center of the LT cross section passing through the width direction W of the laminate 2. Next, the exposed cross section is observed with a scanning electron microscope, and various values ​​are measured.

[0040] In the LT cross section of the third reference area A3, the first lead-out portion 17A may or may not have a bent portion. However, if the first lead-out portion 17A of the third reference area A3 has a bent portion, it is preferable that the first lead-out portion 17A of the third reference area A3 has a configuration corresponding to the first lead-out portion 17A of the first reference area A1.

[0041] (Manufacturing Method of Multilayer Ceramic Capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0042] A dielectric sheet for the dielectric layer 14 and a conductive paste for the internal electrode 15 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0043] On the dielectric sheets, a conductive paste for the internal electrodes 15 is printed in a predetermined pattern by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode 15A is formed and a dielectric sheet on which the pattern of the second internal electrode 15B is formed are prepared.

[0044] A predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first main surface-side outer layer portion 12A on the first main surface AA side. A dielectric sheet printed with a pattern of the first internal electrode 15A and a dielectric sheet printed with a pattern of the second internal electrode 15B are stacked in this order on top of that to form the portion that will become the internal layer portion 11. A predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the second main surface-side outer layer portion 12B on the second main surface AB side. In this way, a laminated sheet is produced.

[0045] The laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block. During the hydrostatic press, the laminated sheet is sandwiched between metal plates having a convex shape at a position corresponding to a region (lead-out region) in the length direction L corresponding to a region in the laminated sheet where the lead portions of the internal electrodes are present. This causes the density of the central portion in the lamination direction of the lead-out region to increase earlier than that of the other portions of the lead-out region, causing bending of the lead-out region to avoid this portion, thereby obtaining the structure of this embodiment.

[0046] The laminated block is cut to a predetermined size to cut out laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0047] The laminated chip is fired to produce the laminate 2. The firing temperature depends on the materials of the dielectric layers 14 and the internal electrodes 15, but is preferably 900°C or higher and 1400°C or lower.

[0048] A conductive paste that will become the base electrode layer 31 is applied to both end surfaces of the laminate 2. In this embodiment, the base electrode layer 31 is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 2 by a method such as dipping. A baking process is then performed to form the base electrode layer 31. The temperature of the baking process at this time is preferably 700°C or higher and 950°C or lower.

[0049] In this embodiment, dipping is performed so that the base electrode layer 31 on the first end face CA side extends from the first end face CA to parts of the first principal face AA and the second principal face AB. Furthermore, dipping is performed so that the base electrode layer 31 on the second end face CB side extends from the second end face CB to parts of the first principal face AA and the second principal face AB. At the same time, dipping is preferably performed so that the base electrode layer on the first end face CA side extends to parts of the first side face BA and the second side face BB. Furthermore, dipping is preferably performed so that the base electrode layer 31 on the second end face CB side extends to parts of the first side face BA and the second side face BB.

[0050] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 14 as the ceramic material added. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form the laminate 2 with the fired layer formed.

[0051] Thereafter, a plating layer is formed on the surface of the base electrode layer 31. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the base electrode layer. The Ni plating layer and the Sn plating layer are formed sequentially using an electrolytic plating method. As the plating method, for example, barrel plating is preferably used.

[0052] In this manner, the multilayer ceramic capacitor 1 shown in FIG. 1 is obtained.

[0053] (Effects of the first embodiment) According to this embodiment, the following effects can be obtained.

[0054] According to this embodiment, in the LT cross section, the first lead portion 17A is led out from the opposing portion 16 and has a first inclined portion 18A that is inclined toward the center in the stacking direction from the opposing portion 16 side toward the side away from the opposing portion 16, a second inclined portion 19A that extends from the first inclined portion 18A toward the side away from the opposing portion 16 and inclined toward the outside T1 in the stacking direction from the opposing portion 16 side toward the side away from the opposing portion 16, and a bent portion 20A that connects the first inclined portion 18A and the second inclined portion 19A. A straight line that is a tangent to the first end face CA and extends parallel to the stacking direction T is defined as a first end face side reference line LC1, and a tangent to the first main surface AA is defined as a first end face side reference line LC2. Let the straight line extending parallel to the length direction L be the first main surface side reference line LA1, the distance between the bent portion 20A and the first end face side reference line LC1 be x, the distance between the bent portion 20A and the first main surface side reference line LA1 be y, and the region of the laminate 2 divided into four by a line passing through the center of the laminate 2 in the stacking direction T and a line passing through the center of the laminate 2 in the length direction L be the region on the first main surface AA side and the first end face CA side be the first reference region A1, and let the regression line derived based on the values ​​of x and y for the bent portion 20A in the first reference region A1 be the virtual connecting line VL, so that the virtual connecting line VL intersects with the effective layer portion 10.

[0055] With this configuration, the bent portions 20A of the first internal electrode 15A tend to be farther away from the first end face CA as they are closer to the center T2 in the stacking direction, which makes it possible to prevent the bent portions 20A from being cut in the cutting process, thereby making it possible to prevent interfacial peeling from occurring during the manufacturing process.

[0056] According to this embodiment, if the bending portion 20A located on the outermost side T1 in the stacking direction is defined as the outermost bending portion 21A, the bending angle of the outermost bending portion 21A is smaller than the bending angle of the bending portion 20A located on the inner side T2 in the stacking direction from the outermost bending portion 21A.

[0057] In the laminate 2, the closer to the first end face CA, the more likely stress is applied during cutting, making interfacial peeling more likely to occur. With this configuration, the closer the internal electrode 15 is to the first principal face AA, the smaller the bending angle of the bent portion 20A. The smaller the bending angle of the bent portion 20A, the greater the adhesive strength between the internal electrode 15 and the dielectric layer 14. Therefore, the occurrence of interfacial peeling during the manufacturing process can be efficiently suppressed.

[0058] Second Embodiment Next, a multilayer ceramic capacitor 1 according to a second embodiment of the present invention will be described with reference to Fig. 4. The following description will focus on differences from the first embodiment, and the same components as those in the first embodiment will be given the same reference numerals and descriptions thereof will be omitted.

[0059] As shown in FIG. 4, in the second embodiment, the shape of the internal electrode 15 is different from that in the first embodiment.

[0060] The internal electrode 15 closest to the first main surface AA is referred to as the "first main surface side outermost internal electrode 151A." The internal electrode 15 closest to the second main surface AB is referred to as the "second main surface side outermost internal electrode 151B." In other words, the first main surface side outermost internal electrode 151A is the internal electrode 15 located outermost in the stacking direction T1 in the region on the first main surface AA side of the laminate 2. The second main surface side outermost internal electrode 151B is the internal electrode 15 located outermost in the stacking direction T1 in the region on the second main surface AB side of the laminate 2.

[0061] The first principal surface side outermost internal electrode 151A and the second principal surface side outermost internal electrode 151B may be collectively referred to as "outermost internal electrodes 151." The first principal surface side outermost internal electrode 151A is, for example, the first internal electrode 15A. The second principal surface side outermost internal electrode 151B is, for example, the second internal electrode 15B.

[0062] The length of the contour line of the facing portion 16 on the outer side T1 in the stacking direction is defined as "D1." The distance between each end of the facing portion 16 in the length direction L is defined as "D2." The amount obtained by dividing D1 by D2 is defined as the "amount of waviness."

[0063] The waviness amount of the facing portion 16 of the first main surface side outermost internal electrode 151A is larger than the waviness amount of the facing portion 16 of the internal electrode 15 adjacent to the first main surface side outermost internal electrode 151A. The waviness amount of the facing portion 16 of the second main surface side outermost internal electrode 151B is larger than the waviness amount of the facing portion 16 of the internal electrode 15 adjacent to the second main surface side outermost internal electrode 151B.

[0064] When measuring D1 and D2, the laminate 2 is polished to expose a predetermined cross section at the center of the LT cross section passing through the width direction W of the laminate 2. Then, D1 and D2 are measured on the exposed cross section. D1 is measured using a contour measuring instrument. D2 is measured using a scanning electron microscope.

[0065] The multilayer ceramic capacitor 1 of the second embodiment can be manufactured by the following method.

[0066] First, a dielectric sheet on which the pattern of the first internal electrode 15A is printed and a dielectric sheet on which the pattern of the second internal electrode 15B is printed are sequentially laminated to form the portion that will become the inner layer portion 11. This portion that will become the inner layer portion 11 is sandwiched between highly fluid dielectric sheets on which no internal electrode pattern is printed, thereby producing a laminated sheet. When this laminated sheet is isostatically pressed, the highly fluid dielectric sheets that make up the outer layer portions flow, which in turn deforms the internal electrodes in the inner layer portions, thereby obtaining the structure of this embodiment.

[0067] (Effects of the second embodiment) According to this embodiment, the following effects can be obtained.

[0068] According to this embodiment, the waviness amount of the facing portion 16 of the first main surface side outermost internal electrode 151A is larger than the waviness amount of the facing portion 16 of the internal electrode 15 adjacent to the first main surface side outermost internal electrode 151A. Also, the waviness amount of the facing portion 16 of the second main surface side outermost internal electrode 151B is larger than the waviness amount of the facing portion 16 of the internal electrode 15 adjacent to the second main surface side outermost internal electrode 151B.

[0069] The outer layer portions 12 and the inner layer portions 11 have different elastic moduli. Therefore, when stress is applied to the laminate chip during the manufacturing process of the multilayer ceramic capacitor, stress is likely to be applied to the interface between the outer layer portions 12 and the inner layer portions 11. This makes it easy for interfacial peeling to occur between the outer layer portions 12 and the inner layer portions 11. However, with this configuration, by increasing the amount of waviness of each outermost internal electrode 151, it is possible to increase the contact area between each outermost internal electrode 151 and the outer layer portion 12, thereby improving the adhesive strength between each outermost internal electrode 151 and the outer layer portion 12. This makes it possible to suppress interfacial peeling between the outer layer portions 12 and the inner layer portion 11.

[0070] Third Embodiment Next, a multilayer ceramic capacitor 1 according to a third embodiment of the present invention will be described with reference to Fig. 5. The following description will focus on differences from the first embodiment, and the same components as those in the first embodiment will be given the same reference numerals and descriptions thereof will be omitted.

[0071] As shown in FIG. 5, in the third embodiment, the bending angle of the outermost bent portion 21A of the first principal surface side outermost internal electrode 151A is smaller than that of the above-described embodiments.

[0072] The bending angle of the outermost bent portion 21A is smaller than 30°.

[0073] The multilayer ceramic capacitor 1 of the third embodiment can be manufactured by the following method.

[0074] During isostatic pressing, the laminated sheet is sandwiched between metal plates having a convex shape at a position corresponding to the drawing region of the laminated sheet, as in the first embodiment. Here, by adjusting the convex shape of the metal plates and further increasing the pressure of the isostatic press, bending progresses and the structure of this embodiment can be obtained.

[0075] (Effects of the third embodiment) According to this embodiment, the following effects can be obtained.

[0076] The bending angle of the outermost bent portion 21A is smaller than 30°.

[0077] This configuration allows the outer layer portion 12 to be deeply embedded in the outermost internal electrode. This improves the adhesive strength between the outer layer portion 12 and the first-principal-surface-side outermost internal electrode 151A. This makes it possible to suppress the progression of peeling of the outer layer portion 12 at the position of the outermost bent portion 21A when the outer layer portion 12 attempts to peel from the first end face CA side. This makes it possible to suppress interfacial peeling between the outer layer portion 12 and the inner layer portion 11.

[0078] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible.

[0079] In the above-described embodiment, a multilayer ceramic capacitor in which the dielectric layers 14 made of a dielectric ceramic are used as ceramic layers has been described as an example of the multilayer ceramic electronic component. However, the multilayer ceramic electronic component of the present disclosure is not limited to this. For example, the ceramic electronic component of the present disclosure can also be applied to various other multilayer ceramic electronic components, such as piezoelectric components using piezoelectric ceramic as ceramic layers, thermistors using semiconductor ceramic as ceramic layers, and inductors using magnetic ceramic as ceramic layers. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ceramics such as ferrite. [Explanation of symbols]

[0080] 1. Multilayer ceramic capacitors 2. Laminate 3 External electrode 10 Effective layer 14 Dielectric layer (ceramic layer) 15 Internal electrode 16 Opposing part 17A 1st drawer section (drawer section) 17B 2nd drawer section (drawer section) 18A 1st slope section 19A 2nd slope section 20A bend 21A Outermost bend 151A First main surface side outermost internal electrode (outermost internal electrode) 151B Second main surface side outermost internal electrode (outermost internal electrode) AA First principal surface AB Second principal surface BA 1st side BB 2nd side CA 1st end face CB 2nd end face A1 1st reference area (reference area) A2 2nd reference area (reference area) A3 Third reference area (reference area) A4 4th reference area (reference area) LA1 First main surface side reference line (main surface side reference line) LC1 1st end side reference line (end side reference line) VL Virtual connecting line

Claims

1. a laminate having an inner layer portion including alternately stacked ceramic layers and internal electrodes, a first main surface and a second main surface facing each other in a stacking direction, a first side surface and a second side surface facing each other in a width direction that is a direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in a length direction that is a direction perpendicular to the stacking direction and the width direction; external electrodes arranged in pairs on each end surface; A multilayer ceramic electronic component comprising: the internal electrodes each have an opposing portion opposing the internal electrode adjacent to the internal electrode in the stacking direction, and an extraction portion extracted from the opposing portion and connected to the external electrode, the laminate has an effective layer portion including each of the opposing portions and a portion of each of the ceramic layers sandwiched between the adjacent opposing portions, In the stacking direction, a direction in which each main surface is viewed from a center portion of the stacking direction of the laminate is defined as an outer side in the stacking direction, and a direction in which the center portion of the stacking direction of the laminate is viewed from each main surface is defined as a center side in the stacking direction, If a cross section parallel to the stacking direction and the length direction is defined as an LT cross section, In the LT cross section, the drawn-out portion includes a first inclined portion drawn out from the opposing portion and inclined toward the center in the stacking direction as it moves from the opposing portion side toward a side away from the opposing portion, a second inclined portion extending from the first inclined portion toward the side away from the opposing portion and inclined outward in the stacking direction as it moves from the opposing portion side toward the side away from the opposing portion, and a bent portion connecting the first inclined portion and the second inclined portion, A straight line that is a tangent to the end surface and extends parallel to the stacking direction is defined as an end surface side reference line, A straight line that is a tangent to the main surface and extends parallel to the length direction is defined as a main surface side reference line, The distance between the bent portion and the end face side reference line is defined as x, The distance between the bent portion and the main surface side reference line is defined as y, One of the regions divided into four by a straight line passing through a center portion of the stacking direction of the stack and a straight line passing through a center portion of the length direction of the stack is set as a reference region, When a regression line derived based on the values ​​of x and y related to the bend portion in the reference region is defined as a virtual connecting line, The virtual connecting line intersects with the effective layer portion.

2. In the reference region, the bent portion located most outward in the stacking direction is defined as an outermost bent portion, 2. The multilayer ceramic electronic component according to claim 1, wherein the bending angle of the outermost bent portion is smaller than the bending angle of the bent portion located closer to the center in the stacking direction than the outermost bent portion.

3. 3. The multilayer ceramic electronic component according to claim 2, wherein the bending angle of the outermost bending portion is smaller than 30 degrees.

4. the internal electrode positioned most outside in the stacking direction is defined as an outermost internal electrode, When the amount of waviness is determined by dividing the length of the contour line of the opposing portion on the outer side in the stacking direction by the distance between the ends of the opposing portion in the length direction, 4. The multilayer ceramic electronic component according to claim 1, wherein the waviness of the facing portion of the outermost internal electrode is larger than the waviness of the facing portion of the internal electrode adjacent to the outermost internal electrode.

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