Display device

Abstract

To provide a display device capable of inhibiting leak light.SOLUTION: Each of a plurality of switching elements included in the display device comprises: a semiconductor layer; one scan line of a plurality of scan lines provided on the semiconductor layer; one signal line of the plurality of signal lines in contact with a first portion of the semiconductor layer; a first insulator layer provided between a third portion of the semiconductor layer and one scan line; a second insulator layer covering the first insulator layer and one scan line; and a first contact hole provided in the first insulator layer and the second insulator layer and reaching the first portion of the semiconductor layer. The one signal line is in contact with the first portion of the semiconductor layer through the first contact hole. The first contact hole is provided over the plurality of pixels and has a rectangular shape in plan view.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] An active matrix liquid crystal display device has, on a substrate, scanning lines, signal lines, and pixels (sub-pixels) arranged in areas where the scanning lines and the signal lines intersect. When selected by the scanning lines, the pixels (sub-pixels) have switching elements that are driven in response to video signals supplied from the signal lines. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-276485 Summary of the Invention [Problem to be solved by the invention]

[0004] The present embodiment provides a display device capable of suppressing light leakage. [Means for solving the problem]

[0005] A display device according to an embodiment includes: a first substrate; A second substrate; a liquid crystal layer disposed between the first substrate and the second substrate; Equipped with The first substrate is a plurality of scan lines extending along a first direction; a plurality of signal lines extending along a second direction intersecting the first direction; a plurality of pixels provided at intersections of the plurality of scanning lines and the plurality of signal lines; A plurality of switching elements provided in the plurality of pixels; Equipped with Each of the plurality of switching elements a semiconductor layer; one of the plurality of scanning lines provided on the semiconductor layer; one signal line among the plurality of signal lines contacting a first portion of the semiconductor layer; a first insulating layer provided between the third portion of the semiconductor layer and the one scan line; a second insulating layer covering the first insulating layer and the one scan line; a first contact hole provided in the first insulating layer and the second insulating layer and reaching the first portion of the semiconductor layer; Equipped with the one signal line contacts the first portion of the semiconductor layer through the first contact hole; The first contact hole is provided across the plurality of pixels and has a rectangular shape in a plan view.

[0006] Moreover, the display device according to one embodiment includes: a first substrate; A second substrate; a liquid crystal layer disposed between the first substrate and the second substrate; Equipped with The first substrate is a plurality of scan lines extending along a first direction; a plurality of signal lines extending along a second direction intersecting the first direction; a plurality of pixels provided at intersections of the plurality of scanning lines and the plurality of signal lines; A plurality of switching elements provided in the plurality of pixels; Equipped with Each of the plurality of switching elements a semiconductor layer; one of the plurality of scanning lines provided on the semiconductor layer; one signal line among the plurality of signal lines contacting a first portion of the semiconductor layer; a first insulating layer provided between the third portion of the semiconductor layer and the one scan line; a second insulating layer covering the first insulating layer and the one scan line; a first contact hole provided in the first insulating layer and the second insulating layer and reaching a first portion of the semiconductor layer; a third insulating layer provided to cover the second insulating layer, the first portion of the semiconductor layer, and the one signal line; a second contact hole provided in the first insulating layer, the second insulating layer, and the third insulating layer; Equipped with the one signal line contacts the first portion of the semiconductor layer through the first contact hole; The first contact hole is provided across the plurality of pixels so as to pass through the plurality of signal lines, and has a rectangular shape in a plan view. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing the configuration of the display device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing an example of a schematic configuration of the display device of the first embodiment. [Figure 3] FIG. 3 is a plan view showing an example of a schematic configuration of a display device of Comparative Example 1. As shown in FIG. [Figure 4] FIG. 4 is a plan view showing an example of a schematic configuration of a display device of Comparative Example 1. As shown in FIG. [Figure 5] FIG. 5 is a cross-sectional view showing a schematic example of a display device of Comparative Example 2. As shown in FIG. [Figure 6] FIG. 6 is a plan view showing an example of a schematic configuration of the display device of the first embodiment. [Figure 7] FIG. 7 is a plan view showing an example of a schematic configuration of the display device of the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view showing the cross-sectional structure of the display device taken along the line A1-A2 shown in FIG. [Figure 9] FIG. 9 is a plan view showing another example of the configuration of the display device according to the second embodiment. [Figure 10]FIG. 10 is a cross-sectional view showing the cross-sectional structure of the display device taken along line B1-B2 shown in FIG. [Figure 11] FIG. 11 is a plan view showing an example of a schematic configuration of a display device according to the second embodiment. [Figure 12] FIG. 12 is a plan view showing only the contact hole CH1 among the components of FIG. [Figure 13] FIG. 13 is a plan view of a display device of Comparative Example 3. As shown in FIG. [Figure 14] FIG. 14 is a plan view showing only the contact hole CH1 among the components of FIG. [Figure 15] FIG. 15 is a cross-sectional view showing the cross-sectional structure of the display device taken along the line C1-C2 shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view showing the cross-sectional structure of the display device taken along line D1-D2 shown in FIG. [Figure 17] FIG. 17 is a plan view showing another configuration example of the display device according to the second embodiment. [Figure 18] FIG. 18 is a cross-sectional view showing the cross-sectional structure of the display device taken along the line E1-E2 shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those described above with reference to the previous drawings may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0009] The embodiments described in this specification are not general but are embodiments that describe the same or corresponding special technical features of the present invention. Hereinafter, a display device according to an embodiment will be described in detail with reference to the drawings.

[0010] In this embodiment, the first direction X, the second direction Y, and the third direction Z are perpendicular to one another, but may intersect at an angle other than 90 degrees. The direction toward the tip of the arrow of the third direction Z is defined as up or upward, and the direction opposite to the direction toward the tip of the arrow of the third direction Z is defined as down or downward. The first direction X, the second direction Y, and the third direction Z may also be referred to as the X direction, the Y direction, and the Z direction, respectively.

[0011] Furthermore, when the terms "second member above the first member" and "second member below the first member" are used, the second member may be in contact with the first member or may be located apart from the first member. In the latter case, a third member may be interposed between the first and second members. On the other hand, when the terms "second member above the first member" and "second member below the first member" are used, the second member is in contact with the first member.

[0012] Furthermore, it is assumed that an observation position for observing the display device is located at the tip of the arrow in the third direction Z, and viewing from this observation position toward the XY plane defined by the first direction X and the second direction Y is called planar view. Viewing a cross section of the display device in the XZ plane defined by the first direction X and the third direction Z, or in the YZ plane defined by the second direction Y and the third direction Z, is called cross-sectional view.

[0013] [Embodiment 1] Fig. 1 is a plan view showing the configuration of a display device according to embodiment 1. The display device DSP1 shown in Fig. 1 includes a display panel PNL and an illumination device IPD. The display panel PNL includes a substrate SUB1, a substrate SUB2, and a liquid crystal layer LC. The liquid crystal layer LC is an example of a display function layer, and is sealed between the substrate SUB1 and the substrate SUB2.

[0014] The display panel PNL has a display area DA where an image is displayed in an area where the substrates SUB1 and SUB2 overlap, and a peripheral area SA around the display area DA. The display panel PNL has a plurality of pixels PX in the display area DA. The plurality of pixels PX are arranged in a matrix.

[0015] The substrate SUB1 has a plurality of scanning lines GL and a plurality of signal lines SL in the display area DA. The scanning lines GL extend in a first direction X and are aligned in a second direction Y. The signal lines SL extend in the second direction Y and are aligned in the first direction X.

[0016] The substrate SUB1 includes a scanning line driving circuit GD and a signal line driving circuit SD in the peripheral area SA. The scanning lines GL are electrically connected to the scanning line driving circuit GD. The signal lines SL are electrically connected to the signal line driving circuit SD.

[0017] A pixel PX includes a plurality of sub-pixels SP. Each sub-pixel SP corresponds to an area defined by, for example, two adjacent scanning lines GL and two adjacent signal lines SL. In this disclosure, the sub-pixels SP may be simply referred to as pixels PX. The sub-pixels SP (pixels PX) can also be said to be arranged in areas where the scanning lines GL and the signal lines SL intersect.

[0018] In the example shown in Fig. 1, one pixel PX has three subpixels: SPR, SPG, and SPB. The subpixel SPR displays red, the subpixel SPG displays green, and the subpixel SPB displays blue. However, the pixel PX may have more subpixels SP. Furthermore, the colors displayed by the subpixels SP are not limited to red, green, and blue, and may be other colors such as white or yellow.

[0019] In each sub-pixel SP, the substrate SUB1 includes a switching element SW and a pixel electrode PE. The switching element SW is electrically connected to the scanning line GL and the signal line SL. The pixel electrode PE is electrically connected to the switching element SW. A common electrode CE is provided in common to the plurality of sub-pixels SP. The common electrode CE is provided on the substrate SUB1.

[0020] The substrate SUB1 has a terminal area TA that does not overlap with the substrate SUB2. In the example shown in Fig. 1, an IC chip ICP and a flexible printed circuit board FPC are mounted in the terminal area TA. The IC chip ICP may also be mounted on the flexible printed circuit board FPC.

[0021] For example, the IC chip ICP is electrically connected to the common electrode CE, the scanning line driving circuit GD, and the signal line driving circuit SD. The IC chip ICP supplies a common voltage Vcom to the common electrode CE. The IC chip ICP supplies various signals to the scanning line driving circuit GD and the signal line driving circuit SD. The signal line driving circuit SD supplies a video signal to each of the signal lines SL.

[0022] The illumination device IPD is provided on the rear side of the display panel PNL and illuminates the display area DA. Although details of the illumination device IPD are omitted, the illumination device IPD includes a flat light guide plate and a plurality of light sources arranged along the edge surface of the light guide plate.

[0023] Fig. 2 is a cross-sectional view showing an example of a schematic configuration of the display device of Embodiment 1. The display device DSP1 shown in Fig. 2 includes a substrate SUB1, a substrate SUB2, a liquid crystal layer LC, and polarizers PL1 and PL2.

[0024] The substrate SUB1 includes a base material BA1, a switching element SW, an insulating layer INS1, a pixel electrode PE, an insulating layer INS2, a common electrode CE, and an alignment film AL1. The substrate SUB2 includes a base material BA2, a light-shielding layer BM, and an alignment film AL2.

[0025] The substrates SUB1 and SUB2 are bonded together with a sealant SAL. The liquid crystal layer LC is disposed between the substrates SUB1 and SUB2 in a space surrounded by the sealant SAL.

[0026] The substrate BA1 is formed of a transparent insulating substrate, such as glass. The insulating layers INS1 and INS2 are each formed of a single layer of an inorganic insulating material, a single layer of an organic insulating material, or a laminate of an inorganic insulating material and an organic insulating material.

[0027] The pixel electrode PE is provided on the insulating layer INS1 and is connected to the switching element SW via a contact hole provided in the insulating layer INS1.

[0028] The common electrode CE is provided on the pixel electrode PE with an insulating layer INS2 sandwiched therebetween. However, the first embodiment is not limited to this. The pixel electrode PE connected to the switching element SW may be provided on the common electrode CE with an insulating layer INS2 sandwiched therebetween. The electrode formed above the pixel electrode PE or the common electrode CE, that is, the common electrode CE in the first embodiment, is provided with a slit CST through which electric lines of force pass.

[0029] An alignment film AL1 is provided to cover either the pixel electrode PE or the common electrode CE, which is an electrode formed above the pixel electrode PE or the common electrode CE, in embodiment 1. The alignment film AL1 and an alignment film AL2, which will be described later, may be horizontal alignment films or vertical alignment films.

[0030] The light-shielding layer BM is provided in contact with the base material BA2 and faces the switching element SW in the third direction Z.

[0031] An alignment film AL2 is provided to cover the substrate BA2 and the light-shielding layer BM.

[0032] Polarizer PL1 is provided in contact with the surface of substrate BA1 opposite to the surface facing liquid crystal layer LC. Polarizer PL2 is provided in contact with the surface of substrate BA2 opposite to the surface facing liquid crystal layer LC. As will be described in detail later, the polarization axes of polarizer PL1 and polarizer PL2 are parallel to the first direction X or the second direction, or one of them is parallel to the first direction X and the other is parallel to the second direction Y.

[0033] 3 and 4 are plan views showing an example of a schematic configuration of a display device of Comparative Example 1. The display device DSPr1 shown in Fig. 3 includes scanning lines GL, a light-shielding layer LS, a semiconductor layer SCS, signal lines SL, a drain electrode DE, and a light-shielding layer BM. Fig. 4 shows the configuration of Fig. 3 excluding the light-shielding layer LS and the light-shielding layer BM.

[0034] The two scanning lines GL extend along the first direction X and are arranged side by side along the second direction Y. The two signal lines SL extend along the second direction Y and are arranged side by side along the first direction X. As described above, the area surrounded by the two scanning lines GL and the two signal lines SL is a sub-pixel SP (pixel PX). One sub-pixel SP (pixel PX) has one scanning line GL, one signal line SL, and a semiconductor layer SCS.

[0035] The light-shielding layer LS is provided so as to overlap the scanning lines GL in a plan view. The light-shielding layer LS is provided below the scanning lines GL. The light-shielding layer LS is made of a conductive material, for example, a metal material. The light-shielding layer LS may be connected to the scanning lines GL and may be given the same potential as the scanning lines GL.

[0036] The scanning lines GL, signal lines SL, and light-shielding layer LS are made of, for example, a metal material, such as a single layer or multilayer of titanium (Ti), aluminum (Al), tungsten (W), tantalum (Ta), or the like, or a nitride or oxide of these metal materials.

[0037] 3 and 4 is formed of, for example, polycrystalline silicon (polysilicon). The semiconductor layer SCS includes a first portion SCS1 extending along the second direction Y, a second portion SCS2 extending along the first direction X, and a third portion SCS3 extending along the second direction Y.

[0038] A first portion SCS1 of the semiconductor layer SCS overlaps the signal line SL, a third portion SCS3 of the semiconductor layer SCS overlaps the drain electrode DE, and a second portion SCS2 of the semiconductor layer SCS overlaps an opening region OP, which will be described later.

[0039] The semiconductor layer SCS, the region of the scanning line GL that overlaps with the semiconductor layer SCS, the region of the signal line SL that overlaps with the semiconductor layer SCS, and the drain electrode DE are collectively referred to as the switching element SWr. The switching element SWr includes an insulating layer (not shown) that is provided between these components. The switching element SWr is provided in each pixel PX (sub-pixel SP) provided in the display area DA.

[0040] The light-shielding layer BM covers the light-shielding layer LS, the scanning lines GL, the signal lines SL, the drain electrodes DE, and part of the semiconductor layer SCS. The region of the light-shielding layer BM that covers the scanning lines GL and the light-shielding layer LS and extends along the first direction X is referred to as the light-shielding region BMX. The region of the light-shielding layer BM that covers the signal lines SL and extends along the second direction Y is referred to as the light-shielding region BMY.

[0041] In each subpixel SP, a region where the light-shielding layer BM is not provided is defined as an opening region OP. The opening region OP overlaps with the second portion SCS2 of the semiconductor layer SCS. In other words, the second portion SCS2 does not overlap with the light-shielding layer BM.

[0042] Contact holes CHR1 and CHR2 are provided in regions where the first portion SCS1 of the semiconductor layer SCS and the signal line SL overlap, and in regions where the third portion SCS3 of the semiconductor layer SCS and the drain electrode DE overlap, respectively. The contact holes CHR1 and CHR2 are contact holes provided in an insulating layer provided between the semiconductor layer SCS and the signal line SL, and between the semiconductor layer SCS and the drain electrode DE, respectively. The contact holes CHR1 and CHR2 have a circular shape in plan view. Also, it is assumed that the contact holes CHR1 and CHR2 have the same size.

[0043] Let the length (width) of the signal line SL along the first direction X be length ws. Let the length (width) of the drain electrode DE along the first direction X be length wd. In the light-shielding region BMY that overlaps the signal line SL and extends along the second direction Y, let the length (width) along the first direction X be length wb. Let the diameter of the contact holes CHR1 and CHR2 be diameter dc.

[0044] As shown in FIGS. 3 and 4, the diameter dc of the contact holes CHR1 and CHR2 is longer than the length ws of the signal line SL (ws < dc). As shown in FIG. 3, the diameter dc of the contact hole CHR1 is longer than the length wb of the light-shielding region BMY (wb < dc). In FIG. 3, the length wd and the diameter dc are substantially the same, but they may be different.

[0045] In a high-definition display device DSPr1, in order to obtain a high aperture ratio, it is necessary to make the light-shielding layer BM thinner together with the signal line SL. It is difficult to reduce the diameter in the processing of the contact holes CHR1 and CHR2. Therefore, the diameter of the contact holes CHR1 and CHR2 becomes larger than the width of the signal line SL and the width of the light-shielding layer BM. Due to the portions of the contact holes CHR1 and CHR2 that do not overlap the signal line SL and the light-shielding layer BM, polarization cancellation occurs, resulting in a decrease in contrast.

[0046] Fig. 5 is a cross-sectional view showing a schematic example of a display device of Comparative Example 2. In the display device DSPr2 shown in Fig. 5, the scanning line driving circuit GD and the signal line driving circuit SD provided in the peripheral area SA are formed of transistors having polycrystalline silicon as a semiconductor layer. On the other hand, the switching element SWr provided in the display area DA is formed of a transistor having an oxide semiconductor as a semiconductor layer.

[0047] The display device DSPr2 shown in Fig. 5 differs from the display device DSPr1 shown in Fig. 3 in that the switching element SWr is formed of a transistor having an oxide semiconductor as a semiconductor layer. Furthermore, while Fig. 3 shows the structure of the pixel PX (sub-pixel SP) in the display area DA, Fig. 5 also shows the structures of the components provided in the display area DA and the peripheral area SA.

[0048] An insulating layer UC is provided on a base material BA1. Semiconductor layers SCSA and SCSB are provided on the insulating layer UC in the peripheral area SA. The semiconductor layers SCSA and SCSB are semiconductor layers made of polycrystalline silicon.

[0049] An insulating layer GI1 is provided to cover the insulating layer UC, the semiconductor layer SCSA, and the semiconductor layer SCSB.

[0050] A gate electrode GE11 is provided on the semiconductor layer SCSA with an insulating layer GI1 sandwiched therebetween. A gate electrode GE12 and a gate electrode GE13 are provided on the semiconductor layer SCSB with an insulating layer GI1 sandwiched therebetween. The gate electrodes GE12 and GE13 are arranged apart from each other with a gap therebetween. A light-shielding layer LS1 is provided in the display area DA. The gate electrodes GE11, GE12, GE13, and the light-shielding layer LS1 are formed of the same material and in the same process. In this specification, elements formed of the same material and in the same process are said to be formed in the same layer.

[0051] An insulating layer ILI is provided to cover the insulating layer GI1, the gate electrodes GE11, GE12, GE13, and the light-shielding layer LS1. A semiconductor layer SCOR is provided on the light-shielding layer LS1 with the insulating layer ILI sandwiched therebetween.

[0052] An insulating layer GI2 is provided to cover the insulating layer ILI and the semiconductor layer SCOR. An electrode EG21, an electrode EG22, an electrode EG23, an electrode EG24, an electrode EG25, and a gate electrode GE21 are provided on the insulating layer GI2.

[0053] The electrodes EG21 and EG22 are in contact with the semiconductor layer SCSA via contact holes provided in the insulating layers GI1, ILI, and GI2. The electrodes EG23, EG24, and EG25 are in contact with the semiconductor layer SCSB via contact holes provided in the insulating layers GI1, ILI, and GI2. The electrode EG24 is provided between the gate electrodes GE12 and GE13. The gate electrode GE21 is provided on the semiconductor layer SCOR, with the insulating layer GI2 sandwiched therebetween.

[0054] An insulating layer PAS1 is provided to cover the insulating layer GI2, the electrodes EG21, EG22, EG23, EG24, EG25, and the gate electrode GE21.

[0055] Electrodes ES1, ES2, ES3, ES4, ES5, and signal lines SL are provided on the insulating layer PAS1.

[0056] The electrode ES1 is connected to the electrode EG21 through a contact hole provided in the insulating layer PAS1. The electrode ES2 is connected to the electrode EG22 through a contact hole provided in the insulating layer PAS1. The electrode ES3 is connected to the electrode EG23 through a contact hole provided in the insulating layer PAS1. The electrode ES4 is connected to the electrode EG24 through a contact hole provided in the insulating layer PAS1. The electrode ES5 is connected to the electrode EG25 through a contact hole provided in the insulating layer PAS1.

[0057] The signal line SL is connected to the semiconductor layer SCOR via a contact hole CHR1 provided in the insulating layer GI2 and the insulating layer PAS1.

[0058] An insulating layer PAS2 is provided to cover the insulating layer PAS1, the electrodes ES1, ES2, ES3, ES4, ES5, and the signal lines SL.

[0059] The electrodes IT11 and IT12 are provided on the insulating layer PAS2. The electrodes IT11 and IT12 are made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide.

[0060] The electrode IT11 is connected to the semiconductor layer SCOR through contact holes provided in the insulating layer GI2, the insulating layer PAS1, and the insulating layer PAS2. The electrode IT11 extends onto the insulating layer PAS2 up to above the gate electrode GE21.

[0061] The semiconductor layer SCOR, the insulating layer GI2, the gate electrode GE21, the insulating layer PAS1, the signal line SL, and the electrode IT11 constitute a switching element SWr. Furthermore, when the same voltage as that applied to the gate electrode GE21 is applied to the light-shielding layer LS1, the light-shielding layer LS1 and the insulating layer ILI may also be included in the switching element SWr. The switching element SWr is provided for each pixel (sub-pixel) provided in the display area DA.

[0062] The electrode IT12 is connected to the electrode ES4 via a contact hole provided in the insulating layer PAS2.

[0063] An insulating layer PAS3 is provided so as to cover the insulating layer PAS2, the electrode IT11, and a part of the electrode IT12. A contact hole CP31 is formed in the insulating layer PAS3 on the gate electrode GE21. The insulating layer PAS3 on the electrode ES4 and the electrode IT12 is removed to form a contact hole CP32.

[0064] A color filter CF1 and a color filter CF2 are provided on the insulating layer PAS3. The color filter CF1 and the color filter CF2 are color filters of different colors.

[0065] Color filter CF1 is provided from the left side of contact hole CP31 on the paper surface to over electrode IT11. Color filter CF2 is provided from the right side of contact hole CP31 on the paper surface to over signal line SL.

[0066] An insulating layer PLL is provided to cover the insulating layer PAS3, color filter CF1, and color filter CF2. However, the insulating layer PLL is not provided on contact holes CP31 and CP32, and opening regions OPR1 and OPR2 of the insulating layer PLL are formed instead. The insulating layer PLL is made of an organic resin material, such as polyimide resin or acrylic resin.

[0067] Electrodes IT21 and IT22 are provided on the insulating layer PLL. Electrodes IT21 and IT22 are made of the above-mentioned transparent conductive material. Electrode IT21 is connected to electrode IT11 via contact hole CP31 and opening region OPR1. Electrode IT11 corresponds to the drain electrode DE. Electrode IT21 corresponds to the pixel electrode PE. Electrode IT22 is connected to electrode IT12 via contact hole CP32 and opening region OPR2.

[0068] An insulating layer LSN is provided to cover the insulating layer PLL, the electrode IT21, and the electrode IT22. The insulating layer LSN may be formed of, for example, an inorganic insulating material, more specifically, silicon oxide or silicon nitride. A contact hole PC1 is formed in the insulating layer LSN above the gate electrode GE12.

[0069] Electrodes TME1 and TME2 are provided on the insulating layer LSN. The electrodes TME1 and TME2 are made of a metal material. The electrode TME1 is provided on the electrode IT21 with the insulating layer LSN sandwiched therebetween. The electrode TME2 is provided on the electrode IT22 with the insulating layer LSN sandwiched therebetween, and is connected to the electrode IT22 via a contact hole PC1.

[0070] The electrode IT3 is provided to cover the insulating layer LSN, the electrode TME1, and the electrode TME2. The electrode IT3 is made of the transparent conductive material described above. The electrode IT3 has a plurality of slits CST. The electrode IT3 corresponds to the common electrode CE. The electrode TME1 is an auxiliary electrode for the common electrode CE (electrode IT3).

[0071] An insulating layer OC2 is provided on the electrode IT3, filling the recess caused by the opening region OPR1. The insulating layer OC2 may be formed of the organic resin material described above. The insulating layer OC2 flattens the surface above the gate electrode GE21 and in contact with the liquid crystal layer LC.

[0072] An alignment film (not shown) is provided to cover the common electrode CE (electrode IT3) and the insulating layer OC2. Spacers PS are provided on the alignment film on a surface that is planarized by the insulating layer OC2. Spacers PS are also provided on the alignment film above the semiconductor layer SCSA.

[0073] The configuration from the base material BA1 to the alignment film is the cross-sectional configuration of the substrate SUB1.

[0074] A light-shielding layer BM is provided in contact with the base material BA2 in an area overlapping the peripheral area SA. An insulating layer OC3 is provided in contact with the base material BA2 and the light-shielding layer BM. The insulating layer OC3 may be formed from the organic insulating material described above. An alignment film (not shown) is provided to cover the insulating layer OC3.

[0075] The configuration from the base material BA2 to the alignment film is the cross-sectional configuration of the substrate SUB2.

[0076] The above-mentioned spacers PS, sealant SAL, and liquid crystal layer LC are provided between the substrates SUB1 and SUB2. The sealant SAL is provided in the peripheral area SA. The spacers PS function to maintain the distance between the substrates SUB1 and SUB2.

[0077] 6 and 7 are plan views showing an example of a schematic configuration of the display device of embodiment 1. The display device DSP1 shown in Fig. 6 differs from the display device DSPr1 shown in Fig. 3 in that the contact hole CH1 has a rectangular shape extending along the first direction X rather than a circular shape in plan view (the contact holes CHR1 and CHR2 shown in Fig. 3). Fig. 7 shows the configuration of Fig. 6 excluding the light-shielding layer LS and the light-shielding layer BM.

[0078] 6 includes a scanning line GL, a light-shielding layer LS, a semiconductor layer SCS, a signal line SL, a drain electrode DE, and a light-shielding layer BM. One sub-pixel SP (pixel PX) includes one scanning line GL, one signal line SL, and a semiconductor layer SCS.

[0079] The light-shielding layer LS is provided so as to overlap the scanning lines GL in a plan view, and is provided below the scanning lines GL.

[0080] The semiconductor layer SCS included in the display device DSP1 in Fig. 6 is made of, for example, polycrystalline silicon (polysilicon). As in Fig. 3, the semiconductor layer SCS includes a first portion SCS1 extending along the second direction Y, a second portion SCS2 extending along the first direction X, and a third portion SCS3 extending along the second direction Y.

[0081] The first portion SCS1 of the semiconductor layer SCS overlaps the signal line SL, and the third portion SCS3 of the semiconductor layer SCS overlaps the drain electrode DE.

[0082] The light-shielding layer BM covers the light-shielding layer LS, the scanning lines GL, the signal lines SL, the drain electrodes DE, and a part of the semiconductor layer SCS. In the light-shielding layer BM, a light-shielding region BMX covers the scanning lines GL and the light-shielding layer LS. In the light-shielding layer BM, a light-shielding region BMY covers the signal lines SL.

[0083] In each of the subpixels SP, the opening region OP where the light-shielding layer BM is not provided overlaps with the second portion SCS2 of the semiconductor layer SCS. That is, the second portion SCS2 does not overlap with the light-shielding layer BM.

[0084] 6, an opening region OPH is provided so as to overlap the third portion SCS3 of the semiconductor layer SCS and the drain electrode DE. As will be described in detail later, the opening region OPH is a contact hole through which the drain electrode DE comes into contact with the semiconductor layer SCS (third portion SCS3).

[0085] A contact hole CH1 is provided to connect the signal line SL to the semiconductor layer SCS. The contact hole CH1 overlaps a part of the third portion SCS3 of the semiconductor layer SCS, a part of the drain electrode DE, a part of the signal line SL, and the first portion SCS1 and second portion SCS2 of the semiconductor layer SCS. The contact hole CH1 overlaps an opening region OP of the light-shielding layer BM.

[0086] For example, one of the polarization axes of the polarizers PL1 and PL2 is a polarization axis DX parallel to the first direction X, and the other is a polarization axis DY parallel to the second direction Y. The extension direction of the contact hole CH1 shown in FIGS. 6 and 7 is parallel to the polarization axis DX.

[0087] When the extension direction of the contact hole CH1 is parallel to the polarization axis DX or the polarization axis DY, depolarization due to the contact hole CH1 does not occur, and therefore the contrast of the display device DSP1 can be improved.

[0088] The contact hole CH1 overlaps the entire opening region OP of the light-shielding layer BM. The end of the contact hole CH1 overlaps the light-shielding layer LS. As described above, the contact hole CH1 extends parallel to the polarization axis DX. However, the extension direction of the contact hole CH1 may also be parallel to the polarization axis DY.

[0089] Furthermore, the contact hole CH1 is provided not only within one subpixel SP, but also across a plurality of subpixels SP that are arranged adjacent to each other in the first direction X.

[0090] Fig. 8 is a cross-sectional view showing the cross-sectional structure of the display device taken along line A1-A2 shown in Fig. 6. Fig. 8 is a cross-sectional view showing a thin film transistor (TFT) serving as a switching element SW and its periphery.

[0091] In the present disclosure, the thin film transistor that is the switching element SW includes a semiconductor layer made of silicon containing polycrystalline silicon or a semiconductor layer made of an oxide semiconductor, a gate electrode, a signal line SL or a source electrode that is a part of the signal line SL, a drain electrode, an insulating layer (gate insulating layer) provided between the semiconductor layer and the gate electrode, and an insulating layer provided between the semiconductor layer and the signal line SL (source electrode) and drain electrode. In the present disclosure, the switching element SW is defined as a thin film transistor that includes these components.

[0092] A light-shielding layer LS is provided on a base material BA1. An insulating layer UC is provided to cover the base material BA1 and the light-shielding layer LS. A semiconductor layer SCS is provided on the insulating layer UC. The semiconductor layer SCS faces the light-shielding layer LS with the insulating layer UC sandwiched between them. In particular, a third portion SCS3 of the semiconductor layer SCS faces the light-shielding layer LS along the third direction Z.

[0093] A drain electrode DE is provided in contact with the third portion SCS3 of the semiconductor layer SCS. A signal line SL is provided in contact with the first portion SCS1 of the semiconductor layer SCS. An insulating layer GI is provided in a region where the third portion SCS3 of the semiconductor layer SCS intersects with the light-shielding layer LS and the scanning line GL.

[0094] A gate electrode GE, which is a part of the scan line GL, is provided on the insulating layer GI. An insulating layer PAS1 is provided to cover the insulating layer GI and the gate electrode GE. A drain electrode DE is provided on the insulating layer PAS1. The drain electrode DE extends from a region on the insulating layer PAS1 along the side surfaces of the insulating layer PAS1 and the insulating layer GI, and is in contact with the third portion SCS3 of the semiconductor layer SCS as described above.

[0095] An insulating layer PLL is provided to cover the insulating layer UC, the drain electrode DE, the semiconductor layer SCS, the insulating layer GI, the insulating layer PAS1, and the signal line SL. The insulating layer PLL has an opening region OPH on the semiconductor layer SCS and the gate electrode GE, which reaches the drain electrode DE.

[0096] Between the signal line SL and the drain electrode DE, a contact hole CH1 reaching the semiconductor layer SCS is provided in the insulating layers GI and PAS1. That is, the signal line SL is in contact with the first portion SCS1 of the semiconductor layer SCS through the contact hole CH1 provided in the insulating layers GI and PAS1.

[0097] In the display device DSP1 of the first embodiment, the contact hole CH1 extends in a direction parallel to the polarization axis DX (or the polarization axis DY), which prevents depolarization caused by the contact hole CH1 and improves the contrast of the display device DSP1.

[0098] [Embodiment 2] Fig. 9 is a plan view showing another configuration example of the display device according to embodiment 2. The configuration example shown in Fig. 9 differs from the configuration example shown in Fig. 6 in that the semiconductor layer is an oxide semiconductor layer.

[0099] 9 includes a semiconductor layer SCO, which is an oxide semiconductor layer. The semiconductor layer SCO includes a first portion SCO1 extending along the second direction Y, a second portion SCO2 extending along the first direction X, and a third portion SCO3 extending along the second direction Y.

[0100] A first portion SCO1 of the semiconductor layer SCO overlaps the signal line SL. A third portion SCO3 of the semiconductor layer SCO overlaps the electrode IT1. The electrode IT1 is connected to the third portion SCO3 via a contact hole CH2.

[0101] The electrode IT1 is made of a transparent conductive material such as indium tin oxide, indium zinc oxide, etc. The contact hole CH2 does not overlap with the light-shielding layer BM. In other words, the contact hole CH2 is disposed within the opening region OP.

[0102] Fig. 10 is a cross-sectional view showing the cross-sectional structure of the display device taken along line B1-B2 shown in Fig. 9. The display device DSP2 shown in Fig. 9 has the same structure as the display device DSP2 shown in Fig. 8 from the base material BA1 to the insulating layer PAS1. However, the semiconductor layer is a semiconductor layer SCO that is an oxide semiconductor layer.

[0103] A contact hole CH1 is provided in the insulating layer PAS1 and the insulating layer GI, similarly to Fig. 8. The signal line SL is in contact with the first portion SCO1 of the semiconductor layer SCO via the contact hole CH1 provided in the insulating layer GI and the insulating layer PAS1.

[0104] An insulating layer PAS2 is provided to cover the insulating layer PAS1, the first portion SCO1 and second portion SCO2 of the semiconductor layer SCO, the signal line SL, and the insulating layer UC. A contact hole CH2 is provided in the insulating layer GI, the insulating layer PAS1, and the insulating layer PAS2, reaching the third portion SCO3 of the semiconductor layer SCO. The insulating layer PAS2 also covers the contact hole CH1.

[0105] An electrode IT1 is provided on the insulating layer PAS2. The electrode IT1 extends from a region on the insulating layer PAS2 along the side surface of the insulating layer PAS2 and is in contact with the third portion SCS3 of the semiconductor layer SCS via a contact hole CH2.

[0106] An insulating layer PLL is provided to cover the electrode IT1 and the insulating layer PAS2. The insulating layer PLL has an opening region OPH that reaches the electrode IT1 on the semiconductor layer SCO and the gate electrode GE. The opening region OPH corresponds to the opening region OPR1 in FIG. 5.

[0107] Fig. 11 is a plan view showing an example of a schematic configuration of a display device of embodiment 2. Fig. 12 is a plan view showing only a contact hole CH1 among the components of Fig. 11. In Fig. 11, subpixels SP (pixels PX) in a display area DA are arranged in a matrix along a first direction X and a second direction Y. A color filter CF is provided for each subpixel SP (pixel PX). For example, the color filter CF is formed on a substrate SUB2.

[0108] 11 and 12, the contact hole CH1 is provided across a plurality of subpixels SP. In the entire display area DA, the contact hole CH1 has a rectangular shape along the first direction X.

[0109] Fig. 13 is a plan view of a display device of Comparative Example 3. Fig. 14 is a plan view showing only the contact hole CH1 among the components of Fig. 13. In Fig. 13, similar to Fig. 11, subpixels SP (pixels PX) in the display area DA are arranged in a matrix along the first direction X and the second direction Y. A switching element SWr and a color filter CF are provided for each subpixel SP (pixel PX).

[0110] 13 and 14, the contact hole CHR1 is provided in each of the subpixels SP so as to overlap the semiconductor layer SCOR. The contact hole CHR1 is provided at the boundary between adjacent subpixels SP, and it can be said that one contact hole CHR1 is provided for each of the subpixels SP.

[0111] In the display device DSPr3 shown in Figures 13 and 14, similar to the display device DSPr1 shown in Figures 3 and 4, depolarization occurs due to the portion of the contact hole CHR1 that does not overlap with the signal line SL, etc., resulting in a decrease in contrast.

[0112] In the display device DSP2 of the second embodiment, the extension direction of the contact hole CH1 is parallel to the polarization axis DX or the polarization axis DY. Therefore, depolarization due to the contact hole CH1 does not occur. Therefore, it is possible to improve the contrast of the display device DSP2.

[0113] Furthermore, the display device DSP2 of Embodiment 2 is advantageous in that the taper angle of the sidewall of the contact hole CH2 is smaller than that of Comparative Example 3. Fig. 15 is a cross-sectional view showing the cross-sectional structure of the display device taken along line C1-C2 shown in Fig. 9. Fig. 16 is a cross-sectional view showing the cross-sectional structure of the display device taken along line D1-D2 shown in Fig. 13.

[0114] The display device DSP2 shown in Fig. 15 has a substrate BA1, an insulating layer UC, a semiconductor layer SCO, a signal line SL, an insulating layer PAS2, and an electrode IT1. The substrate BA1, the insulating layer UC, and the insulating layer PAS2 are stacked in this order along the third direction Z. The signal line SL is provided on the insulating layer UC via a contact hole CH1. The insulating layer PAS1 is provided to cover the insulating layer UC and the signal line SL. The contact hole CH2 is provided in the insulating layer PAS2.

[0115] The semiconductor layer SCO is provided on the insulating layer UC and at the bottom of the contact hole CH2. The electrode IT1 covers the contact hole CH2 and is in contact with the semiconductor layer SCO. The taper angle of the sidewall of the contact hole CH2 provided in the insulating layer PAS2 is defined as θ.

[0116] The display device DSPr3 shown in Fig. 16 has a substrate BA1, an insulating layer UC, a semiconductor layer SCOR, an insulating layer GI, a signal line SL, an insulating layer PAS1, an insulating layer PAS2, and an electrode IT1. The substrate BA1, the insulating layer UC, the insulating layer GI, the insulating layer PAS1, and the insulating layer PAS2 are stacked in this order along the third direction Z. The signal line SL is provided on the insulating layer PAS1. The insulating layer PAS2 is provided to cover the insulating layer PAS1 and the signal line SL. A contact hole CH2 is provided in the insulating layer GI, the insulating layer PAS1, and the insulating layer PAS2.

[0117] The semiconductor layer SCOR is provided on the insulating layer UC and at the bottom of the contact hole CH2. The electrode IT1 covers the contact hole CH2 and is in contact with the semiconductor layer SCOR. The taper angle of the sidewall of the contact hole CH2 provided in the insulating layers GI, PAS1, and PAS2 is defined as θr.

[0118] The contact hole CH2 of the second embodiment (see FIG. 15 ) is provided only in the insulating layer PAS2, whereas the contact hole CH2 of the third comparative example (see FIG. 16 ) is provided in the insulating layers GI, PAS1, and PAS2. When the taper angle θ and the taper angle θr are equal (θ=θr), the contact hole CH2 of the third comparative example has a shorter distance from the sidewall of the contact hole CH2 to one signal line SL than the contact hole CH2 of the second embodiment by a distance that satisfies (thickness of the insulating layer GI+thickness of the insulating layer PAS1) / tan θr. In other words, the contact hole CH2 of the second embodiment can increase the distance from the sidewall of the contact hole CH2 to one signal line SL by a distance that satisfies (thickness of the insulating layer GI+thickness of the insulating layer PAS1) / tan θr. Therefore, in the second embodiment, the increased distance reduces the risk of a short circuit between the signal line SL and the electrode IT1 and the disconnection of the electrode IT1 due to the high taper.

[0119] <Configuration Example 1 of Embodiment 2> Fig. 17 is a plan view showing another configuration example of the display device according to embodiment 2. In the configuration example shown in Fig. 17, in contrast to the configuration example shown in Fig. 11, a color filter is provided on the array substrate side as in Fig. 5.

[0120] 17, a color filter CF is provided so as to overlap an aperture region OP of a subpixel SP (pixel PX). The color filter CF has a rectangular shape in a plan view. Of the sides of the rectangle, the sides parallel to the second direction Y overlap adjacent signal lines SL. Of the sides of the rectangle, the sides parallel to the first direction X are disposed between the scanning lines GL and the light-shielding layer LS.

[0121] Fig. 18 is a cross-sectional view showing the cross-sectional structure of the display device taken along line E1-E2 shown in Fig. 17. Fig. 18 shows the cross-sectional structure of two subpixels SP (pixels PX) arranged side by side along a direction parallel to the second direction Y.

[0122] A light-shielding layer LS is provided on a base material BA1. An insulating layer UC is provided to cover the base material BA1 and the light-shielding layer LS. A semiconductor layer SCO is provided on the insulating layer UC. An insulating layer GI is provided on the semiconductor layer SCO. The insulating layer GI does not cover the entire semiconductor layer SCO, and part of the semiconductor layer SCO is exposed from the insulating layer GI.

[0123] The semiconductor layer SCO shown in Fig. 18 includes a part of the third portion SCO3 and a part of the second portion SCO2. The third portion SCO3 is located on the left side of the paper in Fig. 18, and the second portion SCO2 is located on the right side of the paper. The parts of the semiconductor layer SCO exposed from the insulating layer GI described above are the part of the third portion SCO3 at the right end of the paper and the part of the second portion SCO2 at the left end of the paper.

[0124] The scanning lines GL are provided on the semiconductor layers SCO with the insulating layers GI sandwiched therebetween. An insulating layer PAS1 is provided to cover the insulating layers GI and the scanning lines GL. The insulating layer PAS1 does not contact the semiconductor layers SCO.

[0125] The insulating layer PAS1 and the insulating layer GI are provided with a contact hole CH1 extending in a direction parallel to the first direction X. In FIG. 18, the contact hole CH1 is provided between the ends of the insulating layers GI of two adjacent subpixels SP.

[0126] An insulating layer PAS2 is provided to cover the insulating layer PAS1 and a portion of the exposed semiconductor layer SCO. The insulating layer PAS2 covers a portion of the second portion SCO2 of the semiconductor layer SCO at the right edge of the page. On the other hand, the insulating layer PAS2 does not cover a portion of the third portion SCO3 of the semiconductor layer SCO at the left edge of the page, and a contact hole CH2 is formed in that portion.

[0127] An electrode IT1 is provided on the insulating layer PAS2. The electrode IT1 extends from a region on the scan line GL to the second portion SCO2. The electrode IT1 is in contact with the third portion SCO3 of the semiconductor layer SCO through a contact hole CH2.

[0128] A color filter CF is provided on the insulating layer PAS2 and the electrode IT1. The color filter CF is provided independently for each subpixel SP.

[0129] An insulating layer PLL is provided on the color filters CF. An opening region OPH where the color filters CF and the insulating layer PLL are not provided is located above the scanning lines GL.

[0130] The distance along the third direction Z from the boundary between the semiconductor layer SCO and the insulating layer GI to the boundary between the insulating layer PAS1 and the insulating layer PAS2 is defined as thickness t1. The distance along the third direction Z from the boundary between the electrode IT1 and the color filter CF to the surface of the insulating layer PLL is defined as thickness t2.

[0131] Increasing the thickness of the color filter CF improves color reproduction. However, there are limitations to increasing the thickness due to the manufacturing method. More specifically, there are limitations on the thickness t2 due to the manufacturing method.

[0132] In the display device DSP21 shown in this configuration example, by providing the contact hole CH1 across the subpixel SP, it is possible to increase the thickness of the color filter CF by the thickness t1 without changing the thickness t2.

[0133] In this configuration example, in addition to the effects described in the first and second embodiments, it is possible to obtain an effect of improving color reproducibility. This configuration example also provides the same effects as those of the first and second embodiments described above.

[0134] In the present disclosure, the substrate SUB1 and the substrate SUB2 are also referred to as the first substrate and the second substrate, respectively, and the polarizers PL1 and PL2 are also referred to as the first polarizer and the second polarizer, respectively.

[0135] 8 are also referred to as the first insulating layer, the second insulating layer, and the third insulating layer, respectively. The contact hole CH1 and the opening region OPH are also referred to as the first contact hole and the opening region, respectively.

[0136] In this disclosure, the insulating layer GI, insulating layer PAS1, insulating layer PAS2, and insulating layer PLL shown in Figure 10 are also referred to as the first insulating layer, second insulating layer, third insulating layer, and fourth insulating layer, respectively. The contact holes CH1, contact holes CH2, and opening region OPH are also referred to as the first contact hole, second contact hole, and opening region, respectively. The electrode IT1 is also referred to as a transparent electrode.

[0137] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0138] CH1...contact hole, CH2...contact hole, DE...drain electrode, DSP...display device, GL...scanning line, PLL...insulating layer, IT1...electrode, PAS1...insulating layer, PAS2...insulating layer, PL1...polarizer, PL2...polarizer, PX...pixel, SCO...semiconductor layer, SCO1...first portion, SCO2...second portion, SCO3...third portion, SCS1...first portion, SCS...semiconductor layer, SCS2...second portion, SCS3...third portion, SL...signal line, SP...subpixel, SW...switching element.

Claims

1. a first substrate; A second substrate; a liquid crystal layer disposed between the first substrate and the second substrate; Equipped with The first substrate is a plurality of scan lines extending along a first direction; a plurality of signal lines extending along a second direction intersecting the first direction; a plurality of pixels provided at intersections of the plurality of scanning lines and the plurality of signal lines; A plurality of switching elements provided in the plurality of pixels; Equipped with Each of the plurality of switching elements a semiconductor layer; one of the plurality of scanning lines provided on the semiconductor layer; one signal line among the plurality of signal lines contacting a first portion of the semiconductor layer; a first insulating layer provided between the third portion of the semiconductor layer and the one scan line; a second insulating layer covering the first insulating layer and the one scan line; a first contact hole provided in the first insulating layer and the second insulating layer and reaching the first portion of the semiconductor layer; Equipped with the one signal line contacts the first portion of the semiconductor layer through the first contact hole; The display device, wherein the first contact hole is provided across the plurality of pixels and has a rectangular shape in a plan view.

2. The display device according to claim 1 , wherein the semiconductor layer is made of polycrystalline silicon.

3. a drain electrode in contact with the third portion of the semiconductor layer; a third insulating layer provided to cover the signal line, the drain electrode, and the semiconductor layer; an opening region provided on the scanning line and in the third insulating layer; The display device of claim 1 further comprising:

4. the third portion of the semiconductor layer is parallel to the one signal line and intersects the scanning line; the semiconductor layer has a second portion that connects the first portion and the third portion and is parallel to the scanning line; The display device according to claim 1 , wherein the second portion is located within the first rectangular contact hole.

5. a first substrate; A second substrate; a liquid crystal layer disposed between the first substrate and the second substrate; Equipped with The first substrate is a plurality of scan lines extending along a first direction; a plurality of signal lines extending along a second direction intersecting the first direction; a plurality of pixels provided at intersections of the plurality of scanning lines and the plurality of signal lines; A plurality of switching elements provided in the plurality of pixels; Equipped with Each of the plurality of switching elements a semiconductor layer; one of the plurality of scanning lines provided on the semiconductor layer; one signal line among the plurality of signal lines contacting a first portion of the semiconductor layer; a first insulating layer provided between the third portion of the semiconductor layer and the one scan line; a second insulating layer covering the first insulating layer and the one scan line; a first contact hole provided in the first insulating layer and the second insulating layer and reaching a first portion of the semiconductor layer; a third insulating layer provided to cover the second insulating layer, the first portion of the semiconductor layer, and the one signal line; a second contact hole provided in the first insulating layer, the second insulating layer, and the third insulating layer; Equipped with the one signal line contacts the first portion of the semiconductor layer through the first contact hole; the first contact hole is provided across the plurality of pixels so as to pass through the plurality of signal lines, and has a rectangular shape in a plan view.

6. The display device according to claim 5 , wherein the semiconductor layer is formed of an oxide semiconductor.

7. a transparent electrode in contact with the third portion of the semiconductor layer through the second contact hole; a fourth insulating layer provided to cover the transparent electrode and the third insulating layer; an opening region provided on the scanning line and in the fourth insulating layer; The display device of claim 5 further comprising:

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