Signal processing device, method for processing signal, and display device

Abstract

To provide a signal processing device capable of suppressing generation of ringing itself and further improving gradation reproducibility.SOLUTION: A step waveform data generation unit (409) generates step waveform generation data having, for each horizontal scanning period, the data value corresponding to each display gradation and the temporal length corresponding to the number of pixels of each display gradation, for generating a step waveform signal, based on a gradation value of each display gradation and a start time of a display gradation period for each display gradation. A gradation conversion video data generation unit (410) generates gradation conversion video data, which is video data obtained by converting pixel values of the pixels in each horizontal scanning period of video data into dispersed pixel values corresponding to selection periods corresponding to the display gradations.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a signal processing device, a signal processing method, and a display device. [Background technology]

[0002] The display device includes a display device and a signal processing device that processes video data input to the display device. An example of the display device is a liquid crystal device. The display device can display a gradation of an image based on the video data by driving the display device based on gradation data for each pixel. The display device is provided with analog switches corresponding to the number of pixels in the horizontal direction. The display device turns off the analog switches at the timing when the gradation data for each pixel matches the counter value within a horizontal scanning period, and applies to each pixel a voltage value determined by a ramp waveform signal at the matching timing.

[0003] Patent Document 1 describes that when many analog switches of pixels having the same gray level are turned off simultaneously within a horizontal scanning period, a large load fluctuation occurs in the ramp waveform signal, causing ringing. Patent Document 1 also describes a method for suppressing deterioration in gray level reproducibility due to the occurrence of ringing. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2020-173439 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, the frame rate of video data has been increasing. When the frame rate is 120 Hz, one horizontal scanning period is half that of when the frame rate is 60 Hz. If the number of analog switches that are turned off simultaneously is the same, the ringing period during which ringing occurs in the ramp waveform signal is the same when the display device displays video data with a frame rate of 60 Hz and when the display device displays video data with a frame rate of 120 Hz. Therefore, as the frame rate of video data increases, the ringing period becomes longer relative to the horizontal scanning period, and the deterioration of gradation reproducibility due to the ringing becomes more problematic.

[0006] The method for suppressing deterioration of gradation reproducibility due to the occurrence of ringing, which is described in Patent Document 1, is insufficient in terms of the effect of suppressing deterioration of gradation reproducibility when displaying video data at a high frame rate. There is a demand for further improvement in gradation reproducibility by suppressing the occurrence of ringing itself.

[0007] An object of the present invention is to provide a signal processing device, a signal processing method, and a display device that can suppress the occurrence of ringing itself and further improve tone reproducibility. [Means for solving the problem]

[0008] The present invention includes a grayscale histogram generating unit that generates a grayscale histogram indicating the number of pixels for each display grayscale in each horizontal scanning period of input video data; a non-selection period setting unit that sets a non-selection period corresponding to each display grayscale based on a settling time from the start time of each step when a voltage value corresponding to each display grayscale increases in a step-like manner to the settling time when the voltage value of each step falls within an allowable range of a target value in a step waveform signal that is an analog signal in which a voltage value increases in a step-like manner corresponding to each display grayscale in each horizontal scanning period; and a non-selection period setting unit that sets a non-selection period corresponding to each display grayscale based on the grayscale histogram, a non-selection total period that is the sum of the non-selection periods corresponding to each display grayscale in each horizontal scanning period, and a selection total period that is the total number of grayscales of the video data minus the non-selection total period. a display gradation period start time acquisition unit that acquires a start time of the display gradation period for each of the display gradations based on the display gradation period, which is a period combining the non-selection period and the selection period; a step waveform generation data generation unit that generates step waveform generation data for generating the step waveform signal based on the gradation value of each of the display gradations and the start time of the display gradation period for each of the display gradations; and a gradation conversion video data generation unit that generates gradation conversion video data, which is video data obtained by converting the pixel values ​​of each pixel in each of the horizontal scanning periods of the video data into pixel values ​​that are distributed so as to correspond to the selection periods corresponding to each of the display gradations.

[0009] The present invention provides a display device comprising: the above-mentioned signal processing device; a step waveform signal generation circuit that converts the step waveform generation data into an analog signal to generate the step waveform signal; and a display device having a plurality of pixels and generating a gradation drive voltage for each of the pixels based on the gradation-converted video data and the step waveform signal.

[0010] The present invention generates a grayscale histogram indicating the number of pixels for each display grayscale in each horizontal scanning period of input video data, and in a step waveform signal which is an analog signal in which a voltage value rises in a step manner corresponding to each display grayscale present in each horizontal scanning period, sets a non-selection period corresponding to each display grayscale based on a settling time from the start time of each step when the voltage value corresponding to each display grayscale increases in a step manner until the voltage value of each step falls within an allowable range of a target value, and a selection period corresponding to each display gradation following the non-selection period based on a non-selection total period obtained by summing up all selection periods and all non-selection total periods, and a selection total period obtained by subtracting the non-selection total period from the total number of gradations of the video data; a start time of the display gradation period for each display gradation is obtained based on a display gradation period which is a period obtained by combining the non-selection period and the selection period; and a signal processing method for generating gradation-converted video data, which is video data obtained by converting the pixel values ​​of each pixel in each horizontal scanning period of the video data into pixel values ​​distributed so as to correspond to the selection periods corresponding to each display gradation. [Effects of the Invention]

[0011] According to the signal processing device, signal processing method, and display device of the present invention, the occurrence of ringing itself can be suppressed, and tone reproducibility can be further improved. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing the configuration of a display device according to an embodiment. [Figure 2] FIG. 2 is a time chart showing a schematic operation of the display device according to one embodiment. [Figure 3A] FIG. 3A is a waveform diagram showing step waveform generating data and a step waveform signal used when a display device according to an embodiment determines a voltage value to be applied to each pixel. [Figure 3B]FIG. 3B is a waveform diagram showing ramp waveform control data and ramp waveform signals used when a typical display device determines the voltage value to be applied to each pixel. [Figure 4] FIG. 4 is a block diagram illustrating a signal processing device according to an embodiment. [Figure 5] FIG. 5 is a diagram showing a video format of video data input to a signal processing device according to an embodiment. [Figure 6] FIG. 6 is a diagram showing an example of a frame of video data input to a signal processing device according to an embodiment. [Figure 7] FIG. 7 is a diagram showing a gray scale histogram generated by the gray scale histogram generating unit included in the signal processing device according to one embodiment on the j line of the frame shown in FIG. [Figure 8] FIG. 8 is a waveform diagram showing a step waveform signal generated based on the gradation histogram shown in FIG. [Figure 9] FIG. 9 is a characteristic diagram showing the relationship between the amount of change in the step waveform generation data and the time it takes for the voltage value of the step waveform signal to stabilize. [Figure 10] FIG. 10 is a characteristic diagram showing the relationship between the amount of change in the step waveform generation data and the settling time. [Figure 11] FIG. 11 is a diagram showing the operation of the tone-converted video data generating unit included in the signal processing device according to one embodiment in association with step waveform generating data generated based on the tone histogram shown in FIG. [Figure 12] FIG. 12 is a diagram showing how the tone-converted video data generating unit performs tone conversion on video data to generate tone-converted video data. DETAILED DESCRIPTION OF THE INVENTION

[0013] A display device according to one embodiment will be described with reference to FIG. 1. The display device 1 according to one embodiment includes a timing generating circuit 2, a step waveform signal generating circuit 3, a signal processing device 4, and a display device 5. Typically, the display device 5 is a liquid crystal device, and the display device 1 is a liquid crystal display device. However, the display device 5 is not limited to a liquid crystal device, and the display device 1 is not limited to a liquid crystal display device. The display device 5 includes a display pixel section 50, a horizontal scanning circuit 51, and a vertical scanning circuit 52. The display pixel section 50 has a plurality of (x×y) pixels 53 arranged in a matrix at each intersection of a plurality of (x) column data lines D (D1 to Dx) arranged in the horizontal direction and a plurality of (y) row scanning lines G (G1 to Gy) arranged in the vertical direction.

[0014] The time chart shown in Fig. 2 shows a schematic operation of the display device 1. In Fig. 2, (a) shows the horizontal synchronization signal SHD input to the signal processing device 4, (b) shows the gradation-converted video data SVDS obtained by gradation-converting the video data VDS input to the signal processing device 4, (c) shows the clock signal CLK input to the signal processing device 4 and the display device 5, (d) shows the gradation data DL generated by the horizontal scanning circuit 51, and (e) shows the counter clock signal CCLK generated by the timing generating circuit 2.

[0015] (f) shows the gradation counter value QD generated by the horizontal scanning circuit 51, (g) shows the all-pixel reset signal SELRST generated by the timing generating circuit 2, and (h) shows the coincidence pulse signal AP generated by the horizontal scanning circuit 51. (i) shows an example of the step waveform signal VSTP generated by the step waveform signal generating circuit 3, and (j) shows two examples of the sampling period and the hold period during which the horizontal scanning circuit 51 samples and holds the step waveform signal VSTP.

[0016] A typical display device uses a ramp waveform signal VREF, which is an analog signal whose voltage value rises from black level to white level during each horizontal scanning period, and is generated based on ramp waveform control data RCD, which is a digital signal whose data value increases sequentially as shown in Figure 3B. A typical display device applies to each pixel a voltage value determined by the ramp waveform signal VREF at the timing when the grayscale data of each pixel matches the counter value during the horizontal scanning period.

[0017] In a display device 1 according to one embodiment, a signal processing device 4 generates step waveform generation data SCD, which is a digital signal whose data value increases in steps as shown in Fig. 3A. Based on the step waveform generation data SCD, a step waveform signal generation circuit 3 generates a step waveform signal VSTP, which is an analog signal whose voltage value increases in steps. In the step waveform generation data SCD, Gd1 to Gd3 indicate display grayscales (pixel values) present within a horizontal scanning period, and H1 to H3 indicate time lengths corresponding to the number of pixels of the display grayscale present within the horizontal scanning period. Here, a case is shown in which three pixel values ​​representing display grayscales Gd1 to Gd3 exist within the horizontal scanning period.

[0018] When the voltage in the step waveform signal VSTP rises, it does not suddenly reach a voltage value corresponding to the display gradations Gd1 to Gd3. Instead, it takes a certain amount of time for the voltage to reach a voltage value corresponding to the display gradations Gd1 to Gd3 at the rise of each step. The rate of change in the slope of the voltage value at this time is called the slew rate. The time it takes for the voltage to fall within the allowable range of the voltage value (target value) corresponding to each display gradation at the rise of each step is determined by the slew rate, and this time is called the settling time. The display device 5 applies to each pixel an analog voltage value determined by the step waveform signal VSTP at the timing when the gradation data of each pixel matches the counter value within the horizontal scanning period.

[0019] Video data VDS, which is a digital signal, a horizontal synchronization signal SHD, a vertical synchronization signal SVD, and a clock signal CLK that are synchronized with the video data VDS are input to the signal processing device 4. The signal processing device 4 converts the input video data VDS into gradation-converted video data SVDS and supplies it to the horizontal scanning circuit 51 of the display device 5. Details of how the signal processing device 4 performs gradation conversion on the video data VDS to generate the gradation-converted video data SVDS will be described later.

[0020] The signal processing device 4 generates step waveform generation data SCD for holding grayscale data based on the video data VDS, horizontal synchronization signal SHD, and clock signal CLK, and supplies the data to the step waveform signal generation circuit 3. A specific configuration example of the signal processing device 4 and a signal processing method executed by the signal processing device 4 will be described later.

[0021] A clock signal CLK, a horizontal synchronization signal SHD, and a vertical synchronization signal SVD are input to the timing generation circuit 2. Based on the clock signal CLK and the horizontal synchronization signal SHD, the timing generation circuit 2 generates a counter clock signal CCLK, a counter reset signal CRST, a latch pulse signal SL, and an all-pixel reset signal SELRST, and supplies them to the horizontal scanning circuit 51. The timing generation circuit 2 supplies a grayscale counter clock signal ACLK to the step waveform signal generation circuit 3. Based on the clock signal CLK, the horizontal synchronization signal SHD, and the vertical synchronization signal SVD, the timing generation circuit 2 generates a row selection signal VCK and a vertical reset signal VST, and supplies them to the vertical scanning circuit 52.

[0022] The step waveform signal generating circuit 3 generates a step waveform signal VSTP as shown in Fig. 3A based on the step waveform generating data SCD and the gradation counter clock signal ACLK, and supplies it to the horizontal scanning circuit 51. The number of steps in the step waveform signal VSTP is determined by the number of display gradations present in each horizontal scanning period, and the time length of each step is determined by the number of pixels of each display gradation.

[0023] The horizontal scanning circuit 51 is connected to pixels 53 of the display pixel section 50 via column data lines D1 to Dx. For example, the column data line D1 is connected to y pixels 53 in the first column of the display pixel section 50. The column data line D2 is connected to y pixels 53 in the second column of the display pixel section 50, and the column data line Dx is connected to y pixels 53 in the xth column of the display pixel section 50. The horizontal scanning circuit 51 has a shift register 61, a latch circuit 62, a counter circuit 63, x comparator circuits 64 (641 to 64x), and x selection circuits 65 (651 to 65x).

[0024] The gradation-converted video data SVDS and a clock signal CLK are input to the shift register 61. Based on the clock signal CLK, the gradation-converted video data SVDS is sequentially input to the shift register 61 as gradation data DL corresponding to x number of pixels 53 on one row scanning line G in units of one horizontal scanning period.

[0025] The gradation data DL has m bits of gradation data. For example, if m=8 bits, the display device 5 can display 256 gradations for each pixel 53. The shift register 61 shifts the m bits of gradation data input sequentially in parallel. For example, if the display pixel unit 50 supports full high-definition television (x=1920), the shift register 61 shifts the m bits of gradation data corresponding to each of the 1920 pixels 53 during one horizontal scanning period.

[0026] A latch pulse signal SL is input to the latch circuit 62 during a horizontal blanking period. Based on the latch pulse signal SL, the latch circuit 62 retrieves grayscale data DL corresponding to x pixels 53 on one row scanning line G from the shift register 61 during one horizontal scanning period. The latch circuit 62 holds the retrieved m-bit grayscale data corresponding to each of the x pixels 53 for the next horizontal scanning period.

[0027] The counter circuit 63 receives a counter clock signal CCLK and a counter reset signal CRST from the timing generating circuit 2. The counter circuit 63 sequentially counts up an m-bit gradation counter value QD based on the counter clock signal CCLK. As a result, the counter circuit 63 counts up 2 m-bit gradation counter values ​​QD every horizontal scanning period. m Gradation counter value QD(0~(2 m −1)) to the comparator circuits 64 (641 to 64x). Therefore, the counter circuit 63 supplies each comparator circuit 64 with a gradation counter value QD having the same number of gradations as the gradation data.

[0028] The comparator circuits 64 (641 to 64x) correspond to the respective column data lines D (D1 to Dx). Each comparator circuit 64 receives a grayscale counter value QD from the counter circuit 63 and receives grayscale data DL corresponding to each pixel 53 from the latch circuit 62. The comparator circuits 64 compare the grayscale data DL with the grayscale counter value QD bit by bit, and when the two match, generate a match pulse signal AP and supply it to the corresponding selection circuit 65.

[0029] The selection circuits 65 (651 to 65x) correspond to the comparator circuits 64 (641 to 64x). The selection circuits 65 (651 to 65x) are connected to the respective column data lines D (D1 to Dx). For example, the selection circuit 651 is connected to y pixels 53 in the first column of the display pixel section 50 via the column data line D1. The selection circuit 652 is connected to y pixels 53 in the second column of the display pixel section 50 via the column data line D2, and the selection circuit 65x is connected to y pixels 53 in the xth column of the display pixel section 50 via the column data line Dx.

[0030] Each selection circuit 65 receives the coincidence pulse signal AP from the corresponding comparator circuit 64. Each selection circuit 65 also receives the step waveform signal VSTP from the step waveform signal generation circuit 3 and the all-pixel reset signal SELRST from the timing generation circuit 2.

[0031] The selection circuit 65 has analog switches for starting and ending sampling of the step waveform signal VSTP. When the all-pixel reset signal SELRST is input from the timing generation circuit 2 during one horizontal blanking period, each selection circuit 65 turns on its analog switch and starts sampling of the step waveform signal VSTP, as shown in (j) of Figure 2. The selection circuit 65 turns off its analog switch at the rising edge of the match pulse signal AP, ending sampling, and holds the voltage value of the step waveform signal VSTP during the period of the match pulse signal AP.

[0032] 2(j) shows an example in which the match pulse signal AP is generated at the second step within a certain horizontal scanning period, and then at the third step within the following horizontal scanning period. If the match pulse signal AP is generated at the second step, the selection circuit 65 holds the voltage value at the second step, and if the match pulse signal AP is generated at the third step, the selection circuit 65 holds the voltage value at the third step. The sampling period is the period from when the selection circuit 65 starts sampling the step waveform signal VSTP to the falling edge of the match pulse signal AP, and the hold period is the period from the falling edge of the match pulse signal AP to when the all-pixel reset signal SELRST is input.

[0033] The selection circuit 65 samples the step waveform signal VSTP based on the timing of the coincidence pulse signal AP in units of one horizontal scanning period, and supplies the sampled voltage to the corresponding column data line D as the grayscale drive voltage VID.

[0034] The vertical scanning circuit 52 is connected to the pixels 53 of the display pixel section 50 via row scanning lines G (G1 to Gy). For example, the row scanning line G1 is connected to x number of pixels 53 in the first row of the display pixel section 50. The row scanning line G2 is connected to x number of pixels 53 in the second row of the display pixel section 50, and the row scanning line Gy is connected to x number of pixels 53 in the yth row of the display pixel section 50.

[0035] The vertical scanning circuit 52 receives a row selection signal VCK and a vertical reset signal VST from the timing generating circuit 2. The vertical scanning circuit 52 sequentially supplies the row selection signal VCK, which sequentially selects the row scanning lines G (G1 to Gy) one by one in units of one horizontal scanning period, to the row scanning lines G1 to Gy.

[0036] Each pixel 53 of the display pixel section 50 has a pixel selection transistor 66 and a pixel drive section 67. The pixel selection transistor 66 has a gate connected to a row scanning line G, a drain connected to a column data line D, and a source connected to the pixel drive section 67. A thin film transistor may be used as the pixel selection transistor 66.

[0037] The pixel selection transistor 66 is switched based on a row selection signal VCK input from the vertical scanning circuit 52 via a row scanning line G. When the pixel selection transistor 66 is turned on based on the row selection signal VCK, a gradation drive voltage VID is applied to the pixel drive unit 67.

[0038] The pixel driving section 67 is driven based on the gradation driving voltage VID. As a result, each pixel 53 displays an image in gradation according to the voltage value of the applied gradation driving voltage VID. All pixels 53 of the display pixel section 50 display an image in gradation, allowing the display device 5 to display an image of each frame in gradation.

[0039] 4, the specific configuration and operation of the signal processing device 4 will be described. The signal processing device 4 includes a grayscale histogram generation unit 401, a display grayscale number acquisition unit 402, a non-selection period setting unit 403, a non-selection total period acquisition unit 404, a selection total period acquisition unit 405, and a selection period setting unit 406. The signal processing device 4 also includes a display grayscale period acquisition unit 407, a display grayscale period start time acquisition unit 408, a step waveform generation data generation unit 409, and a grayscale-converted video data generation unit 410. The grayscale-converted video data generation unit 410 includes a delay unit 411.

[0040] 5 shows the video format of the video data VDS input to the signal processing device 4. The video data VDS has an effective video period corresponding to the number of pixels of the display pixel section 50, which is 1920 horizontal pixels and 1080 vertical pixels (number of vertical lines). The number of horizontal pixels of 1920 corresponds to 1920 clocks of the counter clock signal CCLK. The 280 clocks in the horizontal direction outside the effective video period are horizontal blanking periods. The 45 lines in the vertical direction outside the effective video period are vertical blanking periods.

[0041] Suppose a certain frame has an image as shown in Fig. 6. The frame shown in Fig. 6 has regions R1 and R3 of gradation 80, region R2 of gradation 30, and region R4 of gradation 255. Gradations 80, 30, and 255 are display gradations. The operation of the signal processing device 4 during the horizontal scanning period of line j in the frame shown in Fig. 6 will be described as an example. In line j, regions R1 and R3 have 10 pixels, region R2 has 940 pixels, and region R4 has 960 pixels.

[0042] In Fig. 4, the grayscale histogram generation unit 401 generates a grayscale histogram indicating the number of pixels for each display grayscale in each horizontal scanning period of the input video data VDS. Fig. 7 shows a grayscale histogram generated by the grayscale histogram generation unit 401 in the horizontal scanning period of line j of the frame shown in Fig. 6. Since the display grayscale in line j of the frame shown in Fig. 6 is 3, as explained in Fig. 3A, the step waveform signal VSTP may have a voltage waveform having three steps as shown in Fig. 8. The voltage values ​​of the step waveform signal VSTP are assumed to be 0.3 V at grayscale 30, 0.8 V at grayscale 80, and 2.55 V at grayscale 255.

[0043] As described above, when the voltage of each step in the step waveform signal VSTP rises, the voltage value rises to a voltage value corresponding to each display gradation over a settling time determined by the slew rate. As shown in Figure 9, the time until the voltage value of the step waveform signal VSTP stabilizes is proportional to the amount of change in the step waveform generating data SCD. Figure 10 shows the relationship between the amount of change in the step waveform generating data SCD and the settling time when the settling time is converted into the count value of the gradation counter clock signal ACLK. The settling time is proportional to the amount of change in the step waveform generating data SCD. In this way, the settling time is determined by the slew rate characteristics according to the amount of change in the step waveform generating data SCD.

[0044] 4, a gradation histogram generated by a gradation histogram generation unit 401 is input to a display gradation number acquisition unit 402. The display gradation number acquisition unit 402 acquires the display gradation number based on the input gradation histogram. In this example, the display gradation number acquisition unit 402 acquires 3 as the display gradation number. The display gradation number acquisition unit 402 supplies the gradation histogram and the display gradation number to a selection period setting unit 406.

[0045] Grayscale values ​​based on the grayscale histogram generated by the grayscale histogram generator 401 are input to the non-selection period setting unit 403. Here, grayscale values ​​of 30, 80, and 255 are input to the non-selection period setting unit 403. The signal processing device 4 generates step waveform generation data SCD, which is a step waveform of a digital signal, and the step waveform signal generating circuit 3 generates a step waveform signal VSTP, which is an analog signal, based on the step waveform generation data SCD. Therefore, although the step waveform signal VSTP is not generated at the time of signal processing by the signal processing device 4, the non-selection period setting unit 403 sets a non-selection period within the total number of grayscales in each horizontal scanning period as follows, assuming that the step waveform signal VSTP will be generated as a result based on the step waveform generation data SCD. Here, the total number of grayscales is 256.

[0046] As shown in FIG. 8, the non-selection period setting unit 403 sets non-selection periods Ns1 to Ns3 corresponding to each display gradation within the total number of gradations of the step waveform signal VSTP having each display gradation existing in each horizontal scanning period and a temporal length corresponding to the number of pixels of each display gradation within each horizontal scanning period, which is generated based on the gradation histogram. The non-selection periods Ns1 to Ns3 are based on the setting time from the start time of the latest step when the voltage value of the step waveform signal VSTP corresponding to each display gradation increases stepwise from the previous step to the latest step until the voltage value of the latest step falls within the allowable range of the target value. The non-selection period setting unit 403 supplies the non-selection periods Ns1 to Ns3 to the non-selection total period acquisition unit 404 and the display gradation period acquisition unit 407.

[0047] Although the step waveform signal VSTP is not generated in the signal processing device 4, in FIG. 8, the step waveform signal VSTP is shown to facilitate understanding of the non-selection periods Ns1 to Ns3 based on the setting time. In the first step, the gradation increases from gradation 0 to display gradation 30, in the next step, the gradation increases from display gradation 30 to display gradation 80, and in the subsequent step, the gradation increases from display gradation 80 to display gradation 255. Based on FIG. 10, the non-selection period setting unit 403 sets non-selection periods Ns1 to Ns3 represented by the gradation counter value by the clock signal CLK having the relationship Ns1 < Ns2 < Ns3.

[0048] The non-selection periods Ns1 to Ns3 may be the same period as the setting time or a period slightly longer than the setting time. The non-selection periods Ns1 to Ns3 only need to be determined based on the setting time.

[0049] The non-selection total period acquisition unit 404 acquires a non-selection total period by summing up the non-selection periods Ns1 to Ns3. The selection total period acquisition unit 405 acquires a selection total period by subtracting the non-selection total period from the total number of gradations. In FIG. 8, the selection total period is the total time of the selection periods S1, S2, and S3. However, when the non-selection total period acquisition unit 404 acquires the selection total period, only the total time of the selection periods S1, S2, and S3 is obtained, and the selection periods S1, S2, and S3 have not yet been determined. The selection total period acquisition unit 405 supplies the selection total period to the selection period setting unit 406.

[0050] The selection period setting unit 406 sets selection periods S1 to S3 corresponding to each display grayscale, which follow non-selection periods Ns1 to Ns3 corresponding to each display grayscale, within the total number of grayscales based on the grayscale histogram and the selection sum period. The selection periods S1 to S3 preferably have a time length corresponding to the number of pixels of each display grayscale. Since the selection sum period is based on the non-selection sum period, the selection period setting unit 406 sets the selection periods S1 to S3 based on the grayscale histogram, the non-selection sum period, and the selection sum period. The selection period setting unit 406 sets the selection periods S1 to S3 by dividing the selection sum period by a time corresponding to the number of pixels of each display grayscale. The selection period setting unit 406 supplies the selection periods S1 to S3 to the display grayscale period acquisition unit 407.

[0051] The display gradation period acquisition unit 407 acquires display gradation periods Dg1 to Dg3, which are combinations of non-selection periods Ns1 to Ns3 and selection periods S1 to S3 corresponding to each display gradation. The display gradation period start time acquisition unit 408 acquires the start time of the display gradation periods Dg1 to Dg3 for each display gradation, from the lowest display gradation (here, gradation 30) to the highest display gradation (here, gradation 255) present in each horizontal scanning period, based on the display gradation periods Dg1 to Dg3. The start time of the display gradation period Dg1 is the time corresponding to the gradation counter value 0. The start time of the display gradation period Dg2 is the end time of the display gradation period Dg1. The start time of the display gradation period Dg3 is the time when the cumulative time of the display gradation periods Dg1 and Dg2 has elapsed.

[0052] When acquiring the start time of the display gradation period of the display gradation of the third step or later, the display gradation period start time acquisition unit 408 may accumulate the display gradation periods of the display gradation up to the immediately preceding step.

[0053] The step waveform generating data generator 409 generates step waveform generating data SCD shown in FIG. 11 for generating the step waveform signal VSTP based on the grayscale value of each display grayscale and the start time of the display grayscale periods Dg1 to Dg3 for each display grayscale. The step waveform generating data SCD has steps of data values ​​corresponding to each display grayscale within each horizontal scanning period. The data values ​​for obtaining grayscales of 30, 80, and 255 are 30, 80, and 255, respectively. It is preferable that each step in the step waveform generating data SCD has a time length corresponding to the number of pixels of each display grayscale.

[0054] The gradation-converted video data generation unit 410 generates gradation-converted video data SVDS, which is video data obtained by converting the pixel values ​​(multiple identical pixel values) of each pixel constituting each display gradation in each horizontal scanning period of the video data VDS into pixel values ​​that are distributed so as to correspond to the selection periods S1 to S3 in the display gradation periods Dg1 to Dg3 corresponding to each display gradation.

[0055] The gradation histograms obtained in sequence from the first pixel of a line to the next pixel are input to the gradation-converted video data generator 410. The number of pixels with the same pixel value can be determined from the gradation histogram finally obtained at the end of the line. Based on the gradation histogram finally obtained at the end of the line, the gradation-converted video data generator 410 determines the intervals at which to arrange multiple pixel values ​​within the selection periods S1 to S3. The delay unit 411 delays the gradation histograms. The gradation-converted video data generator 410 sequentially arranges identical pixel values ​​based on the gradation histograms in sequence at predetermined intervals.

[0056] 6 and 11, the gradation of the 10 pixels from the 1st pixel to the 10th pixel on line j and the 951st pixel to the 960th pixel is 80. The gradation-converted video data generation unit 410 distributes and arranges the 20 pixels having a pixel value of 80, from the 1st pixel to the 10th pixel on line j and the 951st pixel to the 960th pixel, as pixels having multiple pixel values, at timings within a selection period S2, which is a step of gradation 80. The reason that the same pixel values, for example, pixel values ​​121, 122, and 123 exist in the gradation-converted video data SVDS is because the 1,920 pixels are distributed based on the 256 gradation counter values.

[0057] The gradation of 940 pixels from the 11th pixel to the 950th pixel on the j line is 30. The gradation-converted video data generation unit 410 distributes and arranges the 940 pixels from the 11th pixel to the 950th pixel on the j line, which have a pixel value of 30, as pixels having a plurality of pixel values, at timings within a selection period S1, which is in steps of gradation 30. The gradation of 960 pixels from the 961st pixel to the 1920th pixel on the j line is 255. The gradation-converted video data generation unit 410 distributes and arranges the 960 pixels from the 961st pixel to the 1920th pixel on the j line, which have a pixel value of 30, as pixels having a plurality of pixel values, at timings within a selection period S3, which is in steps of gradation 255.

[0058] As described above, the gradation-converted video data generation unit 410 converts the gradation in the video data VDS on the vertical axis to generate the gradation-converted video data SVDS. As a result, if the horizontal axis represents time t and the vertical axis represents the pixel values ​​of the video data VDS and gradation-converted video data SVDS, the change in pixel value over time t is shown in Figure 12. In the gradation-converted video data SVDS, the pixel values ​​increase linearly.

[0059] 1, when the gradation data DL and gradation counter value QD match, each comparator circuit 64 supplies a match pulse signal AP to the corresponding selection circuit 65. As shown in FIGS. 11 and 12, during a period in which the same pixel value continues in the video data VDS, the gradation-converted video data SVDS is replaced with pixels having multiple pixel values. Therefore, the timing of the match pulse signal AP input to the selection circuit 65 is dispersed, preventing many analog switches in the selection circuit 65 from being turned off simultaneously. Because many analog switches are not turned off simultaneously, the load fluctuation occurring in the step waveform signal VSTP shown in FIG. 8 is slight, and ringing hardly occurs.

[0060] Although consecutive identical pixel values ​​in the video data VDS are replaced with pixels having multiple pixel values ​​in the gradation-converted video data SVDS, the image of each frame displayed on the display pixel section 50 is the same as the image displayed using the video data VDS. This is because the selection circuit 65 supplies, as the gradation drive voltage VID, a voltage value determined based on the step waveform signal VSTP, rather than a voltage value determined based on the ramp waveform signal VREF as shown in Figure 3B, to the corresponding column data line D.

[0061] As described above, the occurrence of ringing itself can be suppressed and gradation reproducibility can be further improved according to the signal processing device 4, the signal processing method executed by the signal processing device 4, and the display device 1 including the signal processing device 4. According to the signal processing device 4, the signal processing method executed by the signal processing device 4, and the display device 1 including the signal processing device 4, even if the ringing period becomes relatively longer with respect to the horizontal scanning period due to the display device 1 displaying video data at a high frame rate, the occurrence of ringing itself is suppressed, so gradation reproducibility is hardly deteriorated.

[0062] 4 may be configured as either hardware or software. In the former case, each unit of the signal processing device 4 may be configured as an integrated circuit, a field programmable gate array (FPGA), or a programmable logic device (PLD).

[0063] The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit of the present invention. [Explanation of symbols]

[0064] 1 Display device 2 Timing generator circuit 3 Step waveform signal generation circuit 4. Signal Processing Device 5 Display Devices 50 Display pixel section 51 Horizontal scanning circuit 52 Vertical scanning circuit 53 pixels 401 Gradation histogram generation unit 402 Display gradation number acquisition unit 403 Non-selection period setting section 404 Non-selection total period acquisition part 405 Selection sum period acquisition unit 406 Selection period setting section 407 Display grayscale period acquisition unit 408 Display grayscale period start time acquisition unit 409 Step waveform generation data generation unit 410 Gradation conversion video data generation unit 411 Delay

Claims

1. a grayscale histogram generating unit that generates a grayscale histogram indicating the number of pixels for each display grayscale in each horizontal scanning period of input video data; a non-selection period setting unit that sets a non-selection period corresponding to each display gradation based on a settling time from a start time of each step when a voltage value corresponding to each display gradation increases in a step-like manner to a settling time until the voltage value of each step falls within an allowable range of a target value, in a step waveform signal that is an analog signal whose voltage value increases in a step-like manner corresponding to each display gradation present in each horizontal scanning period; a selection period setting unit that sets a selection period corresponding to each display grayscale level subsequent to the non-selection period based on the grayscale histogram, a non-selection total period obtained by summing up the non-selection periods corresponding to each display grayscale level in each horizontal scanning period, and a selection total period obtained by excluding the non-selection total period from the total number of grayscale levels of the video data; a display gradation period start time acquisition unit that acquires a start time of the display gradation period for each of the display gradations based on a display gradation period that is a combined period of the non-selection period and the selection period; a step waveform generating data generating section that generates step waveform generating data for generating the step waveform signal based on the gradation value of each of the display gradations and the start time of the display gradation period for each of the display gradations; a gradation-converted video data generating unit that generates gradation-converted video data, which is video data obtained by converting pixel values ​​of each pixel in each horizontal scanning period of the video data into pixel values ​​that are distributed so as to correspond to the selection periods corresponding to each display gradation; A signal processing device comprising:

2. the selection period setting unit sets the selection period corresponding to each of the display gradations, the selection period having a time length according to the number of pixels of each of the display gradations; The step waveform generating data generating section generates step waveform generating data having a time length corresponding to the number of pixels of each display gradation. The signal processing device according to claim 1 .

3. a signal processing device according to claim 1 or 2; a step waveform signal generating circuit that converts the step waveform generating data into an analog signal to generate the step waveform signal; a display device having a plurality of pixels, the display device generating a grayscale driving voltage for each pixel based on the grayscale converted video data and the step waveform signal; A display device comprising:

4. generating a gradation histogram indicating the number of pixels for each display gradation in each horizontal scanning period of the input video data; a step waveform signal which is an analog signal whose voltage value rises in a step manner in response to each display gradation present in each horizontal scanning period, setting a non-selection period corresponding to each display gradation based on a settling time from the start time of each step when the voltage value corresponding to each display gradation increases in a step manner until the voltage value of each step falls within an allowable range of a target value; setting a selection period corresponding to each display gray level following the non-selection period based on the gray level histogram, a non-selection total period obtained by summing up the non-selection periods corresponding to each display gray level in each horizontal scanning period, and a selection total period obtained by subtracting the non-selection total period from the total number of gray levels of the video data; acquiring a start time of the display gradation period for each of the display gradations based on the display gradation period, which is a combined period of the non-selection period and the selection period; Generate gradation-converted video data, which is video data obtained by converting the pixel values ​​of each pixel in each horizontal scanning period of the video data into pixel values ​​distributed so as to correspond to the selection periods corresponding to each display gradation. Signal processing methods.

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