Semiconductor device, serial transmission system, and serial transmission method for data

Abstract

To provide a semiconductor device having a self-detection function which is capable of detecting abnormality of a serial data value after format conversion from parallel data to serial data.SOLUTION: A semiconductor device includes: a parallel-serial conversion circuit 13 having parallel data input 25 and parallel data output 23, the parallel-serial conversion circuit 13 configured to generate a serial data signal including each data value in a set of serial data converted from a set of parallel data in a parallel data signal received with the parallel data input 25 and to provide the serial data signal to the parallel data output 23; a regeneration circuit 15 configured to generate a regeneration signal indicating a set of regenerated parallel data from the serial data signal from the parallel data output 23; and a determination circuit 17 for determining match / mismatch between at least a part of the regeneration signal and at least a part of the set of parallel data signals.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a serial transmission system, and a method for serially transmitting data. [Background technology]

[0002] Patent Document 1 discloses a parallel-to-serial conversion circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-9629 Summary of the Invention [Problem to be solved by the invention]

[0004] A high-speed serial interface is used for data transmission between semiconductor devices, for example, video data transmission. The high-speed serial interface includes a parallel-serial conversion circuit that converts a parallel data format into a serial data format. A transmission circuit of this serial interface receives serial data from the parallel-serial conversion circuit. The transmission circuit transmits the serial data from the parallel-serial conversion circuit in synchronization with a high-speed transfer clock. The transmitted data is received by a reception circuit in synchronization with the transfer clock. While the reception circuit can detect an abnormality in the transfer clock during serial data transmission, it cannot detect an abnormality in the value of the received serial data.

[0005] The parallel-to-serial conversion circuit is located in front of a transmission circuit that operates in synchronization with a serial data transfer clock, and therefore includes a logic circuit that operates at a serial data transfer clock that is faster than the parallel data clock. The logic circuit of the parallel-to-serial conversion circuit operates to generate signals converted from a parallel data sequence to a serial data sequence. Specifically, these logic gate circuits process electrical signals having amplitudes approximately equal to the power supply voltage of the logic gate circuit in synchronization with the transfer clock. Furthermore, such logic gate circuits serially process the signals sequentially converted from parallel data to a serial data sequence.

[0006] The semiconductor device includes a serial data transmission circuit that operates in various environments and sequentially transmits data in synchronization with a serial data transfer clock. What is required is to detect an abnormality in the value of the serial data in such environments, not only in a test mode but also without setting the test mode.

[0007] The present disclosure aims to provide a semiconductor device having a self-detection function capable of detecting an abnormal value in serial data after parallel data has been format-converted into serial data, a serial transmission system including the semiconductor device, and a method for serially transmitting data using the serial transmission system. [Means for solving the problem]

[0008] A semiconductor device according to a first aspect of the present disclosure includes a parallel-serial conversion circuit having a plurality of parallel data inputs configured to receive a set of parallel data signals, and a parallel data output, the parallel-serial conversion circuit configured to generate a plurality of serial data signals each including a plurality of serial data values ​​in a set of serial data converted from the set of parallel data of the parallel data signals received at the parallel data inputs, and to sequentially provide the serial data signals to the parallel data output; a reproduction circuit configured to generate a reproduction signal indicating a set of reproduced parallel data from the serial data signal from the parallel data output; and a determination circuit configured to determine whether at least a portion of the set of reproduction signals matches or does not match at least a portion of the set of parallel data signals.

[0009] A serial transmission system according to a second aspect of the present disclosure includes the semiconductor device described in the first aspect, and a serial transmission receiving device connected to the semiconductor device via a wired serial transmission path.

[0010] A method for serially transmitting data according to a third aspect of the present disclosure includes preparing the serial transmission system described in the second aspect, serially transmitting data from the semiconductor device to the serial transmission receiving device via the serial transmission path, and generating a notification signal when a mismatch is detected in the data converted from the parallel data to the serial data. [Effects of the Invention]

[0011] According to the first aspect, a semiconductor device having a self-detection function capable of detecting an abnormality in the value of serial data after parallel data has been format-converted into serial data can be provided. Also, according to the second aspect, a serial transmission system including the semiconductor device can be provided. Furthermore, according to the third aspect, a method for serially transmitting data using the serial transmission system can be provided. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram schematically showing a semiconductor device according to this embodiment. [Figure 2] FIG. 2 is a diagram schematically illustrating an exemplary semiconductor device according to this embodiment. [Figure 3] FIG. 3 is a diagram showing an exemplary operation timing of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a diagram schematically illustrating an exemplary semiconductor device according to this embodiment. [Figure 5] FIG. 5 is a diagram showing an exemplary operation timing of the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a diagram schematically illustrating a serial transmission system according to an embodiment of the present invention. [Figure 7] FIG. 7 is a diagram illustrating a data transmission method in a serial transmission system according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Identical parts are designated by the same reference numerals and redundant description will be omitted.

[0014] FIG. 1 is a diagram schematically showing a semiconductor device according to this embodiment.

[0015] The semiconductor device 11 includes a parallel-serial conversion circuit 13, a reproduction circuit 15, a decision circuit 17, parallel inputs 19 (19b, 19c, 19d, 19f), and a serial output 21. The serial output 21 provides a serial array signal SSIL.

[0016] The parallel-serial conversion circuit 13 has parallel data outputs 23 (23b, 23c, 23d, 23f) and parallel data inputs 25 (25b, 25c, 25d, 25f). The parallel data inputs 25 (25b, 25c, 25d, 25f) are used to convert the parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>The parallel-to-serial conversion circuit 13 converts the parallel data signal SPLE into a set of serial data ( <d0> 、 <d1> 、 <d2> 、 <d3>) array.

[0017] The regeneration circuit 15 has a number of inputs (15b, 15c, 15d, 15f) which are connected to outputs such as the serial output 21 or the parallel data outputs (23b, 23c, 23d, 23f). The regeneration circuit 15 receives the signal on the output, for example the serial output 21, at its inputs (15b, 15c, 15d, 15f). The regeneration circuit 15 generates a set of regenerated parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>The reproduced signals (SRSIL1, SRSIL2, SRSIL3, SRSIL4) are referred to as "SRSIL" except when referring to individual reproduced signals.

[0018] The determination circuit 17 is configured to determine whether or not at least a part of the set of reproduction signals SRSIL matches or does not match at least a part of the parallel data signal SPLE.

[0019] Specifically, the parallel-serial conversion circuit 13 operates as follows.

[0020] The parallel-serial conversion circuit 13 generates serial data signals (SSIL1 to SSIL4), and each of the serial data signals (SSIL1 to SSIL4) is data ( <d0> ~ <d3>) is included.

[0021] The serial data signals (SSIL1 to SSIL4) are provided at the parallel data outputs (23b, 23c, 23d, 23f) of the parallel-serial conversion circuit 13, respectively. Specifically, the parallel-serial conversion circuit 13 provides the serial data signals (SSIL1 to SSIL4) to the parallel data outputs 23 (23b, 23c, 23d, 23f) so that the serial array signal SSIL is generated on the serial output 21. This provision is made so that the serial array signal SSIL is <d0> <d1> <d2> <d3>) can be included.

[0022] The exemplary parallel-to-serial conversion circuit 13 converts serial data ( <d0> 、 <d1> 、 <d2> 、 <d3>) and selectively provides serial data signals (SSIL1 to SSIL4) in the order of arrangement.

[0023] In addition, the parallel-serial conversion circuit 13 converts the parallel data sequence ( <d0> 、 <d1> 、 <d2> 、 <d3>) parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>) can be held.

[0024] The regenerator 15 receives the serially arranged signal SSIL or the serial data signal SSIL1 to SSIL4 at its inputs (15b, 15c, 15d, 15f) and generates a set of regenerated parallel data ( <d0> ~ <d3>) are generated.

[0025] In the exemplary semiconductor device 11, the parallel data outputs (23b, 23c, 23d, 23f) are connected to the serial output 21. In the exemplary parallel-to-serial conversion circuit 13, the parallel data outputs (23b, 23c, 23d, 23f) are connected to the serial output 21, respectively, during periods corresponding to the order of selective data provision. <d0> 、 <d1> 、 <d2> 、 <d3>) are output. The parallel data outputs (23b, 23c, 23d, 23f) close the signal output during periods other than the period corresponding to the selective providing sequence, and are set to, for example, a high impedance state. The exemplary parallel data outputs 23 (23b, 23c, 23d, 23f) can be connected to the outputs of a ternary (tristate) logic gate.

[0026] Alternatively, the semiconductor device 11 may be provided with a selector circuit, which is connected between the serial output 21 and the parallel-to-serial conversion circuit 13 to convert signals from the parallel data outputs (23b, 23c, 23d, 23f) into a serial data sequence ( <d0> <d1> <d2> <d3>) in that order.

[0027] According to the semiconductor device 11, the parallel-serial conversion circuit 13 converts parallel data ( <d0> ~ <d3>) values ​​are sequentially provided to the parallel data outputs (23b, 23c, 23d, 23f) to generate parallel data ( <d0> ~ <d3>) to generate serial data signals (SSIL1 to SSIL4) and serial array signals SSIL. The regeneration circuit 15 selectively receives the serial data signals (SSIL1 to SSIL4) and serial array signals SSIL from the parallel-to-serial conversion circuit 13 in the order in which they are provided at the inputs (15b, 15c, 15d, 15f). By this selective reception, the regeneration circuit 15 regenerates data ( <d0> 、 <d1> 、 <d2> 、 <d3>) can generate regenerated signals (SRSIL1, SRSIL2, SRSIL3, SRSIL4). The decision circuit 17 is configured to use the regenerated signals SRSIL to decide whether or not there is an abnormality in the signal provided to the serial output 21, for example, the serial array signal SSIL.

[0028] The semiconductor device 11 further includes a serial data transmission circuit 27. The serial data transmission circuit 27 is connected to a serial output 21 that provides the serial array signal SSIL from the parallel-to-serial conversion circuit 13. The serial data transmission circuit 27 includes a transmitter 28 that is connected to an electrode 30, such as a pad electrode, of the semiconductor device 11. The transmitter 28, such as a differential transmitter, generates a differential signal or a single-phase signal from the serial array signal SSIL. The exemplary transmitter 28 provides a serial data differential signal to a transmission path, such as a differential transmission path. The signal amplitude of this serial data differential signal is smaller than the signal amplitude of the digital signal in the parallel-to-serial conversion circuit 13 and the regeneration circuit 15.

[0029] The semiconductor device 11 further includes a clock generation circuit 31. The exemplary clock generation circuit 31 generates a serial data sequence ( <d0> <d1> <d2> <d3>The output timing clocks (ck0 to ck3) do not overlap each other except during transition periods.

[0030] The parallel-serial conversion circuit 13 outputs the respective data ( <d0> 、 <d1> 、 <d2> 、 <d3>) is provided.

[0031] Specifically, the output timing clock (ck0) is the serial data ( <d0>) output period can be specified. The output timing clock (ck1) is the serial data ( <d1>) output period can be specified. The output timing clock (ck2) is the serial data ( <d2>) output period can be specified. The output timing clock (ck3) is the serial data ( <d3>) output period can be specified.

[0032] In the exemplary semiconductor device 11 in which the parallel data output 23 of the parallel-serial conversion circuit 13 is connected to the serial output 21, the exemplary regeneration circuit 15 is connected to the serial output 21. Specifically, the regeneration circuit 15 receives serial data signals (SSIL1 to SSIL4) and serial array signals SSIL at inputs (15b, 15c, 15d, 15f). From the received signals, the regeneration circuit 15 generates regenerated signals SRSIL in synchronization with clock signals associated with output timing clocks (ck0 to ck3). These regenerated signals (SRSIL1 to SRSIL4) correspond to the regenerated parallel data, and specifically, each corresponds to the parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>)

[0033] Accordingly, the regeneration circuit 15 can generate regenerated signals (SRSIL1 to SRSIL4) from the serial data signals (SSIL1 to SSIL4) and the serial array signal SSIL received at the inputs (15b, 15c, 15d, 15f). In the exemplary regeneration circuit 15, the inputs (15b, 15c, 15d, 15f) are parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>)

[0034] Specifically, the regeneration circuit 15 detects whether the output timing clock (ck0) is a serial data ( <d0>The regeneration circuit 15 can be configured to define the capture period of the serial data ( <d1>The regeneration circuit 15 can be configured to define the capture period of the serial data ( <d2>The regeneration circuit 15 can be configured to define the capture period of the serial data ( <d3>) can be configured to define the capture period of each of the reproduction circuits 15. In this way, the clock generation circuit 31 is configured to generate timing clocks such as output timing clocks (ck0 to ck3) so as to define the capture period of each of the reproduction circuits 15.

[0035] In the semiconductor device 11, the parallel-serial conversion circuit 13 can include a plurality of first storage circuits 33 (33b, 33c, 33d, 33f). The first storage circuits 33 can operate in response to output timing clocks (ck0 to ck3). The first storage circuits 33 have respective outputs connected to the parallel data outputs (23b, 23c, 23d, 23f) of the parallel-serial conversion circuit 13. The first storage circuits 33 store serial data ( <d0> 、 <d1> 、 <d2> 、 <d3>) in the order of their arrangement. An exemplary first storage circuit 33 may include a latch circuit or a flip-flop circuit.

[0036] In the semiconductor device 11, the reproduction circuit 15 can include a plurality of second storage circuits 35 (35b, 35c, 35d, 35f). When the inputs (15b, 15c, 15d, 15f) are connected to the serial output 21, the inputs of the second storage circuits 35 are also connected to the serial output 21 accordingly. Specifically, the second storage circuit 35 can be connected to the parallel data outputs (23b, 23c, 23d, 23f) and the serial output 21. The second storage circuit 35 receives signals from the parallel data outputs (23b, 23c, 23d, 23f) in response to timing clocks associated with the output timing clocks (ck0 to ck3). The second storage circuit 35 generates reproduction signals (SRSIL1, SRSIL2, SRSIL3, SRSIL4) from the signals received at the inputs (15b, 15c, 15d, 15f). The reproduced signals (SRSIL1 to SRSIL4) are reproduced parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>) is shown. An exemplary second storage circuit 35 may include a latch circuit or a flip-flop circuit.

[0037] As such, the second storage circuits (35b, 35c, 35d, 35f) respectively provide reproduced signals (SRSIL1 to SRSIL4). These reproduced signals (SRSIL1 to SRSIL4) are parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>) is judged by the judgment circuit 17. The judgment circuit 17 judges the parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>) a decision signal SDET (SDET1, SDET2, SDET3, SDET4).

[0038] In the exemplary semiconductor device 11, the parallel-serial conversion circuit 13 includes a plurality of third storage circuits 37 (37b, 37c, 37d, 37f), and the third storage circuits 37 receive input signals from parallel data inputs (25b, 25c, 25d, 25f). The third storage circuits 37 are arranged in parallel in association with the parallel inputs (19b, 19c, 19d, 19f). The third storage circuits 37 receive input signals from parallel data inputs (25b, 25c, 25d, 25f). <d0> ~ <d3>) for each parallel data ( <d0> ~ <d3>) individual values ​​from parallel inputs (19b, 19c, 19d, 19f). The third storage circuit 37 receives the parallel data ( <d0> ~ <d3>) is synchronized with a capture clock (ck) that defines the timing of capturing individual values, and the parallel data ( <d0> ~ <d3>) value.

[0039] The parallel-serial conversion circuit 13 has parallel data outputs 24 (24b, 24c, 24d, 24f), which are configured to provide respective internal parallel data signals (SPARIT1, SPARIT2, SPARIT3, SPARIT4) from the parallel data inputs (25b, 25c, 25d, 25f). Except when referring to an individual one of the internal parallel data signals (SPARIT1 to SPARIT4), the internal parallel data signals will be referred to as "SPARIT."

[0040] The decision circuit 17 can compare the internal parallel data signal SPARIT from the parallel data output 24 with the reproduced signal SRSIL and decide whether they match or do not match.

[0041] In the exemplary parallel-to-serial conversion circuit 13, the parallel data outputs (24b, 24c, 24d, 24f) can be directly connected to the outputs of the third storage circuit 37 associated with the parallel data inputs (25b, 25c, 25d, 25f), respectively.

[0042] Alternatively, the exemplary parallel-to-serial conversion circuit 13 can include a plurality of fourth storage circuits 39 (39b, 39c, 39d, 39f), with inputs of the fourth storage circuits 39 connected to respective outputs of the third storage circuit 37. The fourth storage circuits 39 have outputs (39g, 39h, 39j, 39k) connected to the parallel data outputs (24b, 24c, 24d, 24f). The data latches of the fourth storage circuits 39 store the parallel data ( <d0> ~ <d3>) is associated with a capture clock (ck) that defines the timing of capturing the data. Specifically, the data latch of the fourth storage circuit 39 stores, for example, parallel data ( <d2> 、 <d3>) is shifted by, for example, half a cycle of the capture clock (ck). The exemplary data latch of the fourth storage circuit 39 is performed at the capture timing according to the inverse clock of the capture clock (ck). The exemplary fourth storage circuit 39 may include a latch circuit or a flip-flop circuit.

[0043] The fourth storage circuit 39 is connected to the second storage circuits (35b, 35c, 35d, 35f) of the reproduction circuit 15, and the second storage circuits (35b, 35c, 35d, 35f) provide reproduction signals (SRSIL1 to SRSIL4) based on the received signals from the fourth storage circuit 39, respectively.

[0044] As such, the decision circuit 17 receives the internal parallel data signal SPARIT and the reproduction signal SRSIL for each input parallel data.

[0045] The decision circuit 17 includes a plurality of decision elements 43, which compare the reproduction signals (SRSIL1 to SRSIL4) with the internal parallel data signals (SPARIT1 to SPARIT4) or determine whether they match or mismatch. The decision elements 43 (decision circuit 17) generate decision signals (SDET1 to SDET4) for each parallel data value.

[0046] An exemplary determiner 43 may include a plurality of exclusive OR gates 41 provided for each of the internal parallel data signals (SPARIT1 to SPARIT4). The exclusive OR gates 41 compare the reproduction signal SRSIL with the internal parallel data signal SPARIT or determine whether they match or do not match.

[0047] In addition, the exclusive OR gate 41 receives the parallel data ( <d0> ~ <d3>) for each of the above-mentioned periods, a determination signal SDET (SDET1 to SDET4) is generated.

[0048] The semiconductor device 11 may include a total determination circuit 45. The total determination circuit 45 receives all of the determination signals SDET for each parallel data value, for example, four determination signals (SDET1 to SDET4), and provides a notification signal SABN to the alert output 20 in response to at least one of these signals indicating "abnormality present."

[0049] As can be understood from the above description, the decision circuit 17 decides whether the signals from the two propagation paths match or do not match.

[0050] One path is associated with the following path: The parallel-serial conversion circuit 13 converts the parallel data ( <d0> ~ <d3>) to generate the internal parallel data signal SPARIT.

[0051] The other path is associated with the following path: The parallel-serial conversion circuit 13 converts the parallel data ( <d0> ~ <d3>) to generate a serial array signal SSIL. The reproduction circuit 15 generates a reproduction signal SRSIL from the serial array signal SSIL.

[0052] The other path converts the parallel data into serial data (serial array signal SSIL) and also reproduces individual parallel data from the serial data (serial array signal SSIL), which causes a data delay when the data is reproduced.

[0053] To compensate for this delay, the decision circuit 17 may be provided with a plurality of fifth storage circuits 47 (47b, 47c, 47d, 47f) for each decider 43. The fifth storage circuits (47b, 47c, 47d, 47f) receive decision signals SDET (SDET1 to SDET4) from the decider 43. The fifth storage circuits 47 may capture each signal at a different timing clock for each bit position of the parallel data. Alternatively, the fifth storage circuit 47 may capture each signal for the first half and second half of a set of parallel data values ​​at a different timing clock. Alternatively, the fifth storage circuit 47 may divide a set of parallel data values ​​into four parts and capture each signal for each quarter at a different timing clock.

[0054] In the exemplary decision circuit 17, this is handled as follows.

[0055] Conversion of 4-bit parallel data: Divide a set of parallel data values ​​into the first and second halves, and consider a delay of at least half a cycle with respect to the output timing clock (ck0 to ck3) (for example, ck3 for the output of ck0; ck3 for the output of ck1; the next ck1 for the output of ck2; the next ck1 for the output of ck3).

[0056] Conversion of 8-bit parallel data: Divide a set of parallel data values ​​into four parts, and consider a delay of at least half a cycle of the output timing clock, just as in the case of conversion of 4-bit parallel data.

[0057] A longer data string can be processed by dividing a set of parallel data values ​​into two bits from the least significant or most significant bits of the parallel data.

[0058] Figure 2 is a diagram schematically illustrating an exemplary semiconductor device according to this embodiment. Figure 3 is a diagram illustrating exemplary operation timing in the semiconductor device shown in Figure 2. In the following description, where possible, the reference numerals used in Figure 1 will be used to omit redundant description.

[0059] 2, in the parallel-serial conversion circuit 13, the third storage circuit 37 can be configured as four flip-flop circuits 51 (51b, 51c, 51d, 51f). The flip-flop circuits (51b, 51c, 51d, 51f) respectively receive parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>) is received. The flip-flop circuits (51b, 51c, 51d, 51f) receive the parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>) is determined in synchronization with the clock (ck).

[0060] The third storage circuit 37 further includes flip-flop circuits 51 (51g, 51h), and the flip-flop circuits (51d, 51f) are connected to the flip-flop circuits (51g, 51h), respectively. <d2> 、 <d3>) is a parallel data ( <d0> 、 <d1>) is transmitted after the flip-flop circuit 51 (51g, 51h). <d2> 、 <d3>) is determined in synchronization with the inverse clock (ck_) of the clock (ck).

[0061] In the parallel-serial conversion circuit 13, the first storage circuit 33 can be configured as four latch circuits 53 (53b, 53c, 53d, 53f). The latch circuits (53b, 53c, 53d, 53f) respectively receive parallel data ( <d0> ~ <d3>) The latch circuits (53b, 53c, 53d, 53f) receive the parallel data ( <d0> ~ <d3>) are synchronized with the clocks (ck0 to ck3) and provided to the parallel data outputs 23 (23b, 23c, 23d, 23f). Specifically, the latch circuits (53b, 53c, 53d, 53f) respectively output the parallel data ( <d0> ~ <d3>) to outputs (23b, 23c, 23d, 23f). In addition, exemplary latch circuits (53b, 53c, 53d, 53f) can close the parallel data outputs (23b, 23c, 23d, 23f) outside the periods of clocks (ck0 to ck3), respectively.

[0062] In the reproduction circuit 15, the second storage circuit 35 can be configured as four flip-flop circuits 55 (55b, 55c, 55d, 55f). The flip-flop circuits (55b, 55c, 55d, 55f) receive serial data ( <d0> ~ <d3>) is taken in. The flip-flop circuits (55b, 55c, 55d, 55f) take in the serial data ( <d0> <d1> <d2> <d3>) are determined in synchronization with the inverted clocks (ck0_, ck1_, ck2_, ck3_) of the clocks (ck0, ck1, ck2, ck3). The flip-flop circuits (55b, 55c, 55d, 55f) are used to determine the parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>) are generated.

[0063] The determination circuit 17 determines whether the internal parallel data signals (n01, n11, n22 (n21), n32 (n31)) from the parallel data outputs (24b, 24c, 24d, 24f) match or mismatch with the reproduced signals (n0s to n3s). Specifically, an exclusive OR gate 41 determines whether the signals (n0s to n3s) match or mismatch with the internal parallel data signals (n01, n11, n22, n32) and generates determination signals (SDET1 to SDET4).

[0064] In the decision circuit 17, the decision signals (SDET1 to SDET4) from the four exclusive OR gates 41 are stored in flip-flop circuits (57b, 57c, 57d, 57f), respectively. The flip-flop circuits (57b, 57c) read the decision signals (SDET1, SDET2) in synchronization with a clock (ck3). In addition, the flip-flop circuits 57 (57d, 57f) read the decision signals (SDET3, SDET4) in synchronization with a clock (ck1 of the next cycle).

[0065] In the decision circuit 17, the outputs of the flip-flop circuits (57b, 57c, 57d, 57f) are connected to an OR gate 59. The OR gate 59 outputs four parallel data ( <d0> 、 <d1> 、 <d2> 、 <d3>) and generates a notification signal SABN at the alert output 20.

[0066] Referring to FIG. 2, the exemplary semiconductor device 11 includes a serial data latch circuit (e.g., a flip-flop circuit 55) for holding serial data. The serial data latch circuit holds the converted serial data for at least one cycle of the conversion clock. The temporal overlap between the pre-conversion parallel data and the converted serial data is ensured to be at least one-quarter (>T / 4) of the clock (ck) period T. Therefore, by selecting an appropriate clock from the four-phase clock, it is possible to compare the parallel data with the serial data. Accordingly, the determination circuit 17 can detect whether or not there is an abnormality in the serial data and generate a notification signal SABN.

[0067] The exemplary semiconductor device 11 can determine data (D0, D1) at the rising edge of the clock (ck3), and data (D2, D3) at the rising edge of the clock (ck1) in the next cycle.

[0068] The circuit shown in Figure 2 can be used for factory tests and diagnostic tests during startup and standby. It can also compare data before and after parallel-to-serial conversion in parallel with serial data transfer, for example, in real time. This allows continuous monitoring during normal operation. Continuous monitoring allows for rapid detection of abnormalities and notification of the detection to a host system.

[0069] Figure 4 is a diagram schematically illustrating an exemplary semiconductor device according to this embodiment. Figure 5 is a diagram illustrating exemplary operation timing in the semiconductor device shown in Figure 4. In the following description, where possible, the reference numerals used in Figures 1 and 2 will be used to omit redundant description.

[0070] 4, the fourth storage circuit 39 can be configured as four flip-flop circuits 61 (61b, 61c, 61d, 61f). The flip-flop circuits (61b, 61c, 61d, 61f) are connected between the flip-flop circuits (51b, 51c, 51d, 51f) and the parallel data outputs (24b, 24c, 24d, 24f), respectively. The flip-flop circuits (61b, 61c, 61d, 61f) receive signals from the flip-flop circuits (51b, 51c, 51d, 51f) and provide the received signals to the parallel data outputs (24b, 24c, 24d, 24f).

[0071] The operation of the flip-flop circuits (61b, 61c, 61d, 61f) is related to a capture clock (ck) that defines the timing for capturing the parallel data signal SPLE. Specifically, the flip-flop circuits (61b, 61c) are read in synchronization with the capture clock (ck) that defines the timing for capturing the parallel data signal SPLE. Furthermore, the flip-flop circuits (61g, 61h) are read in synchronization with the inverted clock (ck_) of the capture clock (ck) that defines the timing for capturing the parallel data signal SPLE.

[0072] The determination circuit 17 determines whether the signals (n0p, n1p, n2p, n3p) from the flip-flop circuits (61b, 61c, 61d, 61f) match or mismatch with the reproduced signals (n0s, n1s, n2s, n3s).

[0073] Referring to FIG. 4, the exemplary semiconductor device 11 is provided with serial data latch circuits (flip-flop circuits 55) to enable serial data retention. These serial data latch circuits retain the serial data after conversion for at least one conversion clock cycle. The temporal overlap between the pre-conversion parallel data and the converted serial data is ensured to be at least three-quarters (>3T / 4) of the clock (ck) period T. This allows for comparison of the parallel data and the serial data by selecting an appropriate clock from the four-phase clock. The determination circuit 17 detects whether the serial data is abnormal and generates a notification signal SABN.

[0074] The exemplary semiconductor device 11 can compare the data (D0, D1) at the rising edge of the clock (ck3) and can compare the data (D2, D3) at the rising edge of the clock (ck1) in the next cycle.

[0075] The circuit in Figure 4 can compare data before and after parallel-to-serial conversion in real time. Therefore, this circuit can be used for shipping tests and diagnostic tests during startup and standby. In addition, this circuit enables continuous monitoring during normal operation. Continuous monitoring makes it possible to quickly detect abnormalities and notify the host system of this detection.

[0076] By adding a parallel data latch circuit, the temporal overlap between the parallel data before conversion and the serial data after conversion can be ensured to be at least three-quarters (>3T / 4) of the clock (ck) period T. This makes it possible to expand the comparison timing margin, more reliably detect serial data anomalies, and also to notify the host system.

[0077] FIG. 6 is a diagram schematically illustrating a serial transmission system according to an embodiment of the present invention.

[0078] The serial transmission system 63 includes a semiconductor device 11 and a serial transmission receiver 65. The semiconductor device 11 is connected to the serial transmission receiver 65 via a wired transmission path 67 (e.g., a single-phase or differential transmission path). The semiconductor device 11 transmits data via serial transmission to a differential receiver 69 of the serial transmission receiver 65. The serial transmission system 63 can compare data before and after parallel-to-serial conversion of the semiconductor device 11 in real time. This allows this circuit to be used for shipping tests and diagnostic tests during startup and standby. In addition, this circuit enables continuous monitoring during normal operation. During continuous monitoring, abnormalities can be quickly detected and this detection can be notified to a higher-level system.

[0079] FIG. 7 is a diagram illustrating a data transmission method in a serial transmission system according to an embodiment of the present invention.

[0080] Referring to FIG. 7, a data transmission method 100 is shown.

[0081] The data transmission method 100 may include exemplary step ST01. In step ST01, a serial transmission system 63 is prepared. This preparation includes manufacturing the serial transmission system 63, obtaining the serial transmission system 63, and renting the serial transmission system 63. The prepared serial transmission system 63 is used in the following exemplary steps.

[0082] The data transmission method 100 may include an exemplary step ST02 in which power is supplied to the serial transmission system 63.

[0083] The data transmission method 100 may include an exemplary step ST03, in which serial transmission is performed in the serial transmission system 63.

[0084] The data transmission method 100 may include an exemplary step ST04. In step ST04, in parallel with the serial transmission of the serial transmission system 63, the semiconductor device 11 determines whether or not there is a data mismatch in the serial transmission.

[0085] The data transmission method 100 can include exemplary step ST05. Step ST05 is performed when a mismatch is detected in the data converted from parallel data to serial data in step ST04. In step ST05, the semiconductor device 11 generates a notification signal SABN indicating the data mismatch. The notification signal SABN is sent to a higher-level system.

[0086] In step ST04, if no mismatch is detected in the data converted from parallel data to serial data, step ST03 is carried out.

[0087] As described above, according to the present embodiment, it is possible to provide a semiconductor device including a parallel-to-serial conversion circuit having a self-detection function capable of detecting an abnormality in the serial data value after parallel data has been format-converted into serial data. Furthermore, according to the present embodiment, it is possible to provide a serial transmission system including the semiconductor device. Furthermore, according to the present embodiment, it is possible to provide a method for serially transmitting data using the serial transmission system.

[0088] As can be understood from the above description, the present embodiment can have various aspects as shown below.

[0089] A semiconductor device according to a first aspect of this embodiment includes a parallel-serial conversion circuit having a plurality of parallel data inputs configured to receive a set of parallel data signals, and a parallel data output, the parallel-serial conversion circuit configured to generate a plurality of serial data signals each including a plurality of serial data values ​​in a set of serial data converted from the set of parallel data of the parallel data signals received at the parallel data inputs, and to sequentially provide the serial data signals to the parallel data output; a reproduction circuit configured to generate a reproduction signal indicating a set of reproduced parallel data from the serial data signal from the parallel data output; and a determination circuit configured to determine whether at least a portion of the set of reproduction signals matches or does not match at least a portion of the set of parallel data signals.

[0090] In a semiconductor device according to a second aspect of the first aspect of this embodiment, the parallel-serial conversion circuit includes a plurality of first storage circuits, each having an output connected to the parallel data output, and the first storage circuits can be configured to sequentially send out the parallel data signals in respective periods defined by a plurality of timing clocks that define an arrangement of the serial data.

[0091] In a semiconductor device of a third aspect according to the second aspect of this embodiment, the reproduction circuit includes a plurality of second storage circuits, each having an input connected to the parallel data output, and the second storage circuits are capable of capturing a signal from the parallel data output in response to an inverted timing clock from the timing clock.

[0092] In a semiconductor device of a fourth aspect according to the second or third aspect of this embodiment, the parallel-serial conversion circuit includes a plurality of third storage circuits, the third storage circuits are connected to the parallel data inputs, the third storage circuits capture values ​​from the parallel data inputs in synchronization with a capture clock that defines the timing of capturing the parallel data signals, and the third storage circuits can be connected to the inputs of the first storage circuits.

[0093] In a semiconductor device of a fifth aspect according to the fourth aspect of this embodiment, the parallel-serial conversion circuit has a parallel data output configured to provide an internal parallel data signal from the parallel data input, and the determination circuit can be configured to determine whether the internal parallel data signal from the parallel data output matches or does not match the reproduced signal.

[0094] In a semiconductor device of a sixth aspect according to a fifth aspect of this embodiment, the third storage circuits may have respective outputs connected to the parallel data outputs.

[0095] In the semiconductor device of the seventh aspect according to the fifth aspect of this embodiment, the parallel-serial conversion circuit includes a plurality of fourth storage circuits, each having an input connected to the output of the third storage circuit, and each of the fourth storage circuits can have an output connected to the parallel data output.

[0096] In a semiconductor device of an eighth aspect according to any one of the first to seventh aspects of this embodiment, the judgment circuit includes a determiner configured to determine whether at least a portion of a set of the parallel data signals matches / mismatches the parallel data signal, and the judgment circuit includes a logical OR circuit connected to the output of the determiner.

[0097] In a semiconductor device of a ninth aspect according to any one of the first to eighth aspects of this embodiment, the determination circuit may include an exclusive OR configured to determine whether the reproduction signal and the parallel data signal match or mismatch.

[0098] The serial transmission system of the tenth aspect of this embodiment comprises a semiconductor device described in any one of the first to ninth aspects, and a serial transmission receiving device connected to the semiconductor device via a wired serial transmission path.

[0099] A method for serially transmitting data according to an eleventh aspect of this embodiment comprises preparing a serial transmission system as described in claim 10, serially transmitting data from the semiconductor device to the serial transmission receiving device via the serial transmission path, and generating a notification signal when a mismatch is detected in the data converted from the parallel data to the serial data.

[0100] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0101] 11. Semiconductor device, 13...Parallel-serial conversion circuit, 15...Regeneration circuit, 17...judgment circuit, 19, 19b, 19c, 19d, 19f...Parallel input, 20 Alert output, 21...Serial output, 23, 23b, 23c, 23d, 23f...Parallel data output 24, 24b, 24c, 24d, 24f...Parallel data output 25, 25b, 25c, 25d, 25f...Parallel data input 27... Serial data transmission circuit, 28... transmitter, 30...electrode, 31. Clock generation circuit, 33, 33b, 33c, 33d, 33f...first storage circuit, 35, 35b, 35c, 35d, 35f... Second storage circuit, 37, 37b, 37c, 37d, 37f...Third storage circuit, 39, 39b, 39c, 39d, 39f...4th storage circuit, 41... Exclusive OR gate, 43...determiner, 45... Total decision circuit, 47, x47b, 47c, 47d, 47f···5th storage circuit, 51, 55, 57, 61...flip-flop circuit, 53... latch circuit, 59... OR gate, 63...Serial transmission system, 65...Serial transmission receiving device, 67···Transmission line, 69... Differential receiver, SABN notification signal, SDET (DET1, SDET2, SDET3, SDET4)...Determination signal, SPARIT (SPARIT1, SPARIT2, SPARIT3, SPARIT4) Internal parallel data signal, SPLE: parallel data signal, SRSIL (SRSIL1, SRSIL2, SRSIL3, SRSIL4)... playback signal, SSIL: Serial Array Signal, SSIL1, SSIL2, SSIL3, SSIL4...Serial data signal, T...period. < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d0> < / d0> < / d0> < / d0> < / d2> < / d0> < / d2> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d0> < / d0> < / d0> < / d2> < / d0> < / d0> < / d0> < / d0> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d0> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0> < / d2> < / d1> < / d0>

Claims

1. a parallel-to-serial conversion circuit having a plurality of parallel data inputs configured to receive a set of parallel data signals, and a parallel data output, the parallel-to-serial conversion circuit configured to generate a plurality of serial data signals each containing a plurality of serial data values ​​in a set of serial data converted from the set of parallel data of the parallel data signals received at the parallel data inputs, and to provide the serial data signals in sequence to the parallel data output; a recovery circuit configured to generate a recovery signal representing a set of recovered parallel data from the serial data signal from the parallel data output; a determination circuit configured to determine whether at least a portion of the set of reproduced signals matches or does not match at least a portion of the set of parallel data signals; A semiconductor device comprising:

2. the parallel-serial conversion circuit includes a plurality of first storage circuits; the first storage circuit has an output connected to the parallel data output; the first storage circuit is configured to sequentially transmit the parallel data signals in respective periods defined by a plurality of timing clocks that define an arrangement of the serial data; 2. The semiconductor device according to claim 1.

3. the reproduction circuit includes a plurality of second storage circuits; the second storage circuit has an input connected to the parallel data output; the second storage circuit captures a signal from the parallel data output in response to an inverted timing clock from the timing clock; 3. The semiconductor device according to claim 2.

4. the parallel-serial conversion circuit includes a plurality of third storage circuits; the third storage circuit is connected to the parallel data input; the third storage circuit captures values ​​from the parallel data inputs in synchronization with a capture clock that defines timing for capturing the parallel data signals; the third storage circuit is connected to the input of the first storage circuit; 3. The semiconductor device according to claim 2.

5. the parallel-to-serial conversion circuit has a parallel data output configured to provide an internal parallel data signal from the parallel data input; the determination circuit is configured to determine whether the internal parallel data signal from the parallel data output matches or does not match the reproduced signal.

5. The semiconductor device according to claim 4.

6. the third storage circuits having respective outputs connected to the parallel data outputs; 6. The semiconductor device according to claim 5.

7. the parallel-serial conversion circuit includes a plurality of fourth storage circuits; the fourth storage circuit has an input connected to the output of the third storage circuit; the fourth storage circuits having respective outputs connected to the parallel data outputs; 6. The semiconductor device according to claim 5.

8. the determination circuit includes a determiner configured to determine whether at least a portion of the set of parallel data signals matches or does not match the parallel data signal; the determination circuit includes a logical OR circuit connected to an output of the determiner; 2. The semiconductor device according to claim 1.

9. the determination circuit includes an exclusive OR configured to determine whether the reproduced signal and the parallel data signal match or mismatch; 2. The semiconductor device according to claim 1.

10. A semiconductor device according to any one of claims 1 to 9; a serial transmission receiving device connected to the semiconductor device via a wired serial transmission path; A serial transmission system comprising:

11. Providing a serial transmission system according to claim 10; transmitting serial data from the semiconductor device to the serial transmission receiving device via the serial transmission path; generating a notification signal when detecting a mismatch between the data converted from the parallel data to the serial data; A method for serially transmitting data, comprising:

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