Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor having a high breakdown voltage specification capable of suppressing the occurrence of cracks and noise due to an electrostrictive effect.SOLUTION: In a multilayer ceramic capacitor 1, an inner layer portion 11 includes a capacitor effective portion 11E1 in which two layers of a first internal electrode layer 31, a second internal electrode layer 32, and an intermediate electrode layer 33 are alternately stacked with a dielectric layer 20 interposed therebetween, and a series connection region MG in which the dielectric layer 20 and the intermediate electrode layer 33 are alternately stacked. In a LT cross section, when a ratio (L1 / L0) of a length L1 measured along a cross-sectional shape of the internal electrode layer in a predetermined region to a linear distance L0 in a longitudinal direction of the internal electrode layer 30 in a predetermined region is defined as an undulation amount, the undulation amount of the intermediate electrode layer 33 in the series connection region MG is larger than the undulation amount of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in the capacitor effective portion 11E1.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Multilayer ceramic capacitors are sometimes required to withstand high voltages. A multilayer ceramic capacitor with a structure in which multiple capacitor sections are connected in series, known as a series structure, is known as a multilayer ceramic capacitor that can achieve high voltages (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-209495 Summary of the Invention [Problem to be solved by the invention]

[0004] In a series-structure multilayer ceramic capacitor, the capacitance decreases due to the formation of multiple capacitor parts connected in series. In order to increase the capacitance, it is necessary to increase the number of laminated internal electrode layers, but increasing the number of laminated internal electrode layers poses the problem of increasing the likelihood of cracks and noise due to the electrostrictive effect, a phenomenon in which distortion occurs when an electric field is applied to the dielectric.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor with high voltage resistance that can suppress the occurrence of cracks and noise due to electrostrictive effects. [Means for solving the problem]

[0006] The multilayer ceramic capacitor of the present invention is a multilayer ceramic capacitor having a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in the lamination direction, a first side surface and a second side surface opposing each other in the width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in the length direction perpendicular to the lamination direction and the width direction, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, wherein the plurality of internal electrode layers are the first internal electrode layer and the second internal electrode layer. the first internal electrode layer has a first lead portion, one end of which is drawn out to the first end surface and connected to the first external electrode, and a first opposing portion, which is connected to the first lead portion and faces the internal electrode layer arranged adjacently in the stacking direction; the second internal electrode layer has a second lead portion, one end of which is drawn out to the second end surface and connected to the second external electrode, and a second opposing portion, which is connected to the second lead portion and faces the internal electrode layer arranged adjacently in the stacking direction; the intermediate electrode layer has a an internal electrode layer that is not connected to either the first external electrode or the second external electrode and forms a series-connected capacitor element together with the first internal electrode layer and the second internal electrode layer, and the laminate has an internal layer portion in which the dielectric layers and the internal electrode layers are alternately laminated, a first side surface side external layer portion that is arranged on the first side surface side of the internal layer portion and in which only the dielectric layers are laminated, and a second side surface side external layer portion that is arranged on the second side surface side of the internal layer portion and in which only the dielectric layers are laminated, and the internal layer portion has an effective layer portion in which two of the intermediate electrode layers are alternately stacked with the dielectric layer sandwiched therebetween; a first end face side outer layer portion disposed on the first end face side of the internal layer portion and in which the dielectric layers and the first internal electrode layers are alternately stacked; a second end face side outer layer portion disposed on the second end face side of the internal layer portion and in which the dielectric layers and the second internal electrode layers are alternately stacked; and an intermediate gap in which the dielectric layers and the intermediate electrode layers are alternately stacked, and in a cross section on a plane parallel to the longitudinal direction and stacking direction,When the waviness is defined as the ratio (L1 / L0) of the length (L1) measured along the cross-sectional shape of the internal electrode layer in a predetermined region, the waviness of the intermediate electrode layer in the intermediate gap is larger than the waviness of the first internal electrode layer, the second internal electrode layer and the intermediate electrode layer in the effective layer portion. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor with high voltage resistance that can suppress the occurrence of cracks and noise due to electrostrictive effects. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is an external perspective view of a double-structure multilayer ceramic capacitor according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, illustrating the schematic configuration of a double-structure laminate according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 2. [Figure 4A] FIG. 3 is a cross-sectional view taken along line IVA-IVA in FIG. 2, along a first internal electrode layer and a second internal electrode layer. [Figure 4B] 4 is a cross-sectional view taken along line IVB-IVB of FIG. 2, taken along the intermediate electrode layer. [Figure 5] FIG. 2 is a cross-sectional view schematically showing an intermediate electrode layer in a series connection region MG. [Figure 6] FIG. 10 is a schematic diagram for explaining the general configuration of a triple-structure multilayer ceramic capacitor according to a second embodiment. [Figure 7] FIG. 10 is a schematic diagram for explaining the general configuration of a four-layer structure multilayer ceramic capacitor according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] First Embodiment A multilayer ceramic capacitor 1 as a double-array structure multilayer ceramic electronic component according to a first embodiment of the present disclosure will be described with reference to the drawings. FIG. 1 is an external perspective view of the double-array structure multilayer ceramic capacitor 1 according to the first embodiment. FIG. 2 is a cross-sectional view taken along II-II in FIG. 1, illustrating a schematic configuration of a double-array structure laminate according to the first embodiment. FIG. 3 is a cross-sectional view taken along III-III in FIG. 2. FIG. 4A is a cross-sectional view taken along IVA-IVA in FIG. 2, taken along the first internal electrode layer and the second internal electrode layer. FIG. 4B is a cross-sectional view taken along IVB-IVB in FIG. 2, taken along the intermediate electrode layer.

[0010] The drawings may be simplified and schematic for the purpose of explaining the invention, and the dimensional ratios of the depicted components or between the components may not match those described in the specification. Furthermore, components described in the specification may be omitted from the drawings, or the number of components may be omitted. For example, the number of internal electrode layers shown in Figures 2 and 3 is seven for the sake of convenience, but this does not indicate the actual number of internal electrode layers 30. Terms used in the present invention that specify shapes and geometric conditions, as well as their degrees of similarity, such as "parallel," "orthogonal," and "identical," as well as values ​​of length and angle, are not limited to their strict meanings but are interpreted to encompass a range within which similar functionality can be expected.

[0011] 1, the multilayer ceramic capacitor 1 according to the embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 10 while being spaced apart from each other.

[0012] In FIG. 1, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T also corresponds to the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. In FIG. 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T. In FIG. 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T and the length direction L. A pair of external electrodes 40 are respectively disposed at one end and the other end of the length direction L of the laminate 10.

[0013] 1 to 4B show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as an LT cross section. The cross section shown in FIG. 3 is also referred to as a WT cross section. The cross sections shown in FIGS. 4A and 4B are also referred to as LW cross sections.

[0014] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing in the stacking direction T, a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T and the length direction L.

[0015] As shown in FIG. 1, the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0016] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, then the T dimension is preferably 0.1 mm or more and 10 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0017] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0018] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in the stacking direction T. The inner layer portion 11 includes the internal electrode layer 30 located closest to the first principal surface TS1 to the internal electrode layer 30 located closest to the second principal surface TS2 in the stacking direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0019] The plurality of dielectric layers 20 are made of a dielectric material. The dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. The dielectric material may also be a material containing these main components plus a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound. It is particularly preferable that the dielectric material contain BaTiO3 as the main component.

[0020] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. In particular, the thickness of the dielectric layer 20 is preferably 3 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 1200 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers 20 in the inner layer portion 11 and the number of the dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0021] The multiple internal electrode layers 30 include multiple first internal electrode layers 31, multiple second internal electrode layers 32, and intermediate electrode layers 33. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged adjacent to each other while being spaced apart in the length direction L, and the first internal electrode layers 31 and the second internal electrode layers 32 and the intermediate electrode layers 33 are arranged alternately in the stacking direction T with the dielectric layer 20 sandwiched therebetween.

[0022] The first internal electrode layer 31 is extended to the first end face LS1 and connected to a first external electrode 40A (described later). The second internal electrode layer 32 is extended to the second end face LS2 and connected to a second external electrode 40B (described later). The intermediate electrode layer 33 is not extended to either the first end face LS1 or the second end face LS2, and is not connected to either the first external electrode 40A or the second external electrode 40B (described later). The first internal electrode layer 31, the intermediate electrode layer 33, and the second internal electrode layer 32 included in the multiple internal electrode layers 30 form a series-connected capacitor element. Note that, hereinafter, when it is not necessary to distinguish between the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be collectively referred to as the internal electrode layer 30.

[0023] As shown in FIGS. 2 and 4A , the first internal electrode layer 31 has a first opposing portion EA and a first lead portion D1. The first opposing portion EA is a region facing the intermediate electrode layer 33 arranged adjacent to the first internal electrode layer 31 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The first internal electrode layer 31 has a first opposing portion EA connected to the first lead portion D1 and facing the internal electrode layer 30 arranged adjacent to the first internal electrode layer 31 in the stacking direction T. The first lead portion D1 is a portion extending from the first opposing portion EA to the first end face LS1 and exposed at the first end face LS1. The first internal electrode layer 31 has a first lead portion D1, one end of which is extended to the first end face LS1 and connected to the first external electrode 40A.

[0024] As shown in FIGS. 2 and 4A, the second internal electrode layer 32 has a second opposing portion EB and a second lead portion D2. The second opposing portion EB is a region facing the intermediate electrode layer 33 arranged adjacent to the second internal electrode layer 32 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second internal electrode layer 32 has a second opposing portion EB connected to the second lead portion D2 and facing the internal electrode layer 30 arranged adjacent to the second internal electrode layer 32 in the stacking direction T. The second lead portion D2 is a portion drawn from the second opposing portion EB to the second end face LS2 and is exposed at the second end face LS2. The second internal electrode layer 32 has a second lead portion D2, one end of which is drawn to the second end face LS2 and connected to the second external electrode 40B.

[0025] 2 and 4B, the intermediate electrode layer 33 has a first electrode layer side facing portion ECA, a second electrode layer side facing portion ECB, and a connecting portion E0. The first electrode layer side facing portion ECA is a region facing the first internal electrode layer 31 arranged adjacent to the first internal electrode layer 31 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second electrode layer side facing portion ECB is a region facing the second internal electrode layer 32 arranged adjacent to the first internal electrode layer 31 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The connecting portion E0 is a portion that connects the first electrode layer side facing portion ECA and the second electrode layer side facing portion ECB, and is located between the first electrode layer side facing portion ECA and the second electrode layer side facing portion ECB.

[0026] In the multilayer ceramic capacitor 1 according to this embodiment, the end of the intermediate electrode layer 33 on the first end face LS1 side is disposed away from the first end face LS1. In the multilayer ceramic capacitor 1 according to this embodiment, the end of the intermediate electrode layer 33 on the first end face LS1 side is disposed closer to the first end face LS1 than the end of the first external electrode 40A. However, this is not limiting, and the end of the intermediate electrode layer 33 on the first end face LS1 side may be disposed closer to the second end face LS2 than the end of the first external electrode 40A.

[0027] An end of the intermediate electrode layer 33 on the second end face LS2 side is disposed away from the second end face LS2. In the multilayer ceramic capacitor 1 according to this embodiment, the end of the intermediate electrode layer 33 on the second end face LS2 side is disposed closer to the second end face LS2 than the end of the second external electrode 40B. However, this is not limiting, and the end of the intermediate electrode layer 33 on the second end face LS2 side may be disposed closer to the first end face LS1 than the end of the second external electrode 40B.

[0028] 2, in the multilayer ceramic capacitor 1 according to the first embodiment, the first internal electrode layer 31 and the second internal electrode layer 32 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the first embodiment, the first internal electrode layer 31 and the second internal electrode layer 32 are stacked alternately with the intermediate electrode layer 33 interposed between them, with the dielectric layer 20 interposed therebetween.

[0029] In this embodiment, the first opposing portion EA and the first electrode layer side opposing portion ECA face each other via the dielectric layer 20, thereby forming a capacitance CAP1 (first capacitor portion CAP1). The second opposing portion EB and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33 including the first electrode layer side opposing portion ECA face each other via the dielectric layer 20, thereby forming a capacitance CAP2 (second capacitor portion CAP2). The coupling portion E0 connects the capacitances CAP1 and CAP2 in series. The multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 of a so-called double series structure in which two capacitor portions connected in series are formed.

[0030] The shapes of the first opposing portion EA, the second opposing portion EB, the first electrode layer side opposing portion ECA, and the second electrode layer side opposing portion ECB are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first lead portion D1 and the second lead portion D2 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shape of the connecting portion E0 is not particularly limited, but is preferably rectangular.

[0031] The width direction W dimension of the first opposing portion EA and the width direction W dimension of the first lead portion D1 may be the same dimension, or one of the dimensions may be smaller. The width direction W dimension of the second opposing portion EB and the width direction W dimension of the second lead portion D2 may be the same dimension, or one of the dimensions may be smaller. The width direction W dimension of the first electrode layer side opposing portion ECA and the second electrode layer side opposing portion ECB and the width direction W dimension of the connecting portion E0 may be the same dimension, or one of the dimensions may be smaller.

[0032] The first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be made of, for example, an Ag-Pd alloy.

[0033] The thickness of each of the first internal electrode layers 31, the second internal electrode layers 32, and the intermediate electrode layers 33 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31, the second internal electrode layers 32, and the intermediate electrode layers 33 is preferably 15 or more and 1000 or less.

[0034] As shown in FIGS. 2 and 3 , the first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 11.

[0035] The laminate 10 has a series capacitor-forming portion 11E. The series capacitor-forming portion 11E includes a portion where the first opposing portion EA of the first internal electrode layer 31 faces the first-electrode-layer-side opposing portion ECA of the intermediate electrode layer 33 (portion forming capacitance CAP1), a portion where the second opposing portion EB of the second internal electrode layer 32 faces the second-electrode-layer-side opposing portion ECB of the intermediate electrode layer 33 (portion forming capacitance CAP2), and a portion connecting the capacitances CAP1 and CAP2 in series. The series capacitor-forming portion 11E is configured as a part of the inner layer portion 11. FIGS. 4A and 4B show the width direction W and length direction L of the series capacitor-forming portion 11E. The portion of the series capacitor-forming portion 11E where the capacitance CAP1 is formed as a capacitor element (first capacitor portion CAP1) and the portion where the capacitance CAP2 is formed as a capacitor element (second capacitor portion CAP2) are also referred to as a capacitor effective portion 11E1 or effective layer portion 11E1.

[0036] The laminate 10 has side surface-side outer layer portions. The side surface-side outer layer portions include a first side surface-side outer layer portion WG1 and a second side surface-side outer layer portion WG2. The first side surface-side outer layer portion WG1 is a portion including the dielectric layer 20 located between the series capacitor-forming portion 11E and the first side surface WS1. The second side surface-side outer layer portion WG2 is a portion including the dielectric layer 20 located between the series capacitor-forming portion 11E and the second side surface WS2. FIGS. 3, 4A, and 4B show the ranges in the width direction W of the first side surface-side outer layer portion WG1 and the second side surface-side outer layer portion WG2. The side surface-side outer layer portions are also referred to as W gaps or side gaps.

[0037] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion has a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion located between the series capacitor forming portion 11E and the first end surface LS1 and including the dielectric layers 20 and the first lead portion D1. That is, the first end surface side outer layer portion LG1 is an assembly of the portions of the multiple dielectric layers 20 on the first end surface LS1 side and the multiple first lead portions D1. The second end surface side outer layer portion LG2 is a portion located between the series capacitor forming portion 11E and the second end surface LS2 and including the dielectric layers 20 and the second lead portion D2. That is, the second end surface side outer layer portion LG2 is an assembly of the portions of the multiple dielectric layers 20 on the second end surface LS2 side and the multiple second lead portions D2. 2, 4A, and 4B show the range of the first end-side outer layer portion LG1 and the second end-side outer layer portion LG2 in the length direction L. The end-side outer layer portions are also called L gaps or end gaps.

[0038] The series capacitor forming portion 11E of the laminate 10 has a series connection region MG. The series connection region MG is a portion that includes the dielectric layer 20 and the coupling portion E0 and is located between the portion that forms the capacitance CAP1 and the portion that forms the capacitance CAP2. In other words, the series connection region MG is an assembly of the central portions of the multiple dielectric layers 20 in the length direction L and the multiple coupling portions E0. The series connection region MG is also referred to as a middle gap MG.

[0039] As shown in Figures 1 and 2, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0040] The first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B have shapes that are approximately plane-symmetric with respect to a WT cross section at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.

[0041] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is in contact with the first lead portions D1 of each of the first internal electrode layers 31 exposed at the first end face LS1. This electrically connects the first external electrode 40A to the first internal electrode layers 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0042] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is in contact with the second lead portions D2 of each of the second internal electrode layers 32 exposed at the second end face LS2. This electrically connects the second external electrode 40B to the second internal electrode layers 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0043] As described above, in the laminate 10, the capacitance CAP1 (first capacitor portion CAP1) is formed by the first opposing portion EA of the first internal electrode layer 31 and the first electrode layer side opposing portion ECA of the intermediate electrode layer 33 facing each other via the dielectric layer 20. The capacitance CAP2 (second capacitor portion CAP2) is formed by the second opposing portion EB of the second internal electrode layer 32 and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33 facing each other via the dielectric layer 20.

[0044] The coupling portion E0 connects the capacitances CAP1 and CAP2 in series, so that the characteristics of a capacitor due to the series connection capacitance are exhibited between the first outer electrode 40A connected to the first internal electrode layer 31 and the second outer electrode 40B connected to the second internal electrode layer 32.

[0045] 2, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0046] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first lead portions D1 of each of the first internal electrode layers 31 exposed at the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0047] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the second lead portions D2 of each of the second internal electrode layers 32 exposed at the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0048] The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a baked layer, a thin film layer, and the like.

[0049] The first and second base electrode layers 50A and 50B of this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, and Au. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, and Li. The ceramic component may be the same ceramic material as that of the dielectric layer 20, or a different ceramic material. The ceramic component may include at least one selected from, for example, BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, and CaZrO3.

[0050] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate 10 and baking it. The baked layer can be formed by co-firing a pre-fired laminate chip, which is the material for the laminate 10 having multiple internal electrode layers and dielectric layers, with a conductive paste applied to the laminate chip. Alternatively, the baked layer can be formed by first firing the laminate chip to obtain the laminate 10, and then applying a conductive paste to the laminate 10 and baking it. In the above configuration, the baked layer is preferably formed by baking a material to which a ceramic material is added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be multiple layers.

[0051] The thickness of the first base electrode layer 50A located on the first end face LS1 in the longitudinal direction L is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.

[0052] The thickness of the second base electrode layer 50B located on the second end face LS2 in the longitudinal direction L is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.

[0053] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided on this portion, corresponding to the stacking direction T, is preferably, for example, approximately 3 μm or more and 25 μm or less at the center of the first base electrode layer 50A provided on this portion in the length direction L and width direction W.

[0054] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided on this portion in the width direction W is preferably, for example, approximately 3 μm or more and 25 μm or less at the center of the first base electrode layer 50A provided on this portion in the length direction L and stacking direction T.

[0055] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided on this portion in the stacking direction T is preferably, for example, approximately 3 μm or more and 25 μm or less at the center in the length direction L and width direction W of the second base electrode layer 50B provided on this portion.

[0056] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness corresponding to the width direction W of the second base electrode layer 50B provided on this portion is preferably, for example, approximately 3 μm or more and 25 μm or less at the center of the length direction L and stacking direction T of the second base electrode layer 50B provided on this portion.

[0057] In this embodiment, the first base electrode layer 50A and the second base electrode layer 50B may be thin film layers, which are layers on which metal particles are deposited.

[0058] When the first base electrode layer 50A and the second base electrode layer 50B are formed as thin film layers, they are preferably formed by a thin film formation method such as sputtering or vapor deposition. Here, a sputtered electrode formed by sputtering will be described.

[0059] In this embodiment, the first base electrode layer 50A may be composed of a first thin film layer formed by a sputtered electrode. The second base electrode layer 50B may be composed of a second thin film layer formed by a sputtered electrode. When forming the base electrode layer by a sputtered electrode, it is preferable to form the sputtered electrode directly on a portion of at least one of the first main surface TS1 and the second main surface TS2 of the laminate 10. The first thin film layer formed by the sputtered electrode is disposed on a portion of the first main surface TS1 on the side of the first side surface WS1. The second thin film layer formed by the sputtered electrode is disposed on a portion of the first main surface TS1 on the side of the second side surface WS2.

[0060] The thin film layer formed by the sputtered electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This increases the adhesive strength of the external electrode 40 to the laminate 10. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed of a two-layer structure consisting of a layer of Ni-Cr alloy and a layer of Ni-Cu alloy.

[0061] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0062] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0063] The first plating layer 60A and the second plating layer 60B may contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0064] In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0065] In this embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0066] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 10 μm or less.

[0067] The external electrode 40 of this embodiment may have, for example, a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be disposed so as to cover the baked layer. When the conductive resin layer is disposed so as to cover the baked layer, the conductive resin layer is disposed between the baked layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baked layer or may cover only a portion of the baked layer.

[0068] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0069] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. The conductive particles preferably contain Ag. The conductive particles may be, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, Ag is a noble metal, so it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as the conductive particles.

[0070] The conductive particles may also be metal powders whose surfaces are coated with Ag. When using metal powders whose surfaces are coated with Ag, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy powder thereof. In order to maintain the properties of Ag while making the base metal inexpensive, it is preferable to use Ag-coated metal powders.

[0071] Furthermore, the conductive particles may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive particles may be metal powder whose surface is coated with Sn, Ni, or Cu. When using metal powder whose surface is coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0072] The shape of the conductive particles is not particularly limited. The conductive particles may be spherical, flat, or other shapes, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0073] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. Specifically, the contact between the conductive particles forms an electrical path within the conductive resin layer.

[0074] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, the resin of the conductive resin layer preferably includes a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0075] The conductive resin layer may be formed of multiple layers. The thickness of the thickest part of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0076] Note that the first plating layer 60A and the second plating layer 60B may be disposed directly on the laminate 10 without providing the first base electrode layer 50A and the second base electrode layer 50B. That is, the multilayer ceramic capacitor 1 may include plating layers that are directly and electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, a catalyst may be disposed on the surface of the laminate 10 as a pretreatment, and then the plating layers may be formed.

[0077] Even in this case, the plating layer preferably comprises multiple layers. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni, which has solder barrier properties. The upper plating layer is more preferably formed using Sn or Au, which have good solder wettability. For example, when the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, the lower plating layer is preferably formed using Cu, which has good bonding properties with Ni. The upper plating layer may be formed as needed, and the external electrode 40 may be composed of only the lower plating layer. Furthermore, the upper plating layer may be the outermost layer, or another plating layer may be formed on the surface of the upper plating layer.

[0078] The thickness of each plating layer, which is disposed without a base electrode layer, is preferably 2 μm or more and 10 μm or less. The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0079] Note that when the plating layer is formed directly on the laminate 10, the thickness of the base electrode layer can be reduced. Therefore, the dimension of the multilayer ceramic capacitor 1 in the stacking direction T can be reduced by the amount of the reduced thickness of the base electrode layer, thereby making it possible to reduce the height of the multilayer ceramic capacitor 1. Alternatively, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 can be increased by the amount of the reduced thickness of the base electrode layer, thereby improving the thickness of the element body. In this way, by forming the plating layer directly on the laminate 10, the degree of freedom in designing the multilayer ceramic capacitor can be improved.

[0080] The above is the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 is defined as T, then the T dimension is preferably 0.1 mm or more and 10 mm or less. If the widthwise dimension of the multilayer ceramic capacitor 1 is defined as W, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0081] Next, the internal electrode layers 30 of this embodiment will be described in detail with reference to FIGS.

[0082] In the multilayer ceramic capacitor 1 of this embodiment, in a cross section (LT cross section) on a plane parallel to the longitudinal direction L and the stacking direction T, the amount of waviness of the intermediate electrode layer 33 in the series connection region MG as the intermediate gap MG is larger than the amount of waviness of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in the capacitor effective portion 11E1 as the effective layer portion 11E1.

[0083] Here, the amount of waviness is defined as the ratio (L1 / L0) of a length L1 measured along the cross-sectional shape of the internal electrode layer 30 in a predetermined region to a linear distance L0 in the length direction L of the internal electrode layer 30 in the predetermined region. Note that the predetermined region when calculating the amount of waviness of the intermediate electrode layer 33 in the series connection region MG is the region of the series connection region MG, and the predetermined region when calculating the amount of waviness of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in the capacitor effective portion 11E1 is the region of the corresponding capacitor effective portion 11E1.

[0084] FIG. 5 is an LT cross-sectional view that schematically shows, as an example of the internal electrode layer 30, an intermediate electrode layer 33 as the internal electrode layer 30 in the series connection region MG.

[0085] 5, the internal electrode layers 30 of this embodiment have a wave-like shape and have undulations. The internal electrode layers 30 have undulations and exist over a range of a distance d in the stacking direction. For example, this distance d may be twice or more the thickness t of the internal electrode layers 30.

[0086] 5 shows the linear distance L0 in the length direction L of the intermediate electrode layer 33 serving as the internal electrode layer 30 in the series connection region MG serving as the predetermined region. Also shown is the length L1 measured along the cross-sectional shape of the intermediate electrode layer 33 serving as the internal electrode layer 30 in the series connection region MG serving as the predetermined region. The amount of waviness of the intermediate electrode layer 33 in the series connection region MG is calculated from the ratio (L1 / L0) of the length L1 to the linear distance L0. The amount of waviness of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in the capacitor effective portion 11E1 is calculated in a similar manner.

[0087] The waviness of the intermediate electrode layer 33 in the series connection region MG is preferably 100.1% or more and 100.8% or less. The waviness of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in the capacitor effective portion 11E1 is preferably more than 100.0% and 100.5% or less.

[0088] As described above, a high-dielectric-constant material is used for the dielectric layers 20 of the multilayer ceramic capacitor 1, and when a voltage is applied between the external electrodes 40 of the multilayer ceramic capacitor 1, an electrostrictive effect occurs in which the dielectric layers 20 expand in the electric field direction and contract in a direction perpendicular to the electric field direction, causing deformation. In this case, the amount of deformation due to the electrostrictive effect increases as the amount of the internal electrode layers 30 increases. Compared to a normal structure, the series structure has a larger amount of internal electrode layers 30, so the amount of deformation due to the electrostrictive effect increases, and there is a greater concern about cracking and noise.

[0089] In this embodiment, the amount of waviness of the intermediate electrode layer 33 in the series connection region MG is larger than the amount of waviness of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in the capacitor effective portion 11E1. When a voltage is applied between the external electrodes 40 of the multilayer ceramic capacitor 1, the internal electrode layer 30 in which an electric field is generated has waviness, so it is possible to shift the local electric field direction near the surface of the internal electrode layer 30. In particular, by shifting the electric field direction in a region near the center in the length direction L of the laminate where a force of delamination between layers is likely to act due to the electrostrictive effect, it is possible to cancel out or weaken strains due to the electrostrictive effect in nearby regions.

[0090] Therefore, the influence of strain due to the electrostrictive effect can be suppressed across the dielectric layer 20 as a whole, thereby achieving the effect of suppressing cracks and noise due to electrostriction. If the waviness of the internal electrode layer 30 is too large, the dielectric layer may become locally thin in some areas, resulting in a decrease in insulation resistance and an inability to ensure a long high-temperature load life. Therefore, the waviness of the intermediate electrode layer 33 in the series connection region MG is preferably 100.1% or more and 100.8% or less, and the waviness of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in the capacitor effective portion 11E1 is preferably greater than 100.0% and 100.5% or less. Compared to the series connection region MG, the capacitor effective portion 11E1 is more susceptible to excessively large waviness, making it more likely that the dielectric layer will become locally thin in some areas. Therefore, it is preferable that the amount of waviness of the first internal electrode layer 31, the second internal electrode layer 32 and the intermediate electrode layer 33 in the capacitor effective portion 11E1 is smaller than the amount of waviness of the intermediate electrode layer 33 in the series connection region MG.

[0091] In addition, the distance Lm in the longitudinal direction L of the series connection region MG, in which the portion of the internal electrode layer 30 having a larger waviness than the internal electrode layer 30 in the capacitor effective portion 11E1 is arranged, may be longer than the distance La in the longitudinal direction L of the first end face side outer layer portion LG1 and the distance Lb in the longitudinal direction L of the second end face side outer layer portion LG2.

[0092] <Method for measuring the amount of waviness> A method for measuring the amount of waviness will be described below.

[0093] First, the multilayer ceramic capacitor 1 is polished from the first side surface WS1 or the second side surface WS2 to expose the LT cross section where the series capacitor forming portion 11E of the laminate 10 is exposed. If necessary, the exposed LT cross section at the observation position is etched to remove the internal electrode layers 30 that have been stretched by polishing. Of the LT cross section at the center in the width direction W, measurement points M1 to M6, which will be described later, are observed using an optical microscope.

[0094] Measurement points are set in the capacitor effective portion 11E1 and the series connection region MG. In this embodiment, measurement points M1 to M6 are set in the first capacitor portion CAP1 and the second capacitor portion CAP2 as the capacitor effective portion, and in the series connection region MG including the coupling portion E0. Measurement points M1 to M3 are set on the first main surface TS1 side of the inner layer portion 11, and measurement points M4 to M6 are set on the second main surface TS2 side of the inner layer portion 11.

[0095] Measurement points M1 and M4 are set in an area including the first opposing portion EA of the first internal electrode layer 31 in the first capacitor portion CAP1 and the first electrode layer side opposing portion ECA of the intermediate electrode layer 33. Measurement point M1 is set on the first main surface TS1 side of the inner layer portion 11, and measurement point M4 is set on the second main surface TS2 side of the inner layer portion 11.

[0096] Measurement points M2 and M5 are set in a region in the series connection region MG that includes the coupling portion E0 of the intermediate electrode layer 33. Measurement point M2 is set on the first main surface TS1 side of the inner layer portion 11, and measurement point M5 is set on the second main surface TS2 side of the inner layer portion 11.

[0097] Measurement points M3 and M6 are set in a region including the second opposing portion EB of the second internal electrode layer 32 in the second capacitor portion CAP2 and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33. Measurement point M3 is set on the first main surface TS1 side of the inner layer portion 11, and measurement point M6 is set on the second main surface TS2 side of the inner layer portion 11.

[0098] In the case of a multilayer ceramic capacitor having three or more rows as shown in the embodiment described later, it is preferable that the measurement points be set in an area according to the structure, but as in this embodiment, they are set in the capacitor effective portion 11E1 and the series connection area MG.

[0099] The amount of waviness is measured on the exposed LT cross section using an optical microscope. The amount of waviness is measured at the measurement points M1 to M6. The magnification for observing each measurement point is 1000 times.

[0100] The amount of waviness is calculated based on the cross-sectional shape of the internal electrode layer 30 extracted from an optical microscope image, as the ratio (L1 / L0) of the length L1 measured along the cross-sectional shape of the internal electrode layer 30 in a predetermined region to the linear distance L0 in the length direction L of the internal electrode layer 30 in the predetermined region. The length L1 can be obtained by measuring the length along the cross-sectional shape of the internal electrode layer, including the waviness, using, for example, a multi-point mode of image analysis software.

[0101] For example, the waviness amounts of the six internal electrode layers 30 are calculated on the cross section at each measurement point, and the average value is calculated as the waviness amount at each measurement point. Then, the average value of the waviness amounts at a predetermined measurement point is calculated as the waviness amount of the intermediate electrode layer 33 in the series connection region MG, and the waviness amounts of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in the capacitor effective portion 11E1.

[0102] Specifically, when measuring the amount of waviness of the intermediate electrode layer 33 in the series connection region MG, the amount of waviness of the intermediate electrode layer 33 in the series connection region MG is measured at measurement points M2 and M5, and the average value is calculated as the amount of waviness of the intermediate electrode layer 33 in the series connection region MG. When measuring the amount of waviness of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in the capacitor effective portion 11E1, the amount of waviness of each electrode layer in the capacitor effective portion 11E1 is calculated at measurement points M1, M3, M4, and M6, and the average value is calculated as the amount of waviness of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in the capacitor effective portion 11E1.

[0103] <Manufacturing method> Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0104] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0105] On the dielectric sheets, a conductive paste for the internal electrode layers 30 is printed in a predetermined pattern by, for example, screen printing or gravure printing. As a result, a dielectric sheet on which the patterns of the first internal electrode layers 31 and the second internal electrode layers 32 are formed, and a dielectric sheet on which the pattern of the intermediate electrode layers 33 is formed are respectively prepared. Note that the printing method is not limited to screen printing or the like.

[0106] A predetermined number of dielectric sheets on which the patterns of the internal electrode layers 30 are not printed are stacked to form a portion that will become the first main surface side outer layer portion 12 on the first main surface TS1 side.

[0107] Next, the portion that will become the inner layer portion 11 is formed by sequentially laminating screen-printed dielectric sheets on the surface of the portion that will become the first main surface side outer layer portion 12.

[0108] Pressure is applied sequentially each time a screen-printed dielectric sheet is stacked. The dielectric sheet has areas where the conductive paste is applied and areas where it is not, and the overall thickness is not uniform. Therefore, when a dielectric sheet on which the patterns of the first internal electrode layer 31 and the second internal electrode layer 32 are formed is stacked with a dielectric sheet on which the pattern of the intermediate electrode layer 33 is formed, a space equal to the thickness of the conductive paste is generated between the two dielectric sheets in the area where the conductive paste is not applied to either of the two dielectric sheets. When pressure is applied in the thickness direction to a part of this area, the dielectric sheet distorts to fill the space. At this time, stacking while applying uneven pressure causes wrinkles to form in the dielectric sheet.

[0109] A predetermined number of dielectric sheets, on which the pattern of the internal electrode layer 30 is not printed, are laminated on the surface of the portion that will become the inner layer portion 11, thereby forming a portion that will become the second principal surface side outer layer portion 13 on the second principal surface TS2 side. In this way, a laminated sheet is produced.

[0110] The laminated sheets are pressed in the height direction using a means such as a hydrostatic press to produce a laminated block. Here, wrinkles generated during lamination of the dielectric sheets are retained to a certain extent even after compression bonding by pressing, which can cause undulations in the elements of the dielectric layer 20.

[0111] The laminated block is cut to a predetermined size to cut out laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0112] The laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.

[0113] A conductive paste that will become a base electrode layer is applied to both end surfaces of the laminate 10 .

[0114] The above is an example of the manufacturing method, and the method is not limited to this. The base electrode layer can also be removed after the baking treatment for adjustment.

[0115] In this embodiment, the base electrode layer is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0116] When the unfired laminated chip and the conductive paste applied to the laminated chip are simultaneously fired, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the unfired laminated chip, and the laminated chip and the conductive paste applied to the laminated chip are simultaneously fired to form the laminate 10 with the fired layer.

[0117] Thereafter, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Furthermore, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and an Sn plating layer are formed as the plating layers. Either electrolytic plating or electroless plating may be used for the plating process.

[0118] However, electroless plating has the disadvantage of requiring pretreatment with a catalyst to improve plating deposition speed, which makes the process more complicated. Therefore, electrolytic plating is usually preferred. The Ni plating layer and Sn plating layer are formed sequentially, for example, by barrel plating.

[0119] When a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be disposed so as to cover the baked layer. When providing the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the baked layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to thermally harden, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, the oxygen concentration is preferably 100 ppm or less.

[0120] Through these manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0121] <Second embodiment> 1 to 4B. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a triple structure as shown in FIG. 6, and the effects of the present disclosure can be obtained.

[0122] The multilayer ceramic capacitor 1 according to the second embodiment will be described below with reference to Fig. 6. In the following description, detailed description of the same configuration as in the first embodiment may be omitted. Fig. 6 is a schematic diagram for explaining the general configuration of the triple-structure multilayer ceramic capacitor according to the second embodiment.

[0123] The multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the configuration of the internal electrode layers 30 inside the laminate 10 and the external electrodes 40. Specifically, the multilayer ceramic capacitor 1 according to the first embodiment has a double structure internal electrode layers 30, whereas the multilayer ceramic capacitor 1 according to the second embodiment has a triple structure internal electrode layers 30, and the configuration of the internal electrode layers 30 inside the laminate 10 differs from that of the first embodiment.

[0124] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductor layers, multiple second internal electrode layers 32 as multiple second internal conductor layers, and an intermediate electrode layer 33.

[0125] As shown in FIG. 6, the intermediate electrode layer 33 according to the second embodiment includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332.

[0126] The first intermediate electrode layer 331 has a first electrode layer side facing portion EC1A, a first intermediate electrode layer facing portion EC1B, and a first connecting portion E10. The first electrode layer side facing portion EC1A is a region facing the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, and is located inside the laminate 10. The first intermediate electrode layer facing portion EC1B is a region facing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T, and is located inside the laminate 10. The first connecting portion E10 is a portion connecting the first electrode layer side facing portion EC1A and the first intermediate electrode layer facing portion EC1B, and is located between the first electrode layer side facing portion EC1A and the first intermediate electrode layer facing portion EC1B.

[0127] The second intermediate electrode layer 332 has a second electrode layer side facing portion EC2A, a second intermediate electrode layer facing portion EC2B, and a second connecting portion E20. The second electrode layer side facing portion EC2A faces the second internal electrode layer 32 arranged adjacent to it in the stacking direction T. The second intermediate electrode layer facing portion EC2B faces the first intermediate electrode layer 331 arranged adjacent to it in the stacking direction T. The second connecting portion E20 connects the second electrode layer side facing portion EC2A and the second intermediate electrode layer facing portion EC2B, and is arranged between the second electrode layer side facing portion EC2A and the second intermediate electrode layer facing portion EC2B.

[0128] 6, in the multilayer ceramic capacitor 1 according to the second embodiment, the first internal electrode layer 31 and the second intermediate electrode layer 332 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the second embodiment, the second internal electrode layer 32 and the first intermediate electrode layer 331 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the second embodiment, the first internal electrode layer 31 and the second intermediate electrode layer 332, and the second internal electrode layer 32 and the first intermediate electrode layer 331 are stacked alternately with the dielectric layer 20 interposed therebetween.

[0129] In this embodiment, the first opposing portion EA and the first electrode layer side opposing portion EC1A face each other via the dielectric layer 20, thereby forming a capacitance CAP1 (first capacitor portion CAP1). The second opposing portion EB and the second electrode layer side opposing portion EC2A face each other via the dielectric layer, thereby forming a capacitance CAP2 (second capacitor portion CAP2). The first intermediate electrode layer opposing portion EC1B and the second intermediate electrode layer opposing portion EC2B face each other via the dielectric layer 20, thereby forming a capacitance CAP3 (third capacitor portion CAP3). The first connecting portion E10 connects the capacitance CAP1 and the capacitance CAP3 in series. The second connecting portion E20 connects the capacitance CAP2 and the capacitance CAP3 in series. The multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 with a so-called triplet series structure in which three capacitor portions are connected in series.

[0130] The laminate 10 has a series capacitor-forming portion 11E. The series capacitor-forming portion 11E includes a portion that forms capacitance CAP1, a portion that forms capacitance CAP2, a portion that forms capacitance CAP3, a portion that connects capacitances CAP1 and CAP3 in series, and a portion that connects capacitances CAP2 and CAP3 in series. The series capacitor-forming portion 11E is configured as a part of the inner layer portion 11. Of the series capacitor-forming portion 11E, the portion that forms capacitance CAP1 (first capacitor portion CAP1), the portion that forms capacitance CAP2 (second capacitor portion CAP2), and the portion that forms capacitance CAP3 (third capacitor portion CAP3) are also referred to as effective capacitor portions.

[0131] The series capacitor forming portion 11E of the laminate 10 has a series connection region MG. The series connection region MG has a first series connection region MG1 as a first intermediate gap and a second series connection region MG2 as a second intermediate gap. The first series connection region MG1 is a portion that includes the dielectric layer 20 and the first coupling portion E10 and is located between the portion that forms the capacitance CAP1 and the portion that forms the capacitance CAP3. The second series connection region MG2 is a portion that includes the dielectric layer 20 and the second coupling portion E20 and is located between the portion that forms the capacitance CAP2 and the portion that forms the capacitance CAP3. In other words, the first series connection region MG1 is an aggregate of the portions of the multiple dielectric layers 20 that overlap with the first coupling portion E10 when viewed from the stacking direction T, and the multiple first coupling portions E10. The second series connection region MG2 is an aggregate of portions of the plurality of dielectric layers 20 that overlap with the second coupling portion E20 when viewed from the stacking direction T, and the plurality of second coupling portions E20.

[0132] As shown in FIG. 6, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0133] The first connecting portion E10 connects the capacitances CAP1 and CAP3 in series. The second connecting portion E20 connects the capacitances CAP2 and CAP3 in series. Therefore, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0134] In the multilayer ceramic capacitor 1 according to the second embodiment, the amount of waviness of the intermediate electrode layer 33 in the first series connection region MG1 and the second series connection region MG2 is greater than the amount of waviness of the first internal electrode layer 31, the second internal electrode layer 32 and the intermediate electrode layer 33 in the capacitor effective portion 11E1.

[0135] For example, the waviness of the first intermediate electrode layer 331 in the first series connection region MG1 is preferably 100.1% or more and 100.8% or less, and the waviness of the second intermediate electrode layer 332 in the second series connection region MG2 is preferably 100.1% or more and 100.8% or less.

[0136] In addition, it is preferable that the waviness of the first internal electrode layer 31, the second internal electrode layer 32, the first intermediate electrode layer 331 and the second intermediate electrode layer 332 of the intermediate electrode layer 33 in the capacitor effective portion 11E1 is greater than 100.0% and not more than 100.5%.

[0137] Furthermore, the distance Lm1 in the length direction L of the first series connection region MG1 may be longer than the distance La in the length direction L of the first end face side outer layer portion LG1 and the distance Lb in the length direction L of the second end face side outer layer portion LG2. The distance Lm2 in the length direction L of the second series connection region MG2 may be longer than the distance La in the length direction L of the first end face side outer layer portion LG1 and the distance Lb in the length direction L of the second end face side outer layer portion LG2.

[0138] In the multilayer ceramic capacitor 1 according to the second embodiment, the influence of strain due to the electrostrictive effect can also be suppressed across the dielectric layers 20 as a whole, and the effect of suppressing cracks and noise due to electrostriction can be obtained.

[0139] <Third embodiment> 1 to 4B. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a four-layer structure as shown in FIG. 7, and the effects of the present disclosure can be obtained.

[0140] The multilayer ceramic capacitor 1 according to the third embodiment will be described below with reference to Fig. 7. In the following description, detailed description of the same configuration as in the first embodiment will be omitted. Fig. 7 is a schematic diagram for explaining the general configuration of the four-layer structure multilayer ceramic capacitor according to the third embodiment.

[0141] The multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the configuration of the internal electrode layers 30 inside the laminate 10 and the external electrodes 40. Specifically, while the multilayer ceramic capacitor 1 according to the first embodiment has a double structure for the internal electrode layers 30, the multilayer ceramic capacitor 1 according to the third embodiment has a quadruple structure for the internal electrode layers 30 inside the laminate 10, and the configuration of the internal electrode layers 30 inside the laminate 10 differs from that of the first embodiment.

[0142] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductor layers, multiple second internal electrode layers 32 as multiple second internal conductor layers, and an intermediate electrode layer 33.

[0143] As shown in FIG. 7, the intermediate electrode layer 33 includes a first intermediate electrode layer 331 , a second intermediate electrode layer 332 , and a third intermediate electrode layer 333 .

[0144] The first intermediate electrode layer 331 has a first electrode layer side opposing portion EC1A opposing the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, a first intermediate electrode layer opposing portion EC1B opposing the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T, and a first connecting portion E10.

[0145] The second intermediate electrode layer 332 has a second electrode layer side opposing portion EC2A that faces the second internal electrode layer 32 arranged adjacent to it in the stacking direction T, a second intermediate electrode layer opposing portion EC2B that faces the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T, and a second connecting portion E20.

[0146] The third intermediate electrode layer 333 has a third intermediate electrode layer opposing portion EC3A opposing the first intermediate electrode layer 331 arranged adjacent to it in the stacking direction T, a fourth intermediate electrode layer opposing portion EC3B opposing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T, and a third connecting portion E30.

[0147] 7, in the multilayer ceramic capacitor 1 according to the third embodiment, the first internal electrode layer 31, the third intermediate electrode layer 333, and the second internal electrode layer 32 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the third embodiment, the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are arranged adjacent to each other in the length direction L.

[0148] In the multilayer ceramic capacitor 1 of the third embodiment, the first internal electrode layer 31, the third intermediate electrode layer 333 and the second internal electrode layer 32, and the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are stacked alternately with the dielectric layer 20 interposed therebetween.

[0149] In this embodiment, the first opposing portion EA and the first electrode layer side opposing portion EC1A face each other via the dielectric layer 20, thereby forming a capacitance CAP1 (first capacitor portion CAP1). The second opposing portion EB and the second electrode layer side opposing portion EC2A face each other via the dielectric layer 20, thereby forming a capacitance CAP2 (second capacitor portion CAP2). The first intermediate electrode layer opposing portion EC1B and the third intermediate electrode layer opposing portion EC3A face each other via the dielectric layer 20, thereby forming a capacitance CAP3 (third capacitor portion CAP3). The second intermediate electrode layer opposing portion EC2B and the fourth intermediate electrode layer opposing portion EC3B face each other via the dielectric layer 20, thereby forming a capacitance CAP4 (fourth capacitor portion CAP4). The first connecting portion E10 connects the capacitance CAP1 and the capacitance CAP3 in series. The second connecting portion E20 connects the capacitance CAP2 and the capacitance CAP4 in series. The third coupling portion E30 connects the capacitance CAP3 and the capacitance CAP4 in series. The multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 having a so-called four-series structure in which four capacitor units are connected in series.

[0150] The laminate 10 has a series capacitor-forming portion 11E. The series capacitor-forming portion 11E is configured as a part of the inner layer portion 11. Of the series capacitor-forming portion 11E, the portion forming capacitance CAP1 (first capacitor portion CAP1), the portion forming capacitance CAP2 (second capacitor portion CAP2), the portion forming capacitance CAP3 (third capacitor portion CAP3), and the portion forming capacitance CAP4 (fourth capacitor portion CAP4) are also referred to as effective capacitor portions.

[0151] The series capacitor forming portion 11E of the laminate 10 has a series connection region MG. The series connection region MG has a first series connection region MG1 as a first intermediate gap, a second series connection region MG2 as a second intermediate gap, and a third series connection region MG3 as a third intermediate gap. The first series connection region MG1 is a portion that includes the dielectric layer 20 and a first coupling portion E10 and is located between the portion that forms the capacitance CAP1 and the portion that forms the capacitance CAP3. The second series connection region MG2 is a portion that includes the dielectric layer 20 and a second coupling portion E20 and is located between the portion that forms the capacitance CAP2 and the portion that forms the capacitance CAP4. The third series connection region MG3 is a portion that includes the dielectric layer 20 and a third coupling portion E30 and is located between the portion that forms the capacitance CAP3 and the portion that forms the capacitance CAP4.

[0152] That is, the first series connection region MG1 is an aggregate of a plurality of first coupling portions E10 and portions of the plurality of dielectric layers 20 that overlap with the first coupling portion E10 when viewed from the stacking direction T. The second series connection region MG2 is an aggregate of a plurality of second coupling portions E20 and portions of the plurality of dielectric layers 20 that overlap with the second coupling portion E20 when viewed from the stacking direction T. The third series connection region MG3 is an aggregate of a plurality of third coupling portions E30 and portions of the plurality of dielectric layers 20 that overlap with the third coupling portion E30 when viewed from the stacking direction T.

[0153] As shown in FIG. 7, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0154] The first connecting portion E10 connects the capacitances CAP1 and CAP3 in series. The second connecting portion E20 connects the capacitances CAP2 and CAP4 in series. The third connecting portion E30 connects the capacitances CAP3 and CAP4 in series. Therefore, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0155] In the multilayer ceramic capacitor 1 according to the third embodiment, the amount of waviness of the intermediate electrode layer 33 in the first series connection region MG1, the second series connection region MG2, and the third series connection region MG3 is greater than the amount of waviness of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in the capacitor effective portion 11E1.

[0156] For example, the waviness of the first intermediate electrode layer 331 in the first series connection region MG1 may be 100.1% or more and 100.8% or less. The waviness of the second intermediate electrode layer 332 in the second series connection region MG2 may be 100.1% or more and 100.8% or less. The waviness of the third intermediate electrode layer 333 in the third series connection region MG3 may be 100.1% or more and 100.8% or less.

[0157] In addition, the waviness of the first internal electrode layer 31, the second internal electrode layer 32, the first internal electrode layer 331, the second internal electrode layer 332 and the third internal electrode layer 333 of the internal electrode layer 33 in the capacitor effective portion 11E1 may be greater than 100.0% and less than or equal to 100.5%.

[0158] Furthermore, the distance Lm1 in the length direction L of the first series connection region MG1 may be longer than the distance La in the length direction L of the first end face side outer layer portion LG1 and the distance Lb in the length direction L of the second end face side outer layer portion LG2. The distance Lm2 in the length direction L of the second series connection region MG2 may be longer than the distance La in the length direction L of the first end face side outer layer portion LG1 and the distance Lb in the length direction L of the second end face side outer layer portion LG2. The distance Lm3 in the length direction L of the third series connection region MG3 may be longer than the distance La in the length direction L of the first end face side outer layer portion LG1 and the distance Lb in the length direction L of the second end face side outer layer portion LG2.

[0159] In the multilayer ceramic capacitor 1 according to the third embodiment, the influence of strain due to the electrostrictive effect can also be suppressed across the dielectric layers 20 as a whole, and the effect of suppressing cracks and noise due to electrostriction can be obtained.

[0160] The multilayer ceramic capacitor 1 according to the embodiment described above has the following advantages. In a typical multilayer ceramic capacitor, the external electrodes 40 are disposed on the end faces of the laminate 10, which is made up of alternately stacked dielectric layers 20 and internal electrode layers 30. In particular, a multilayer ceramic capacitor for medium to high voltage applications employs a series structure that introduces, in addition to the internal electrode layers 30 exposed on the end faces, intermediate electrode layers 33 that are not exposed on the end faces, thereby dispersing the voltage applied to the dielectric layers 20, which are elements, and improving voltage resistance.

[0161] However, the dielectric layers 20 in multilayer ceramic capacitors are made of high-dielectric-constant materials, which are generally known to undergo an electrostrictive effect, expanding in the direction of the electric field and contracting in the direction perpendicular to the electric field. When the inverse piezoelectric effect occurs, the dielectric layers 20 are unable to withstand the expanding stress, causing parallel cracks to form in the dielectric layers 20 near the center of the stacking direction T. Furthermore, repeated expansion and contraction due to the application of a DC voltage can cause the mounting board to vibrate, resulting in acoustic noise. Furthermore, it is known that the stress increases as the number of stacked element layers, i.e., the number of internal electrode layers 30, increases, which poses a barrier to multilayering.

[0162] Multilayer ceramic capacitors in the medium-to-high voltage range, in particular, use a series structure to distribute the voltage applied to each element, but to reduce the voltage applied to each element without changing the capacitance, it is necessary to increase the number of layers in accordance with the number of series.As a result, with a series structure, it is necessary to increase the number of layers compared to a normal structure, which increases the stress generated and makes problems such as cracking and squealing more pronounced.

[0163] According to the present disclosure, when a voltage is applied to the multilayer ceramic capacitor 1, which is a multilayer chip, the local electric field direction can be shifted to suppress electric field concentration in the entire multilayer chip, thereby having the effect of suppressing electrostriction and acoustic noise.

[0164] The multilayer ceramic capacitor 1 according to this embodiment includes a laminate 10 including a plurality of laminated dielectric layers 20 and a plurality of laminated internal electrode layers 30, and including a first main surface TS1 and a second main surface TS2 facing in a stacking direction T, a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T and the width direction W, a first external electrode 40A arranged on the first end surface LS1, and a second external electrode 40B arranged on the second end surface LS2. The laminated capacitor 1 includes a plurality of internal electrode layers 30 including a first internal electrode layer 31, a second internal electrode layer 32, and an intermediate electrode layer 33, one end of the first internal electrode layer 31 being drawn to a first end face LS1 and having a first lead portion D1 connected to the first external electrode 40A, and a first opposing portion EA connected to the first lead portion D1 and facing the internal electrode layer 30 arranged adjacently in the stacking direction T, and one end of the second internal electrode layer 32 being drawn to a second end face LS2 and having a second lead portion D2 connected to the second external electrode 40B, and and a second opposing portion EB opposed to the internal electrode layer 30 arranged adjacent to the first external electrode 40A in the stacking direction T, and the intermediate electrode layer 33 is not connected to either the first external electrode 40A or the second external electrode 40B, and is the internal electrode layer 30 which forms a series-connected capacitor element together with the first internal electrode layer 31 and the second internal electrode layer 32. The laminate 10 comprises an inner layer portion 11 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated, a first side surface side outer layer portion WG1 arranged on the first side surface WS1 side of the inner layer portion 11 and in which only the dielectric layers 20 are laminated, and a second side surface side outer layer portion WG2 arranged on the second side surface WS2 side of the inner layer portion 11. and a second side surface side outer layer portion WG2 in which only the dielectric layers 20 are laminated, and the inner layer portion 11 comprises a capacitor effective portion 11E1 (effective layer portion 11E1) in which two layers of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 are alternately laminated with the dielectric layer 20 sandwiched therebetween, a first end surface side outer layer portion LG1 in which the dielectric layers 20 and the first internal electrode layers 31 are alternately laminated, and a second end surface side outer layer portion LG2 in which the dielectric layers 20 and the second internal electrode layers 32 are alternately laminated, andThe capacitor has a series connection region MG (middle gap MG) where the dielectric layers 20 and the intermediate electrode layers 33 are alternately stacked, and in a cross section on a plane parallel to the length direction L and stacking direction T, when the waviness amount is defined as the ratio (L1 / L0) of the length (L1) measured along the cross-sectional shape of the internal electrode layer 30 in a predetermined region to the linear distance (L0) in the length direction L of the internal electrode layer 30 in the predetermined region, the waviness amount of the intermediate electrode layer 33 in the series connection region MG is larger than the waviness amount of the first internal electrode layer 31, the second internal electrode layer 32 and the intermediate electrode layer 33 in the capacitor effective portion 11E1.

[0165] This makes it possible to provide a multilayer ceramic capacitor 1 that can suppress the occurrence of cracks and noise due to electrostrictive effects, even in a multilayer ceramic capacitor 1 with high voltage resistance specifications.

[0166] In addition, in the multilayer ceramic capacitor 1 according to this embodiment, the waviness of the intermediate electrode layer 33 in the series connection region MG is 100.1% or more and 100.8% or less.

[0167] This makes it possible to provide a multilayer ceramic capacitor 1 that can suppress the occurrence of cracks and noise due to electrostrictive effects while suppressing a decrease in insulation resistance, even in a multilayer ceramic capacitor 1 with high voltage resistance specifications.

[0168] In the multilayer ceramic capacitor 1 according to this embodiment, the waviness of the first internal electrode layer 31, the second internal electrode layer 32 and the intermediate electrode layer 33 in the effective capacitor portion 11E1 is 100.5% or less.

[0169] This makes it possible to provide a multilayer ceramic capacitor 1 that can suppress the occurrence of cracks and noise due to electrostrictive effects while suppressing a decrease in insulation resistance, even in a multilayer ceramic capacitor 1 with high voltage resistance specifications.

[0170] In the multilayer ceramic capacitor 1 according to this embodiment, the distance Lm in the length direction L of the series connection region MG is longer than the distance La in the length direction L of the first lead portion D1 and the distance Lb in the length direction L of the second lead portion D2.

[0171] This makes it possible to provide a multilayer ceramic capacitor 1 that can suppress the occurrence of cracks and noise due to electrostrictive effects, even in a multilayer ceramic capacitor 1 with high voltage resistance specifications.

[0172] In the multilayer ceramic capacitor 1 according to this embodiment, the intermediate electrode layer 33 includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332. The first intermediate electrode layer 331 has a first electrode layer side opposing portion EC1A opposing the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, and a first intermediate electrode layer side opposing portion EC1B opposing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T. The second intermediate electrode layer 332 has a second electrode layer side opposing portion EC2A opposing the second internal electrode layer 32 arranged adjacent to it in the stacking direction T, and a second intermediate electrode layer side opposing portion EC3B opposing the second internal electrode layer 32 arranged adjacent to it in the stacking direction T. The capacitor has a first intermediate electrode layer 331 arranged between the first internal electrode layer 31 and the second intermediate electrode layer 332 and a second intermediate electrode layer opposing portion EC2B opposing the first intermediate electrode layer 331, and the series connection region MG has a first series connection region MG1 located between the first internal electrode layer 31 and the second intermediate electrode layer 332 and a second series connection region MG2 located between the second internal electrode layer 32 and the first intermediate electrode layer 331, and the amount of waviness of the intermediate electrode layer 33 in the first series connection region MG1 and the second series connection region MG2 is greater than the amount of waviness of the first internal electrode layer 31, the second internal electrode layer 32 and the intermediate electrode layer 33 in the capacitor effective portion 11E1.

[0173] This makes it possible to provide a multilayer ceramic capacitor 1 that can suppress the occurrence of cracks and noise due to electrostatic distortion, even in a multilayer ceramic capacitor 1 with a triple structure and high voltage resistance.

[0174] In the multilayer ceramic capacitor 1 according to this embodiment, the intermediate electrode layer 33 includes a first intermediate electrode layer 331, a second intermediate electrode layer 332, and a third intermediate electrode layer 333. The first intermediate electrode layer 331 has a first electrode layer side opposing portion EC1A opposing the first internal electrode layer 31 arranged adjacently in the stacking direction T, and a first intermediate electrode layer opposing portion EC1B opposing the third intermediate electrode layer 333 arranged adjacently in the stacking direction T. The second intermediate electrode layer 332 has a second electrode layer side opposing portion EC2A opposing the second internal electrode layer 32 arranged adjacently in the stacking direction T, and a second intermediate electrode layer opposing portion EC2B opposing the third intermediate electrode layer 333 arranged adjacently in the stacking direction T. 31, and a fourth intermediate electrode layer facing portion EC3B facing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T, and the series connection region MG has a first series connection region MG1 located between the first internal electrode layer 31 and the third intermediate electrode layer 333, a second series connection region MG2 located between the second internal electrode layer 32 and the third intermediate electrode layer 333, and a third series connection region MG3 located between the first intermediate electrode layer 331 and the second intermediate electrode layer 332, and the amount of waviness of the intermediate electrode layer 33 in the first series connection region MG1, the second series connection region MG2 and the third series connection region MG3 is greater than the amount of waviness of the first internal electrode layer 31, the second internal electrode layer 32 and the intermediate electrode layer 33 in the capacitor effective portion 11E1.

[0175] This makes it possible to provide a multilayer ceramic capacitor 1 that can suppress the occurrence of cracks and noise due to electrostrictive effects, even in a multilayer ceramic capacitor 1 with a four-row structure and high voltage resistance specifications.

[0176] The present invention is not limited to the configurations of the above-described embodiments, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0177] <1> a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode disposed on the first end surface; a second external electrode disposed on the second end surface, the plurality of internal electrode layers include a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer, the first internal electrode layer has a first lead portion, one end of which is led out to the first end face and connected to the first external electrode, and a first opposing portion, which is connected to the first lead portion and faces the internal electrode layer disposed adjacent to it in the stacking direction; the second internal electrode layer has a second lead portion, one end of which is led out to the second end face and connected to the second external electrode, and a second opposing portion, which is connected to the second lead portion and faces the internal electrode layer disposed adjacent to it in the stacking direction, the intermediate electrode layer is an internal electrode layer that is not connected to either the first external electrode or the second external electrode, and forms a series-connected capacitor element together with the first internal electrode layer and the second internal electrode layer; the laminate has an inner layer portion in which the dielectric layers and the internal electrode layers are alternately laminated, a first side surface side outer layer portion disposed on the first side surface side of the inner layer portion and in which only the dielectric layers are laminated, and a second side surface side outer layer portion disposed on the second side surface side of the inner layer portion and in which only the dielectric layers are laminated, the inner layer portion includes an effective layer portion in which two layers of the first inner electrode layer, the second inner electrode layer, and the intermediate electrode layer are alternately stacked with the dielectric layer sandwiched therebetween; a first end face side outer layer portion disposed on the first end face side of the inner layer portion and in which the dielectric layers and the first internal electrode layers are alternately laminated, a second end face side outer layer portion disposed on the second end face side of the inner layer portion and in which the dielectric layers and the second internal electrode layers are alternately laminated, and an intermediate gap in which the dielectric layers and the intermediate electrode layers are alternately laminated, In the cross section on a plane parallel to the length direction and stacking direction, When the ratio (L1 / L0) of the length (L1) measured along the cross-sectional shape of the internal electrode layer in a predetermined area to the linear distance (L0) in the longitudinal direction of the internal electrode layer in a predetermined area is defined as the amount of waviness, A multilayer ceramic capacitor, wherein the amount of waviness of the intermediate electrode layer in the intermediate gap is greater than the amount of waviness of the first internal electrode layer, the second internal electrode layer and the intermediate electrode layer in the effective layer portion. <2> The waviness of the intermediate electrode layer in the intermediate gap is 100.1% or more and 100.8% or less. <1> The multilayer ceramic capacitor according to claim 1. <3> The waviness of the first internal electrode layer, the second internal electrode layer and the intermediate electrode layer in the effective layer portion is 100.5% or less. <1> or <2> The multilayer ceramic capacitor according to claim 1. <4> The length of the intermediate gap is longer than the length of the first lead portion and the second lead portion. <1> from <3> 10. The multilayer ceramic capacitor according to claim 9, wherein the first and second electrodes are electrically connected to the first and second electrodes. <5> the intermediate electrode layer includes a first intermediate electrode layer and a second intermediate electrode layer, the first intermediate electrode layer has a first electrode layer side opposing portion opposing the first internal electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, and a first intermediate electrode layer opposing portion opposing the second intermediate electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, the second intermediate electrode layer has a second electrode layer side opposing portion opposing the second internal electrode layer arranged adjacent to the second intermediate electrode layer in the stacking direction, and a second intermediate electrode layer opposing portion opposing the first intermediate electrode layer arranged adjacent to the second intermediate electrode layer in the stacking direction, the intermediate gap includes a first intermediate gap located between the first internal electrode layer and the second intermediate electrode layer, and a second intermediate gap located between the second internal electrode layer and the first intermediate electrode layer, the amount of waviness of the intermediate electrode layer in the first intermediate gap and the second intermediate gap is larger than the amount of waviness of the first internal electrode layer, the second internal electrode layer, and the intermediate electrode layer in the effective layer portion; <1> from <4> 10. The multilayer ceramic capacitor according to claim 9, wherein the first and second electrodes are electrically connected to the first and second electrodes. <6> the intermediate electrode layers include a first intermediate electrode layer, a second intermediate electrode layer, and a third intermediate electrode layer; the first intermediate electrode layer has a first electrode layer side opposing portion opposing the first internal electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, and a first intermediate electrode layer opposing portion opposing the third intermediate electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, the second intermediate electrode layer has a second electrode layer side opposing portion opposing the second internal electrode layer arranged adjacent to the second internal electrode layer in the stacking direction, and a second intermediate electrode layer opposing portion opposing the third intermediate electrode layer arranged adjacent to the second internal electrode layer in the stacking direction, the third intermediate electrode layer has a third intermediate electrode layer facing portion facing the first intermediate electrode layer disposed adjacent to the first intermediate electrode layer in the stacking direction, and a fourth intermediate electrode layer facing portion facing the second intermediate electrode layer disposed adjacent to the first intermediate electrode layer in the stacking direction, the intermediate gaps include a first intermediate gap located between the first internal electrode layer and the third intermediate electrode layer, a second intermediate gap located between the second internal electrode layer and the third intermediate electrode layer, and a third intermediate gap located between the first intermediate electrode layer and the second intermediate electrode layer, the amount of waviness of the intermediate electrode layers in the first intermediate gap, the second intermediate gap, and the third intermediate gap is greater than the amount of waviness of the first internal electrode layers, the second internal electrode layers, and the intermediate electrode layers in the effective layer portion; <1> from <4> 10. The multilayer ceramic capacitor according to claim 9, wherein the first and second electrodes are electrically connected to the first and second electrodes. [Explanation of symbols]

[0178] 1. Multilayer ceramic capacitors 10 Laminate 11 Inner layer 11E1 Capacitor effective part (effective layer part) 20 dielectric layer 30 Internal electrode layer 31 First internal electrode layer 32 Second internal electrode layer 33 Intermediate electrode layer 40A First outer electrode 40B Second external electrode D1 First drawer D2 Second drawer EA First opposing part EB Second opposing part L lengthwise L0 maximum distance L1 distance LG1 First outer layer on the end face side LG2 Second outer layer on the end face side LS1 First end face LS2 Second end face MG series connection area (middle gap) T Stacking direction TS1 First principal surface TS2 Second principal surface W width direction WG1 First side outer layer WG2 Second outer layer on the side WS1 First Aspect WS2 Second Aspect

Claims

1. a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode disposed on the first end surface; a second external electrode disposed on the second end surface, the plurality of internal electrode layers include a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer, the first internal electrode layer has a first lead portion, one end of which is led out to the first end face and connected to the first external electrode, and a first opposing portion, which is connected to the first lead portion and opposed to the internal electrode layer disposed adjacent to it in the stacking direction, the second internal electrode layer has a second lead portion, one end of which is led out to the second end face and connected to the second external electrode, and a second opposing portion, which is connected to the second lead portion and opposed to the internal electrode layer disposed adjacent to it in the stacking direction, the intermediate electrode layer is an internal electrode layer that is not connected to either the first external electrode or the second external electrode, and forms a series-connected capacitor element together with the first internal electrode layer and the second internal electrode layer, the laminate has an inner layer portion in which the dielectric layers and the internal electrode layers are alternately laminated, a first side surface side outer layer portion disposed on the first side surface side of the inner layer portion and in which only the dielectric layers are laminated, and a second side surface side outer layer portion disposed on the second side surface side of the inner layer portion and in which only the dielectric layers are laminated, the inner layer portion includes an effective layer portion in which two layers of the first inner electrode layer, the second inner electrode layer, and the intermediate electrode layer are alternately stacked with the dielectric layer interposed therebetween; a first end face side outer layer portion disposed on the first end face side of the inner layer portion and in which the dielectric layers and the first internal electrode layers are alternately laminated, a second end face side outer layer portion disposed on the second end face side of the inner layer portion and in which the dielectric layers and the second internal electrode layers are alternately laminated, and an intermediate gap in which the dielectric layers and the intermediate electrode layers are alternately laminated, In the cross section on a plane parallel to the length direction and stacking direction, When the ratio (L1 / L0) of the length (L1) measured along the cross-sectional shape of the internal electrode layer in a predetermined region to the linear distance (L0) in the length direction of the internal electrode layer in a predetermined region is defined as the waviness amount, A multilayer ceramic capacitor, wherein the amount of waviness of the intermediate electrode layer in the intermediate gap is greater than the amounts of waviness of the first internal electrode layer, the second internal electrode layer and the intermediate electrode layer in the effective layer portion.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the amount of waviness of said intermediate electrode layer in said intermediate gap is 100.1% or more and 100.8% or less.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein the amount of waviness of said first internal electrode layer, said second internal electrode layer and said intermediate electrode layer in said effective layer portion is 100.5% or less.

4. 3. The multilayer ceramic capacitor according to claim 1, wherein the distance of the intermediate gap in the longitudinal direction is longer than the distance of the first lead portion and the second lead portion in the longitudinal direction.

5. the intermediate electrode layer includes a first intermediate electrode layer and a second intermediate electrode layer; the first intermediate electrode layer has a first electrode layer side opposing portion opposing the first internal electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, and a first intermediate electrode layer opposing portion opposing the second intermediate electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, the second intermediate electrode layer has a second electrode layer side opposing portion opposing the second internal electrode layer arranged adjacent to the second internal electrode layer in the stacking direction, and a second intermediate electrode layer opposing portion opposing the first intermediate electrode layer arranged adjacent to the second internal electrode layer in the stacking direction, the intermediate gap includes a first intermediate gap located between the first internal electrode layer and the second intermediate electrode layer, and a second intermediate gap located between the second internal electrode layer and the first intermediate electrode layer, 2. The multilayer ceramic capacitor according to claim 1, wherein the amount of waviness of the intermediate electrode layers in the first intermediate gap and the second intermediate gap is larger than the amount of waviness of the first internal electrode layers, the second internal electrode layers, and the intermediate electrode layers in the effective layer portion.

6. the intermediate electrode layers include a first intermediate electrode layer, a second intermediate electrode layer, and a third intermediate electrode layer; the first intermediate electrode layer has a first electrode layer side opposing portion opposing the first internal electrode layer arranged adjacent to the first internal electrode layer in the stacking direction, and a first intermediate electrode layer opposing portion opposing the third intermediate electrode layer arranged adjacent to the first internal electrode layer in the stacking direction, the second intermediate electrode layer has a second electrode layer side opposing portion opposing the second internal electrode layer arranged adjacent to the second internal electrode layer in the stacking direction, and a second intermediate electrode layer opposing portion opposing the third intermediate electrode layer arranged adjacent to the second internal electrode layer in the stacking direction, the third intermediate electrode layer has a third intermediate electrode layer facing portion facing the first intermediate electrode layer disposed adjacent to the first intermediate electrode layer in the stacking direction, and a fourth intermediate electrode layer facing portion facing the second intermediate electrode layer disposed adjacent to the first intermediate electrode layer in the stacking direction, the intermediate gaps include a first intermediate gap located between the first internal electrode layer and the third intermediate electrode layer, a second intermediate gap located between the second internal electrode layer and the third intermediate electrode layer, and a third intermediate gap located between the first intermediate electrode layer and the second intermediate electrode layer, 2. The multilayer ceramic capacitor according to claim 1, wherein the amount of waviness of the intermediate electrode layers in the first intermediate gap, the second intermediate gap, and the third intermediate gap is greater than the amount of waviness of the first internal electrode layers, the second internal electrode layers, and the intermediate electrode layers in the effective layer portion.

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