Dimmer and dimming method

Abstract

To provide a dimmer and a dimming method with which it is possible to improve dimming performance.SOLUTION: A dimmer according to the present disclosure comprises a dimming layer, a plurality of first electrodes, a plurality of second electrodes, a row drive circuit, a column drive circuit, and a control circuit. The dimming layer has a first principal plane and a second principal plane. The second principal plane is located on the side reverse from the first principal plane. Each of the plurality of first electrodes extends in the row direction. The plurality of first electrodes face the first principal plane. Each of the plurality of second electrodes extends in the column direction. The plurality of second electrodes face the second principal plane. The row drive circuit is capable of applying a voltage to the first electrodes. The column drive circuit is capable of applying a voltage to the second electrodes. The control circuit adjusts the timing of either the voltage that the row drive circuit applies to the first electrodes or the voltage that the column drive circuit applies to the second electrodes.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a light control device and a light control method. [Background technology]

[0002] The light control device can transmit or attenuate external light from the backside, and it is desirable to improve the light control performance of the light control device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-162262 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a dimming device and a dimming method that can improve dimming performance. [Means for solving the problem]

[0005] A light control device according to the present disclosure includes a light control layer, a plurality of first electrodes, a plurality of second electrodes, a row drive circuit, a column drive circuit, and a control circuit. The light control layer has a first main surface and a second main surface. The second main surface is disposed on the opposite side of the first main surface. The plurality of first electrodes each extend in the row direction. The plurality of first electrodes face the first main surface. The plurality of second electrodes each extend in the column direction. The plurality of second electrodes face the second main surface. The row drive circuit is capable of applying a voltage to the first electrodes. The column drive circuit is capable of applying a voltage to the second electrodes. The control circuit adjusts the timing of either the voltage applied by the row drive circuit to the first electrodes or the voltage applied by the column drive circuit to the second electrodes. [Effects of the Invention]

[0006] The dimming device and dimming method according to the present disclosure can improve dimming performance. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a light control device according to an embodiment. [Figure 2] FIG. 1 is a perspective view showing a configuration of a light control panel according to an embodiment. [Figure 3] FIG. 2 is a plan view showing a plurality of regions partitioned by a light control panel in the embodiment. [Figure 4] 5A and 5B are diagrams showing characteristics of a light-adjusting liquid crystal display according to the embodiment. [Figure 5] FIG. 2 is a block diagram showing the configuration of an arithmetic circuit according to the embodiment. [Figure 6] FIG. 10 is a diagram showing calculation of a load amount in the embodiment. [Figure 7] FIG. 10 is a diagram showing an estimation of a delay amount in the embodiment. [Figure 8] FIG. 2 is a block diagram showing the configuration of a column electrode drive circuit (or a row electrode drive circuit) in the embodiment. [Figure 9] FIG. 2 is a block diagram showing the configuration of a delay amount selection circuit according to the embodiment. [Figure 10] 5A and 5B are waveform diagrams showing the operation of a delay amount selection circuit in the embodiment. [Figure 11] FIG. 4 is a waveform diagram showing fluctuations in the voltage applied to the light-control layer in the embodiment. [Figure 12] FIG. 10 is a diagram showing an estimation of a delay amount in a first modified example of the embodiment. [Figure 13] FIG. 10 is a block diagram showing the configuration of a column electrode drive circuit (or a row electrode drive circuit) in a second modified example of the embodiment. [Figure 14] FIG. 10 is a circuit diagram showing the configuration of a delay amount selection circuit according to a second modified example of the embodiment. [Figure 15] FIG. 10 is a waveform diagram showing the operation of a delay amount selection circuit according to a second modified example of the embodiment. [Figure 16] FIG. 10 is a block diagram showing the configuration of a column electrode drive circuit (or a row electrode drive circuit) in a third modified example of the embodiment. [Figure 17]FIG. 10 is a waveform diagram showing the operations of the current detection circuit and the AD conversion circuit according to the third modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of a light control device according to the present disclosure will be described with reference to the drawings.

[0009] (Embodiment) The light control device according to the embodiment can transmit or attenuate external light from the rear surface, but is devised to improve the light control performance.

[0010] The light control device 1 can be configured as shown in Fig. 1. Fig. 1 is a block diagram showing the configuration of the light control device 1.

[0011] The light control device 1 can two-dimensionally control light by transmitting or attenuating external light from the rear surface.

[0012] In this specification, a state in which a dimmer transmits external light is referred to as an on state, and a state in which a dimmer attenuates external light is referred to as an off state. Attenuating external light can also be said to block light. Furthermore, when a portion of a dimmer transmits external light, that portion is referred to as being in an on state, and that portion may be referred to as a transmissive region. Similarly, when a portion of a dimmer attenuates external light, that portion is referred to as being in an off state, and that portion may be referred to as a shading region.

[0013] In this specification, when a first element and a second element are "electrically connected," this includes a connection between the first element and the second element via a third element interposed therebetween, as long as the respective functions of the first element and the second element are not impeded.

[0014] The light control device 1 can be communicatively connected to an analysis device 201. The analysis device 201 receives a request for light control from a higher-level controller. The request may be, for example, an illuminance distribution relative to external light, or a request for the two-dimensional position of an area to be blocked. The analysis device 201 analyzes the request for light control, generates a light control signal according to the analysis result, and supplies the signal to the light control device 1. The light control device 1 has multiple areas to be dimmed, and can determine whether each of the multiple areas should be a light-transmitting area or a light-blocking area according to the light control signal.

[0015] The light control device 1 includes a light control panel 2, a row electrode drive circuit 3, a column electrode drive circuit 4, an arithmetic circuit 5, a reference voltage generation circuit 6, and a timing generation circuit .

[0016] As shown in Fig. 2, the light control panel 2 has a light control layer 21, a plurality of column electrodes EY1 to EY8, and a plurality of row electrodes EX1 to EX4. Fig. 2 is a perspective view showing the configuration of the light control panel 2. In Fig. 2, the direction perpendicular to the surface of the light control panel 2 is the Z direction, the longitudinal direction of the light control panel 2 is the X direction, and the direction perpendicular to the X and Z directions is the Y direction. Fig. 2 illustrates eight column electrodes EY1 to EY8, but the number of column electrodes EY may be two to seven, or nine or more. Fig. 2 illustrates four row electrodes EX1 to EX4, but the number of row electrodes EX may be two to three, or five or more.

[0017] The light-controlling layer 21 extends in a substantially plate-like shape in the XY directions. The light-controlling layer 21 may be configured by sealing a light-controlling liquid crystal 21b in a plate-shaped member 21a. The light-controlling layer 21 has a front surface on the +Z side and a back surface on the -Z side. The +Z side surface of the box-shaped member 21a may form the front surface of the light-controlling layer 21, and the -Z side surface of the member 21a may form the back surface of the light-controlling layer 21.

[0018] The plurality of column electrodes EY1 to EY8 are arranged on the +Z side of the light control layer 21. The plurality of column electrodes EY1 to EY8 may be arranged on a substrate 22 arranged on the front surface of the light control layer 21. The substrate 22 may be adhered to the front surface of the light control layer 21 via an adhesive or the like. The substrate 22 extends in a plate shape in the X and Y directions. Each column electrode EY may be made of a transparent conductive material such as ITO. The substrate 22 may be made of a transparent insulating resin or the like.

[0019] On the substrate 22, the multiple column electrodes EY1 to EY8 are insulated from one another by insulating portions 22a and insulating portions 22b and are arranged in the X direction. As a result, the multiple column electrodes EY1 to EY8 are arranged in the X direction along the front surface of the light control layer 21. On the substrate 22, each column electrode EY extends in the Y direction. The insulating portions 22a extend in the Y direction between the multiple column electrodes EY1 to EY8. The insulating portions 22b extend in the X direction and connect the +Y side ends of the multiple insulating portions 22a.

[0020] The row electrodes EX1 to EX4 are arranged on the -Z side of the light control layer 21. The row electrodes EX1 to EX4 may be arranged on a substrate 23 arranged on the back surface of the light control layer 21. The row electrodes EX1 to EX4 face the column electrodes EY1 to EY8 with the light control layer 21 in between. The substrate 23 may be attached to the back surface of the light control layer 21 via an adhesive or the like. The substrate 23 extends in a plate shape in the X and Y directions. Each row electrode EX may be made of a transparent conductive material such as ITO. The substrate 23 may be made of a transparent insulating resin or the like.

[0021] On the substrate 23, the row electrodes EX1 to EX4 are insulated from one another by the insulating portions 23a and 23b and are arranged in the Y direction. As a result, the row electrodes EX1 to EX4 are arranged in the Y direction along the front surface of the light-switching layer 21. On the substrate 23, each row electrode EX extends in the X direction. The insulating portions 23a extend in the X direction between the row electrodes EX1 to EX4. The insulating portions 23b extend in the Y direction and connect the +X side ends of the insulating portions 23a.

[0022] In the light-controlling layer 21, a plurality of regions R(1,1) to R(8,4) as shown in Fig. 3 are defined at a plurality of intersection positions of the plurality of column electrodes EY1 to EY8 and the plurality of row electrodes EX1 to EX4. Fig. 3 is a plan view showing a plurality of regions R(1,1) to R(8,4) defined in the light-controlling panel 2.

[0023] The light-switching layer 21 includes a plurality of regions R(1,1) to R(8,4) partitioned in a matrix. Each row extends in the X direction, and each column extends in the Y direction. The X direction can also be referred to as the row direction, and the Y direction as the column direction.

[0024] Region R(1,1) is formed at a position where the column electrode EY1 and row electrode EX1 intersect when viewed from the Z direction in the light-control layer 21. A voltage is applied to region R(1,1) from the column electrode EY1 on the +Z side, and a voltage is applied to region R(1,1) from the row electrode EX1 on the -Z side.

[0025] Region R(2,1) is formed at a position where the column electrode EY2 and row electrode EX1 intersect when viewed from the Z direction in the light-control layer 21. A voltage is applied to region R(2,1) from the column electrode EY2 on the +Z side, and a voltage is applied to region R(2,1) from the row electrode EX1 on the -Z side.

[0026] Region R(8,4) is formed at a position where the column electrode EY8 and row electrode EX4 intersect when viewed from the Z direction in the light-control layer 21. A voltage is applied to region R(8,4) from the column electrode EY8 on the +Z side, and a voltage is applied to region R(8,4) from the row electrode EX4 on the -Z side.

[0027] The light control device 1 can control the on / off state of each of the multiple regions R(1,1) to R(8,4). The regions R that are controlled to be in the on state may be called transmissive regions. The regions R that are controlled to be in the off state may be called light-blocking regions.

[0028] In FIG. 3, the row electrode drive circuit 3 supplies a voltage V A ,V B ,V B ,V AThe column electrode drive circuit 4 applies a voltage V to each of the column electrodes EY1, EY2, EY3, EY4, EY5, EY6, EY7, and EY8. C ,V B ,V B ,V C ,V C ,V B ,V C ,V A Apply a voltage V A ,V B ,V C may be different from each other.

[0029] As a result, the light control device 1 attempts to apply a substantially uniform voltage to both ends in the Z direction to the regions R(8,1), R(2,2), R(3,2), R(6,2), R(2,3), R(3,3), R(6,3), and R(8,4) among the multiple regions R(1,1) to R(8,4). If a substantially uniform voltage is applied to both ends in the Z direction, a light-blocking pattern can be realized in which the regions R(8,1), R(2,2), R(3,2), R(6,2), R(2,3), R(3,3), R(6,3), and R(8,4) in the light control layer 21 are selectively turned off, as illustrated in FIG.

[0030] For example, a high contrast ratio is required for a display that displays an image, and an STN (Super Twisted Nematic) liquid crystal that is used together with a polarizing plate and can ensure a high contrast ratio can be used.

[0031] On the other hand, it is useful for the light control device 1 to have high transmittance in the on state where external light is transmitted. Therefore, the light control layer 21 of the light control panel 2 can use a light control liquid crystal 21b that does not require a polarizing plate and can ensure high transmittance. The light control liquid crystal 21b includes a GH (Guest Host) liquid crystal. The GH liquid crystal may be a liquid crystal in which a dichroic dye is added to a twisted liquid crystal material. The dichroic dye is a dye that has anisotropic absorption characteristics.

[0032] For example, the characteristics of the change in transmittance with respect to the applied voltage for the light-control liquid crystal (e.g., GH liquid crystal) 21b and the STN liquid crystal are shown in Figure 4. In Figure 4, the vertical axis represents the magnitude of the transmittance, which is the relative value when the transmittance in the on state is the same, and the horizontal axis represents the magnitude of the effective voltage applied to the liquid crystal.

[0033] 4, the change characteristics when the light control liquid crystal 21b is a GH liquid crystal are shown by a solid line, and the change characteristics of an STN liquid crystal are shown by a dotted line as a comparative example. The change characteristics of both the light control liquid crystal 21b and the STN liquid crystal are shown as examples of a normally black mode in which the transmittance is low when the effective voltage is low.

[0034] The light control liquid crystal 21b changes its transmittance more gradually with respect to the applied effective voltage than the STN liquid crystal. For example, the minimum applied voltage at which the transmittance becomes almost the maximum, that is, the ON voltage, is V A The maximum applied voltage at which the transmittance becomes smaller than the threshold value Tth, that is, the off voltage, is the voltage V A A voltage slightly lower than V B On the other hand, in the GH LCD, the voltage V A Significantly lower voltage V C becomes.

[0035] In the light control device 1, when voltages having substantially equal amplitudes but different timings are applied to both ends of each light-shielding region R in the Z direction in the light control layer 21, a voltage V C This may temporarily degrade the dimming performance.

[0036] Therefore, in this embodiment, the dimming device 1 improves dimming performance by adjusting the timing of either the voltage applied to the row electrode EX by the row electrode driving circuit 3 or the voltage applied to the column electrode EY by the column electrode driving circuit 4.

[0037] In the light control device 1, the arithmetic circuit 5 estimates the amount of delay in each of the row electrode drive circuit 3 and the column electrode drive circuit 4, adjusts the row control signal and the column control signal according to the estimated amount of delay, and supplies them to the row electrode drive circuit 3 and the column electrode drive circuit 4. In this way, the arithmetic circuit 5 adjusts the timing of either the voltage applied to the row electrodes by the row electrode drive circuit 3 or the voltage applied to the column electrodes by the column electrode drive circuit 4. The arithmetic circuit 5 may delay the timing of either the voltage applied to the row electrodes by the row electrode drive circuit 3 or the voltage applied to the column electrodes by the column electrode drive circuit 4, whichever has a smaller amount of delay from a reference timing. The reference timing may be the edge timing of a timing signal generated by the timing generation circuit 7. The edge timing may be the timing of a rising edge or the timing of a falling edge.

[0038] The arithmetic circuit 5 can be configured as shown in Fig. 5. Fig. 5 is a block diagram showing the configuration of the arithmetic circuit 5.

[0039] The arithmetic circuit 5 includes a selection signal generation circuit 51, a load amount calculation circuit 52, and a delay amount generation circuit 53.

[0040] The selection signal generation circuit 51 receives a dimming signal from the analysis device 201. A plurality of application waveform signals are preset in the dimming device 1. The plurality of application waveform signals may be preset in each of the selection signal generation circuit 51, the row electrode drive circuit 3, and the column electrode drive circuit 4. The dimming signal includes an instruction to specify which of the plurality of application waveform signals should be supplied to the plurality of column electrodes EY1 to EY8 and an instruction to specify which application waveform signals should be supplied to the plurality of row electrodes EX1 to EX4. The selection signal generation circuit 51 generates a column control signal corresponding to the dimming signal in synchronization with a clock signal and supplies it to the column electrode drive circuit 4, and generates a row control signal corresponding to the dimming signal and supplies it to the row electrode drive circuit 3. The column control signal includes an instruction for the voltage waveform to be supplied to each column electrode EY. The row control signal includes an instruction for the voltage waveform to be supplied to each row electrode EX. A signal including the row control signal and the column control signal may be called an application waveform selection signal.

[0041] The load calculation circuit 52 receives a dimming signal from the analysis device 201, and receives a row control signal and a column control signal from the selection signal generation circuit 51. The load calculation circuit 52 identifies a shading pattern for each time segment in accordance with the dimming signal, row control signal, and column control signal, and calculates the load of voltage supply to each shading region R in accordance with the shading pattern.

[0042] For example, the load amount of each light-shielding region R due to the row electrode EX is determined by the load due to the parasitic resistance component of the row electrode EX and the load due to the parasitic capacitance component formed between the row electrode EX and the column electrode EY. Compared to the light-shielding region R, the light-transmitting region R is considered to have a relatively large load because a larger voltage is applied between the row electrode EX and the column electrode EY. Taking this into consideration, the load amount can be roughly calculated using the following equation 1. The load amount is a numerical value that allows the magnitude of the load to be understood relatively. [Load due to row electrode EX] = [Number of transparent regions from the input end of row electrode EX to the self-shielding region] + [Number of transparent regions from the self-shielding region of row electrode EX to the far end] / 4 Formula 1

[0043] In the light-shielding pattern shown in Fig. 3, the load amount of each light-shielded region R by the row electrode EX can be estimated using Equation 1 as shown in Fig. 6(a). Fig. 6 is a diagram showing the calculation of the load amount. The load amount calculation circuit 52 calculates the load amounts of the region R(8,1), region R(2,2), region R(3,2), region R(6,2), region R(2,3), region R(3,3), region R(6,3), and region R(8,4) by the row electrode EX to be 7, 2, 2, 3.5, 2, 2, 3.5, and 7, respectively.

[0044] Similarly, the load amount of each light-shielding region R due to the column electrode EY is determined by the load due to the parasitic resistance component of the column electrode EY and the load due to the parasitic capacitance component formed between the column electrode EY and the row electrode EX. The light-transmitting region R is considered to have a relatively larger load than the light-shielding region R because a larger voltage is applied between the column electrode EY and the row electrode EX. Taking this into consideration, the load amount can be roughly calculated using the following equation 2. The load amount is a numerical value for capturing the magnitude of the load relatively.

[0045] [Load caused by column electrode EY] = [Number of transparent regions from the input end of column electrode EY to the self-shielding region] + [Number of transparent regions from the self-shielding region of column electrode EY to the far end] / 4 Formula 2

[0046] 3, the load amount of each light-shielded region R due to the column electrode EY can be estimated as shown in FIG. 6(b) using Equation 2. The load amount calculation circuit 52 calculates the load amounts of the region R(8,1), region R(2,2), region R(3,2), region R(6,2), region R(2,3), region R(3,3), region R(6,3), and region R(8,4) due to the row electrode EX as 0.5, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, and 2, respectively.

[0047] The difference in load amount between both ends of each light-shielding region R in the Z direction can be calculated as the difference between the load amount due to the row electrode EX and the load amount due to the column electrode EY, as shown in the following formula 3.

[0048] [Load difference between both ends in the Z direction] = [Load due to row electrode EX] - [Load due to column electrode EY] Formula 3

[0049] For the light-shielding pattern shown in Fig. 3, the load amount difference between both ends in the Z direction can be estimated as shown in Fig. 6(c) using Equation 3. The load amount calculation circuit 52 calculates the load amount differences between both ends in the Z direction of region R(8,1), region R(2,2), region R(3,2), region R(6,2), region R(2,3), region R(3,3), region R(6,3), and region R(8,4) to be 6.5, 0.75, 0.75, 2.25, 0.75, 0.75, 2.25, and 5, respectively.

[0050] The load calculation circuit 52 supplies the calculation result of the load difference between both ends in the Z direction to the delay generation circuit 53 as a load signal.

[0051] The delay amount generation circuit 53 receives a load amount signal. The load amount signal includes information that associates the row position and column position of the light-shielded region R with the load amount difference between both ends in the Z direction for a plurality of light-shielded regions R. The load amount signal may include map information such as that shown in FIG. 6(c). The delay amount generation circuit 53 calculates a delay amount to be added to the voltage supply to each light-shielded region R in accordance with the load amount signal. The delay amount generation circuit 53 may calculate a delay amount to delay the timing of either the voltage applied to the row electrodes EX by the row electrode drive circuit 3 or the voltage applied to the column electrodes EY by the column electrode drive circuit 4, whichever has a smaller delay amount from a reference timing.

[0052] In the shading pattern shown in Figure 3, when comparing Figures 6(a) and 6(b), it is expected that in all shading areas R, the load caused by the column electrodes EY is less than the load caused by the row electrodes EX, and the delay in the voltage applied by the column electrode drive circuit 4 to the column electrodes EY is less than the delay in the voltage applied by the row electrode drive circuit 3 to the row electrodes EX.

[0053] Therefore, the delay generation circuit 53 delays the column control signals without delaying the row control signals so that the difference in load amount between both ends in the Z direction approaches zero.

[0054] 7(a), the delay generation circuit 53 sets the delay amount to be added to the voltages applied to the row electrodes EX1, EX2, EX3, and EX4 to zero. As a result, the voltages applied to the row electrodes EX1, EX2, EX3, and EX4 are respectively V A ,V B ,V B ,V A This becomes:

[0055] 7(b), the delay generation circuit 53 adds delays of 0, 0.75, 0.75, 0, 0, 2.25, 0, and 6.5 to the voltages applied to the column electrodes EY1, EY2, EY3, EY4, EY5, EY6, and EY7, respectively. As a result, the voltages applied to the column electrodes EY1, EY2, EY3, EY4, EY5, EY6, and EY7 are V C ,V B +0.75,V B+0.75,V C ,V C ,V B +2.25,V C ,V A The result is +6.5.

[0056] As a result, the load difference between both ends of each light-shielded region R in the Z direction approaches zero, as shown in Figure 7(c). The load differences between both ends of the Z direction for region R(8,1), region R(2,2), region R(3,2), region R(6,2), region R(2,3), region R(3,3), region R(6,3), and region R(8,4) are 0, 0, 0, 0, 0, 0, 0, and -1.5, respectively.

[0057] Note that Figures 6 and 7 illustrate an example in which the delay amount is adjusted so that the load difference at both ends of the shading region R in the Z direction, where the load difference is large, is preferentially brought closer to zero, but the delay amount may also be adjusted so that the total value of the load difference is minimized.

[0058] The delay generation circuit 53 generates a row-side delay selection signal indicating the delay to be added to the row control signal and supplies it to the row electrode drive circuit 3. The delay generation circuit 53 generates a column-side delay selection signal indicating the delay to be added to the column control signal and supplies it to the column electrode drive circuit 4. A signal including the row-side delay selection signal and the column-side delay selection signal may be called a delay selection signal.

[0059] The arithmetic circuit 5 may be connected to the column electrode drive circuit 4 and the row electrode drive circuit 3 via serial communication lines. The arithmetic circuit 5 may supply the column control signal and the column side delay amount selection signal as serial signals to the column electrode drive circuit 4. The arithmetic circuit 5 may supply the row control signal and the row side delay amount selection signal as serial signals to the row electrode drive circuit 3.

[0060] The column electrode drive circuit 4 receives a column control signal and a column delay amount selection signal from the calculation circuit 5. The column electrode drive circuit 4 is electrically connected to a plurality of column electrodes EY1 to EY8. The column electrode drive circuit 4 drives each of the plurality of column electrodes EY1 to EY8 in synchronization with a clock signal, using a reference voltage, with a voltage waveform corresponding to the column control signal and the column delay amount selection signal. The column electrode drive circuit 4 can drive each of the plurality of column electrodes EY1 to EY8 individually.

[0061] The column electrode drive circuit 4 may be configured to adjust the delay amount digitally, as shown in Fig. 8. The column electrode drive circuit 4 adjusts the delay amount before performing DA conversion. The column electrode drive circuit 4 has a serial-to-parallel conversion circuit 41, an application waveform generation circuit 42, an application waveform selection circuit 43, a serial-to-parallel conversion circuit 44, a delay trigger generation circuit 45, a delay amount selection circuit 46, and a DA conversion circuit 47. Fig. 8 is a block diagram showing the configuration of the column electrode drive circuit 4 (or the row electrode drive circuit 3). Although Fig. 8 illustrates the configuration of the column electrode drive circuit 4, the row electrode drive circuit 3 has a similar configuration.

[0062] The serial-parallel conversion circuit 41 receives an application waveform selection signal from the arithmetic circuit 5. The serial-parallel conversion circuit 41 converts the application waveform selection signal from serial format to parallel format, and supplies the converted application waveform selection signal to the application waveform selection circuit 43. The application waveform generation circuit 42 generates a plurality of application waveform signals and supplies them to the application waveform selection circuit 43. The application waveform selection circuit 43 selects an application waveform signal to be used from the plurality of application waveform signals in accordance with the application waveform selection signal.

[0063] The serial-to-parallel conversion circuit 44 receives a delay amount selection signal from the arithmetic circuit 5. The serial-to-parallel conversion circuit 44 converts the delay amount selection signal from serial format to parallel format and supplies the converted delay amount selection signal to the delay amount selection circuit 46. The delay trigger generation circuit 45 generates a plurality of delay trigger signals and supplies them to the delay amount selection circuit 46. The delay amount selection circuit 46 selects a delay trigger signal to be used from the plurality of delay trigger signals in accordance with the delay amount selection signal.

[0064] The delay amount selection circuit 46 can be configured as shown in Fig. 9. Fig. 9 is a block diagram showing the configuration of the delay amount selection circuit 46.

[0065] The delay amount selection circuit 46 includes a selection circuit 461 and a latch circuit 462. The selection circuit 461 receives a plurality of delay trigger signals from the delay trigger generation circuit 45, and receives a delay amount selection signal from the serial-parallel conversion circuit 44.

[0066] The multiple delayed trigger signals may be pulses with different edge timings, as shown in FIG. 10. The edge timing of each of the multiple delayed trigger signals may indicate the timing to be delayed. FIG. 10 is a waveform diagram showing the operation of the delay amount selection circuit 46. FIG. 10 illustrates four delayed trigger signals 0 to 3. The delay amount selection signal is a signal that indicates the amount of delay to be added. FIG. 10 illustrates a case where the delay amount selection signal includes "2" or "1" that indicates the amount of delay to be added.

[0067] The selection circuit 461 shown in Fig. 9 may be a multiplexer having a plurality of input nodes corresponding to a plurality of delayed trigger signals and a control node that receives a delay amount selection signal. The selection circuit 461 selects one of the plurality of delayed trigger signals in accordance with the delay amount selection signal. Fig. 10 illustrates a case in which delayed trigger signal 2 is selected from among the four delayed trigger signals 0 to 3 in accordance with the delay amount selection signal including "2." Alternatively, it illustrates a case in which delayed trigger signal 1 is selected from among the four delayed trigger signals 0 to 3 in accordance with the delay amount selection signal including "1."

[0068] 9 supplies the selected delayed trigger signal as a selected trigger signal to the latch circuit 462. In FIG. 10, a case where delayed trigger signal 2 or delayed trigger signal 1 is supplied to the latch circuit 462 as a selected trigger signal is illustrated.

[0069] Latch circuit 462 shown in FIG. 9 receives the application waveform signal from application waveform selection circuit 43 and the selection trigger signal from selection circuit 461. Latch circuit 462 delays the timing of the application waveform signal in response to the selection trigger signal. Latch circuit 462 may be a flip-flop having a data node D that receives the application waveform signal, a clock node CK that receives the selection trigger signal, and an output node Q. Latch circuit 462 latches the application waveform signal in synchronization with the rising edge of the selection trigger signal and outputs the latched application waveform signal from output node Q to DA conversion circuit 47 as a delayed application waveform signal. In FIG. 10, a signal indicates that the application waveform signal changes in synchronization with the timing signal. However, by latching circuit 462 in synchronization with the selection trigger signal, the timing of the change in the delayed application waveform signal is delayed from the timing signal.

[0070] 9 delays the timing of the application waveform signal to a timing synchronized with the rising edge of the selection trigger signal, and outputs it as a delayed application waveform signal. DA conversion circuit 47 uses a reference voltage to perform DA conversion on the delayed application waveform signal to generate an application analog voltage, which is applied to column electrode EY.

[0071] 11(b), for example, the fluctuation range ΔV2 of the voltage applied to both ends of the light-shielded region R(8,1) in the Z direction can be kept small compared to the fluctuation range ΔV1 when neither of the voltages at both ends is delayed as shown in FIG. 11(a). Note that as shown in FIG. 11(b), the delay time Δt between the edge timing of the voltage applied to the column electrode EY8 and the edge timing of the voltage applied to the row electrode EX1 corresponds to the delay amount 6.5 calculated by the arithmetic circuit 5.

[0072] As described above, in this embodiment, the dimming device 1 adjusts the timing of either the voltage applied to the row electrodes EX by the row electrode drive circuit 3 or the voltage applied to the column electrodes EY by the column electrode drive circuit 4. This allows the dimming device 1 to stably dim the region R in the off state of the dimming panel 2, thereby improving dimming performance.

[0073] As a first modified example of the embodiment, the arithmetic circuit 5 shown in FIG. 1 may advance the timing of the voltage applied to the row electrodes by the row electrode driving circuit 3 or the voltage applied to the column electrodes by the column electrode driving circuit 4, whichever has a larger delay amount relative to the reference timing.

[0074] 5 may further have a function of calculating not only the delay amount but also the phase lead amount. The delay amount generation circuit 53 calculates the delay amount or phase lead amount to be added to the voltage supply to each light-shielded region R in accordance with the load amount signal. The delay amount generation circuit 53 may calculate a delay amount to delay the timing of either the voltage applied to the row electrodes EX by the row electrode drive circuit 3 or the voltage applied to the column electrodes EY by the column electrode drive circuit 4, whichever has a smaller delay amount from the reference timing, or may calculate a phase lead amount to advance the timing of either the voltage applied to the row electrodes by the row electrode drive circuit 3 or the voltage applied to the column electrodes by the column electrode drive circuit 4, whichever has a larger delay amount from the reference timing, or may calculate both.

[0075] 3, comparing Figures 6(a) and 6(b), it is expected that in any of the light-shielding regions R, the load due to the column electrodes EY is smaller than the load due to the row electrodes EX, and the delay amount of the voltage applied to the column electrodes EY by the column electrode drive circuit 4 is smaller than the delay amount of the voltage applied to the row electrodes EX by the row electrode drive circuit 3. In other words, it is expected that the delay amount of the voltage applied to the row electrodes EX by the row electrode drive circuit 3 is larger than the delay amount of the voltage applied to the column electrodes EY by the column electrode drive circuit 4.

[0076] Therefore, the delay generation circuit 53 advances the row control signal and delays the column control signal so that the load difference between both ends in the Z direction approaches zero.

[0077] 12(a), the delay amount generating circuit 53 adds phase advance amounts of -6.5, 0, 0, and -5 to the voltages applied to the row electrodes EX1, EX2, EX3, and EX4, respectively. As a result, the voltages applied to the row electrodes EX1, EX2, EX3, and EX4 are V A -6.5,VB ,V B ,V A The result is -5.

[0078] 12(b), the delay generation circuit 53 adds delay amounts of 0, 0.75, 0.75, 0, 0, 2.25, 0, and 0 to the voltages applied to the column electrodes EY1, EY2, EY3, EY4, EY5, EY6, and EY7, respectively. As a result, the voltages applied to the column electrodes EY1, EY2, EY3, EY4, EY5, EY6, and EY7 are V C ,V B +0.75,V B +0.75,V C ,V C ,V B +2.25,V C ,V A This becomes:

[0079] As a result, the difference in load amount between both ends of each light-shielded region R in the Z direction approaches zero, as shown in Figure 12(c). The total load amounts of region R(8,1), region R(2,2), region R(3,2), region R(6,2), region R(2,3), region R(3,3), region R(6,3), and region R(8,4) are 0, 0, 0, 0, 0, 0, 0, respectively.

[0080] In this way, by combining a delay in the timing of the voltage with a smaller delay amount relative to the reference timing and an advance in the timing of the voltage with a larger delay amount relative to the reference timing, the timing adjustment for the dimming panel 2 can be made even more accurate.

[0081] Alternatively, as a second modified example of the embodiment, the column electrode drive circuit 4i (or the row electrode drive circuit 3i) may be configured to adjust the delay amount in an analog manner, as shown in FIG. 13. The column electrode drive circuit 4i (or the row electrode drive circuit 3i) adjusts the delay amount after performing DA conversion. FIG. 13 is a block diagram showing the configuration of the column electrode drive circuit 4i (or the row electrode drive circuit 3i) in the second modified example of the embodiment. Although FIG. 13 illustrates the configuration of the column electrode drive circuit 4i, the row electrode drive circuit 3i has a similar configuration.

[0082] The column electrode driving circuit 4 has a serial-parallel conversion circuit 44i, a delay amount selection circuit 46i, and a DA conversion circuit 47i instead of the serial-parallel conversion circuit 44, the delay amount selection circuit 46, and the DA conversion circuit 47 (see FIG. 8), and the delay trigger generation circuit 45 is omitted.

[0083] The DA conversion circuit 47i receives the application waveform signal from the application waveform selection circuit 43. The DA conversion circuit 47i uses a reference voltage to perform DA conversion on the application waveform signal to generate an application analog voltage, which is then supplied to the delay amount selection circuit 46i.

[0084] The delay amount selection circuit 46i receives the applied analog voltage from the DA conversion circuit 47i and receives a delay amount selection signal from the serial-parallel conversion circuit 44i. The delay amount selection circuit 46i adds a delay amount to the applied analog voltage in accordance with the delay amount selection signal.

[0085] The delay amount selection circuit 46i can be configured as shown in Fig. 14. Fig. 14 is a circuit diagram showing the configuration of the delay amount selection circuit 46i in a second modified example of the embodiment.

[0086] The delay amount selection circuit 46i has a resistive element R1, a plurality of capacitive elements C1 to C4, and a plurality of switches SW1 to SW4. The resistive element R1 is electrically inserted on a signal line SL. The plurality of capacitive elements C1 to C4 correspond to the plurality of switches SW1 to SW4. One end of each of the capacitive elements C1 to C4 is connected to the signal line SL, and the other end is connected to ground potential via the corresponding switch SW.

[0087] Each switch SW1 to SW4 receives a delay amount selection signal at its control terminal. When each switch SW1 to SW4 is maintained in the off state, the corresponding capacitance element C is deactivated, thereby reducing the delay amount of the signal line SL. For example, when all switches SW1 to SW4 are turned off, a delay of zero is added to the applied analog voltage, as shown in the second waveform from the top in FIG. 15, to generate a delayed applied analog voltage and apply it to the column electrode EY. FIG. 15 is a waveform diagram showing the operation of the delay amount selection circuit 46i in the second modified example of the embodiment.

[0088] Each of the switches SW1 to SW4 is maintained in the on state to activate the corresponding capacitance element C and increase the delay amount of the signal line SL. For example, when all of the switches SW1 to SW4 are turned on, a desired delay amount is added to the applied analog voltage to generate a delayed applied analog voltage, which is applied to the column electrode EY, as shown in the third waveform from the top in Figure 15.

[0089] This allows the delay amount selection circuit 46i to add a delay amount according to the delay amount selection signal to the applied analog voltage transmitted through the signal line SL.

[0090] In this way, a voltage to which a desired amount of delay has been added can be applied to each region R of the light control panel 2 by adjusting the amount of delay in an analog manner using the column electrode drive circuit 4i (or the row electrode drive circuit 3i).

[0091] Alternatively, as a third modified example of the embodiment, the column electrode drive circuit 4j (or the row electrode drive circuit 3j) may be configured to internally generate a delay amount selection signal, as shown in FIG. 16. The column electrode drive circuit 4j (or the row electrode drive circuit 3j) performs feedback control by monitoring the current applied to the column electrodes EY (or the row electrodes EX) and feeding back a delay amount selection signal according to the monitoring result. FIG. 16 is a block diagram showing the configuration of the column electrode drive circuit 4j (or the row electrode drive circuit 3j) in the third modified example of the embodiment. Although FIG. 16 illustrates the configuration of the column electrode drive circuit 4j, the row electrode drive circuit 3j has a similar configuration.

[0092] The column electrode driving circuit 4j further includes a current detection circuit 48j, an AD conversion circuit 49j, and a pulse width counter 50j in addition to the column electrode driving circuit 4 (see FIG. 8).

[0093] The current detection circuit 48j monitors the current applied from the DA conversion circuit 47 to the column electrode EY.

[0094] For example, as shown in FIG. 17(a), if the applied current falls between the upper threshold Ith1 and the lower threshold Ith2, the current detection circuit 48j generates an excess signal indicating that the applied current exceeds the upper threshold Ith1 and the lower threshold Ith2 by zero, and supplies the excess signal to the AD conversion circuit 49j. FIG. 17 is a waveform diagram showing the operation of the current detection circuit 48j and the AD conversion circuit 49j in the third modified example of the embodiment. The AD conversion circuit 49j performs AD conversion on the excess signal, generates an AD conversion circuit output that maintains a level of zero, and outputs the output to the pulse width counter 50j. The pulse width counter 50j counts zero as the pulse width of the AD conversion circuit output, generates a delay amount selection signal indicating a delay amount of zero, and supplies the delay amount selection signal to the delay amount selection circuit 46.

[0095] On the other hand, as shown in FIG. 17(b), if the applied current does not fall between the upper threshold Ith1 and the lower threshold Ith2, i.e., if the applied current exceeds the upper threshold Ith1 and the lower threshold Ith2, the current detection circuit 48j generates an excess signal indicating that the applied current exceeds the upper threshold Ith1 and the lower threshold Ith2, and supplies the excess signal to the AD conversion circuit 49j. The excess signal may be a signal indicating the absolute value of the amount of the applied current exceeding the upper threshold Ith1 and the lower threshold Ith2. The AD conversion circuit 49j performs AD conversion on the excess signal, generates an AD conversion circuit output including a pulse having a width corresponding to the time the applied current exceeded the upper threshold Ith1 and the lower threshold Ith2, and outputs the AD conversion circuit output to the pulse width counter 50j. The pulse width counter 50j counts a finite value as the pulse width of the AD conversion circuit output, generates a delay amount selection signal indicating the desired delay amount, and supplies the delay amount selection signal to the delay amount selection circuit 46.

[0096] In this way, a voltage to which a desired amount of delay has been added can be applied to each region R of the light control panel 2 by internally generating a delay amount selection signal in the column electrode drive circuit 4j (or the row electrode drive circuit 3j).

[0097] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0098] 1. Dimmer 2 Dimming Panel 3, 3i, 3j Row electrode drive circuit 4, 4i, 4j Column electrode drive circuit 5 Arithmetic circuit 6 Reference voltage generation circuit 7 Timing generation circuit 21 Photochromic Layer 201 Analysis equipment

Claims

1. a light-modulating layer having a first major surface and a second major surface disposed on the opposite side of the first major surface; a plurality of first electrodes each extending in a row direction and facing the first main surface; a plurality of second electrodes each extending in a column direction and facing the second main surface; a row driver circuit capable of applying a voltage to the first electrode; a column driver circuit capable of applying a voltage to the second electrode; a control circuit that adjusts the timing of either the voltage that the row driver circuit applies to the first electrode or the voltage that the column driver circuit applies to the second electrode; A dimmer device comprising:

2. The control circuit delays the timing of one of the voltages applied to the first electrode by the row drive circuit and the voltage applied to the second electrode by the column drive circuit, whichever has a smaller delay amount relative to a reference timing. The light control device according to claim 1 .

3. The control circuit advances the timing of one of the voltages applied to the first electrode by the row drive circuit and the voltage applied to the second electrode by the column drive circuit, whichever has a larger delay amount relative to a reference timing. The light control device according to claim 1 .

4. the light-controlling layer has a plurality of regions partitioned in a matrix form according to voltages applied to the plurality of first electrodes and voltages applied to the plurality of second electrodes; The control circuit identifies, for each of the plurality of regions, one of the voltages applied by the row drive circuit to the first electrode and the voltage applied by the column drive circuit to the second electrode, which has a smaller delay amount with respect to a reference timing, and delays the timing of the identified voltage. The light control device according to claim 2 .

5. the light-controlling layer has a plurality of regions partitioned in a matrix form according to voltages applied to the plurality of first electrodes and voltages applied to the plurality of second electrodes; The control circuit identifies, for each of the plurality of regions, one of the voltages applied to the first electrode by the row drive circuit and the voltage applied to the second electrode by the column drive circuit, which voltage has a larger delay amount with respect to a reference timing, and advances the timing of the identified voltage. The light control device according to claim 3 .

6. A light control device including a light control layer having a first main surface and a second main surface disposed on the opposite side of the first main surface, a plurality of first electrodes each extending in a row direction and facing the first main surface, a plurality of second electrodes each extending in a column direction and facing the second main surface, a row drive circuit capable of applying a voltage to the first electrodes, and a column drive circuit capable of applying a voltage to the second electrodes, the method comprising: adjusting the timing of one of a voltage applied by the row drive circuit to the first electrodes and a voltage applied by the column drive circuit to the second electrodes; Drive method.

Images