Semiconductor Devices

Abstract

To suppress a malfunction of a circuit due to a deterioration in a transistor in the circuit having at least two inputs acting on one output of a logic circuit or the like.SOLUTION: In a circuit having at least two inputs acting on one output of a logic circuit or the like, the direction of current flowing through a transistor that continuously outputs a signal (an L level signal) of a certain specific level is configured to be changed (inverted). Namely, a source and a drain are configured to be changed (inverted) in each arbitrary period by changing the magnitude of voltage applied to a first terminal and a second terminal (a terminal to be the source or the drain) of the transistor in each arbitrary period. Concretely, in the circuit having the transistor, an L level signal (an L level signal with potential changing in each arbitrary period) having a plurality of potentials different from each other is used as a signal of the specific level at a part that continuously outputs the signal (the L level signal) of the certain specific level.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device configured using a transistor or an operating method thereof. The present invention also relates to a display device to which a semiconductor device is applied and an electronic device equipped with the display device. do. [Background technology]

[0002] In recent years, development of display devices such as liquid crystal display devices and light emitting devices has been actively promoted. In addition, pixel circuits and shift registers are constructed using transistors formed of non-single-crystal semiconductors on insulators. The technology for integrally forming a driver circuit (hereinafter referred to as an internal circuit) including a drive resistor circuit etc. It is being actively developed to contribute significantly to power consumption, cost reduction, improved reliability, narrower frame, etc. The internal circuit formed on the insulator is FPC (Flexible Printed Circuit). controller ICs, etc. (hereinafter referred to as "controller ICs") located outside the insulator via a connected circuit, etc. The external circuit (hereinafter referred to as the external circuit) controls its operation.

[0003] In addition, non-single crystal semiconductor transistors are used as internal circuits integrally formed on an insulator. A shift register circuit configured as above has been devised (see Patent Document 1).

[0004] However, the output terminal of the shift register circuit is in a floating state for a certain period of time. Therefore, noise is likely to occur at the output terminal, and the noise generated at the output terminal can cause the shift register There was a problem with the circuit malfunctioning.

[0005] To solve the above problem, we developed a shift register that does not allow the output terminal to be in a floating state. For example, in Patent Document 2, a circuit is devised by so-called static driving. It has been proposed to operate a shift register circuit, in which the shift register circuit Since the output terminal is not in a floating state, noise generated at the output terminal can be reduced. This can be done. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 95 / 31804 Brochure [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-78172 Summary of the Invention [Problem to be solved by the invention]

[0007] As shown in Patent Document 2, when the device is operated by static driving, the operation period is The operation period is divided into a selection period in which a signal is output and a non-selection period in which a non-selection signal is output. Most of the time is the non-selection period. The selection signal is at a high potential (high level signal). In this case, during the non-selection period, a non-selection signal (low potential ( In other words, it is a transformer that supplies a low potential to the output terminal. The transistor is in an on state for most of the time that the circuit is in operation.

[0008] A transistor made using a non-single-crystal semiconductor has a low-energy content depending on the time it is on and the applied potential. Therefore, it is known that the transistor deteriorates. When the transistor deteriorates, for example, the threshold voltage A problem where the voltage shifts to the positive side, causing a threshold voltage shift and resulting in circuit malfunction. There is.

[0009] In addition, digital circuits such as shift register circuits and latch circuits are connected to pixels and analog switches ( For example, unlike transfer gates, the direction of current flow is often fixed. In other words, since the source and drain of the transistor are fixed, the current is not transferred to the drain side. The field is concentrated, making the transistors more susceptible to degradation.

[0010] In view of the above problems, it is an object to reduce the deterioration of a transistor. One object is to suppress malfunction of a circuit due to deterioration of a transistor. An object is to improve the reliability of a circuit having a transistor. [Means for solving the problem]

[0011] To reduce the degradation of transistors, a certain level of signal (e.g. In a transistor that continues to output an L-level signal (low-level signal), The direction of the current flowing through the transistor is reversed. The magnitude relationship between the voltages applied to the first and second terminals (source or drain terminals) of the capacitor By swapping the above at any time, the source and drain can be switched at any time. The composition is as follows.

[0012] Therefore, in a circuit having a transistor, a signal of a certain level (for example, L level) In the part where the signal (signal) is continuously output, a plurality of different voltages are used as the signal of the specific level. An L-level signal with a potential that changes every arbitrary period is used. For example, when a low-level signal is continuously output through a transistor, the low-level signal is The potential is V LHand a first potential consisting of V LL A second potential (V LH >V LL ) can be used as a signal that switches every arbitrary period. is used as an L-level signal to reverse the direction of current flow through the transistor (source and drain By switching the source and drain, the concentration of the electric field on the source or drain side is suppressed. Reduces transistor degradation.

[0013] In addition, the first potential (V LH ) and the second potential (V LL ) is used as an L level signal in the circuit. For example, an L level signal is used as a non-selected signal in a circuit. When the first potential and the second potential are used as a non-selection signal, the potential is set so that the first potential and the second potential function as a non-selection signal. Furthermore, three or more potentials may be set as the plurality of potentials.

[0014] Also, if an H level signal (high level signal) continues to be output through the transistor, As a H level signal, the potential is V HH and a first potential consisting of V HL The second consists of Potential (V HH >V HL ) is switched at any time. HH ) and the second potential (V HL ) functions as a high-level signal in the circuit. For example, if a H level signal is used as a selection signal in the circuit, The potentials may be set so that the first potential and the second potential function as selection signals.

[0015] In addition, one example of the disclosed invention is a semiconductor device in which one of the source and the drain is electrically connected to a first wiring. the other end of the first transistor is electrically connected to a third wiring; and the other end of the first transistor is electrically connected to a source or drain One of the first and second wirings is electrically connected to the second wiring, and the other is electrically connected to the third wiring. A transistor and a gate electrically connected to the third wiring. a third transistor that is turned on by a select signal and turned off by a non-select signal, A select signal is supplied from the first wiring to the third wiring while the first transistor is on. A non-selection signal is supplied from the second wiring to the third wiring while the second transistor is on. At least one of the selection signal and the non-selection signal is a signal whose potential changes every predetermined period. It is characterized by the fact that

[0016] In addition, one example of the disclosed invention is a semiconductor device in which one of the source and the drain is electrically connected to a first wiring. the other end of the first transistor is electrically connected to a third wiring; and the other end of the first transistor is electrically connected to a source or drain One of them is electrically connected to the second wiring, the other is electrically connected to the third wiring, and A plurality of second transistors are provided in parallel with each other, and the gates of the second transistors are electrically connected to the third wiring. The third wiring is turned on by a selection signal and turned off by a non-selection signal. a third transistor that is connected to the first transistor while the first transistor is turned on; The non-selection signal is supplied from the first wiring to the third wiring, and the potential of the non-selection signal changes every predetermined period. and a third wiring is connected to the second wiring while any of the plurality of second transistors is turned on. The present invention is characterized in that the power supply is supplied to the wiring.

[0017] In addition, one example of the disclosed invention is a semiconductor device in which one of the source and the drain is electrically connected to a first wiring. the other end of the first transistor is electrically connected to a third wiring; and the other end of the first transistor is electrically connected to a source or drain One of the first and second wirings is electrically connected to the second wiring, and the other is electrically connected to the third wiring. One of the source and drain of the transistor is electrically connected to the fourth wiring, and the other is electrically connected to the fourth wiring. a fourth transistor electrically connected to the third wiring; The third wiring is connected to the transistor 100, and the transistor 100 is turned on by a selection signal supplied to the third wiring and turned off by a non-selection signal. and a third transistor, wherein the selection signal is A non-selection signal is supplied from the first wiring to the third wiring, and the second transistor is turned on. During the period when the fourth transistor is turned on, the second wiring or the fourth wiring is connected to the third wiring. a potential different from each other is applied to the second wiring and the fourth wiring; The potential applied to the first wiring and the potential applied to the fourth wiring are interchanged. do.

[0018] In this specification, when a transistor is used as a switch, the transistor is a single Since the transistor operates as a switch, the polarity (conductivity type) of the transistor is not particularly limited. However, if you want to suppress the off-state current, you can use a transistor with a polarity that reduces the off-state current. As a transistor with a low off-state current, a transistor having an LDD region is preferable. There are transistors with a multi-gate structure, and transistors that operate as switches. The potential of the source terminal of the transistor is lower than the potential of the low-potential power supply (Vss, GND, 0V, etc.). When operating at values ​​close to the maximum, it is preferable to use an N-channel transistor. , when the potential of the source terminal is close to the potential of the high-potential power supply (such as Vdd), It is preferable to use an N-channel transistor because When the source terminal operates at a potential close to the low-potential power supply, the P-channel transistor In a capacitor, when the source terminal operates at a potential close to that of the high-potential power supply, the The absolute value of the voltage can be increased, allowing for more accurate operation as a switch. Furthermore, the transistor rarely operates as a source follower. This is because the magnitude of the output voltage is less likely to become small.

[0019] In addition, CMOS transistors are used to implement both N-channel and P-channel transistors. A CMOS switch can be used as the switch. Either the N-channel transistor or the N-channel transistor is conducting. If the input voltage is 0.05V, a current will flow, making it easier to function as a switch. Whether the signal voltage is high or low, the voltage can be output appropriately. Therefore, the voltage amplitude of the signal used to turn the switch on or off can be reduced. Therefore, power consumption can also be reduced.

[0020] When using a transistor as a switch, the switch must be connected to the input terminal (source terminal or the other of the source and drain terminals), the output terminal (the other of the source and drain terminals), and the The diode is used as a switch. In this case, the switch may not have a terminal that controls conduction. Using diodes as switches rather than transistors reduces the amount of wiring required to control the terminals. It can be eliminated.

[0021] When it is explicitly stated that "A and B are connected," it means that A and B are electrically connected. A and B are connected functionally, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) Therefore, the predetermined connection relationship For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be applied to the connections shown in the drawings or text. This also includes things other than relationships.

[0022] For example, if A and B are electrically connected, the electrical connection between A and B can be The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more electrodes (such as a diode) may be connected between A and B. Alternatively, A and B may In the case of functional connection, a circuit that allows functional connection between A and B (e.g. , logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, voltage sources, current sources, Switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, etc.), operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, signal generation circuits, memory circuits, control One or more control circuits may be connected between A and B. For example, Even if there is another circuit between them, if the signal output from A is transmitted to B, then A and B are It is assumed that they are functionally connected.

[0023] When it is explicitly stated that "A and B are electrically connected," it means that A and B are electrically connected. When A and B are electrically connected (i.e., when another element or circuit is placed between A and B), A and B are functionally connected (i.e., there is no other connection between A and B) and B are functionally connected (i.e., there is no other connection between A and B). When A and B are connected functionally through a circuit) and when A and B are connected directly ( In other words, A and B are connected without any other element or circuit between them. In other words, when explicitly stating that something is electrically connected, it simply means that it is connected. is the same as if it were expressly stated only that it is

[0024] Note that the term "display element," "display device having a display element," "light-emitting element," and "device having a light-emitting element" may be used interchangeably. The light-emitting device can be used in various forms. The light-emitting element or light-emitting device may be an EL (electroluminescence) element (organic and EL elements containing inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs) D, green LED, blue LED, etc.), transistors (transistors that emit light according to the current ), electron emission element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GLV), plasma display panel (PDP), digital micromirror device (DMD), piezoelectric ceramic display, carbon nanotube, etc. These can be used to change the contrast, brightness, reflectance, transmittance, etc. due to electromagnetic effects. The display device using the EL element can have a display medium that changes color. Examples of display devices that use electron-emitting devices include field emission displays. flat panel displays (FED) and SED (Surface-Enhanced Display) conduction electron-emitter display) Display devices using liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, etc.). Transmissive LCD, Reflective LCD, Direct-view LCD, Projection LCD Examples of display devices that use electronic ink or electrophoretic elements include electronic pens. There are also other products.

[0025] The EL element is an element having an anode, a cathode, and an EL layer sandwiched between the anode and the cathode. The EL layer is made up of a number of types, including those that utilize light emission (fluorescence) from singlet excitons, Those that utilize light emission from doublet excitons (phosphorescence) and those that utilize light emission from singlet excitons (fluorescence). Some utilize light emission from triplet excitons (phosphorescence), while others utilize organic materials. formed by inorganic matter, formed by organic matter and formed by inorganic matter. Materials formed by organic materials, including polymeric materials, low molecular weight materials, and polymeric materials However, it is not limited to this, and E There can be a variety of L elements.

[0026] An electron-emitting device is an element that extracts electrons by concentrating a high electric field on a cathode. For example, As electron emitters, Spindt type, carbon nanotube (CNT) type, metal-insulator- MIM (Metal-Insulator-Metal) type with metal layers, metal-insulator MIS (Metal-Insulator-Semiconductor) tor type, MOS type, silicon type, thin film diode type, diamond type, metal-insulator - Thin film type such as semiconductor-metal type, HEED type, EL type, porous silicon type, surface conduction (S However, the electron emission element is not limited to this, and various types of electron emission elements may be used. It can have a variety of things.

[0027] A liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystals. It is composed of a pair of electrodes and liquid crystal. Controlled by the electric field applied to the crystal (including the horizontal electric field, the vertical electric field, or the diagonal electric field) The liquid crystal elements include nematic liquid crystal, cholesteric liquid crystal, smectic Liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, Polymer liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, Examples include side-chain polymer liquid crystals, plasma-addressed liquid crystals (PALCs), and banana-shaped liquid crystals. The liquid crystal driving method is Twisted Nematic (TN). mode, STN (Super Twisted Nematic) mode, IPS (In- Plane-Switching mode, FFS (Fringe Field Switching) mode tching) mode, MVA (Multi-domain Vertical Alignment gnment) mode, PVA(Patterned Vertical Alignm) ent) mode, ASV (Advanced Super View) mode, ASM ( Axially Symmetrically aligned Micro-cell) mode , OCB (Optically Compensated Birefringence) ) mode, ECB (Electrically Controlled Birefringence ngence) mode, FLC (Ferroelectric Liquid Crystal tal) mode, AFLC(AntiFerroelectric Liquid Cr systal mode, PDLC (Polymer Dispersed Liquid Crystal Crystal mode, guest host mode, Blue Phase mode However, the present invention is not limited to this, and the liquid crystal element and its driving method can be used. A variety of different types can be used.

[0028] In addition, electronic paper is displayed by molecules (optical anisotropy, dye molecule orientation, etc.). (electrophoresis, particle migration, particle rotation, phase change, etc.), It is displayed by the movement of one end of the film, and by the coloring / phase change of molecules. Some are displayed by molecular light absorption, and others by spontaneous light emission caused by electron-hole combinations. For example, one method of displaying electronic paper is to use microcapsules. Horizontally moving electrophoresis, vertically moving electrophoresis, spherical twist ball, magnetic twist Twist ball, cylindrical twist ball method, charged toner, electronic liquid powder, magnetophoretic type, magnetic heat sensitive formula, electrowetting, light scattering (transparent / opaque), cholesteric liquid crystal / light guide Layer, Cholesteric Liquid Crystal, Bistable Nematic Liquid Crystal, Ferroelectric Liquid Crystal, Dichroic Dye and Liquid Crystal Dispersion type, movable film, color development and fading by leuco dye, photochromic, electrochromic It can be made using materials such as adhesives, electrodeposition, and flexible organic light-emitting diodes. However, without being limited to this, various electronic paper and display methods can be used. Here, by using microcapsule electrophoresis, the defects of the electrophoresis method can be overcome. This solves the problem of aggregation and precipitation of electrophoretic particles. It has advantages such as low reflectivity, wide viewing angle, low power consumption, and memory properties.

[0029] The plasma display panel is made up of a substrate on which electrodes are formed, and a substrate on which electrodes and minute grooves are formed. A substrate having a surface on which a phosphor layer is formed and a groove in which a phosphor layer is formed is placed opposite to the substrate at a narrow interval, and a rare gas is introduced. Alternatively, the plasma tube is sandwiched between film electrodes from above and below. It is also possible to use a structure that incorporates a plasma tube. It is a plasma display panel that contains gas, RGB phosphors, etc. By applying a voltage between the electrodes, ultraviolet light is generated, causing the phosphor to glow, and the display There are two types of discharge methods: DC and AC. Here, the driving method of the plasma display panel is AWS (Addr ess While Sustain) drive, subframe reset period, address period ADS (Address Display Separated) ) drive, CLEAR (HI-CONTRAST & LOW ENERGY ADDRESS &REDUCTION OF FALSE CONTOUR SEQUENCE) drive, ALIS (Alternate Lighting of Surfaces) method, T ERES(Technology of Reciprocal Sustainer) However, it is not limited to this, and a plasma display panel can also be used. Various methods for driving the rollers can be used.

[0030] In addition, display devices that require a light source, such as liquid crystal displays (transmissive liquid crystal displays), , Transflective LCD, Reflective LCD, Direct-view LCD, Projection LCDs, display devices using grating light valves (GLVs), digital As a light source for a display device using a digital micromirror device (DMD), an electroluminescent Using luminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. However, the light source is not limited to this, and various light sources can be used. do.

[0031] Note that various types of transistors can be used as the transistor. There is no limitation on the type of transistor used. For example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, Crystalline (also called microcrystalline, nanocrystalline, or semi-amorphous) silicon, etc. It is possible to use thin film transistors (TFTs) having non-single crystal semiconductor films, such as There are various advantages to using TFTs. For example, it is This allows for lower manufacturing temperatures, reducing manufacturing costs and enabling the use of larger manufacturing equipment. Since the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Since a large number of display devices can be manufactured, the manufacturing cost can be reduced. Therefore, a substrate with low heat resistance can be used. A transistor on a light-transmitting substrate can be used to manufacture a display element. The thin film of the transistor allows the light transmission to be controlled. A part of the film that makes up the transistor can transmit light, which improves the aperture ratio. It can be done.

[0032] When producing polycrystalline silicon, a catalyst (such as nickel) is used to This will further improve the crystallinity and make it possible to manufacture transistors with good electrical characteristics. As a result, gate driver circuits (scanning line driver circuits) and source driver circuits (signal line driver circuits) , signal processing circuits (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) are integrated on the board It can be achieved.

[0033] When manufacturing microcrystalline silicon, a catalyst (such as nickel) is used to This further improves the crystallinity, making it possible to manufacture transistors with good electrical characteristics. In this case, the crystallinity can be improved by simply applying heat treatment without laser irradiation. As a result, part of the source driver circuit (analog switch, etc.) and gate The gate driver circuit (scanning line driving circuit) can be formed integrally on the substrate. If laser irradiation is not performed for the purpose of crystallization, unevenness in the crystallinity of silicon can be suppressed. Therefore, it is possible to display an image with improved quality.

[0034] However, polycrystalline silicon and microcrystalline silicon are produced without using a catalyst (such as nickel). It is possible.

[0035] In addition, improving the crystallinity of silicon to polycrystalline or microcrystalline allows the entire panel to be It is desirable to perform this in a partial area of ​​the panel, but it is not limited to this. The crystallinity of the crystalline silicon may be improved. For example, the peripheral circuit area, which is an area other than the pixel area, can be selectively irradiated. Alternatively, the laser light may be irradiated only on the gate driver circuit, the source driver circuit, and the Alternatively, the laser light may be irradiated only on a region such as a path. The laser light may be irradiated only on the area of ​​the semiconductor device (for example, an analog switch). It is possible to improve the crystallization of silicon only in areas where high-speed circuit operation is required. Since there is little need for high-speed operation in the pixel area, there is no problem even if the crystallinity is not improved. The pixel circuit can be operated without any problems. The manufacturing process can be shortened, throughput can be improved, and manufacturing costs can be reduced. The number of required manufacturing equipment is small, which reduces manufacturing costs. It is possible to do this.

[0036] Alternatively, a transistor can be formed using a semiconductor substrate, an SOI substrate, or the like. This allows for less variation in characteristics, size, and shape, a high current supply capacity, and a small size. These transistors can be used to fabricate transistors with small capacitances. This allows for lower power consumption and higher circuit integration.

[0037] Alternatively, zinc oxide (ZnO), oxide containing indium, gallium and zinc (InGaZn O), silicon germanium (SiGe), gallium arsenide (GaAs), indium oxide Compound semiconductors such as zinc oxide (IZO), indium tin oxide (ITO), and tin oxide (SnO) Transistors having conductors or oxide semiconductors, and further, compound semiconductors or A thin film transistor made of a thin oxide semiconductor can be used. The manufacturing temperature can be lowered, and for example, it becomes possible to manufacture transistors at room temperature. As a result, transistors are formed directly on substrates with low heat resistance, such as plastic substrates or film substrates. These compound semiconductors or oxide semiconductors can be used in transistors. It can be used not only for the channel portion of the device but also for other purposes. These compound semiconductors or oxide semiconductors are used as resistor elements, pixel electrodes, and light-transmitting electrodes. Furthermore, they can be formed as films or layers at the same time as transistors. , and costs can be reduced.

[0038] Alternatively, a transistor formed by inkjet or printing can be used. These allow fabrication at room temperature, in a low vacuum, or on a large substrate. Since it is possible to manufacture without using a mask (reticle), The layout can be easily changed. Furthermore, since there is no need to use resist, The cost of materials is reduced and the number of processes can be reduced. Furthermore, since the film is applied only to the necessary parts, This method is less wasteful and less costly than the method of forming a film on a surface and then etching it. can.

[0039] Alternatively, a transistor having an organic semiconductor or a carbon nanotube may be used. These features make it possible to form transistors on a flexible substrate. A semiconductor device using such a substrate can be made resistant to shocks.

[0040] Furthermore, transistors of various structures can be used. For example, MOS transistors The use of transistors such as junction transistors and bipolar transistors as transistors By using MOS transistors, the size of the transistors can be reduced. Therefore, multiple transistors can be mounted. By using a transistor, a large current can be passed through, which allows the circuit to operate at high speed. It can be made to work.

[0041] In addition, MOS transistors, bipolar transistors, etc. can be mixed and formed on a single substrate. This allows for low power consumption, miniaturization, high-speed operation, etc. .

[0042] The structure of the transistor can take various forms and is not limited to a specific structure. For example, a multi-gate structure with two or more gate electrodes can be applied. In the gate structure, the channel regions are connected in series, so multiple transistors are connected in series. The multi-gate structure reduces the off-state current and increases the breakdown voltage of the transistor. Alternatively, the multi-gate structure can be used to reduce the saturation region. When operating in the low-voltage range, the drain-source current remains constant even if the drain-source voltage changes. The voltage-current characteristic slope is flat. By taking advantage of the flat slope, it is possible to create ideal current source circuits and circuits with very high resistance values. As a result, it is possible to realize an active load with good characteristics, such as a differential circuit or a current mirror circuit. The path can be realized.

[0043] As another example, a structure in which gate electrodes are arranged above and below the channel can be applied. By using a structure in which gate electrodes are arranged above and below the channel, The current value can be increased by increasing the number of gate electrodes above and below the channel. By using a structure in which the depletion layer is easily formed, the S value can be improved. In addition, by arranging gate electrodes above and below the channel, , a configuration in which a plurality of transistors are connected in parallel.

[0044] A structure in which a gate electrode is placed above a channel region, and a structure in which a gate electrode is placed below a channel region Structures in which the channel region is divided into multiple regions, such as a positive staggered structure, a reverse staggered structure, and a The structure may be a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in series. Furthermore, the source electrode and drain electrode are attached to the channel region (or a part of it). An overlapping structure can also be applied. By using a structure in which the gate electrodes overlap, charges accumulate in part of the channel region, This can prevent the operation from becoming unstable. Alternatively, a structure with an LDD region can be appropriately By providing an LDD region, it is possible to reduce the off-current or improve the breakdown voltage of the transistor. Alternatively, by providing an LDD region, it is possible to reduce saturation. When operating in the sum region, the drain-source current remains constant even if the drain-source voltage is changed. does not change much, and the slope of the voltage-current characteristics can be made flat.

[0045] Note that various types of transistors can be used and can be formed using various substrates. Therefore, all the circuits required to realize a given function can be implemented in the same For example, it is possible to form a circuit on a substrate that is necessary to realize a predetermined function. All of these can be mounted on various substrates such as glass, plastic, single crystal, or SOI. It is also possible to form the entire circuit necessary to realize a predetermined function using a substrate. Since all components are formed using the same substrate, the number of components is reduced, resulting in cost reduction. Alternatively, the reliability can be improved by reducing the number of connection points with the circuit components. A part of the circuit required to realize a certain function is formed on a certain substrate, and the It is also possible that another part of the circuitry required to realize the above may be formed on another substrate. In other words, all of the circuits required to realize a given function are formed using the same substrate. For example, some of the circuits required to realize a specific function may be mounted on a glass substrate. Another part of the circuit formed by transistors on the board and required to realize a specified function. The part is formed on a single crystal substrate and is composed of transistors formed using the single crystal substrate. The IC chip is connected to the glass substrate using COG (Chip On Glass). It is also possible to place the IC chip on the board. (Tape Automated Bonding) and printed circuit boards are used to bond glass substrates. In this way, it is possible to connect the two circuits together. This reduces costs by reducing the number of components, and improves signal quality by reducing the number of connections to circuit components. Alternatively, it is possible to improve reliability in areas where the driving voltage is high and the driving frequency is high. The power consumption of the circuitry for these parts is high, so the circuits for these parts are formed on the same board. Instead, for example, a circuit for that part is formed on a single crystal substrate, and the circuit is configured By using an IC chip that has been fabricated, it is possible to prevent an increase in power consumption.

[0046] Note that one pixel refers to one element whose brightness can be controlled. In this case, one pixel refers to one color element, and the brightness is expressed by one color element. Therefore, in the case of a color display device consisting of R (red), G (green), and B (blue) color elements, In this example, the smallest unit of an image is composed of three pixels: an R pixel, a G pixel, and a B pixel. The color elements are not limited to three colors, and more than three colors may be used. Colors may also be used. For example, adding white makes it possible to use RGBW (W is white). Or, for example, yellow, cyan, magenta, emerald green, vermilion, etc. It is also possible to add one or more colors. It is also possible to add similar colors to RGB, for example R, G, B1, B2. B1 and B2 are both blue, but have different wavelengths. It is also possible to use 1, R2, G, and B. By using such color elements, By using these color elements, power consumption can be reduced. Another example is to use multiple regions for one color element to reduce the brightness. When controlling brightness, it is possible to use one pixel for one area. When performing area gradation or when using sub-pixels, one color element There are multiple areas that control brightness, and the gradation is expressed as a whole, but the brightness is controlled It is also possible to use one pixel for one area. Alternatively, the area for controlling brightness may be a single color element. Even if there are multiple color elements in a pixel, they may be grouped together and one color element may be considered as one pixel. In this case, one color element is composed of one pixel. When controlling brightness using multiple regions for color elements, the pixels contribute to the display. The size of the area to be displayed may be different. Or, there may be multiple areas per color element. In the brightness control area, the signals supplied to each are slightly different to control the visual In other words, for one color element, multiple regions may be The potentials of the pixel electrodes may be different from each other. The voltage applied to each pixel electrode is different, which makes it possible to widen the viewing angle.

[0047] When explicitly stating one pixel (three colors), the three pixels of R, G, and B are considered to be one pixel. When explicitly describing one pixel (one color), it refers to one color element. In this case, when there are multiple regions, they are considered as one pixel.

[0048] In some cases, pixels are arranged (distributed) in a matrix. The pixels are arranged in a straight line in either the vertical or horizontal direction. This includes cases where they are arranged side by side or in a jagged line. For example, when displaying full color using three color elements (e.g., RGB), the stripes are arranged This also includes cases where the dots of the three color elements are arranged in a delta configuration. This also includes cases where the dots of the color elements are arranged in layers. This can reduce power consumption or extend the life of the display element. do.

[0049] In addition, the active matrix type has active elements in the pixels, or the A passive matrix method can be used.

[0050] In the active matrix system, the active element (active element, nonlinear element) is a transistor. Use not only transistors but also various active elements (active elements, nonlinear elements) For example, MIM (Metal Insulator Metal) and TFD ( Thin Film Diodes) can also be used. Since the number of manufacturing steps is small, it is possible to reduce manufacturing costs and improve yields. In addition, the small size of the element allows for an improved aperture ratio, resulting in lower power consumption and higher brightness. It is possible to achieve this.

[0051] In addition to the active matrix method, there are also active elements (active elements, nonlinear It is also possible to use a passive matrix type that does not use active elements. Since it does not use any nonlinear elements, there are fewer manufacturing steps, which reduces manufacturing costs and improves yield. Since no active elements (active elements, non-linear elements) are used, This makes it possible to improve the aperture ratio, thereby achieving lower power consumption and higher brightness.

[0052] A transistor is a device having at least three terminals including a gate, a drain, and a source. The element has a channel region between the drain region and the source region, A current can flow through the in-region, the channel region, and the source region. The source and drain depend on the transistor structure and operating conditions, so it is difficult to know which is the source or drain. Therefore, it is difficult to define whether the source or drain is the In some cases, the region that functions as a source or drain is not called a source or drain. In this case, they may be referred to as the first terminal and the second terminal, respectively. They may be referred to as the first electrode and the second electrode, or as the first region and the second region. There is.

[0053] The transistor has at least three terminals including a base, an emitter, and a collector. In this case, the emitter and the collector may be connected to the first terminal and the second terminal. It may be referred to as a terminal.

[0054] The gate is a gate electrode and a gate wiring (gate line, gate signal line, scanning line, scanning signal line). The term refers to the whole or part of a gate electrode and The gate insulating film is a part that overlaps the semiconductor that forms the channel region. The gate electrode is partially doped with LDD (Lightly Doped Diode). ed Drain) region or source region (or drain region) and The gate wiring is the gate electrode of each transistor. a wiring for connecting between the gate electrodes of each pixel, or This refers to the wiring that connects the gate electrode to another wiring.

[0055] The source includes the source region, the source electrode, and the source wiring (source line, source signal line, It refers to the whole or part of the data line (also called data line, data signal line, etc.). The source region is formed by doping P-type impurities (such as boron or gallium) or N-type impurities (such as phosphorus or arsenic). Therefore, it refers to a semiconductor region that contains a large amount of P-type impurities and N-type impurities. The region containing The source electrode is formed of a material different from the source region and is not included in the source region. The term "conductive layer" refers to the portion of the conductive layer that is electrically connected to the source region. The source electrode is sometimes called the source electrode, including the source region. wiring for connecting the source electrodes of the transistors, and wiring for connecting the source electrodes of each pixel. This refers to a wiring for connecting a source electrode to another wiring, or a wiring for connecting a source electrode to another wiring.

[0056] The drain is the same as the source.

[0057] Semiconductor devices include semiconductor elements (transistors, diodes, thyristors, etc.). It refers to a device that has a circuit. Furthermore, it refers to the entire device that can function by utilizing the characteristics of semiconductors. Generally, a device that has semiconductor material can be called a semiconductor device. say.

[0058] The display device refers to a device having a display element. The display device may include a plurality of pixels including a peripheral circuit for driving the plurality of pixels. The peripheral driving circuit for driving the plurality of pixels may include a driving circuit. The display device may be formed on the same substrate as the element. The peripheral drive circuits arranged on the board by the chip-on-glass (COG) It may include an IC chip connected to the board or an IC chip connected by a tab or the like. The display device may contain IC chips, resistors, capacitors, inductors, transistors, etc. The flexible printed circuit (FPC) may be attached. The display device is connected via a flexible printed circuit (FPC) or the like, and the IC chip Printed wiring with resistors, capacitors, inductors, transistors, etc. attached The display device may include an optical element such as a polarizing plate or a retardation plate. The display device may include a lighting device, a housing, an audio input / output device, a light source, and a display sheet. It may also include a sensor.

[0059] The lighting device includes a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflector, It has a sheet, a light source (LED, cold cathode fluorescent lamp, etc.), a cooling device (water-cooled, air-cooled), etc. is also good.

[0060] The light-emitting device refers to a device having a light-emitting element or the like. When the light-emitting device has an element, it is a specific example of a display device.

[0061] The reflecting device is a device that has a light reflecting element, a light diffracting element, a light reflecting electrode, etc. This refers to...

[0062] The liquid crystal display device refers to a display device having a liquid crystal element. There are various types, including visual, projection, transmissive, reflective, and semi-transmissive.

[0063] The driving device refers to a device that has semiconductor elements, electric circuits, and electronic circuits. For example, a transistor (selection transistor) that controls the input of a signal from a source signal line to a pixel (sometimes called a phototransistor or switching transistor) that applies voltage or current to the pixel electrode The transistors that supply voltage or current to the light-emitting element are Furthermore, a circuit for supplying signals to the gate signal lines (gate driver, gate the source signal line driver circuit, and the circuit that supplies signals to the source signal line (source driver A pixel driver (sometimes called a pixel driver or a source line driver circuit) is an example of a driver.

[0064] In addition, display devices, semiconductor devices, lighting devices, cooling devices, light-emitting devices, reflecting devices, driving devices, etc. For example, a display device may have a semiconductor device and a light emitting device. Alternatively, the semiconductor device may have a display device and a driver. This may be the case. [Effects of the Invention]

[0065] According to one embodiment of the invention disclosed in this specification, deterioration of a transistor can be reduced.

[0066] Furthermore, according to one embodiment of the invention disclosed in this specification, malfunction of a circuit caused by deterioration of a transistor can be prevented. It is possible to suppress the good.

[0067] Furthermore, one embodiment of the invention disclosed in this specification improves the reliability of a circuit including a transistor. It can be raised. [Brief explanation of the drawings]

[0068] [Figure 1]1A and 1B illustrate an example of a semiconductor device. [Figure 2] 1A to 1C illustrate a semiconductor device and its operation. [Figure 3] 1A to 1C illustrate a semiconductor device and its operation. [Figure 4] 1A to 1C illustrate a semiconductor device and its operation. [Figure 5] 1A and 1B illustrate an example of a semiconductor device. [Figure 6] 1A to 1C illustrate an example of the operation of a semiconductor device. [Figure 7] 1A to 1C illustrate an example of the operation of a semiconductor device. [Figure 8] 1A to 1C illustrate an example of the operation of a semiconductor device. [Figure 9] 1A to 1C illustrate an example of the operation of a semiconductor device. [Figure 10] 1A to 1C illustrate an example of the operation of a semiconductor device. [Figure 11] 1A to 1C illustrate an example of the operation of a semiconductor device. [Figure 12] 1A and 1B illustrate an example of a semiconductor device. [Figure 13] 1A to 1C illustrate an example of the operation of a semiconductor device. [Figure 14] 1A to 1C illustrate an example of the operation of a semiconductor device. [Figure 15] 1A to 1C illustrate an example of the operation of a semiconductor device. [Figure 16] 1A and 1B illustrate an example of a semiconductor device. [Figure 17] 1A and 1B illustrate an example of a semiconductor device. [Figure 18] 1A and 1B illustrate an example of a semiconductor device. [Figure 19] 1A and 1B illustrate an example of a semiconductor device. [Figure 20] 1A and 1B illustrate an example of a semiconductor device. [Figure 21] 1A and 1B illustrate an example of a semiconductor device. [Figure 22] 1A and 1B illustrate an example of a semiconductor device. [Figure 23] 1A and 1B illustrate an example of a semiconductor device. [Figure 24] 1A and 1B illustrate an example of a semiconductor device. [Figure 25]1A and 1B illustrate an example of a semiconductor device. [Figure 26] 1A and 1B illustrate an example of a semiconductor device. [Figure 27] 1A and 1B illustrate an example of a semiconductor device. [Figure 28] 1A to 1C are diagrams showing usage modes of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0069] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms and in various ways without departing from the spirit and scope of the invention. It will be readily understood by those skilled in the art that various modifications can be made to the embodiments. It should not be construed as being limited to the contents of the description. In the drawings, parts or parts having similar functions are indicated by the same reference numerals, and the same parts or parts having similar functions are indicated by the same reference numerals. A detailed description of parts having similar functions will be omitted.

[0070] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Other content (or even part of content) described in the above, and / or one or more other implementations The content (or part of the content) described in the form of You can do things like:

[0071] The contents described in the embodiments are explained in detail in each embodiment using various drawings. This refers to the content that is stated or the content that is stated using the text in the specification.

[0072] In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more For the figure(s) (even a part of them) described in another embodiment, by combining them, more figures can be constructed.

[0073] In addition, in the figure or text described in a certain embodiment, taking out a part of it it is possible to constitute an aspect of the invention. Therefore, when a figure or text describing a part is provided, the content obtained by taking out a part of the figure or text is also disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, for example, active elements (such as transistors and diodes), wirings, passive elements (such as capacitor elements and resistor elements), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, substrates, modules, devices, solids, liquids, gases, operation methods, manufacturing methods, etc., when described singly or plurally in drawings (cross-sectional views, plan views, circuit diagrams, block diagrams, flowcharts, process diagrams, perspective views , elevation views, layout diagrams, timing charts, structure diagrams, schematic diagrams, graphs, tables, optical path diagrams, vector diagrams, state diagrams, waveform diagrams, photographs, chemical formulas, etc.) or texts, taking out a part of them it is considered that an aspect of the invention can be constituted. As an example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitor elements), extracting M (M is an integer and M < N) circuit elements (such as transistors and capacitor elements), it is possible to constitute an aspect of the invention. Another example is that from a cross-sectional view composed of N (N is an integer) layers, extracting M (M is an integer and M < N) layers, it is possible to constitute an aspect of the invention. Another example is that from a flowchart composed of N (N is an integer) elements, extracting M (M is an integer and M < N) elements, an aspect of the invention can be constituted. Another example is that from a flowchart composed of N (N is an integer) elements, extracting M (M is an integer and M < N) elements to constitute an aspect of the invention. ​ It is possible to configure it.

[0074] In addition, in the drawings or texts described in a certain embodiment, at least one component When a specific example is described, it is easy for a person skilled in the art to derive a generic concept of the specific example. It is understood that, in a drawing or text describing one embodiment, When at least one specific example is described, the generic concept of that specific example is also considered as one aspect of the invention. and can constitute one aspect of the invention.

[0075] At least the contents shown in the drawings (or even a part of the drawings) are disclosed as one aspect of the invention. This is shown and can constitute one aspect of the invention. If the content is shown in the diagram, it is considered to be a part of the It is disclosed as one embodiment of the present invention and can constitute one embodiment of the present invention. Similarly, even if a part of the drawings is taken out, it is not disclosed as one embodiment of the invention. and can constitute one aspect of the invention.

[0076] In addition, there are active elements (transistors, diodes, etc.), passive elements (capacitance elements, resistance elements, etc.) ) and the like, a person skilled in the art can easily identify the terminals to which they are connected without specifying the terminals. This may be possible to configure one aspect of the invention. In particular, when there are multiple terminals to which the terminals are connected, Therefore, it is not necessary to limit the connection of the terminal to a specific location. Some terminals of passive elements (capacitor elements, resistor elements, etc.) By specifying the connection destination only for the child, it is possible to constitute one aspect of the invention. It may be possible.

[0077] In addition, if a person skilled in the art can identify the invention by at least specifying the connection destination of a certain circuit, Or, for a circuit, it may be possible to at least identify its function. Therefore, a person skilled in the art may be able to identify the invention. In this case, even if the function is not specified, as long as the connection destination is specified, it is disclosed as one aspect of the invention. This can constitute one embodiment of the present invention. Even if the connection is not specified, specifying the function is considered to be an embodiment of the invention. This can constitute one aspect of the invention.

[0078] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor will be described.

[0079] The semiconductor device described in this embodiment mode has a structure in which a transistor is formed by a gate insulating film. The direction of the current flowing through the transistor is reversed while it is conducting (On). In other words, during the period when the transistor is conducting, The voltage applied to the first and second terminals (source and drain terminals) of the transistor By switching the magnitude relationship at any time, the source and drain can be switched at any time. The specific circuit configuration and operation will be described below with reference to the drawings. do.

[0080] The semiconductor device shown in this embodiment mode has a transistor provided between the wiring 101 and the wiring 103. and a transistor 111 provided between the wiring 102 and the wiring 103. (See Figure 1(A)).

[0081] One of the source and drain of the transistor 111 is electrically connected to the wiring 101, and the other The first side is electrically connected to the wiring 103. When the transistor 111 is turned on, A signal (IN1) input to the wiring 101 is supplied to the wiring 103. In the case of the transistor, one of the source and the drain is electrically connected to the wiring 102, and the other is electrically connected to the wiring 103. When the transistor 112 is turned on, the signal input to the wiring 102 is A signal (IN2) to be output is supplied to a wiring 103.

[0082] That is, the wiring 103 is connected to a first signal corresponding to the signal (IN1) input to the wiring 101. Alternatively, a second signal corresponding to the signal (IN2) input to the wiring 102 is supplied.

[0083] For example, the first signal may be a high potential (high (H) level signal) and the second signal may be a low potential ( A low (L) level signal is used to turn on or off the transistors 111 and 112. By controlling the OFF state, an H level signal or an L level signal is selectively output to the wiring 103. As shown in FIG. 2A, the gate of the transistor is connected to the wiring 103. By outputting an H-level signal or an L-level signal from the wiring 103, the transistor can be controlled to be on or off.

[0084] In FIG. 1, the transistors 111 and 112 are N-channel transistors. However, a P-channel transistor may be used. The polarity of the resistors 112 may be different, and each transistor may be implemented as a CMOS. The transistor 111 functions as a switch between the wiring 101 and the wiring 103. The transistor 112 can function as a switch between the wiring 102 and the wiring 103 (see FIG. 1 (See (B)).

[0085] In this embodiment, in the configuration shown in FIG. 1, the transistor 111 and the transistor 11 2, the direction of the current flowing through the transistor is reversed. That is, for at least one of the transistors 111 and 112, The voltage applied to the first and second terminals, which are the source and drain terminals of the transistor The magnitude relationship is swapped (the source and drain are swapped) at any time interval.

[0086] In particular, the transistors that remain on for a long period of time during circuit operation are It is preferable to use a configuration in which the direction of current flowing through the transistor is reversed. For example, as shown in Figure 1 In (A), if the transistor 112 remains on for a long period of time, at least The direction of the current flowing through the transistor 112 (direction A or direction B) is reversed. That is, the magnitude relationship between the voltages applied to the first terminal and the second terminal of the transistor 112 is The structure is such that the source and drain are swapped every period.

[0087] A specific operation method will be described below with reference to FIGS.

[0088] In the following description, the gate of the N-channel transistor 121 is electrically connected to the wiring 103. Regarding the configuration where the wiring 103 functions as a gate line, In addition, as a signal to be input to the wiring 102, a signal having a predetermined potential is input. By using a signal that changes every time the transistor 112 is turned on, A case where the direction of the current flowing through the transistor 112 is reversed will be described.

[0089] 2B to 2F show the signal (Out) supplied to the wiring 103 and the signal (B) supplied to the wiring 101, respectively. A signal (IN1) to be input, a signal (IN2) to be input to the wiring 102, and the transistor 11 A signal (IN3) input to the gate of transistor 112. Of course, these signals (IN1 to IN4) are just examples, and the figures The signals are not limited to those shown in 2.

[0090] First, during a period T1, a gate of the transistor 111 is connected to the transistor 111 to turn it on. As a result, the transistor 111 is turned on, A first signal (here, an H-level signal) corresponding to the signal (IN1) input to the wiring 101 (a selection signal that turns on the transistor 121) is input to the wiring 10 via the transistor 111. 3. Then, the gate of the transistor 121 connected to the wiring 103 is selected. A select signal is input, and the transistor 121 is turned on (see FIG. 3(A)).

[0091] During the period T1, the potential of the signal (IN3) input to the gate of the transistor 111 is V H In this case, if the threshold value of the transistor 111 is Vth, the signal output to the wiring 103 is The potential of the signal is V H The potential of the signal output to the wiring 103 is V H In order to In the period T1, the gate of the transistor 111 is set in a floating state, and the bootstrap operation is performed. By performing this operation, the potential of the signal (IN3) input to the gate of the transistor 111 is V H +Vth. Of course, the potential of the signal output to the wiring 103 is V H In order to achieve this, the potential of the signal (IN3) input to the gate of the transistor 111 is first Jime V H +Vth (for example, V H +Vth+α) may be used.

[0092] During the period T1, the transistor 112 is not conductive (off). However, the present invention is not limited to this, and as long as a selection signal is output to the wiring 103, the transistor 1 In this case, the voltage of the signal (IN2) input to the wiring 102 Place is V H It is preferable that:

[0093] Furthermore, the transistor 111 may be turned on in the period before the period T1. In this case, it is desirable that the signal input to the wiring 101 is an L level signal. .

[0094] Next, in the period T2, the gate of the transistor 112 is connected to the transistor 112 to turn the transistor 112 on. At this time, a signal (IN4) that causes the transistor 112 to The potential of the terminal connected to 2 (in this case, V LL ) is the terminal connected to the wiring 103 potential (in this case, V H ), the terminal connected to the wiring 102 becomes the source As a result, the terminal connected to the wiring 103 becomes the drain. 12, the potential between the gate and source VgsB=V H -V LLis the transistor 112 Since the voltage Vcc exceeds the threshold voltage Vth, the transistor 112 is turned on, and the voltage Vcc is input to the wiring 102. A second signal (here, a signal that turns off transistor 121) corresponding to the input signal (IN2) is generated. The non-selection signal, potential V LL ) is supplied to the wiring 103 through the transistor 112.

[0095] A non-selection signal is supplied to the gate of the transistor 121 connected to the wiring 103. In the period T2, the transistor 111 is turned off. However, this is not limited to the case where IN1 is in the OFF state. LL If you want to become a The starter 111 may be in the ON state.

[0096] In this manner, in the period T2, the transistor 112 The potential of the terminal connected to the wiring 101 becomes lower than the potential of the terminal connected to the wiring 103. The terminal connected to the wiring 103 is the drain. The current flows from the drain to the source (direction B in Fig. 2(A)) (see Fig. 3(B)).

[0097] Next, in a period T3, the transistor 111 remains off, and the input signal to the wiring 102 The potential of the signal (IN2) is V LL From V LH (V LL <V LH ) At this time, In the transistor 112, the potential of the terminal connected to the wiring 102 (in this case, V LH ) is the potential of the terminal connected to the wiring 103 (in this case, V LL ) because it will be higher The terminal connected to the wiring 102 becomes the drain, and the terminal connected to the wiring 103 becomes the drain. In the transistor 112, the potential between the gate and the source VgsA=V H -V LH remains above the threshold of transistor 112, 112 remains on, and a second signal corresponding to the signal (IN2) input to the wiring 102 is output. signal (here, a non-selection signal that turns off transistor 121, a potential V LH ) is a transistor The voltage is supplied to the wiring 103 via the power supply 112 .

[0098] A non-selection signal is input to the gate of the transistor 121 connected to the wiring 103. Therefore, the transistor 121 remains in the off state. LH and potential V L L are different from each other, and when applied to the gate of transistor 121, the voltage of transistor 121 For example, at the source or drain of the transistor 121, The lowest potential is Vmin, the highest voltage is Vmax, and the threshold voltage of the transistor 121 is V When the voltage is Vth, V LH -Vmin <Vth、V H -Vmax>Vth It can be considered a relationship.

[0099] In this manner, in the period T3, the transistor 112 The potential of the terminal becomes higher than the potential of the terminal connected to the wiring 103. The terminal connected to the wiring 103 is the source. The current flows from the drain to the source (direction A in Fig. 2(A)) (see Fig. 3(C)).

[0100] In the subsequent periods Tn to T(n+1), the operations of periods T2 to T3 are repeated. The wiring 103 is supplied with a potential V LL and potential V LH A second signal is provided to switch (Here, the potential is V LH signal, the potential is V during even periods LL A signal is supplied The transistor 121 remains in the off state. The on state is maintained, but the direction of the current is reversed (see Figure 3(D)(E)).

[0101] That is, in this embodiment, the transistor 112 that continues to output the L level signal is By inputting a L level signal (non-selection signal) whose potential changes every period, the transistor In the transistor 112, the magnitude relationship of the voltages of the two terminals serving as the source and drain is swapped. The direction of current flow through transistor 112 is reversed.

[0102] In this way, the direction of current flow through transistor 112 is reversed (the source and drain are reversed). By using a configuration in which the transistor 121 is switched off, the transistor Even if transistor 112 is turned on for a long period of time, the charge of transistor 112 This alleviates the concentration of the electric field at the panel (drain end) and reduces the deterioration of the transistor 112. As a result, circuit malfunctions caused by transistor degradation are suppressed, improving reliability. can be improved.

[0103] In particular, amorphous silicon and microcrystalline silicon (microcrystalline silicon) are used as transistors. When a channel is formed using a material such as a silicon dioxide (SiO2) or a nanocrystal, the circuit can be operated for a long period of time. It is possible to operate a transistor that remains on for a short time as shown in Figures 2 and 3. This is effective in reducing the deterioration of the resistor. Even if there are, for example, polysilicon, oxide semiconductor (ZnO, IGZO (InGaZnO) Even when organic semiconductors, carbon nanotubes, etc. are used as the channel formation region, This is effective in reducing the degradation of the transistor.

[0104] In Figure 2, the potential is V LH a first potential consisting of V L L A second potential (V LH >V LL ) is used, where the signal changes every arbitrary period. However, the signals input to the wiring 102 are not limited to two types of signals having different potentials. Three or more different potentials may be used as long as they do not turn on the transistor 121. The combined signals may be input to transistor 112 .

[0105] In addition, in FIG. 2, the potential of the wiring 102 is V LH a first potential consisting of V LL mosquito The second potential is input alternately and repeatedly for the same period. The period for inputting the potential V can be set arbitrarily. LH a first potential consisting of V LL The second potential consisting of Even if it is necessary, the period can be set arbitrarily.

[0106] Furthermore, the signals (IN1 to IN4) shown in FIG. 2 are merely an example, and are not limited to this. For example, In FIG. 2, when a signal of a constant potential is input to the wiring 101 (for example, when the wiring 101 is connected to a power supply However, when other signals (for example, clock signals) are input to the wiring 101, In addition, in the above-described FIG. 2, the transistor 111 is turned on during the period T2 to the period Tn. However, when an L level signal is supplied from the wiring 101, A period during which the transistor 111 is in the ON state may be provided.

[0107] In addition, in the period T1, the potential of the signal (IN4) input to the gate of the transistor 112 V LL However, this is not limited to the case as long as the transistor 112 is turned off. For example, when the potential of the signal (IN4) input to the gate of the transistor 112 is V LL In this case, when the transistor 112 is off, Vgs may be set to a lower potential. Since the voltage can be made lower than 0 V, deterioration of the transistor 112 can be effectively suppressed. It is possible.

[0108] In addition, in FIG. 2, the transistor 112 maintains an on state during the period T2 to the period Tn. However, the present invention is not limited to this. For example, in a certain period from period T2 to period Tn, In other words, the transistor 112 may be turned off when the The on-period and off-period are combined, and in the on-period, the The direction of the current flowing through the transistor 112 is reversed. This can more effectively suppress the deterioration of the transistor 112. During this period, the potentials of the wiring 102 and the wiring 103 may be equal to or different from each other. The period during which the transistor 112 is turned off is not particularly limited, but it is preferable to turn it off in consideration of ease of control. Therefore, it is preferable to make the ON period and OFF period of the transistor 112 approximately equal. .

[0109] In addition, in the semiconductor device described in this embodiment, as described above, the gate of the transistor 111 By temporarily floating the capacitance between the gate and source of the transistor 111, A circuit configuration can be adopted in which a bootstrap operation utilizing coupling is applied. As shown in FIG. 1C, the gate of the transistor 111 and one of the source and drain A capacitor 115 may be provided between the first and second electrodes. The bootstrap operation can be performed stably. If a sufficient parasitic capacitance occurs between the source or drain, a capacitance element 115 is provided. It is also possible to perform the bootstrap operation without

[0110] In this embodiment, the current flowing through the transistor 112 that continues to output the L level signal is The example shows a configuration in which the direction of the transistor 111 is reversed, but the transistor 111 continues to output an L level signal. In this case, the direction of the current flowing through the transistor 111 may be reversed. In this case, the potential of the signal (IN1) input to the wiring 101 is V LH The first electrode consists of potential and V LL A second potential (V LH >V LL ) will be switched every arbitrary period. A signal can be used.

[0111] Furthermore, when the transistor 112 (or the transistor 111) continues to output an H level signal, In this case, the direction of the current flowing through the transistor 112 (or transistor 111) is entered. In this case, the signal input to the wiring 102 (or the wiring 101) is The potential is V HH a first potential consisting of V HL A second potential (V HH >V HL ) can be used as a signal that switches at any period.

[0112] Of course, the direction of current flow in both transistor 111 and transistor 112 is reversed. For example, the wiring 101 is connected to the wiring 102 through the transistor 111. 3, a high-level signal is supplied to the wiring 102 through the transistor 112. When an L-level signal is supplied, the potential of the signal (IN1) input to the wiring 101 is V H H a first potential consisting of V HL The second potential is switched every arbitrary period. The potential of the signal (IN2) input to the wiring 102 is V LH The first electrode consists of potential and V LL A signal in which the second potential is switched every arbitrary period can be used. can.

[0113] In this embodiment, the transistors 111, 112, and 113 are Although the case where 21 is provided as an N-channel transistor is shown, a P-channel transistor may also be used. It may be provided by a P-channel transistor (see FIGS. 4(A) to 4(F)). In this case, the potential of the signal input to the wiring 102 is V HH a first potential consisting of V HL A second potential (V HH>V HL ) can be switched at any time. By this, the direction of the current flowing through the transistor 112 is reversed. As a result, deterioration of the transistor 112 can be reduced and malfunction of the circuit can be suppressed. In FIG. 4, the transistor 111, the transistor 112, and the transistor Although the case where 121 is provided as a P-channel transistor has been shown, the transistor 121 may be an N-channel transistor. A channel type transistor may be used.

[0114] Note that the configuration shown in this embodiment mode may be different from other configurations shown in this specification (other embodiments). The present invention can be implemented by appropriately combining it with other configurations (including configurations in which the above-mentioned configurations are used).

[0115] (Embodiment 2) In this embodiment mode, an example of a semiconductor device having a different structure from that of the above embodiment mode is shown in the drawings. Please refer to the following for explanation.

[0116] The semiconductor device shown in this embodiment mode has a transistor provided between the wiring 101 and the wiring 103. A transistor 111 and a plurality of transistors arranged in parallel between the wiring 102 and the wiring 103. 5A. That is, the casing 112a and 112b shown in FIG. 5A are included. The configuration shown in A) is a configuration in which a transistor 112b is added to the configuration shown in FIG. (The transistor 112a in FIG. 5 corresponds to the transistor 112 in FIG. 1.) In FIG. 5A, two transistors (transistors 112a and 112b) are arranged in parallel. Although the case where three or more transistors are provided is shown, the number of transistors may be three or more.

[0117] The transistors 112a and 112b have one of a source and a drain electrically connected to the wiring 102. One end is connected to the wiring 103, and the other end is connected to the wiring 103, and they are provided in parallel to each other. When at least one of the transistors 112a and 112b is turned on, the wiring 102 A signal (IN2) to be input to the input terminal is supplied to the wiring 103.

[0118] The wiring 103 is connected to a first signal corresponding to a signal (IN1) input to the wiring 101 or a A second signal corresponding to the signal input on line 102 (IN2) is provided.

[0119] In FIG. 5, the transistor 111 and the transistors 112a and 112b are N-channel transistors. However, it may be a P-channel type or a CMOS type. The transistor 111 functions as a switch between the wiring 101 and the wiring 103. The transistors 112a and 112b function as switches between the wiring 102 and the wiring 103. It works (see Figure 5(B)).

[0120] In this embodiment, a plurality of transistors (transistors 11 in FIG. 5) are arranged in parallel. 2a, 112b) are alternately turned on and off. Then, the current flowing through the multiple transistors The direction of the voltage applied to the source or drain terminal of the transistor is reversed. The magnitude relationship is swapped for each period (the source and drain are swapped). The on / off control of a plurality of transistors arranged in parallel is performed. By controlling the direction of the current flowing through the transistor, the channel (drain) This reduces the concentration of the electric field at the terminals (edges) and reduces degradation.

[0121] A specific operation method will be described below with reference to the drawings.

[0122] [Operation when the IN2 cycle is smaller than the IN4 and IN5 cycles] 6A to 6F show the signal (Out) output from the wiring 103, the signal (B) output from the wiring 101, a signal (IN1) input to the wiring 102; a signal (IN2) input to the transistor 1 A signal (IN3) is input to the gate of transistor 111, and a signal (IN4) is input to the gate of transistor 112a. The signal (IN4) and the signal (IN5) input to the gate of the transistor 112b are shown. In FIG. 6, the cycle of the signal (IN2) input to the wiring 102 is This shows the case where the signal (IN4, IN5) input to the gate of 112b is 1 / 2. Of course, the input signals (IN1 to IN5) are just examples and are not limited to these. No.

[0123] FIG. 6G shows the direction of current flow in the transistors 112a and 112b. A1, A2, B1, and B2 correspond to the directions shown in Figure 5. Furthermore, periods during which the transistor is off and no current flows are indicated by x.

[0124] First, during a period T1, a gate of the transistor 111 is connected to the transistor 111 to turn it on. As a result, the transistor 111 is turned on, A first signal (here, an H-level signal) corresponding to the signal (IN1) input to the wiring 101 A selection signal (selection signal) is supplied to the wiring 103 through the transistor 111. When the gate of the transistor 121 is connected (see FIG. 5C), the wiring 10 A selection signal is input to the gate of transistor 121 connected to transistor 3, and transistor 1 21 turns on.

[0125] During the period T1, the potential of the signal (IN3) input to the gate of the transistor 111 is V H In this case, if the threshold value of the transistor 111 is Vth, the signal output to the wiring 103 is The potential of the signal is V H In this case, the potential of the signal output to the wiring 103 is V H and To achieve this, the gate of the transistor 111 is set to a floating state during the period T1, and the bootstrap Of course, the potential of the signal output to the wiring 103 may be V H In order to achieve this, the potential of the signal (IN3) input to the gate of the transistor 111 is Kajime V H It may be set to +Vth or higher.

[0126] During the period T1, the transistors 112a and 112b are in the off state. However, this is not limiting, and as long as a selection signal is output to the wiring 103, a transistor In this case, the signal input to the wiring 102 is (IN2) potential is V H It is preferable that:

[0127] Next, in the period T2, the transistor 112a is connected to the gate of the transistor 112a. At this time, the transistor 112a is turned on by a signal (IN4). The potential of the terminal connected to the line 102 (in this case, V LL ) is connected to wire 103 The potential of the terminal (in this case, V H ), so that the terminal connected to the wiring 102 The terminal connected to the wiring 103 becomes the drain. In the transistor 112a, the potential between the gate and the source VgsB is VH -V LL is a transistor Since the voltage Vcc exceeds the threshold voltage Vth of the transistor 112a, the transistor 112a is turned on. The potential corresponding to the signal (IN2) input to 102 is V LL The second signal (non-select signal) is supplied to the wiring 103 through the transistor 112a.

[0128] When the gate of the transistor 121 is connected to the wiring 103, A non-selection signal is input to the gate of the connected transistor 121, and the transistor 12 1 turns off.

[0129] Subsequently, in the second half of the period T2, the potential of the signal (IN2) input to the wiring 102 changes. (Here, V LL From V LH At this time, in the transistor 112a, , the potential of the terminal connected to the wiring 102 (in this case, V LH ) is connected to wire 103 The potential of the terminal that is connected (in this case, V LL ) and is therefore connected to the wiring 102. The terminal connected to the wiring 103 becomes the drain, and the terminal connected to the wiring 103 becomes the source. In the transistor 112a, the potential between the gate and the source VgsA=V H -V LL Gatran Since the threshold voltage of the transistor 112a is higher than the threshold voltage of the transistor 112a, the transistor 112a remains on. The potential corresponding to the signal (IN2) input to the wiring 102 is V LH The second signal (non-selected A select signal is supplied to the wiring 103 through the transistor 112a.

[0130] When the gate of the transistor 121 is connected to the wiring 103, Since a non-selection signal is input to the gate of the connected transistor 121, the transistor The timer 121 remains off.

[0131] In this manner, in the first half of the period T2, the transistor 112a connected to the wiring 102 The potential of the terminal connected to the wiring 103 becomes lower than the potential of the terminal connected to the wiring 104. The terminal connected to the wiring 102 is the source, and the terminal connected to the wiring 103 is the drain. The current flows from the drain to the source (direction B1 in FIG. 5). In the second half of the second half, the potential of the terminal of the transistor 112a connected to the wiring 102 is When the potential of the terminal connected to the wiring 102 becomes higher than the potential of the terminal connected to the wiring 103, The terminal connected to the wiring 103 becomes the drain, and the terminal connected to the wiring 104 becomes the source. It flows from the drain to the source (direction A1 in Figure 5).

[0132] Next, in period T3, the transistor 112a is turned off and the gate of the transistor 112b is turned off. A signal (IN5) that turns on the transistor 112b is input to the transistor 112b. In the transistor 112b, the potential of the terminal connected to the wiring 102 (in this case, V L L ) is the potential of the terminal connected to the wiring 103 (in this case, V LH ) is lower than The terminal connected to the wiring 102 is the source, and the terminal connected to the wiring 103 is the drain. As a result, the gate-source potential Vg sB=V H -V LL becomes larger than the threshold of transistor 112b. The inverter 112b is turned on, and the potential V LL The second signal (non-selection signal) is supplied to the wiring 103 through the transistor 112b. do.

[0133] When the gate of the transistor 121 is connected to the wiring 103, Since a non-selection signal is input to the gate of the connected transistor 121, the transistor The timer 121 remains off.

[0134] Next, in the second half of the period T3, the potential of the signal (IN2) input to the wiring 102 changes. (Here, V LL From V LH At this time, in the transistor 112b, , the potential of the terminal connected to the wiring 102 (in this case, V LH ) is connected to wire 103 The potential of the terminal that is connected (in this case, V LL ) and is therefore connected to the wiring 102. The terminal connected to the wiring 103 becomes the drain, and the terminal connected to the wiring 103 becomes the source. In the transistor 112b, the potential between the gate and the source VgsA=V H -V LL Gatran Since the threshold voltage of the transistor 112b is higher than the threshold voltage of the transistor 112b, the transistor 112b remains on. The potential V corresponding to the signal (IN2) input to the wiring 102 LH The second signal (unselected The signal is supplied to the wiring 103 through the transistor 112b.

[0135] When the gate of the transistor 121 is connected to the wiring 103, Since a non-selection signal is input to the gate of the connected transistor 121, the transistor The timer 121 remains off.

[0136] In this way, in the first half of the period T3, the transistor 112b connected to the wiring 102 The potential of the terminal connected to the wiring 103 becomes lower than the potential of the terminal connected to the wiring 104. The terminal connected to the wiring 102 is the source, and the terminal connected to the wiring 103 is the drain. The current flows from the drain to the source (direction B2 in Figure 5). In the second half of the second half, the potential of the terminal of the transistor 112b connected to the wiring 102 is When the potential of the terminal connected to the wiring 102 becomes higher than the potential of the terminal connected to the wiring 103, The terminal connected to the wiring 103 becomes the drain, and the terminal connected to the wiring 104 becomes the source. It flows from the drain to the source (direction A2 in Figure 5).

[0137] In the subsequent periods T4 to Tn, the same operation as in period T2 or period T3 is performed.

[0138] During the periods T3 to Tn, when the transistor 112a is on, During the first half of this period, the potential from the wiring 102 is V LL A second signal is supplied to the wiring 103. During the latter half of the ON period, the potential from the wiring 102 is V LH The second signal is The voltage is supplied to the wiring 103. Therefore, during the period in which the transistor 112a is on, During the first half of the period, the terminal connected to the wiring 102 becomes the source, and the terminal connected to the wiring 103 becomes the source. The terminal where the current flows is the drain, and current flows from the drain to the source (direction B1 in Figure 5). In addition, during the latter half of the period in which the transistor 112a is on, The terminal connected to the wiring 103 becomes the drain, and the terminal connected to the wiring 104 becomes the source, and the current flows from the drain to the source (direction A1 in Figure 5).

[0139] Also, during the period when the transistor 112a is on (while the transistor 112b is off), In the latter half of the period, the potential of the wiring 102 is V LH Therefore, the transistor 112 At point b, the gate-source voltage (Vgs) becomes negative (Vgs<0V). In the transistor 112b, the gate-source voltage (Vgs) is negative (Vgs<0V). By providing a period in which this occurs, deterioration of the transistor can be effectively suppressed.

[0140] During the periods T3 to Tn, when the transistor 112b is on, During the first half of this period, the potential from the wiring 102 is V LL A second signal is supplied to the wiring 103. During the latter half of the ON period, the potential from the wiring 102 is V LH The second signal is The voltage is supplied to the wiring 103. Therefore, during the period in which the transistor 112b is on, During the first half of the period, the terminal connected to the wiring 102 becomes the source, and the terminal connected to the wiring 103 becomes the source. The terminal where the current flows is the drain, and current flows from the drain to the source (direction B2 in Figure 5). In addition, during the latter half of the period in which the transistor 112b is on, The terminal connected to the wiring 103 becomes the drain, and the terminal connected to the wiring 104 becomes the source, and the current flows from the drain to the source (direction A2 in Figure 5).

[0141] Moreover, during the period when the transistor 112b is on (while the transistor 112a is off), In the latter half of the period, the potential of the wiring 102 is V LH Therefore, the transistor 112 At point a, the gate-source voltage (Vgs) becomes negative (Vgs<0V). In the transistor 112a, the gate-source voltage (Vgs) is negative (Vgs<0V). By providing a period in which this occurs, deterioration of the transistor can be effectively suppressed.

[0142] In this way, multiple transistors arranged in parallel are alternately turned on and off, The direction of the current flowing through the transistor is reversed while the transistor is on (transistor The magnitude relationship between the voltage applied to the first terminal and the second terminal (the terminal that becomes the source or drain) of the By using a configuration in which the relationship between the source and drain is swapped every period, This can reduce the concentration of the electric field at the channel part (drain end) of the transistor and reduce degradation. As a result, malfunctions of the circuit caused by the deterioration of the transistors are suppressed, and reliability is improved. It is possible.

[0143] As shown in FIG. 6, the transistors 112a and 112b are turned on. It is preferable to make the on period and the off period approximately equal from the viewpoint of ease of control. In this case, half of the period during which the transistors 112a and 112b are on The direction of the current flowing through the transistor can be changed every time.

[0144] In FIG. 6, a plurality of transistors (transistor 112a, transistor The case where transistor 112a and transistor 112b are alternately turned on and off is shown. The transistor 112b may be operated so that the on and off periods overlap. The period when both the transistor 112a and the transistor 112b are on and the period when both are off are A period of time may be set.

[0145] 6, the cycle of the signal (IN2) input to the wiring 102 is , the case where the signal (IN4, IN5) input to the gate of 112b is 1 / 2 is shown. However, it is not limited to this, and it may be smaller or larger than 1 / 2. The phase of the signal (IN2) input to the line 102 may be shifted. The input signal (IN2) may be shifted in phase by 1 / 2 or 1 / 4 period.

[0146] In addition, in the operation of the structure shown in FIG. 5, the period of the signal (IN2) input to the wiring 102 is the period of the signals (IN4, IN5) input to the gates of the transistors 112a and 112b. The period of the signal (IN2) input to the wiring 102 is not limited to a period smaller than 1 / 2. The period of the signals (IN4, IN5) input to the gates of the transistors 112a and 112b is The cases where the two are the same and where they are larger will be explained with reference to the drawings.

[0147] [Operation when the IN2 cycle is greater than the IN4 and IN5 cycles] In the following description, (A) to (F) in FIG. 7 and FIG. 8 respectively represent the signals output from the wiring 103. A signal (Out) input to the wiring 101 (IN1), a signal (IN2) input to the wiring 102 (IN3), signal (IN2), a signal (IN3) input to the gate of the transistor 111, A signal (IN4) is input to the gate of the transistor 112a, and a signal (IN5) is input to the gate of the transistor 112b. 7 and 8, the signal (IN5) input to the wiring 102 is shown. 2) is input to the gates of the transistors 112a and 112b. 5) (when the period of IN2 is twice the period of IN4 and IN5) Of course, the input signals (IN1 to IN5) are just examples and are not limited to these. No.

[0148] 7 and 8(G) show the current flows of the transistors 112a and 112b. A1, A2, B1, and B2 correspond to the directions shown in Figure 5. The period when the transistor is off and no current flows is indicated by an x. The period when the transistor is on but no current flows is indicated by -.

[0149] First, during a period T1, the gate of the transistor 111 is connected to turn the transistor 111 on. A signal (IN3) corresponding to the period T1 is input. Here, the operation is the same as that in the period T1 in FIG.

[0150] Next, in the period T2, the transistor 112a is connected to the gate of the transistor 112a. At this time, the signal (IN4) that turns on the transistor 112a is input. The potential of the terminal connected to 102 (in this case, V LL ) is connected to the wiring 103 The potential at the terminal (in this case, V H ), the terminal connected to the wiring 102 is The terminal connected to the wiring 103 becomes the drain. In the capacitor 112a, the potential between the gate and the source VgsB=V H -V LL is transistor 1 Since the threshold voltage of the transistor 112a is greater than the threshold voltage of the transistor 112a, the transistor 112a is turned on, and the The potential corresponding to the signal (IN2) input to 02 is V LL The second signal (non-select signal) The voltage is supplied to the wiring 103 through the transistor 112a.

[0151] When the gate of the transistor 121 is connected to the wiring 103 (see FIG. 5C), A non-selection signal is input to the gate of the transistor 121 connected to the wiring 103. , transistor 121 is turned off.

[0152] In this manner, in the period T2, the transistor 112a connected to the wiring 102 The potential of the terminal connected to the wiring 103 becomes lower than the potential of the terminal connected to the wiring 104. The terminal connected to the wiring 102 is the source, and the terminal connected to the wiring 103 is the drain. and current flows from the drain to the source (direction B1 in FIG. 5).

[0153] Next, in the period T3, the transistor 112a is connected to the gate of the transistor 112a. A signal (IN4) for turning off the transistor is input, and the gate of the transistor 112b is connected to the transistor. A signal (IN5) is input to turn on the transistor 112b, and the transistors 112a and At this time, the transistor 112b is turned on and off. The potential of the terminal connected to 102 (in this case, V LH ) is connected to the wiring 103 The potential at the terminal (in this case, V LL ), the terminal connected to the wiring 102 The terminal connected to the wiring 103 becomes the drain, and the terminal connected to the wiring 104 becomes the source. In the transistor 112b, the potential between the gate and the source VgsA is V H -V LL is a transistor Since the voltage Vcc exceeds the threshold voltage Vth of the transistor 112b, the transistor 112b is turned on. The potential corresponding to the signal (IN2) input to 102 is V LH The second signal (non-select signal) is supplied to the wiring 103 through the transistor 112b.

[0154] In this manner, in the period T3, the transistor 112b connected to the wiring 103 The potential of the terminal connected to the wiring 102 becomes lower than the potential of the terminal connected to the wiring 102. The terminal connected to the wiring 102 is the drain. and current flows from the drain to the source (direction A2 in Figure 5).

[0155] Also, in the period T3, the gate-source voltage (Vgs) of the transistor 112a In this way, in the transistor 112a, the gate and By providing a period where the base voltage (Vgs) is negative (Vgs<0V), Compared to when V is used, deterioration of the transistor can be effectively suppressed.

[0156] Next, in the period T4, the gate of the transistor 112a is connected to the transistor 112a. A signal (IN4) to turn on the transistor is input, and the gate of the transistor 112b is connected to the transistor. A signal (IN5) is input to turn off the transistor 112a and the transistor 112b. The on and off states of the capacitor 112b are alternately changed. LH To hold , the potential of the wiring 103 is also V LH Therefore, in the transistor 112a, The potential of the terminal connected to the line 102 is equal to the potential of the terminal connected to the line 103. Therefore, no current flows through transistor 112a.

[0157] Next, in the period T5, the gate of the transistor 112a is connected to the transistor 112a. A signal (IN4) for turning off the transistor is input, and the gate of the transistor 112b is connected to the transistor. A signal (IN5) is input to turn on the transistor 112b, and the transistors 112a and At this time, the transistor 112b is turned on and off. The potential of the terminal connected to 102 (in this case, V LL ) is connected to the wiring 103 The potential at the terminal (in this case, V LH ), so that the terminal connected to the wiring 102 The terminal connected to the wiring 103 becomes the drain. In the transistor 112b, the potential between the gate and the source VgsB is V H -V LL is a transistor Since the voltage Vcc exceeds the threshold voltage Vth of the transistor 112b, the transistor 112b is turned on. The potential corresponding to the signal (IN2) input to 102 is V LL The second signal (non-select signal) is supplied to the wiring 103 through the transistor 112b.

[0158] In this manner, in the period T5, the transistor 112b connected to the wiring 102 The potential of the terminal connected to the wiring 103 becomes lower than the potential of the terminal connected to the wiring 104. The terminal connected to the wiring 102 is the source, and the terminal connected to the wiring 103 is the drain. and current flows from the drain to the source (direction B2 in Figure 5).

[0159] In the subsequent periods T6 to Tn, the operations of the periods T2 to T5 are repeated. The transistor 111 remains off, and the transistors 112a and 112b are alternately turned on. , the wiring 103 is connected to a potential V LH and the potential V LL A signal that switches at any interval is input. Therefore, when the gate of the transistor 121 is connected to the wiring 103, The transistor 121 remains stably off.

[0160] In the operation method shown in FIG. 7, the direction of the current flowing through the transistor 112a is reversed. Therefore, the wiring 10 The period of the signal (IN2) input to the input terminal 2 is shifted, and the direction of the current flowing through the transistor 112a is changed. It is preferable to have a configuration in which the directions are reversed.

[0161] FIG. 8 shows how the signal (IN2) input to the wiring 102 is shifted to change the voltage of the transistor 11. This shows the case where the direction of the current flowing through 2a is reversed. reverses the direction of current flow through transistor 112b (switching the source and drain) Therefore, when the circuit is operating, the operation shown in Figure 7 and the operation shown in Figure 8 By switching the operation for each period, the period of the signal (IN2) input to the wiring 102 can be The period is determined by signals (IN4, IN5) input to the gates of the transistors 112a and 112b. Even if the capacitance is increased, the deterioration of the transistors 112a and 112b is reduced. It is possible.

[0162] 7 and 8, a plurality of transistors (transistor 112a, transistor The case where transistor 112a and transistor 112b are alternately turned on and off is shown. The transistor 112b may be operated so that the on and off periods overlap. The period when both the transistor 112a and the transistor 112b are on and the period when both are off are A period of time may be set.

[0163] 7 and 8, the period of the signal (IN2) input to the wiring 102 is This shows the case where the signal input to the gates 12a and 12b is twice the signal (IN4, IN5). However, the present invention is not limited to this and may be smaller or larger than twice the size.

[0164] [Operation when the IN2 cycle is equal to the IN4 and IN5 cycles] In the following description, (A) to (F) in FIG. 9 and FIG. 10 respectively represent the signals output from the wiring 103. A signal (Out) input to the wiring 101, a signal (IN1) input to the wiring 102, signal (IN2), a signal (IN3) input to the gate of the transistor 111, A signal (IN4) is input to the gate of the transistor 112a, and a signal (IN5) is input to the gate of the transistor 112b. 9 and 10, the signal (IN5) input to the wiring 102 is shown. The period of the signal (IN4, IN2) input to the gates of the transistors 112a and 112b is Of course, the period of the input signal (IN1 to IN5) is equal to the period of the input signal (IN1 to IN5). ) are examples and are not limited to these.

[0165] 9 and 10(G) show the currents of the transistors 112a and 112b. The flow directions are shown as A1, A2, B1, and B2, which correspond to the directions shown in Figure 5. The period when the transistor is off and no current flows is indicated by an x. The period when the transistor is on but no current flows is indicated by -.

[0166] In this embodiment, the operation shown in FIG. 9 and the operation shown in FIG. 10 are alternately performed at intervals of an arbitrary period. This causes the transistor to operate.

[0167] First, during certain periods Tx1 to Txn, when the transistor 112a is on, The potential is V LL A second signal, which is When the potential from the wiring 102 is V LH A second signal, which is reference).

[0168] Therefore, during the periods Tx1 to Txn, when the transistor 112a is on, the transistor In the master 112a, the terminal connected to the wiring 102 is the source, and the terminal connected to the wiring 103 is the The terminal connected to the drain becomes the drain, and current flows from the drain to the source (direction B1 in Figure 5). When the transistor 112b is turned on, the transistor 112b The terminal connected to the wiring 102 is the drain. The current flows from the drain to the source (direction A2 in Figure 5). When the transistor 112a is off, the gate-source voltage (Vg s) can be negative (Vgs<0V), so compared to the case where Vgs=0V This effectively suppresses the deterioration of the transistor.

[0169] Note that when a current flows through the transistors 112a and 112b, The potential of the terminal connected to the wiring 102 and the potential of the terminal connected to the wiring 103 are equal. When the voltage becomes too high, the distinction between source and drain disappears.

[0170] During another period Ty1 to Tyn, when the transistor 112a is on, The potential is V LH A second signal, which is When the potential from the wiring 102 is V LL A second signal, which is reference).

[0171] Therefore, during the period Ty1 to Tyn, when the transistor 112a is on, the transistor In the stator 112a, the terminal connected to the wiring 102 becomes the drain, and the terminal connected to the wiring 103 becomes the drain. The connected terminal becomes the source, and current flows from the drain to the source (direction A1 in Figure 5). When the transistor 112b is turned on, the transistor 112b The terminal connected to the wiring 102 is the source. The current flows from the drain to the source (direction B2 in Figure 5). When the transistor 112b is off, the gate-source voltage (Vg s) can be negative (Vgs<0V), so compared to the case where Vgs=0V This effectively suppresses the deterioration of the transistor.

[0172] Therefore, the cycle of the signal (IN2) input to the wiring 102 is shifted every arbitrary period (for example, 9 and 10 (for example, by inverting the 11), the direction of current flowing through transistor 112a and transistor 112b, respectively. (The magnitude relationship of the voltage applied to the source or drain terminal of the transistor is The source and drain can be switched every period. As a result, the channel portions (drain ends) of the transistors 112a and 112b This can alleviate the concentration of the electric field and reduce deterioration. By alternately turning on and off the transistors (transistor 112a and transistor 112b), This makes it possible to suppress the deterioration of the transistor.

[0173] The arbitrary period may be, for example, a period in which the semiconductor device of this embodiment is connected to a gate driver of a display device. When applied as a driver, the operation shown in Figure 9 and the operation shown in Figure 10 are switched every frame period. can be replaced.

[0174] 9 and 10, the signal (IN2) input to the wiring 102 and the transistor 112 a, the rising and falling edges of the signals (IN4, IN5) input to the gates of 112b However, the present invention is not limited to this. For example, The period of the input signal (IN2) may be shifted in phase by 1 / 4 period.

[0175] As shown in this embodiment mode, a plurality of transistors provided in parallel are alternately turned on and off. At the same time, the direction of the current flowing through the plurality of transistors is switched (transistor The magnitude relationship of the voltage applied to the source or drain terminal of By using a structure in which the channel (drain) of the transistor is swapped, This reduces the concentration of the electric field at the in-edge (the end of the transistor) and effectively suppresses transistor degradation. become.

[0176] In this embodiment, the transistor 111, the transistor 112a, and the transistor 1 Although the case where the transistor 12b and the transistor 121 are N-channel transistors has been shown, In this case, the transistors 112a and 112b may be P-channel transistors. By operating the transistor so that the direction of the current flowing through 2b is reversed, the deterioration of the transistor This reduces the risk of circuit malfunction.

[0177] In this embodiment, the circuit is configured to continuously output an L level signal during operation. However, if the H level signal continues to be output, the wiring 101 and the wiring 103 are parallel to each other. A plurality of transistors are provided, and a signal input to the wiring 101 has a potential of V L H a first potential consisting of V LL The second potential is switched every arbitrary period. The signal may be used.

[0178] Note that the configuration shown in this embodiment mode may be different from other configurations shown in this specification (other embodiments). The present invention can be implemented by appropriately combining it with other configurations (including configurations in which the above-mentioned configurations are used).

[0179] (Embodiment 3) In this embodiment mode, an example of a semiconductor device having a different structure from that of the above embodiment mode is shown in the drawings. Please refer to the following for explanation.

[0180] The semiconductor device shown in this embodiment mode has a transistor provided between the wiring 101 and the wiring 103. a transistor 111, a transistor 112 provided between the wiring 102 and the wiring 103, and a wiring 10 1 and a transistor 114 provided between the first and second wirings 104 and the wiring 103 (FIG. 1). 2(A)).

[0181] One of the source and drain of the transistor 114 is electrically connected to the wiring 104, and the other 12 is connected to the wiring 103. In other words, the configuration shown in FIG. 12 is similar to the configuration shown in FIG. Add a line 104 and connect either the source or drain of the transistor 112b in FIG. The transistor is electrically connected to the wiring 104 instead of the wiring 102. When the inverter 114 is turned on, the signal (IN6) input to the wiring 104 is input to the wiring 103. Supplied.

[0182] Therefore, the wiring 103 is connected to a first signal corresponding to the signal (IN1) input to the wiring 101. a signal input to the wiring 102 (IN1), a second signal corresponding to the signal input to the wiring 104 (IN2), or A third signal corresponding to the input signal (IN6) is provided.

[0183] In this way, by providing the wiring 102 and the wiring 104 separately, the transistor 112 and transistor 114 can be simultaneously supplied with different signals. This reduces the wave number and makes it possible to reduce power consumption.

[0184] In FIG. 12, the transistors 111, 112, and 114 are Although the example shown is an N-channel type, it may be a P-channel type or a CMOS type. The transistor 111 may be a switch between the wiring 101 and the wiring 103. The transistor 112 functions as a switch between the wiring 102 and the wiring 103. The transistor 114 functions as a switch between the wiring 104 and the wiring 103 ( See Figure 12(B)).

[0185] In this embodiment, when a specific signal (for example, a non-selection signal) is continuously supplied to the wiring 103, In this case, one of the source and the drain is connected to the wiring 103, and the other is connected to the wiring 103. Multiple transistors connected to different wirings (in FIG. 12, transistors 112 and 114) ) are alternately turned on and off, and the direction of the current flowing through the transistors is changed. (The magnitude relationship of the voltage applied to the source or drain terminal of the transistor is changed every period.) In other words, the source and drain are swapped. By controlling the on and off state of the transistor and controlling the direction of the current flow, This reduces the concentration of the electric field in the channel part (drain end) of the transistor, thereby reducing degradation.

[0186] A specific operation method will be described below with reference to the drawings.

[0187] In the following description, (A) to (G) in FIG. 13 and FIG. 14 respectively show the output from the wiring 103. A signal (Out) input to the wiring 101, a signal (IN1) input to the wiring 102, a signal (IN2) input to the wiring 104, a signal (IN6) input to the gate of the transistor 111, a signal (IN3) input to the gate of transistor 112; a signal (IN4) input to the gate of transistor 113; ), and the signal (IN5) input to the gate of the transistor 114. The input signals (IN1 to IN6) are just examples and are not limited to these.

[0188] 13 and 14(H) show the current flows of the transistors 112 and 114. A1, A2, B1, and B2 correspond to the directions shown in Figure 12. The period when the transistor is off and no current flows is indicated by an x. The period when the transistor is on but no current flows is indicated by -.

[0189] In FIG. 13 and FIG. 14, the wiring 102 and the wiring 104 are connected to a potential V LL and potential V LH Any In the following description, the potential V LL Apply and distribute A potential V is applied to wire 104. LH and a period Tx1 to a period Txn during which V is applied to the wiring 102. LH Apply and connect wire 104 to V LL The period Ty1 to Tyn during which the voltage is applied can be switched at any time. The following shows how to operate it.

[0190] First, in periods Tx1 to Txn, when the transistor 111 is on (period Tx1), A first signal (here, a H level signal (selected)) corresponding to the signal (IN1) input to 101 is A select signal) is supplied to the wiring 103. The gate of the transistor 121 is connected to the wiring 103. 12C), the transistor connected to the wiring 103 A selection signal is input to the gate of the transistor 121, and the transistor 121 is turned on.

[0191] In addition, during the periods Tx1 to Txn, when the transistor 112 is on (here, during the period Tx2, Tx4, Tx6, Tx8, Txn) from the wiring 102, the potential is V LL The second When a signal is supplied to the wiring 103 and the transistor 114 is turned on (here, during the period Tx3 , Tx5, Tx7) from the wiring 104 to the potential V LH A third signal is supplied to the wiring 103. When the gate of the transistor 121 is connected to the wiring 103, (See FIG. 12C), the transistor 121 is turned off.

[0192] Therefore, during the periods Tx1 to Txn, when the transistor 112 is on, In the capacitor 112, the terminal connected to the wiring 102 is the source, and the terminal connected to the wiring 103 is the The terminal connected to the drain becomes the drain, and current flows from the drain to the source (direction B1 in Figure 12). When the transistor 114 is turned on, the transistor 114 is connected to the wiring 103. The terminal connected to the wiring 102 becomes the source, and the terminal connected to the wiring 102 becomes the drain. The current flows from the drain to the source (direction A2 in FIG. 12).

[0193] In another period Ty1 to Tyn, when the transistor 112 is on (here, During periods Ty4, Ty6, Ty8, and Tyn, the potential from the wiring 102 is V LH The second signal is is supplied to the wiring 103, and the transistor 114 is turned on (here, during the periods Ty3 and T The potential is V from the wiring 104 to LL A third signal is supplied to the wiring 103. (See Figure 14.)

[0194] Therefore, during the period Ty1 to Tyn, when the transistor 112 is on, In the capacitor 112, the terminal connected to the wiring 102 becomes the drain, and the terminal connected to the wiring 103 becomes the drain. The terminal connected to the drain becomes the source, and current flows from the drain to the source (direction A1 in Figure 12). When the transistor 114 is turned on, the transistor 114 is connected to the wiring 103. The terminal connected to the wiring 104 becomes the drain, and the terminal connected to the wiring 104 becomes the source. The current flows from the drain to the source (direction B2 in FIG. 12).

[0195] Therefore, the signal (IN2) input to the wiring 102 and the signal (IN6) input to the wiring 104 ) at any time interval and combine the operations of Figure 13 and Figure 14. 15, the current flows through transistor 112 and transistor 114, respectively. Reverse the direction of the current (the voltage applied to the source or drain terminal of the transistor) The magnitude relationship can be swapped for each period (switching the source and drain). As a result, the channel portions (drain terminals) of the transistors 112 and 114 ) and reduce the concentration of the electric field in the By alternately turning on and off the transistors 112 and 114, Deterioration of the transistor can be suppressed.

[0196] The arbitrary period may be, for example, a period in which the semiconductor device of this embodiment is connected to a gate driver of a display device. When applied as a driver, the operation shown in Figure 13 and the operation shown in Figure 14 are switched every frame period. This can be done by switching between them.

[0197] Furthermore, by using the configuration shown in this embodiment mode, a specific signal (e.g., For example, even if a non-selection signal is continuously supplied to the wiring 103, the wiring 102 and the wiring 10 Since 4 can be set to a constant potential, power consumption can be reduced.

[0198] Note that the configuration shown in this embodiment mode may be different from other configurations shown in this specification (other embodiments). The present invention can be implemented by appropriately combining it with other configurations (including configurations in which the above-mentioned configurations are used).

[0199] (Fourth embodiment) In this embodiment mode, a usage mode of the configuration shown in the above embodiment mode will be described with reference to the drawings. do.

[0200] The configuration shown in the above embodiment is a scanning line driver circuit (gate driver), a signal line driver circuit ( In a display device having a source driver and a pixel portion, a scanning line driver circuit and / or a signal It can be applied to a line driver circuit (see FIG. 16).

[0201] FIG. 17 shows a case where the configuration shown in the first embodiment is applied to a gate driver of a display device. FIG. 17 shows the configuration of the above embodiment applied to a gate driver of a liquid crystal display device provided with a plurality of pixels. This shows the case where the configuration shown in form 1 is applied.

[0202] The transistor 121 provided in each of the pixels has a gate that functions as a gate line. The source or drain is electrically connected to one of the wirings 103a to 103c. It is electrically connected to one of the wirings 141a to 141c that function as source lines, and the other It is electrically connected to the pixel electrode 125. In addition, between the pixel electrode 125 and the counter electrode 126 In FIG. 17, the wirings 101a to 101c are filled with a liquid crystal material. Although the configuration in which the above components are provided electrically independent from each other is shown, they may be provided in common.

[0203] In addition, in order to turn on the transistor 121, the wiring 101a 101c supplies a high level signal as a selection signal to turn off the transistor 121. A low-level signal serving as a non-selection signal is supplied to the Just do that.

[0204] When writing data by selecting pixels in each row, as in the line sequential method, After turning on the selected transistor 121, a non-selected transistor 121 is turned off. A select signal must be supplied to the gate of transistor 121. In particular, In order to stably turn off the It is effective to continue supplying the non-selection signal for a predetermined period of time.

[0205] Here, as shown in the first embodiment, a plurality of L levels serving as non-selection signals are connected to the wiring 102. A bell signal is input, and the transistor 112 is turned on while the transistor 112 is turned on. By switching the direction of the current flowing through the transistor 112, the deterioration of the transistor 112 can be prevented. As a result, the transistor 121 provided in each pixel can be stably driven. In addition, it is possible to suppress malfunction of the circuit due to deterioration of the transistor 112. Cut.

[0206] In particular, amorphous silicon or microcrystalline silicon is used as the channel formation region for transistors. In this case, the deterioration of the transistor that remains on for a long period during the operation of the circuit Reducing this is effective in suppressing malfunctions of the circuit.

[0207] In addition, in FIG. 17, transistors 111 and 11 2. Although the case where all the transistors 121 provided in the pixel are N-channel type has been shown, It may be of a P-channel type, or may be of a CMOS type.

[0208] FIG. 17 shows a case where the configuration shown in the first embodiment is applied to a gate driver. However, the present invention is not limited to this, and the configurations shown in the second and third embodiments can also be applied. can.

[0209] When the configuration shown in the second embodiment is applied, in FIG. One of the terminals is electrically connected to the wiring 102, and the other terminal is connected to the wiring 103a (or the wiring 103b, A transistor 112b is connected to the line 103c and is in parallel with the transistor 112. (See FIG. 18.)

[0210] In addition, when the configuration shown in the third embodiment is applied, in FIG. One of the source and drain is electrically connected to the wiring 104, and the other is connected to the wiring A transistor 114 connected to the wiring 103a (or the wiring 103b or the wiring 103c) is provided. (See Figure 19.)

[0211] 19, one of the source and drain of the transistor 112 is electrically connected to the wiring 102. and electrically connect one of the source and drain of the transistor 114 to the wiring 104. In one case, one of the source and drain of the transistor 112 is connected to the wiring 104. The transistor 114 is electrically connected to the wiring 102 and the source or drain of the transistor 114 is electrically connected to the wiring 102. In the example shown, the electrodes are alternately connected in the row direction, but this is not limited to this. In all rows, one of the source and drain of the transistor 112 is electrically connected to the wiring 102. and one of the source and drain of the transistor 114 is electrically connected to the wiring 104. Alternatively, one of the source and drain of the transistor 112 may be electrically connected to the wiring 104. The transistor 114 is electrically connected to the wiring 102 and the source or drain of the transistor 114 is electrically connected to the wiring 102. Alternatively, the power supply may be connected to the power supply.

[0212] 17 to 19 show the case where the present invention is applied to a liquid crystal display device. The configuration shown may be used for gate drivers and / or source drivers of other display devices (such as organic EL display devices). The present invention can also be applied to drivers. For example, as shown in FIG. , a gate driver of an organic EL display device provided with a transistor 128 and a light emitting element 129. It can be applied as a

[0213] In FIG. 20, the gate of the transistor 121 provided in each of the pixels is connected to the wiring. 103a to 103c, and either the source or the drain is connected to the transistor. The transistor 121 is electrically connected to the gate of the switch transistor 128. The transistor 128 is sometimes called a switching transistor. One of the drains is electrically connected to either the wiring 142a or 142b, and the other is connected to the light-emitting element. The transistor 128 is electrically connected to one electrode of the drive transistor 129. It is sometimes called a transistor.

[0214] The circuit configurations shown in FIGS. 17 to 20 are merely examples, and other circuit configurations may also be applied. It is Noh.

[0215] Next, a circuit configuration applicable to the drive circuit will be described.

[0216] The gate of the transistor 111 is connected to the source of another transistor (here, the transistor 161). Either the source or the drain may be electrically connected (see FIG. 21(A)). In the configuration of FIG. 21(A), the gate of the transistor 111 is connected to another transistor. The source or drain of the transistor (here, transistor 162) is electrically connected. (See FIG. 21(B)). In addition, in the configuration of FIG. 21(A), The gate of the transistor 112 is connected to the source of another transistor (here, the transistor 163). Either the source or the drain may be electrically connected (see FIG. 21(C)). (see).

[0217] In FIG. 21B, the other of the source and the drain of the transistor 162 is connected. The wiring may be electrically connected to the wiring 102 or may be electrically connected to the transistor 112. The gates of the transistors 162 may be electrically connected to the same wiring.

[0218] 21(A) to 21(C), the gate of the transistor 161 is electrically connected to the drain. Alternatively, the diode connection may be used (see FIGS. 22(A) to 22(C)).

[0219] Next, a specific circuit configuration when applied as a gate driver will be described in detail.

[0220] An example of the configuration of a shift register that constitutes a gate driver will be described with reference to FIG. 23 shows the configuration of the nth stage in the shift register.

[0221] The n-th stage includes the first transistor 201 to the seventh transistor 207, the capacitor 208, and the In FIG. 23, the first transistor 201 to the seventh transistor 2 Although the case where 07 is provided as an N-channel type is shown, it may also be provided as a P-channel type.

[0222] The gate of the first transistor 201 is connected to the source of the second transistor 202, and the third transistor The source or drain of the fourth transistor 203 and the source or drain of the fourth transistor 204 are connected to each other. The drain of the fifth transistor 205 is electrically connected to one of the drains of the fifth transistor 205. One of the drains is electrically connected to the wiring 212a, and the other is connected to the gate of the third transistor 203. the gate of the sixth transistor 206 and one electrode of the capacitor 208. It continues.

[0223] The second transistor 202 has a gate electrically connected to the drain (diode-connected). , the source is connected to the gate of the first transistor 201 and the gate of the fifth transistor 205. The signal output from the n-1th stage is input to the drain.

[0224] The third transistor 203 has a gate connected to the source or drain of the first transistor 201. and one of the source and drain electrodes of the capacitor 208. The first terminal is electrically connected to the gate of the fifth transistor 205, and the other terminal is electrically connected to the wiring 212a. is connected to.

[0225] The fourth transistor 204 receives the signal output from the n+1 stage at its gate and Alternatively, one of the drains is electrically connected to the gate of the fifth transistor 205, and the other is It is electrically connected to the line 212a.

[0226] The fifth transistor 205 has a gate connected to the gate of the first transistor 201 and a gate connected to the gate of the second transistor 202. the source of the third transistor 202, one of the source and drain of the third transistor 203, and The source or drain of the fourth transistor 204 is electrically connected to the One of the drains is electrically connected to the wiring 211, and the other is electrically connected to the wiring 213. There are.

[0227] The sixth transistor 206 has a gate connected to the source or drain of the first transistor 201. and one of the source and drain electrodes of the capacitor 208. The first end is electrically connected to the wiring 212b, and the other end is electrically connected to the wiring 213.

[0228] The seventh transistor 207 receives the inverted clock signal (CLKB) at its gate and The wiring 212c is electrically connected to one of the source and drain, and the other is electrically connected to the wiring 213. is connected.

[0229] The capacitor 208 has one electrode connected to the gate of the third transistor 203 and the sixth transistor 204. The other electrode is electrically connected to the gate of the transistor 206, and the other electrode is electrically connected to the wiring 211. There are.

[0230] A clock signal (CLK) is input to the wiring 211, and L A level signal or an L-level signal whose potential changes is input. The number is not limited to this and can be selected as appropriate.

[0231] In the configuration shown in FIG. 23, during the period other than the period when the n-stage gate is selected (when a non-selection signal is applied to the pixel), During a non-selection period in which the third transistor 203 and the sixth transistor 206 The seventh transistor 207 is alternately turned on and operates. As shown in the figure, an L level signal whose potential changes is input to the wirings 212b and 212c, and the sixth The direction of the current flowing through the transistor 206 and the seventh transistor 207 is reversed ( By switching the source and drain positions, the concentration of the electric field on the source side or the drain side is suppressed. In addition, the potential of the wiring 212a can be prevented from changing, thereby reducing deterioration of the transistor. By inputting an L level signal, the direction of the current flowing through the third transistor 203 is changed. A configuration in which they are swapped (source and drain are swapped) may also be used.

[0232] At least two of the wirings 212a, 212b, and 212c are electrically When the wiring 212b and the wiring 212c are electrically connected to each other, In other words, the sixth transistor 206 and the seventh transistor 207 are the same as the transistors in FIG. The transistor 112a functions as a transistor 112b. If the sixth transistor 12c is electrically independent and supplies different signals, The seventh transistor 206 and the seventh transistor 207 are the transistor 112 and the transistor It functions as star 114.

[0233] The circuit configuration applicable to the gate driver is not limited to that shown in FIG. 23. For example, the circuit shown in FIG. 24 As shown in FIG. 1, the first transistor 221 to the twelfth transistor 232 are connected in each stage (here, The number of stages may be n.

[0234] In FIG. 24, the first transistor 221 receives an output signal from the n-1th stage at its gate. One of the source and drain is electrically connected to the wiring 241, and the other is connected to the fourth transistor. the gate of the eighth transistor 224, the gate of the eighth transistor 228, and the gate of the ninth transistor 229 The gate of the eleventh transistor 231 is electrically connected to the gate of the eleventh transistor 232. The output signal from the n+1 stage is input to the gate of the second transistor 222, and the source or drain of the second transistor 222 is One of the drains is electrically connected to the wiring 242a, and the other is connected to the gate of the fourth transistor 224. the gate of the eighth transistor 228, the gate of the ninth transistor 229 and the first The gate of the first transistor 231 is electrically connected to the gate of the third transistor 232. 223 has a gate electrically connected to the drain (diode connection) and a source electrically connected to the fifth transistor. The gate of the transistor 225 is electrically connected to the wiring 241. In addition, one of the source and the drain of the fourth transistor 224 is connected to the wiring 242. a, and the other is electrically connected to the gate of the fifth transistor 225. There are.

[0235] In addition, one of the source and the drain of the fifth transistor 225 is electrically connected to the wiring 241. The other is connected to the gate of the seventh transistor 227 and the gate of the tenth transistor 230. The sixth transistor 231 is electrically connected to the gate of the sixth transistor 232 and the gate of the twelfth transistor 233. The transistor 226 receives the output signal from the n-1 stage at its gate and One of the terminals is electrically connected to the wiring 242a, and the other terminal is connected to the gate of the seventh transistor 227. , the gate of the tenth transistor 230 and the gate of the twelfth transistor 232 are electrically connected to each other. The seventh transistor 227 has either a source or a drain connected to the The other end is electrically connected to the gate of the fourth transistor 224 and the other end is electrically connected to the wiring 242a. The gate of the ninth transistor 228, the gate of the ninth transistor 229 and the gate of the eleventh transistor The eighth transistor 228 is electrically connected to the source or gate of the eighth transistor 231. One of the drains is electrically connected to the wiring 242a, and the other is gate, the gate of the tenth transistor 230 and the gate of the twelfth transistor 232 is electrically connected to

[0236] The ninth transistor 229 receives a clock signal (CLK ) or the clock inverted signal (CLKB) is input. In the eleventh embodiment, one of the source and drain is electrically connected to the wiring 242b. The transistor 231 has a clock signal or an inverted clock signal applied to either its source or drain. The other end is electrically connected to the wiring 243. The capacitor 232 has one of its source and drain electrically connected to the wiring 242b, and the other connected to the wiring 242c. 243.

[0237] In the configuration shown in FIG. 24, during the non-selection period, the seventh transistor 227 and the tenth transistor The twelfth transistor 230 and the twelfth transistor 232 remain in the on state. 242a, and an L-level signal or an L-level signal whose potential changes is input to the wiring 242b. the first transistor 227, the tenth transistor 230 and the twelfth transistor 232 By switching the direction of the current (switching the source and drain), This suppresses the concentration of the electric field on the source or drain side, thereby reducing the degradation of the transistor. .

[0238] In FIG. 24, the first transistor 221 to the twelfth transistor 232 are N-channel transistors. Although the ninth transistor is a P-channel type, it may be a P-channel type. The output from the wiring 243 is not provided without providing the transistor 229 and the tenth transistor 230. The signal may be output to the n-1th stage and the n+1th stage. Alternatively, an H level signal whose potential changes may be input to the wiring 241. In this case, the direction of the current flowing through the fifth transistor 225 is reversed ( By switching the source and drain, the electric field is concentrated on the source side or the drain side. In FIG. 24, the wiring The signal input to is not limited to this and can be selected appropriately.

[0239] In addition, as shown in FIG. 25, the first transistor 251 to the fifth transistor 255 are It may be configured to have stages (here, n stages).

[0240] In FIG. 25, a first transistor 251 has a gate connected to an inverted clock signal (CLKB). is input, and the output signal from the n-1th stage is input to one of the source or drain, and the other is input to the nth stage. The gate of the second transistor 254 is electrically connected to the gate of the third transistor 255. 252, the gate is electrically connected to the wiring 263, and either the source or the drain is connected to the wiring 2 62a, and the other is electrically connected to the gate of the fifth transistor 255. The third transistor 253 has a gate connected to the inverted clock signal (CLKB). is input, one of the source and drain is electrically connected to the wiring 264, and the other is The gate of the fourth transistor 255 is electrically connected to the gate of the fourth transistor 25 4, the gate of which is electrically connected to the other of the source and drain of the first transistor 251. A clock signal (CLK) is input to one of the source and drain, and the other is connected to the wiring 263. The fifth transistor 255 is electrically connected to the source or drain of the One end is electrically connected to the wiring 262b, and the other end is electrically connected to the wiring 263.

[0241] In the configuration shown in FIG. 25, the fifth transistor 255 is kept on during the non-selection period. Therefore, an H level signal whose potential changes is input to the wiring 262b, and the fifth transistor By switching the direction of the current through resistor 255 (switching the source and drain), Therefore, the concentration of the electric field on the source side or the drain side is suppressed, and the deterioration of the transistor is reduced. It is possible.

[0242] In FIG. 25, the first transistor 251 to the fifth transistor 255 are P-channel transistors. Although the wiring 262a is of an N-channel type, it may be of an N-channel type. The wiring 262b may be electrically connected to the wiring 262a. The input signal is not limited to this and can be selected appropriately.

[0243] In addition, as shown in FIG. 26, the first transistor 271 to the tenth transistor 280 are It may be configured to have one in each stage (here, n stages).

[0244] In FIG. 26, a first transistor 271 receives a first clock signal at its gate. , a first input signal is input to one of the source and drain of the eighth transistor 2 The second transistor 272 is electrically connected to the gate of the second transistor 278. A second clock signal is input, and a second input signal is input to either the source or the drain. The other is electrically connected to the gate of the eighth transistor 278. The transistor 273 has one of its source and drain electrically connected to the wiring 282a, and the other The gate of the fourth transistor 278 is electrically connected to the gate of the eighth transistor 279. The transistor 274 has one of its source and drain electrically connected to the wiring 282a, and the other The source or drain of the fifth transistor 275 and the drain of the sixth transistor 276 The fifth transistor 275 is electrically connected to either the source or the drain. In this case, a third clock signal is input to the gate, and either the source or the drain is connected to the fourth transistor. The other is electrically connected to the source or drain of the eighth transistor. The gate of the transistor 278 is electrically connected to the transistor 278 .

[0245] The sixth transistor 276 has a gate electrically connected to a wiring 281 and a source One of the drains is electrically connected to the other of the source and drain of the fourth transistor 274. The other end is electrically connected to the gate of the ninth transistor 279. The transistor 277 of No. 7 has its gate electrically connected to its drain (diode-connected), The source is connected to the gate of the third transistor 273, the gate of the fourth transistor 274, and 10, and a third clock signal The eighth transistor 278 has a source and a drain connected to the wiring 282a. the other is electrically connected to the gate of the third transistor 273, 74 and the gate of the tenth transistor 280. The ninth transistor 279 receives the fourth clock signal at either the source or the drain. The other end is electrically connected to a wiring 283. In this case, one of the source and drain is electrically connected to the wiring 282b, and the other is connected to the wiring 283. are electrically connected.

[0246] In the configuration shown in FIG. 26, the tenth transistor 280 is in an on state during the non-selection period. Therefore, an H level signal whose potential changes is input to the wiring 282b, and the tenth transistor By switching the direction of the current through transistor 280 (switching the source and drain), This suppresses the concentration of the electric field on the source or drain side, reducing the deterioration of the transistor. can be reduced.

[0247] In FIG. 26, the first transistor 271 to the tenth transistor 280 are P-channel transistors. Although the wiring 282 is of a N-channel type, it may be of an N-channel type. a and the wiring 282b may be electrically connected. The signal input to is not limited to this and can be selected appropriately.

[0248] In this embodiment mode, the configuration shown in the above embodiment mode is applied to a gate driver or a source driver. Although the application to the drive circuit of a capacitor or the like has been shown, the present invention is not limited to this. In the case of controlling the potential of the common electrode, the present invention is also applicable.

[0249] Note that the configuration shown in this embodiment mode may be different from other configurations shown in this specification (other embodiments). The present invention can be implemented by appropriately combining it with other configurations (including configurations in which the above-mentioned configurations are used).

[0250] (Embodiment 5) In this embodiment mode, a transistor structure applicable to the circuit shown in the above embodiment mode will be described. The transistors are characterized by the materials used for the semiconductor layers of the transistors. The materials used for the semiconductor layer are mainly silicon. Silicon-based materials are classified into silicon-based materials containing silicon and non-silicon-based materials that do not contain silicon as a main component. Silicon-based materials include amorphous silicon (a-Si:H), microcrystalline silicon (MCS), and stal silicon (μc-Si), polysilicon (p-Si), single crystal silicon (c-Si Non-silicon materials include compound semiconductors such as gallium arsenide (GaAs). Conductors, zinc oxide (ZnO), oxide containing indium, gallium and zinc (InGaZnO ) and other oxide semiconductors.

[0251] Amorphous silicon or microcrystalline silicon is used as the semiconductor layer of the transistor. When used in this way, the uniformity of the transistor characteristics is high and the manufacturing cost is low. This is particularly advantageous when mounting transistors on large substrates with diagonal lengths exceeding 500 mm. This is effective when fabricating a semiconductor layer using amorphous silicon or An example of the structure of a transistor and a capacitor element using polycrystalline silicon will be described. do.

[0252] FIG. 27A shows a cross-sectional structure of a top-gate transistor and a cross-sectional structure of a capacitor. This is a diagram.

[0253] A first insulating film (insulating film 5142) is formed on a substrate 5141. Impurities from the side can affect the semiconductor layer and change the properties of the transistor. The first insulating film can function as a base film to prevent the formation of a silicon oxide film. Silicon nitride film or silicon oxynitride film (SiO x N y ) or a single layer of In particular, a silicon nitride film is a dense film and has high barrier properties. Therefore, it is preferable that the first insulating film contains silicon nitride. The insulating film does not necessarily have to be formed. If the first insulating film is not formed, the number of steps is This can reduce the number of parts, reduce manufacturing costs, and improve yields.

[0254] On the first insulating film, a first conductive layer (conductive layer 5143, conductive layer 5144, and conductive layer 5145) is formed. The conductive layer 5143 is a layer that serves as one of the source and drain of the transistor 5158. The conductive layer 5144 includes a portion that functions as a source and a drain of the transistor 5158. The conductive layer 5145 includes a portion that functions as the other of the first and second electrodes of the capacitor 5159. The first conductive layer includes a portion that functions as an electrode. W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, etc. Alternatively, a stack of these elements (including alloys) can be used. A membrane can be used.

[0255] A first semiconductor layer (semiconductor layer 5146 and semiconductor layer 5147) is formed on the conductive layer 5143 and the conductive layer 5144. The semiconductor layer 5146 functions as either a source or a drain. The semiconductor layer 5147 includes a portion that functions as the other of the source and drain. The first semiconductor layer may be made of silicon containing phosphorus or the like. .

[0256] Between the conductive layer 5143 and the conductive layer 5144 and on the first insulating film, a second semiconductor A layer (semiconductor layer 5148) is formed. A part of the semiconductor layer 5148 is connected to the conductive layer 51. 43 and conductive layer 5144. Semiconductor layer 5148 is The second semiconductor layer includes a portion that functions as a channel region of the first semiconductor layer. Amorphous semiconductor layer such as rufous silicon (a-Si:H) or microcrystalline silicon A semiconductor layer such as (μc-Si) can be used.

[0257] A second insulating film (insulating film 5148) is formed so as to cover at least the semiconductor layer 5148 and the conductive layer 5145. The second insulating film functions as a gate insulating film. The second insulating film may be a silicon oxide film, a silicon nitride film, or an oxynitride film. Silicon film (SiO x N y ) or a laminate thereof can be used.

[0258] The second insulating film in contact with the second semiconductor layer may be a silicon oxide film. This is because the trapping at the interface where the second semiconductor layer and the second insulating film contact each other is prevented. This is because there are fewer levels.

[0259] When the second insulating film is in contact with Mo, the second insulating film in the portion in contact with Mo is oxidized. It is desirable to use a silicon film because silicon oxide film does not oxidize Mo. etc.

[0260] A second conductive layer (conductive layer 5151 and conductive layer 5152) is formed over the second insulating film. The conductive layer 5151 includes a portion that functions as a gate electrode of a transistor 5158. The layer 5152 functions as a second electrode of the capacitor 5159 or a wiring. The second conductive layer may be made of Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, etc., or alloys thereof can be used. Alternatively, a laminate of these elements (including alloys) can be used.

[0261] After the second conductive layer is formed, various insulating films or various conductive films may be formed. It may be made.

[0262] FIG. 27B shows a cross-sectional structure of an inverted staggered (bottom gate) transistor and a capacitor element. In particular, the transistor shown in FIG. 27(B) has a channel etch. This is a structure called a mold.

[0263] A first insulating film (insulating film 5162) is formed on a substrate 5161. Impurities from the side can affect the semiconductor layer and change the properties of the transistor. The first insulating film can function as a base film to prevent the formation of a silicon oxide film. Silicon nitride film or silicon oxynitride film (SiO x N y ) or a single layer of In particular, a silicon nitride film is a dense film and has high barrier properties. Therefore, it is preferable that the first insulating film contains silicon nitride. The insulating film does not necessarily have to be formed. If the first insulating film is not formed, the number of steps is This can reduce the number of parts, reduce manufacturing costs, and improve yields.

[0264] A first conductive layer (conductive layer 5163 and conductive layer 5164) is formed over the first insulating film. The conductive layer 5163 includes a portion that functions as a gate electrode of the transistor 5178. The layer 5164 includes a portion that functions as a first electrode of the capacitor 5179. The conductive layer can be made of Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, etc., or alloys thereof can be used. Alternatively, a laminate of these elements (including alloys) can be used.

[0265] A second insulating film (insulating film 5165) is formed so as to cover at least the first conductive layer. The second insulating film functions as a gate insulating film. silicon oxide film, silicon nitride film or silicon oxynitride film (SiO x N y ) or A laminate of these can be used.

[0266] It is preferable to use a silicon oxide film as the second insulating film in contact with the semiconductor layer. This is because there are fewer trap levels at the interface where the semiconductor layer and the second insulating film contact each other. This is because

[0267] When the second insulating film is in contact with Mo, the second insulating film in the portion in contact with Mo is oxidized. It is desirable to use a silicon film because silicon oxide film does not oxidize Mo. etc.

[0268] A photolithographic pattern is formed on a portion of the second insulating film that overlaps with the first conductive layer. The first semiconductor layer (semiconductor layer 5166) is formed by a film method, an ink jet method, a printing method, or the like. ) is formed. A part of the semiconductor layer 5166 is formed on the first conductive layer on the second insulating film. The semiconductor layer 5166 extends to a portion that is not overlapped with the transistor. The semiconductor layer 5166 includes a portion that functions as a channel region of the semiconductor layer 5178. is a semiconductor layer having non-crystalline properties such as amorphous silicon (a-Si:H) or a microcrystalline A semiconductor layer such as silicon (μc-Si) can be used.

[0269] A second semiconductor layer (semiconductor layer 5167 and semiconductor layer 5168) is formed on a part of the first semiconductor layer. The semiconductor layer 5167 includes a portion that functions as one of a source and a drain. The semiconductor layer 5168 includes a portion that functions as the other of the source and the drain. The semiconductor layer may be made of silicon containing phosphorus or the like.

[0270] A second conductive layer (conductive layer 5169, conductive layer 517) is formed on the second semiconductor layer and the second insulating film. The conductive layer 5169 is the source of the transistor 5178. The conductive layer 5170 includes a portion that functions as one of the source and drain of the transistor 517. The conductive layer 5171 includes a portion that functions as the other of the source and drain of the capacitor 5 The second conductive layer includes a portion that functions as a second electrode 179. The second conductive layer is made of Ti, M o, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, etc., or alloys thereof can be used. A layer of a metal (including gold) can be used.

[0271] After the second conductive layer is formed, various insulating films or various conductive films may be formed. It may be made.

[0272] In the manufacturing process of a channel etch type transistor, the first semiconductor layer and the second The semiconductor layers can be deposited sequentially, and the first semiconductor layer and the second semiconductor layer can be deposited sequentially. The layers can be formed using the same mask.

[0273] Furthermore, after the second conductive layer is formed, a second semiconductor layer is formed using the second conductive layer as a mask. Alternatively, a mask similar to that used for the second conductive layer can be used. A part of the second semiconductor layer is removed using a In this way, a new mask can be formed just to remove a portion of the second semiconductor layer. Since there is no need to use a mask, the manufacturing process is simplified and the manufacturing cost can be reduced. The part of the first semiconductor layer formed under the second semiconductor layer to be removed is a transistor. This becomes the channel region of the transistor.

[0274] FIG. 27C shows a cross-sectional structure of an inverted staggered (bottom gate) transistor and a capacitor element. In particular, the transistor shown in FIG. 27C is a channel protection type. This structure is called an etch-stop type.

[0275] A first insulating film (insulating film 5182) is formed on a substrate 5181. Impurities from the side can affect the semiconductor layer and change the properties of the transistor. The first insulating film can function as a base film to prevent the formation of a silicon oxide film. Silicon nitride film or silicon oxynitride film (SiO x N y ) or a single layer of In particular, a silicon nitride film is a dense film and has high barrier properties. Therefore, it is preferable that the first insulating film contains silicon nitride. The insulating film does not necessarily have to be formed. If the first insulating film is not formed, the number of steps is This can reduce the number of parts, reduce manufacturing costs, and improve yields.

[0276] A first conductive layer (conductive layer 5183 and conductive layer 5184) is formed over the first insulating film. The conductive layer 5183 includes a portion that functions as a gate electrode of the transistor 5198. The layer 5184 includes a portion that functions as a first electrode of the capacitor 5199. The conductive layer can be made of Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, etc., or alloys thereof can be used. Alternatively, a laminate of these elements (including alloys) can be used.

[0277] A second insulating film (insulating film 5185) is formed so as to cover at least the first conductive layer. The second insulating film functions as a gate insulating film. silicon oxide film, silicon nitride film or silicon oxynitride film (SiO x N y ) or A laminate of these can be used.

[0278] It is preferable to use a silicon oxide film as the second insulating film in contact with the semiconductor layer. This is because there are fewer trap levels at the interface where the semiconductor layer and the second insulating film contact each other. This is because

[0279] When the second insulating film is in contact with Mo, the second insulating film in the portion in contact with Mo is oxidized. It is desirable to use a silicon film because silicon oxide film does not oxidize Mo. etc.

[0280] A photolithographic pattern is formed on a portion of the second insulating film that overlaps with the first conductive layer. The first semiconductor layer (semiconductor layer 5186) is formed by a film method, an ink jet method, a printing method, or the like. ) is formed. A part of the semiconductor layer 5188 is formed on the first conductive layer on the second insulating film. The semiconductor layer 5186 extends to a portion that is not overlapped with the transistor. The semiconductor layer 5186 includes a portion that functions as a channel region of the semiconductor layer 5198. is a semiconductor layer having non-crystalline properties such as amorphous silicon (a-Si:H) or a microcrystalline A semiconductor layer such as silicon (μc-Si) can be used.

[0281] A third insulating film (insulating film 5192) is formed on a part of the first semiconductor layer. 92 prevents the channel region of transistor 5198 from being etched away. That is, the insulating film 5192 serves as a channel protective film (etch stop film). The third insulating film functions as a silicon oxide film, a silicon nitride film, or an oxide film. Silicon nitride film (SiO x N y ) or a laminate thereof can be used. .

[0282] A second semiconductor layer (semiconductor layer 518) is formed on a part of the first semiconductor layer and a part of the third insulating film. The semiconductor layer 5187 is formed on one of the source and drain. The semiconductor layer 5188 includes a portion that functions as the other of the source and drain. The second semiconductor layer may be made of silicon containing phosphorus or the like. can be done.

[0283] On the second semiconductor layer, a second conductive layer (conductive layer 5189, conductive layer 5190 and conductive layer 519) is formed. The conductive layer 5189 is formed on one of the source and drain of the transistor 5198. The conductive layer 5190 includes a portion that functions as a source and a drain of the transistor 5198. The conductive layer 5191 includes a portion that functions as the other electrode of the capacitor 5199. The second conductive layer includes a portion that functions as a metal. , Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, etc. Alternatively, stacking of these elements (including alloys) can be used. It can be used.

[0284] After the second conductive layer is formed, various insulating films or various conductive films may be formed. It may be made.

[0285] Next, when polysilicon is used as the semiconductor layer of a transistor, the movement of the transistor It has the advantage of being highly reliable and having low manufacturing costs. Therefore, a highly reliable device can be obtained. An example of the structure of the transistor and capacitor used will be described.

[0286] FIG. 27D shows a cross-sectional structure of a bottom-gate transistor and a cross-sectional structure of a capacitor. This is a diagram.

[0287] A first insulating film (insulating film 5202) is formed on a substrate 5201. Impurities from the side can affect the semiconductor layer and change the properties of the transistor. The first insulating film can function as a base film to prevent the formation of a silicon oxide film. Silicon nitride film or silicon oxynitride film (SiO x N y ) or a single layer of In particular, a silicon nitride film is a dense film and has high barrier properties. Therefore, it is preferable that the first insulating film contains silicon nitride. The insulating film does not necessarily have to be formed. If the first insulating film is not formed, the number of steps is This can reduce the number of parts, reduce manufacturing costs, and improve yields.

[0288] A first conductive layer (conductive layer 5203 and conductive layer 5204) is formed over the first insulating film. The conductive layer 5203 includes a portion that functions as a gate electrode of the transistor 5218. The layer 5204 includes a portion that functions as a first electrode of a capacitor 5219. The conductive layer can be made of Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, etc., or alloys thereof can be used. Alternatively, a laminate of these elements (including alloys) can be used.

[0289] A second insulating film (insulating film 5214) is formed so as to cover at least the first conductive layer. The second insulating film functions as a gate insulating film. silicon oxide film, silicon nitride film or silicon oxynitride film (SiO x N y ) or A laminate of these can be used.

[0290] It is preferable to use a silicon oxide film as the second insulating film in contact with the semiconductor layer. This is because there are fewer trap levels at the interface where the semiconductor layer and the second insulating film contact each other. This is because

[0291] When the second insulating film is in contact with Mo, the second insulating film in the portion in contact with Mo is oxidized. It is desirable to use a silicon film because silicon oxide film does not oxidize Mo. etc.

[0292] A photolithographic pattern is formed on a portion of the second insulating film that overlaps with the first conductive layer. The semiconductor layer is formed by a film method, an ink jet method, a printing method, or the like. A part of the conductor layer is formed on the second insulating film in a portion that is not overlapped with the first conductive layer. The semiconductor layer includes a channel forming region (channel forming region 5210), a Li ghtly Doped Drain (LDD) area (LDD area 5208, LDD area 5209), impurity regions (impurity region 5205, impurity region 5206, impurity region 520 The channel forming region 5210 is a channel forming region of the transistor 5218. The LDD region 5208 and the LDD region 5209 function as the transistor 52 18. The LDD region 5208 and the LDD region 5209 function as the LDD regions 5209. By forming the gate electrode, it is possible to prevent a high electric field from being applied to the drain of the transistor. Therefore, the reliability of the transistor can be improved. However, the LDD region does not necessarily have to be formed. In this case, the manufacturing process can be simplified, and therefore the manufacturing cost can be reduced. The region 5205 is a portion that functions as one of the source and drain of the transistor 5218. The impurity region 5206 serves as the other of the source and drain of the transistor 5218. The impurity region 5207 functions as a second electrode of the capacitor 5219. It includes a functioning part.

[0293] A contact hole is selectively formed in a part of the third insulating film (insulating film 5211). The insulating film 5211 functions as an interlayer film. silicon dioxide, silicon nitride, silicon oxynitride, etc.) or organic compound materials with low dielectric constant Photosensitive or non-photosensitive organic resin materials can be used. Materials containing siloxane can also be used. Siloxane is a compound consisting of silicon (Si) and oxygen ( The skeleton structure of this material is formed by bonding with organic groups (e.g., alkyl groups). Alternatively, the organic group may be a fluoro group. may have

[0294] A second conductive layer (conductive layer 5212 and conductive layer 5213) is formed over the third insulating film. The conductive layer 5212 is connected to the transistor 5 through a contact hole formed in the third insulating film. 218. Therefore, the conductive layer 5 212 includes a portion that functions as the other of the source or drain of the transistor 5218. The conductive layer 5213 and the conductive layer 5204 are electrically connected in a portion not shown. In this case, the conductive layer 5213 includes a portion that functions as a first electrode of the capacitor 5219. Alternatively, the conductive layer 5213 may be electrically connected to the impurity region 5207 in a portion not shown. When the conductive layer 5213 is connected to the capacitor 5219, the conductive layer 5213 functions as a second electrode of the capacitor 5219. Alternatively, the conductive layer 5213 may be electrically connected to the conductive layer 5204 and the impurity region 5207. When the capacitor 5219 is not connected to the capacitor 5219, a capacitor element other than the capacitor 5219 is formed. The conductive layer 5213, the impurity region 5207, and the insulating film 5211 are the capacitor elements. This structure is used as a first electrode, a second electrode, and an insulating film. Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si Zn, Fe, Ba, Ge, etc., or alloys thereof can be used. A laminate of these elements (including alloys) can be used.

[0295] After the second conductive layer is formed, various insulating films or various conductive films may be formed. It may be made.

[0296] In addition, even in transistors that use polysilicon as the semiconductor layer, It may be a transistor.

[0297] Note that the configuration shown in this embodiment mode may be different from other configurations shown in this specification (other embodiments). The present invention can be implemented by appropriately combining it with other configurations (including configurations in which the above-mentioned configurations are used).

[0298] (Embodiment 6) In this embodiment mode, various electronic devices to which the display device described in the above embodiment mode is applied will be described. , will be explained with reference to the drawings.

[0299] Examples of electronic devices to which the display device described in the above embodiment is applied include televisions, video cameras, and the like. cameras, digital cameras, goggle-type displays (head-mounted displays) (a), navigation systems, sound reproduction devices (car audio, audio components, etc.) , notebook computers, game consoles, personal digital assistants (mobile computers, mobile phones) , portable game consoles or electronic books, etc.), image playback devices equipped with recording media (specifically, digital A display that can play recording media such as a versatile disc (DVD) and display the images. Examples of such electronic devices include electronic equipment (devices equipped with electronic devices), lighting fixtures, etc. show.

[0300] FIG. 28(A) shows a display device, which includes a housing 8001, a support base 8002, a display unit 8003, a speaker, and the like. The configuration shown in the above embodiment is also included. The display device is manufactured by using it in the display unit 8003. This includes all information display devices such as those for data capture, TV broadcast reception, and advertisement display. By applying the display device shown in the above embodiment, it is possible to provide a display device with improved reliability. can.

[0301] FIG. 28(B) shows a computer, which includes a housing 8102, a display unit 8103, and a keyboard 810. 4, an external connection port 8105, a pointing device 8106, etc. The computer is manufactured by using the structure shown in the above embodiment mode for the display portion 8103. A computer with improved reliability by applying the display device described in the above embodiment mode. can be provided.

[0302] FIG. 28C shows a video camera, which includes a display unit 8202, an external connection port 8204, a remote control The video camera includes a video receiving unit 8205, an image receiving unit 8206, and operation keys 8209. The display portion 8202 is manufactured by using the structure described in the above embodiment mode. By applying the display device shown in the embodiment, a video camera with improved reliability can be provided. It is possible.

[0303] FIG. 28(D) shows a mobile phone, which includes a display unit 8403, an audio input unit 8404, and an audio output unit 84 05, operation keys 8406, external connection port 8407, etc. The display unit 8403 is manufactured by using the configuration shown in the embodiment. The display device shown in the above embodiment may be a mobile phone equipped with a communication function, a television reception function, etc. By applying the device, it is possible to provide a mobile phone with improved reliability.

[0304] FIG. 28(E) shows a table lamp, which includes a lighting unit 8301, a shade 8302, and an adjustable arm 8303. , a switch 8305, etc. Note that the desk lamp does not have the same structure as that shown in the above embodiment. It is made by using it in the bright part 8301. The lighting fixture is a ceiling-mounted lighting fixture. The display device shown in the above embodiment mode can be applied to a wall-mounted lighting fixture. This makes it possible to provide a desk lighting fixture with improved reliability.

[0305] As described above, electronic devices and lighting devices can be obtained by applying the display devices described in the above embodiment modes. The display device shown in the above embodiment has a very wide range of application, and can be used in a variety of fields. It can be applied to electronic devices in the field.

[0306] Note that the configuration shown in this embodiment mode may be different from other configurations shown in this specification (other embodiments). The present invention can be implemented by appropriately combining it with other configurations (including configurations in which the above-mentioned configurations are used). [Explanation of symbols]

[0307] 101 Wiring 102 Wiring 103 Wiring 104 Wiring 111 Transistor 112 transistors 114 transistors 115 Capacitor element 121 Transistor 122 transistors 125 pixel electrode 126 Counter electrode 128 transistors 129 Light-emitting element 161 transistors 162 transistors 163 Transistor 201 Transistor 202 Transistor 203 Transistor 204 Transistor 205 Transistor 206 Transistor 207 Transistor 208 Capacitor 211 Wiring 213 Wiring 221 Transistor 222 transistor 223 Transistor 224 transistor 225 transistors 226 Transistor 227 Transistor 228 transistors 229 Transistor 230 transistors 231 Transistor 232 transistors 241 Wiring 243 Wiring 251 transistors 252 transistors 253 transistors 254 transistors 255 transistors 263 Wiring 264 Wiring 271 Transistor 272 transistors 273 Transistor 274 transistors 275 transistors 276 transistors 277 Transistors 278 transistors 279 Transistors 280 transistors 281 Wiring 283 Wiring 101a wiring 103a wiring 103b Wiring 103c wiring 112a transistor 112b transistor 141a wiring 142a wiring 212a wiring 212b wiring 212c wiring 242a wiring 242b wiring 262a Wiring 262b Wiring 282a Wiring 282b Wiring 5141 Circuit Board 5142 Insulating film 5143 Conductive layer 5144 Conductive layer 5145 Conductive layer 5146 Semiconductor layer 5147 Semiconductor layer 5148 Semiconductor layer 5149 Insulating film 5150 insulating film 5151 Conductive layer 5152 Conductive layer 5158 Transistor 5159 Capacitor element 5161 Circuit Board 5162 Insulating film 5163 Conductive layer 5164 Conductive layer 5165 Insulating film 5166 Semiconductor layer 5167 Semiconductor layer 5168 Semiconductor layer 5169 Conductive layer 5170 Conductive layer 5171 Conductive layer 5178 Transistor 5179 Capacitor 5181 Circuit Board 5182 Insulating film 5183 Conductive layer 5184 Conductive layer 5185 Insulating film 5186 Semiconductor layer 5187 Semiconductor layer 5188 Semiconductor layer 5189 Conductive layer 5190 Conductive layer 5191 Conductive layer 5192 Insulating film 5198 Transistor 5199 Capacitor 5201 Circuit Board 5202 Insulating film 5203 Conductive layer 5204 Conductive layer 5205 Impurity region 5205 Impurity region 5206 Impurity region 5207 Impurity region 5208 LDD area 5209 LDD area 5210 Channel formation region 5211 Insulating film 5211 Insulating film 5212 Conductive layer 5213 Conductive layer 5214 Insulating film 5218 Transistor 5219 Capacitor element 8001 Case 8002 Support stand 8003 Display section 8004 Speaker section 8005 Video input terminal 8102 Housing 8103 Display section 8104 keyboard 8105 External connection port 8106 Pointing Device 8202 Display section 8204 External connection port 8205 Remote control receiver 8206 Image receiving unit 8209 Operation key 8301 Lighting Department 8302 umbrella 8303 Adjustable Arm 8305 Switch 8403 Display section 8404 Audio input section 8406 Operation key 8407 External connection port

Claims

1. A semiconductor device comprising first to seventh transistors and first to sixth wirings, one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to the sixth wiring; a gate of the sixth transistor is electrically connected to the sixth wiring; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; the first wiring is electrically connected to a pixel; Semiconductor device.

2. A semiconductor device comprising first to seventh transistors and first to sixth wirings, one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to the sixth wiring; a gate of the sixth transistor is electrically connected to the sixth wiring; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; the first wiring is electrically connected to a pixel; a power supply potential is input to the third wiring; a first clock signal is input to the fifth wiring; a second clock signal is input to the sixth wiring; Semiconductor device.

3. A semiconductor device comprising first to seventh transistors and first to sixth wirings, one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor; a gate of the sixth transistor is electrically connected to the sixth wiring; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; the first wiring is electrically connected to a pixel; when the gate of the second transistor is electrically connected to at least the sixth wiring through a channel formation region of the sixth transistor, a potential of the sixth wiring is applied to the gate of the second transistor through at least the channel formation region of the sixth transistor; Semiconductor device.

4. A semiconductor device comprising first to seventh transistors and first to sixth wirings, one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor; a gate of the sixth transistor is electrically connected to the sixth wiring; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; the first wiring is electrically connected to a pixel; a power supply potential is input to the third wiring; a first clock signal is input to the fifth wiring; a second clock signal is input to the sixth wiring; when the gate of the second transistor is electrically connected to at least the sixth wiring through a channel formation region of the sixth transistor, a potential of the sixth wiring is applied to the gate of the second transistor through at least the channel formation region of the sixth transistor; Semiconductor device.

5. In any one of claims 1 to 4, the first to seventh transistors all have the same polarity; Semiconductor device.

6. A semiconductor device comprising first to eighth transistors and first to seventh wirings, one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to the sixth wiring; a gate of the sixth transistor is electrically connected to the sixth wiring; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; one of the source and the drain of the eighth transistor is electrically connected to the gate of the seventh transistor; a gate of the eighth transistor is electrically connected to the seventh wiring; the first wiring is electrically connected to a pixel; Semiconductor device.

7. A semiconductor device comprising first to eighth transistors and first to seventh wirings, one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to the sixth wiring; a gate of the sixth transistor is electrically connected to the sixth wiring; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; one of the source and the drain of the eighth transistor is electrically connected to the gate of the seventh transistor; a gate of the eighth transistor is electrically connected to the seventh wiring; the first wiring is electrically connected to a pixel; a power supply potential is input to the third wiring; a first clock signal is input to the fifth wiring; a second clock signal is input to the sixth wiring; Semiconductor device.

8. A semiconductor device comprising first to eighth transistors and first to seventh wirings, one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor; a gate of the sixth transistor is electrically connected to the sixth wiring; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; one of the source and the drain of the eighth transistor is electrically connected to the gate of the seventh transistor; a gate of the eighth transistor is electrically connected to the seventh wiring; the first wiring is electrically connected to a pixel; when the gate of the second transistor is electrically connected to at least the sixth wiring through a channel formation region of the sixth transistor, a potential of the sixth wiring is applied to the gate of the second transistor through at least the channel formation region of the sixth transistor; Semiconductor device.

9. A semiconductor device comprising first to eighth transistors and first to seventh wirings, one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring; a gate of the fifth transistor is electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor; a gate of the sixth transistor is electrically connected to the sixth wiring; one of a source and a drain of the seventh transistor is electrically connected to the third wiring; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; one of the source and the drain of the eighth transistor is electrically connected to the gate of the seventh transistor; a gate of the eighth transistor is electrically connected to the seventh wiring; the first wiring is electrically connected to a pixel; a power supply potential is input to the third wiring; a first clock signal is input to the fifth wiring; a second clock signal is input to the sixth wiring; when the gate of the second transistor is electrically connected to at least the sixth wiring through a channel formation region of the sixth transistor, a potential of the sixth wiring is applied to the gate of the second transistor through at least the channel formation region of the sixth transistor; Semiconductor device.

10. In any one of claims 6 to 9, the first to eighth transistors all have the same polarity; Semiconductor device.

Images