Display device and electronic apparatus including the same

Abstract

To provide a display device and an electronic apparatus including the same.SOLUTION: A display device comprises: a substrate including a display area and a peripheral area; a plurality of unit pixel areas arranged in the display area and each including a first pixel circuit, a second pixel circuit, and a third pixel circuit; a power voltage supply line disposed in the peripheral area; a first driving voltage line electrically connected to the power voltage supply line and having a mesh structure in the display area; and a second driving voltage line electrically connected to the power voltage supply line, disposed at a different layer from the first driving voltage line, and extending in a first direction in the display area. The first driving voltage line is connected to the second driving voltage line through at least one inner contact hole in the plurality of unit pixel areas.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] Recently, the applications of display devices have become more diverse, and display devices tend to be lighter and thinner, and the range of their use is becoming wider.

[0003] As display devices are increasingly used in a variety of applications, various methods are being adopted to design the configuration of the display device, and designs that expand the display area while maintaining high image quality are increasing. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent Publication No. 2024-0009003 Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by the present invention is to provide a display device with improved display quality, but such problem is merely an example and does not limit the scope of the present invention. [Means for solving the problem]

[0006] An embodiment of the present invention provides a display device including: a substrate including a display area and a peripheral area; a plurality of unit pixel areas arranged in the display area, each including a first pixel circuit, a second pixel circuit, and a third pixel circuit; power supply voltage supply lines arranged in the peripheral area; first driving voltage lines electrically connected to the power supply voltage supply lines and arranged in a mesh structure in the display area; and second driving voltage lines electrically connected to the power supply voltage supply lines, arranged in a layer different from the first driving voltage lines, and extending from the display area in a first direction; wherein the first driving voltage lines are connected to the second driving voltage lines for each of the plurality of unit pixel areas via at least one internal contact hole.

[0007] In an embodiment, a step-like difference may be formed on a side surface of the inner contact hole.

[0008] In one embodiment, the semiconductor device may further include a first insulating layer and a second insulating layer stacked between the first driving voltage line and the second driving voltage line, and the internal contact hole may be formed by overlapping a first through hole of the first insulating layer and a second through hole of the second insulating layer, and a width of the first through hole may be different from a width of the second through hole.

[0009] In one embodiment, the first driving voltage line may include a portion extending in the first direction and a portion extending in a second direction intersecting the first direction, and the second driving voltage line may overlap with the portion of the first driving voltage line extending in the first direction.

[0010] In one embodiment, the display device may further include a third driving voltage line electrically connected to the power supply voltage line and disposed in a different layer from the first driving voltage line and the second driving voltage line, wherein the third driving voltage line extends in a second direction intersecting the first direction in the display area, and the third driving voltage line may be connected to the second driving voltage line for each of the plurality of unit pixel areas through at least one internal via hole.

[0011] In one embodiment, the semiconductor device further includes a third insulating layer disposed between the second driving voltage line and the third driving voltage line, and the internal via hole is defined in the third insulating layer and does not overlap with the internal contact hole.

[0012] In one embodiment, the first driving voltage line may include a portion extending in the first direction and a portion extending in a second direction intersecting the first direction, and the third driving voltage line may overlap with the portion of the first driving voltage line extending in the second direction.

[0013] In one embodiment, the power supply voltage supply lines are arranged in the peripheral region and include a first power supply voltage supply line provided in the same layer as the first driving voltage line, a second power supply voltage supply line provided in the same layer as the second driving voltage line, and a third power supply voltage supply line arranged in a different layer from the first power supply voltage supply line and the second power supply voltage supply line, and the first power supply voltage supply line may be arranged to surround the display region.

[0014] In an embodiment, the second power supply line may extend in the first direction in the peripheral region.

[0015] In one embodiment, the first power supply line and the second power supply line may be connected to each other through a plurality of external contact holes in the peripheral region.

[0016] In an embodiment, a step-like difference may be formed on a side surface of the outer contact hole.

[0017] In one embodiment, the third power supply voltage supply line may be connected to the second power supply voltage supply line through a plurality of external via holes, and at least one of the plurality of external via holes may at least partially overlap with the plurality of external contact holes.

[0018] In an embodiment, the first power supply voltage supply line may be integral with the first driving voltage line.

[0019] In one embodiment, the first pixel circuit may include a first thin film transistor including a silicon semiconductor layer and a second thin film transistor including an oxide semiconductor layer, and the first driving voltage line may overlap with at least one of the first thin film transistor and the second thin film transistor.

[0020] One embodiment of the present invention provides a display device comprising: a substrate including a display region and a peripheral region; a pixel circuit disposed in the display region, the pixel circuit including a first thin film transistor having a first semiconductor layer and a second thin film transistor having a second semiconductor layer disposed in a layer different from the first semiconductor layer; a display element connected to the pixel circuit; a first driving voltage line disposed between the substrate and the first semiconductor layer; a first insulating layer covering the first semiconductor layer and disposed below the second semiconductor layer; a second insulating layer disposed on the first insulating layer and covering the second semiconductor layer; a second driving voltage line disposed on the second insulating layer; a third insulating layer disposed on the second insulating layer and covering the second driving voltage line; and a third driving voltage line disposed on the third insulating layer;

[0021] In an embodiment, the inner contact hole may be formed by overlapping a first through hole of the first insulating layer and a second through hole of the second insulating layer.

[0022] In one embodiment, the width of the first through hole is different from the width of the second through hole.

[0023] In an exemplary embodiment, the third driving voltage line may be connected to the second driving voltage line in the display area through an internal via hole defined in the third insulating layer.

[0024] In an exemplary embodiment, the first driving voltage line may overlap at least one of the first thin film transistor and the second thin film transistor.

[0025] In one embodiment, the display element comprises organic light-emitting elements in a tandem structure, and a pixel defining layer defining an emission region of the organic light-emitting elements may include a separator having a concave structure disposed between the organic light-emitting elements.

[0026] One embodiment of the present invention provides an electronic device including a display device, the display device comprising: a substrate including a display region and a peripheral region; a plurality of unit pixel regions disposed in the display region, each including a first pixel circuit, a second pixel circuit, and a third pixel circuit; power supply voltage supply lines disposed in the peripheral region; first driving voltage lines electrically connected to the power supply voltage supply lines and arranged in a mesh structure in the display region; and second driving voltage lines electrically connected to the power supply voltage supply lines, arranged in a layer different from the first driving voltage lines, and extending from the display region in a first direction; and the first driving voltage lines are connected to the second driving voltage lines for each of the plurality of unit pixel regions via at least one internal contact hole. [Effects of the Invention]

[0027] According to an embodiment of the present invention, a display device having improved display quality may be provided by connecting driving voltage lines disposed on different layers to each other through contact holes for each pixel unit, although the scope of the present invention is not limited by such an effect. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a plan view schematically illustrating a display device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a plan view schematically illustrating a portion of a display area according to one embodiment. [Figure 3] 3 is a cross-sectional view of the area cut along II' in FIG. 2. [Figure 4] FIG. 1 is a circuit diagram showing a pixel circuit that can be applied to an embodiment of the present invention. [Figure 5] 1 is a diagram showing a schematic arrangement of driving voltage lines PL arranged in a unit pixel region. [Figure 6] 5. A partial configuration of the cross section corresponding to II-II' in FIG. 5 is shown. [Figure 7] 5. A partial configuration of the cross section corresponding to III-III' in FIG. 5 is shown. [Figure 8] 1 is a diagram showing a schematic layout of power supply voltage supply lines arranged in a peripheral area PA. [Figure 9] 8. A partial configuration of the cross section corresponding to IV-IV' in FIG. 8 is shown. [Figure 10] 1 is a schematic layout diagram illustrating transistor and storage capacitor locations of a pixel circuit according to an embodiment of the present invention; [Figure 11] 11 is a layout diagram schematically illustrating the components of the pixel circuit shown in FIG. 10 by layer. [Figure 12] 11 is a layout diagram schematically illustrating the components of the pixel circuit shown in FIG. 10 by layer. [Figure 13] 11 is a layout diagram schematically illustrating the components of the pixel circuit shown in FIG. 10 by layer. [Figure 14] 11 is a layout diagram schematically illustrating the components of the pixel circuit shown in FIG. 10 by layer. [Figure 15] 11 is a layout diagram schematically illustrating the components of the pixel circuit shown in FIG. 10 by layer. [Figure 16] 11 is a layout diagram schematically illustrating the components of the pixel circuit shown in FIG. 10 by layer. [Figure 17] 11 is a layout diagram schematically illustrating the components of the pixel circuit shown in FIG. 10 by layer. [Figure 18] 11 is a layout diagram schematically illustrating the components of the pixel circuit shown in FIG. 10 by layer. [Figure 19] 11 is a layout diagram schematically illustrating the components of the pixel circuit shown in FIG. 10 by layer. [Figure 20] 11 is a layout diagram schematically illustrating the components of the pixel circuit shown in FIG. 10 by layer. [Figure 21] 1 is a plan view showing only a portion of the configuration of a display device according to an embodiment of the present invention; [Figure 22]1 is a cross-sectional view schematically illustrating a cross section of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention can be modified in various ways and can have various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The advantages and features of the present invention, and methods for achieving them, will become clearer with reference to the following detailed description of the embodiments together with the drawings. However, the present invention is not limited to the following embodiments and can be embodied in various forms.

[0030] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be denoted by the same reference numerals, and duplicate descriptions thereof will be omitted.

[0031] In the following embodiments, when various components such as layers, films, regions, and plates are described as being "on" other components, this does not only mean that they are "directly on" other components, but also means that other components are interposed between them. Furthermore, for the sake of convenience, the dimensions of components may be exaggerated or reduced in the drawings. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of convenience, and the present invention is not necessarily limited to those shown in the drawings.

[0032] In the following embodiments, a "plan view" means a view from above the target portion, and a "cross-sectional view" means a view from the side of a vertical cross section of the target portion. In the following embodiments, when a first component "overlaps" a second component, it means that the first component is located above or below the second component.

[0033] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes on a Cartesian coordinate system, but may be interpreted in a broad sense to include this. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may refer to different directions that are not perpendicular to each other.

[0034] FIG. 1 is a plan view schematically showing a part of a display device according to one embodiment of the present invention.

[0035] The display device 10 may also be a light-emitting display device including a light-emitting element as a display element. For example, the display device 10 may be an organic light-emitting display device using an organic light-emitting diode including an organic light-emitting layer, a micro light-emitting diode display device using a micro LED, a quantum dot light-emitting display device using a quantum dot light-emitting diode including a quantum dot light-emitting layer, or an inorganic light-emitting display device using an inorganic light-emitting element including an inorganic semiconductor.

[0036] The display device 10 may include a display area DA that displays an image and a peripheral area PA outside the display area DA. The peripheral area PA is also a type of non-display area where no display elements are arranged. The display area DA is entirely surrounded by the peripheral area PA. Various components that make up the display device 10 may be arranged on a substrate 100. Therefore, the substrate 100 can be considered to include the display area DA and the peripheral area PA.

[0037] A plurality of pixels PX may be arranged in the display area DA. The pixels PX may include display elements. The display elements may be connected to pixel circuits that drive the pixels PX. In one embodiment, the display elements may also be organic light-emitting elements. Each pixel PX may emit light, for example, red, green, blue, or white, through the organic light-emitting element OLED. The plurality of pixels PX may include a first pixel that emits light in a first color, a second pixel that emits light in a second color, and a third pixel that emits light in a third color. For example, the first pixel may be a red pixel, the second pixel may be a green pixel, and the third pixel may be a blue pixel. In one embodiment, the plurality of pixels PX may further include a white pixel that emits light in white.

[0038] The peripheral area PA may include various wirings that transmit electrical signals to the display area DA, outer circuits electrically connected to pixel circuits that drive pixels, and pads to which a printed circuit board or a driver IC chip is connected. For example, the peripheral area PA may include a scan driving circuit (not shown), a terminal unit PAD, a power supply voltage supply line PSL, and a common voltage supply line (not shown).

[0039] The terminal pad may be disposed on one side of the substrate 100. The terminal pad may be exposed without being covered by an insulating layer and connected to the display circuit board 30. A display driver 32 may be disposed on the display circuit board 30. The display driver 32 may be formed in the form of one or more integrated circuit chips and mounted on the display circuit board 30.

[0040] The display driver 32 may generate control signals and data signals to be transmitted to the scan driver circuit, and the control signals and data signals may be transmitted to pixel circuits that drive the pixels PX in the display area DA through fan-out lines FW connected to the terminal units PAD.

[0041] The display driver 32 may supply a driving voltage ELVDD to the power supply voltage supply line PSL. The driving voltage ELVDD may be applied to a pixel circuit that drives the pixel PX via a first driving voltage line PL1, a second driving voltage line PL2, and a third driving voltage line PL3 connected to the power supply voltage supply line PSL.

[0042] The power supply voltage supply line PSL can include a first power supply voltage supply line 11, a second power supply voltage supply line 12, and a third power supply voltage supply line 13 arranged on different layers.

[0043] The first power supply voltage supply line 11 may be arranged to surround at least a portion of the display area DA from the peripheral area PA. The first power supply voltage supply line 11 may be arranged to extend in the x-direction below and above the display area DA. When the first power supply voltage supply line 11 is arranged to surround the entire display area DA, the width of the areas below and above the display area DA may be wider than the width of the areas to the left and right of the display area DA.

[0044] The second power supply voltage supply line 12 may be directly connected to the terminal unit PAD via a fanout line FW and may extend in the x-direction from below the display area DA. The second power supply voltage supply line 12 may be provided extending in the x-direction between the terminal unit PAD and the display area DA in a plan view. Alternatively, the second power supply voltage supply line 12 may be provided extending in the x-direction above and below the display area DA. The second power supply voltage supply line 12 may be disposed overlapping the first power supply voltage supply line 11. The second power supply voltage supply line 12 may be connected to the first power supply voltage supply line 11 via at least one external contact hole.

[0045] The third power voltage supply line 13 may be provided below the display area DA and extend in the x-direction. The third power voltage supply line 13 may be provided between the terminal unit PAD and the display area DA in a plan view and extend in the x-direction. The third power voltage supply line 13 may be arranged to overlap the first power voltage supply line 11 and the second power voltage supply line 12. The third power voltage supply line 13 may be connected to the second power voltage supply line 12 via at least one external via hole.

[0046] The first power supply voltage supply line 11, the second power supply voltage supply line 12, and the third power supply voltage supply line 13 are electrically connected to each other and can supply the driving voltage ELVDD.

[0047] The first power voltage supply line 11 may be connected to the first driving voltage line PL1 and transmit the driving voltage ELVDD to the display area DA. The first driving voltage line PL1 may be integral with the first power voltage supply line 11. The first driving voltage line PL1 may be arranged in a mesh structure from the display area DA. That is, the first driving voltage line PL1 may include a portion extending in the x direction and a portion extending in the y direction. The portion of the first driving voltage line PL1 extending in the x direction may be connected to the first power voltage supply lines 11 arranged on the left and right sides of the display area, and the portion of the first driving voltage line PL1 extending in the y direction may be connected to the first power voltage supply lines 11 arranged above and below the display area.

[0048] The second power supply voltage supply line 12 may be connected to the second driving voltage line PL2 and may transmit the driving voltage ELVDD to the display area DA. The second driving voltage line PL2 may be integral with the second power supply voltage supply line 12. The second driving voltage line PL2 may extend in the x-direction in the display area DA.

[0049] The third power voltage supply line 13 may be connected to the third driving voltage line PL3 and may transmit the driving voltage ELVDD to the display area DA. The third driving voltage line PL3 may be integral with the third power voltage supply line 13. The third driving voltage line PL3 may extend in the y direction in the display area DA.

[0050] Fig. 2 is a plan view schematically illustrating a portion of a display area according to an embodiment. Fig. 2 is a view illustrating area A of the display area DA in Fig. 1, illustrating one unit pixel area PU. Fig. 3 is a cross-sectional view of the area taken along line II' in Fig. 2.

[0051] 2 and 3, a plurality of organic light emitting elements OLED, which are light emitting elements, may be arranged on a substrate 100. The organic light emitting element OLED may include a pixel electrode PE, a counter electrode CE, and an emitting layer EL between the pixel electrode PE and the counter electrode CE.

[0052] Hereinafter, a display device according to an embodiment of the present invention will be described as an organic light emitting display device including an organic light emitting element (OLED), but the display device 10 of the present invention is not limited thereto. In other embodiments, the display device 10 of the present invention may be a display device such as an inorganic light emitting display (or inorganic EL display) or a quantum dot light emitting display.

[0053] A plurality of pixel circuits PC may be disposed between the substrate 100 and the plurality of organic light emitting elements OLED, and each of the plurality of organic light emitting elements OLED may be connected to one pixel circuit PC. For example, a pixel electrode PE of the organic light emitting element OLED may be connected to the pixel circuit PC. The pixel circuit PC may include at least one transistor and drive the organic light emitting element OLED. An insulating layer IL may be disposed between the substrate 100 and the organic light emitting element OLED.

[0054] The display area DA of the substrate 100 may include a light-emitting area EA and a non-light-emitting area NEA surrounding the light-emitting area EA. The light-emitting area EA is also an area where an emitting layer of an organic light-emitting element OLED is disposed and emits light. The light-emitting area EA may be defined by an opening OP in the pixel defining layer PDL, as shown in FIG. 3.

[0055] Pixel electrodes PE may be arranged on the substrate 100, and a pixel defining layer PDL may be disposed between the pixel electrodes PE. An opening OP corresponding to a portion of the pixel electrode PE may be defined in the pixel defining layer PDL. An emitting layer EL may be disposed in the opening OP of the pixel defining layer PDL, and a counter electrode CE may be disposed on the emitting layer EL. The counter electrode CE may be disposed on an upper surface of the pixel defining layer PDL.

[0056] In one embodiment, the organic light emitting device OLED is also a tandem light emitting device. The tandem light emitting device may include two or more light emitting units between a pixel electrode PE and a counter electrode CE, and a charge generation layer (CGL) disposed between the two light emitting units. The organic light emitting device OLED has a stacked structure of multiple light emitting units, which may improve color purity and luminous efficiency.

[0057] Separators SPR may be defined in the pixel defining layer PDL between the pixel electrodes PE. The separators SRP may be provided in a shape that surrounds at least a portion of the pixel electrode PE in a plan view. The separators SRP may be provided in a shape that does not completely surround the pixel electrode PE in a plan view, but has a partially open shape. The separators SPR may be spaced apart from each other.

[0058] The separator SPR may also be a recess of a predetermined depth formed by removing a portion or the entire pixel defining layer PDL. In one embodiment, as shown in FIG. 3, after the counter electrode CE is formed, the separator SPR may be formed by removing a portion of the pixel defining layer PDL by etching. In this case, a portion of the counter electrode CE disposed on the pixel defining layer PDL may also be removed, and the counter electrode CE may include a hole corresponding to the separator SPR. The cross section of the separator SPR may have a U-shape, a triangle, a square, a trapezoid, a polygon, or the like. In the drawings, the separator SPR is shown tapered upward (z-direction), but the present invention is not limited thereto. The separator SPR may also be tapered upward (z-direction), narrowing downward. The separator SPR may be a hole penetrating the pixel defining layer PDL or a groove that does not penetrate the pixel defining layer PDL. The separator SPR may prevent leakage current from occurring between adjacent organic light emitting elements due to a charge generation layer or the like.

[0059] 2 shows an example of one unit pixel region PU. In the display area DA, unit pixel regions PU may be repeatedly arranged in the x and y directions. The unit pixel region PU may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. In one embodiment, the first pixel PX1 is a red pixel that emits red light, the second pixel PX2 is a green pixel that emits green light, and the third pixel PX3 is a blue pixel that emits blue light.

[0060] In one embodiment, the pixels PX may be arranged in a matrix. The light-emitting areas EA of the first pixel PX1 and the second pixel PX2 may be alternately arranged in the y direction, and the light-emitting areas EA of the third pixel PX3 may be repeatedly arranged in the y direction in a column adjacent to the column in which the first pixel PX1 and the second pixel PX2 are arranged. The length in the y direction of the light-emitting area EA of the third pixel PX3 is equal to or greater than the sum of the lengths in the y direction of the light-emitting areas EA of the first pixel PX1 and the second pixel PX2.

[0061] The light-emitting area EA of the first pixel PX1, the light-emitting area EA of the second pixel PX2, and the light-emitting area EA of the third pixel PX3 may have different areas. In one embodiment, the light-emitting area EA of the third pixel PX3 may have a larger area than the light-emitting area EA of the first pixel PX1. The light-emitting area EA of the third pixel PX3 may also have a larger area than the light-emitting area EA of the second pixel PX2. The light-emitting area EA of the first pixel PX1 may have a larger area than the light-emitting area EA of the second pixel PX2. In another embodiment, the light-emitting area EA of the third pixel PX3 may have the same area as the light-emitting area EA of the first pixel PX1. The present invention is not limited thereto. For example, the light-emitting area EA of the first pixel PX1 may be larger than the light-emitting area EA of the second pixel PX2 and the light-emitting area EA of the third pixel PX3. Various embodiments are possible.

[0062] The light emitting area EA may have a shape such as a polygon such as a square or octagon, a circle, or an ellipse, and the polygon may have rounded corners (vertices).

[0063] The organic light emitting elements OLED that implement the first pixel PX1, the second pixel PX2, and the third pixel PX3 are connected to pixel circuits PC and can be driven individually.

[0064] FIG. 4 is a circuit diagram showing a pixel circuit that can be applied to one embodiment of the present invention.

[0065] Referring to FIG. 4, an organic light emitting element OLED, which is a light emitting element, is connected to a pixel circuit PC, and the organic light emitting element OLED may include a pixel electrode (anode), a counter electrode (cathode), and an emitting layer between the anode and the cathode.

[0066] The pixel circuit PC is connected to the scan line GWL, the first initialization control line GIL, the second initialization control line GBL, the compensation scan line GCL, and the emission control line EML, respectively, and may receive the scan signal GW, the first initialization control signal GI, the second initialization control signal GB, the compensation scan signal GC, and the emission control signal EM. The pixel circuit PC may also receive the data signal Dm via the data line DL and the driving voltage ELVDD via the driving voltage line PL.

[0067] The pixel circuit PC may include a plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 and a storage capacitive element. The plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6, a second initialization transistor T7, and a bias transistor T8. The storage capacitive element may also be a capacitor, and may be referred to herein as a first storage capacitor Cst1.

[0068] In one embodiment, some of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 are PMOS (p-channel MOSFETs), and the remaining transistors are NMOS (n-channel MOSFETs). For example, the driving transistor T1, the switching transistor T2, the operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8 of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 are PMOS, and the compensation transistor T3 and the first initialization transistor T4 are NMOS. Alternatively, the compensation transistor T3 and the first initialization transistor T4 of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 are PMOS, and the remaining transistors are NMOS. Alternatively, all of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 are NMOS or PMOS. For convenience, the following description will be given assuming that the compensation transistor T3 and the first initialization transistor T4 are NMOS (n-channel MOSFETs) including an oxide semiconductor, and the rest are PMOS (p-channel MOSFETs).

[0069] At least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 is also a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 is also a transistor having an oxide semiconductor layer.

[0070] The driving transistor T1, which directly affects the brightness of the display device, may be configured to include a semiconductor layer made of highly reliable polycrystalline silicon, thereby enabling a high-resolution display device. Meanwhile, oxide semiconductors have high carrier mobility and low leakage current, so they do not significantly drop in voltage even over long drive periods. That is, low-frequency drive is possible because the image color shift due to voltage drop is not significant even during low-frequency drive. Because oxide semiconductors have the advantage of low leakage current, at least one of the compensation transistor T3 and the first initialization transistor T4, which are connected to the drive gate electrode of the driving transistor T1, may be made of an oxide semiconductor to prevent leakage current from flowing through the drive gate electrode and reduce power consumption. For example, the driving transistor T1, the switching transistor T2, the operation control transistor T5, the emission control transistor T6, the second initialization transistor T7, and the bias transistor T8 may be transistors having low-temperature polysilicon semiconductor layers, and the compensation transistor T3 and the first initialization transistor T4 may be transistors having oxide semiconductor layers.

[0071] The driving transistor T1 may be connected between a driving voltage line PL receiving a driving voltage ELVDD and the organic light emitting element OLED. A gate electrode of the driving transistor T1 may be connected to one end of a first storage capacitor Cst1. A gate electrode of the driving transistor T1 may be connected to a first node N1. A source electrode of the driving transistor T1 may be connected to the driving voltage line PL via an operation control transistor T5. A drain electrode of the driving transistor T1 may be electrically connected to an anode of the organic light emitting element OLED via an emission control transistor T6. The driving transistor T1 may receive a data signal Dm transmitted through a data line DL through a switching operation of the switching transistor T2 and supply a driving current to the organic light emitting element OLED.

[0072] A gate electrode of the switching transistor T2 may be connected to the scan line GWL. A first electrode of the switching transistor T2 may be connected to the data line DL, and a second electrode of the switching transistor T2 may be connected to the source electrode of the driving transistor T1. The switching transistor T2 is turned on in response to a scan signal GW transmitted through the scan line GWL to transmit a data signal Dm transmitted to the data line DL to the source electrode of the driving transistor T1. At the same time, the data signal Dm may be transmitted to the gate electrode of the driving transistor T1 by the compensation transistor T3, which is turned on.

[0073] The gate electrode of the compensation transistor T3 may be connected to the compensation scan line GCL. The first electrode of the compensation transistor T3 may be connected to the drain electrode of the driving transistor T1, and the second electrode of the compensation transistor T3 may be connected to the first node N1. The compensation transistor T3 may be turned on in response to a scan signal GW transmitted through the scan line GWL to connect the gate electrode and drain electrode of the driving transistor T1 to each other, thereby diode-connecting the driving transistor T1 and compensating for the threshold voltage Vth of the driving transistor T1.

[0074] The gate electrode of the first initialization transistor T4 may be connected to a first initialization control line GIL. The first electrode of the first initialization transistor T4 may be connected to a first initialization voltage line VL1, and the second electrode may be connected to a first node N1. The first initialization transistor T4 is turned on by a first initialization control signal GI applied from the first initialization control line GIL to transmit a first initialization voltage Vint to the gate electrode of the driving transistor T1, thereby initializing the potential of the gate electrode of the driving transistor T1 (i.e., the potential of the first node N1) to a predetermined voltage. The first initialization voltage Vint may be set to a voltage higher than the common voltage ELVSS or to the common voltage ELVSS.

[0075] The gate electrode of the operation control transistor T5 may be connected to the emission control line EML, the first electrode of the operation control transistor T5 may be connected to the driving voltage line PL, and the second electrode of the operation control transistor T5 may be connected to the source electrode of the driving transistor T1.

[0076] A gate electrode of the emission control transistor T6 may be connected to an emission control line EML. A first electrode of the emission control transistor T6 may be connected to a drain electrode of the driving transistor T1, and a second electrode of the emission control transistor T6 may be electrically connected to an anode of the organic light emitting element OLED. The operation control transistor T5 and the emission control transistor T6 may be simultaneously turned on by an emission control signal EM applied from the emission control line EML. The driving voltage ELVDD applied through the turned-on operation control transistor T5 may be compensated through the driving transistor T1 and then transmitted to the organic light emitting element OLED.

[0077] A gate electrode of the second initialization transistor T7 may be connected to a second initialization control line GBL. A first electrode of the second initialization transistor T7 may be connected to the anode of the organic light emitting element OLED, and a second electrode of the second initialization transistor T7 may be connected to a second initialization voltage line VL2. The second initialization transistor T7 may be turned on by a second initialization control signal GB applied from the second initialization control line GBL to initialize the anode of the organic light emitting element OLED. The second initialization control signal GB may be the same as or different from the first initialization control signal GI.

[0078] Unlike the present invention, even if the minimum current of the driving transistor T1 for displaying a black image flows as a driving current, if the organic light emitting element OLED emits light, the black image will not be displayed properly. However, according to the present invention, the second initialization transistor T7 can disperse a portion of the minimum current of the driving transistor T1 as a bypass current to a current path other than the current path of the organic light emitting element OLED. Here, the minimum current of the driving transistor T1 may refer to a current under a condition where the gate-source voltage Vgs of the driving transistor T1 is lower than a threshold voltage (Vth) and the driving transistor T1 is turned off. In this way, a minimum driving current (e.g., a current of 10 pA or less) under the condition of turning off the driving transistor T1 is transmitted to the organic light emitting element OLED, thereby displaying a black image. When the minimum driving current for displaying a black image flows, the bypass current has a significant effect. On the other hand, when a large driving current for displaying an image such as a normal image or a white image flows, the bypass current has almost no effect. Therefore, when a driving current for displaying a black image flows, an accurate black luminance image can be realized from the driving current using the second initialization transistor T7, thereby improving the contrast ratio and providing a display device with improved display quality.

[0079] A gate electrode of the bias transistor T8 may be connected to the second initialization control line GBL, a first electrode of the bias transistor T8 may be connected to a bias voltage line VL3 to which a bias voltage Vobs is provided, and a second electrode of the bias transistor T8 may be connected to the source electrode of the driving transistor T1.

[0080] One end of the first storage capacitor Cst1 may be connected to the gate electrode of the driving transistor T1, and the other end may be connected to the driving voltage line PL. The first storage capacitor Cst1 may be connected between the driving voltage line PL and a first node N1. The first storage capacitor Cst1 may store a voltage between the driving voltage ELVDD and the first node N1.

[0081] The cathode of the organic light emitting element OLED may be connected to a common voltage line that applies a common voltage ELVSS. The organic light emitting element OLED may emit light by receiving a driving current from the driving transistor T1, thereby displaying an image. The driving voltage ELVDD may be a predetermined high-level voltage, and the common voltage ELVSS may be a voltage lower than the driving voltage ELVDD or a ground voltage.

[0082] A driving process of the pixel PX will now be described. During the initialization period, a low-level first initialization control signal GI may be supplied to the first initialization transistor T4 via the first initialization control line GIL, and a low-level second initialization control signal GB may be supplied to the second initialization transistor T7 via the second initialization control line GBL. As a result, the first initialization transistor T4 and the second initialization transistor T7 may be turned on. A first initialization voltage Vint applied from the first initialization voltage line VL1 may be transferred to the gate electrode of the driving transistor T1 via the first initialization transistor T4 and to the anode via the second initialization transistor T7. As a result, the voltages of the gate electrode and anode of the driving transistor T1 may be initialized.

[0083] Thereafter, during a data write period, a low-level scan signal GW is supplied via the scan line GWL, turning on the switching transistor T2 and the compensation transistor T3. The switching transistor T2 transfers a data signal Dm from the data line DL to the source electrode of the driving transistor T1, and the driving transistor T1 is diode-coupled by the compensation transistor T3. As a result, a compensation voltage, which is reduced from the data signal Dm by the threshold voltage of the driving transistor T1, is applied to the gate electrode of the driving transistor T1.

[0084] The drive voltage ELVDD and the compensation voltage are applied to both ends of the storage capacitor Cst1, and a charge corresponding to the voltage difference between both ends of the storage capacitor Cst1 can be stored in the storage capacitor Cst1.

[0085] Thereafter, during the light-emitting period, the light-emitting control signal EM supplied from the light-emitting control line EML changes from high to low, turning on the operation control transistor T5 and the light-emitting control transistor T6, generating a driving current due to a voltage difference between the gate electrode voltage of the driving transistor T1 and the driving voltage ELVDD, and the driving current is supplied to the organic light-emitting element OLED via the light-emitting control transistor T6, causing it to emit light.

[0086] The characteristics of the driving transistor T1 and the light-emitting element differ from one another for each of the plurality of pixel circuits PC. In particular, the color coordinates of the display device 10 may vary (e.g., become reddish) when driven at a high frequency. However, according to the present invention, the voltage of the source electrode of the driving transistor T1 can be controlled via the bias voltage Vobs through the bias transistor T8. This can improve the brightness deviation (current deviation) and color coordinate variation between pixels by controlling the driving current. This can provide a display device 10 with improved display quality.

[0087] Fig. 5 is a diagram showing a schematic arrangement of driving voltage lines PL arranged in a unit pixel area PU. Fig. 6 illustrates a partial configuration of a cross section corresponding to II-II' in Fig. 5. Fig. 7 illustrates a partial configuration of a cross section corresponding to III-III' in Fig. 5.

[0088] In the unit pixel region PU, a first pixel circuit PC1 for driving a first pixel, a second pixel circuit PC2 for driving a second pixel, and a third pixel circuit PC3 for driving a third pixel may be arranged in a row along the x direction.

[0089] The driving voltage lines PL may include a first driving voltage line PL1, a second driving voltage line PL2, and a third driving voltage line PL3 arranged in different layers.

[0090] The first driving voltage line PL1 may have a mesh structure. The first driving voltage line PL1 may have a portion extending in the x direction and a portion extending in the y direction. The portion extending in the x direction and the portion extending in the y direction may intersect with each other and be integrated. The portions extending in the y direction of the first driving voltage line PL1 may be arranged one by one corresponding to each unit pixel region PU. The portions extending in the y direction of the first driving voltage line PL1 may be arranged one by one and connected to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3.

[0091] The second driving voltage line PL2 may extend in the x-direction and overlap with a portion of the first driving voltage line PL1 extending in the x-direction. The second driving voltage line PL2 may be disposed in correspondence with each unit pixel region PU.

[0092] The third driving voltage line PL3 may extend in the y direction and overlap with the portion of the first driving voltage line PL1 extending in the y direction. The third driving voltage line PL3 may be disposed and connected to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3, one each.

[0093] The first driving voltage line PL1 and the second driving voltage line PL2 may be connected to each other through at least one internal contact hole CNTi for each unit pixel region PU. In FIG. 5, the first driving voltage line PL1 and the second driving voltage line PL2 are connected to the internal contact hole CNTi in the first pixel circuit PC1 region and the internal contact hole CNTi in the third pixel circuit PC3 region in the unit pixel region PU. However, the present invention is not limited thereto. Various modifications are possible, such as forming the internal contact hole CNTi in only one of the first pixel circuit PC1 to the third pixel circuit PC3 regions, or forming the internal contact hole CNTi in all of the first pixel circuit PC1 to the third pixel circuit PC3 regions.

[0094] If the internal contact holes CNTi connecting the first driving voltage lines PL1 and the second driving voltage lines PL2 are not provided in the display area DA, the driving voltage may be applied unevenly as the size of the display area DA increases, which may affect the display quality.

[0095] In an embodiment of the present invention, at least one inner contact hole CNTi may be disposed per unit pixel area PU so that the driving voltage may be uniformly applied within the display area DA.

[0096] The second driving voltage line PL2 and the third driving voltage line PL3 may be connected to each other via an internal via hole VHi. In some embodiments, the second driving voltage line PL2 and the third driving voltage line PL3 may be connected to each other via an internal via hole VHi for each unit pixel region PU. In FIG. 5, the second driving voltage line PL2 and the third driving voltage line PL3 are connected to the internal via hole VHi in the second pixel circuit PC2 region and the internal via hole VHi in the third pixel circuit PC3 region in the unit pixel region PU. However, the present invention is not limited thereto. The internal via hole VHi may be formed in only one of the first pixel circuit PC1 to the third pixel circuit PC3 regions, or may be formed in all of the first pixel circuit PC1 to the third pixel circuit PC3 regions.

[0097] If the internal via hole VHi connecting the second driving voltage line PL2 and the third driving voltage line PL3 is not provided within the display area DA, the driving voltage may be applied unevenly as the size of the display area DA increases, which may affect the display quality.

[0098] In an embodiment of the present invention, at least one internal via hole VHi may be disposed per unit pixel area PU so that the driving voltage may be uniformly applied within the display area DA.

[0099] Meanwhile, in order to realize high integration, the embodiment of the present invention is designed taking into consideration the position and method of forming the inner contact hole CNTi and the relative positions of the inner via hole VHi and the inner contact hole CNTi.

[0100] 6, the first driving voltage line PL1, the second driving voltage line PL2, and the third driving voltage line PL3 may be disposed on different layers. The first driving voltage line PL1 may be disposed on the substrate 100, and a first insulating layer IL1 and a second insulating layer IL2 may be stacked on top of the first driving voltage line PL1. The second driving voltage line PL2 may be disposed on the second insulating layer IL2. A third insulating layer IL3 may be disposed on top of the second driving voltage line PL2. The third driving voltage line PL3 may be disposed on top of the third insulating layer IL3.

[0101] The first insulating layer IL1 and the second insulating layer IL2 may each be composed of a single layer or multiple layers of inorganic insulating layers, and the third insulating layer IL3 may be composed of a single layer or multiple layers of organic insulating layers.

[0102] The first driving voltage line PL1 and the second driving voltage line PL2 may be connected through an internal contact hole CNTi. The internal contact hole CNTi may be formed by overlapping a first through hole TH1 of the first insulating layer IL1 and a second through hole TH2 of the second insulating layer IL2. The internal contact hole CNTi exposes an upper surface of the first driving voltage line PL1, and the second driving voltage line PL2 may be directly connected to the first driving voltage line PL1 through the internal contact hole CNTi.

[0103] To form the internal contact hole CNTi, a first through hole TH1 may be formed in the first insulating layer IL1, and then a second through hole TH2 may be formed in the second insulating layer IL2. This may result in a stepped structure being formed on the side of the internal contact hole CNTi. That is, the width of the first through hole TH1 may be smaller than the width of the second through hole TH2.

[0104] The present invention is not limited thereto. Various modifications are possible, such as the width of the first through hole TH1 being wider than or the same as the width of the second through hole TH2. In some embodiments, the inner contact hole CNTi does not have a stepped structure on the side surface.

[0105] In this embodiment, when forming the inner contact hole CNTi, the first through hole TH1 and the second through hole TH2 are formed to overlap each other, which can effectively reduce the area occupied by the inner contact hole CNTi, thereby enabling high integration.

[0106] 7, the first driving voltage line PL1 and the second driving voltage line PL2 may be connected via an internal contact hole CNTi, and the third driving voltage line PL3 may be connected to the second driving voltage line PL2 via an internal via hole VHi. The internal contact hole CNTi may be formed by overlapping a through hole of the first insulating layer IL1 and a through hole of the second insulating layer IL2. As in FIG. 7, no step structure is formed on the side of the internal contact hole CNTi.

[0107] The third driving voltage line PL3 may be directly connected to the second driving voltage line PL2 through an internal via hole VHi defined in the third insulating layer IL3. The internal via hole VHi exposes an upper surface of the second driving voltage line PL2, and the third driving voltage line PL3 may be connected to the second driving voltage line PL2 through the internal via hole VHi.

[0108] The inner via holes VHi may be formed so as not to overlap with the inner contact holes CNTi. The inner via holes VHi may be formed by applying an organic material that forms the third insulating layer IL3 and then developing it. In this case, the inner via holes VHi may be disposed so as not to overlap with the inner contact holes CNTi in order to form a flat upper surface of the third insulating layer IL3. By flattening the upper surface of the third insulating layer IL3, defects may be minimized when forming the third driving voltage line PL3 and the like disposed thereon.

[0109] 8 is a diagram showing a schematic layout of power supply voltage supply lines arranged in the peripheral area PA. FIG. 8 may correspond to area B in FIG. 1. FIG. 9 illustrates a partial configuration of a cross section corresponding to IV-IV' in FIG. 8.

[0110] 8 and 9, a first power supply voltage supply line 11, a second power supply voltage supply line 12, and a third power supply voltage supply line 13 arranged in different layers may be provided in the peripheral area PA, overlapping each other.

[0111] The first power voltage supply line 11 may extend in the x direction. The first driving voltage line PL1 may branch off in the y direction from one side of the first power voltage supply line 11 and extend to the display area. The first power voltage supply line 11 and the first driving voltage line PL1 may be integrally formed.

[0112] The second power supply voltage supply line 12 may extend in the x-direction and at least partially overlap with the first power supply voltage supply line 11. The second power supply voltage supply line 12 may be connected to the first power supply voltage supply line 11 via an external contact hole CNTo.

[0113] A third driving voltage line PL3 may branch off in the y direction from one side of the third power supply voltage supply line 13 and extend to the display area. The third power supply voltage supply line 13 and the third driving voltage line PL3 may be integrally formed. The third power supply voltage supply line 13 may at least partially overlap the second power supply voltage supply line 12 and extend in the x direction. The third power supply voltage supply line 13 may be connected to the second power supply voltage supply line 12 through an external via hole VHo.

[0114] The first power supply voltage supply line 11 may be disposed on the substrate 100, and a first insulating layer IL1 and a second insulating layer IL2 may be sequentially disposed on the first power supply voltage supply line 11. The second power supply voltage supply line 12 may be disposed on the second insulating layer IL2. A third insulating layer IL3 may be disposed on the second power supply voltage supply line 12. A third power supply voltage supply line 13 may be disposed on the third insulating layer IL3. The first insulating layer IL1 and the second insulating layer IL2 may each be formed of a single layer or multiple layers of inorganic insulating layers. The third insulating layer IL3 may be formed of a single layer or multiple layers of organic insulating layers.

[0115] The external contact hole CNTo is a contact hole connecting the first power voltage supply line 11 and the second power voltage supply line 12 in the peripheral region, and may be formed by overlapping a first through hole TH1 in the first insulating layer IL1 and a second through hole TH2 in the second insulating layer IL2. A stepped structure may be formed on the side of the external contact hole CNTo. The width of the first through hole TH1 and the width of the second through hole TH2 may be different from each other. However, this is not limited thereto. The stepped structure may not be formed on the side of the external contact hole CNTo. A plurality of external contact holes CNTo may be formed, unlike the illustrated embodiment.

[0116] The external via holes VHo are contact holes connecting the second power supply voltage supply line 12 and the third power supply voltage supply line 13 in the peripheral region, and may be provided in multiple numbers. The external via holes VHo may be arranged so as not to overlap the external contact holes CNTo. However, this is not limited thereto. At least one of the external via holes VHo in the peripheral region may be arranged overlapping the external contact holes CNTo. Since the process sensitivity is not high in the peripheral region, the external contact holes CNTo and the external via holes VHo may be arranged overlapping each other. That is, in the peripheral region, it is less necessary to form the top surfaces of insulating layers such as the third insulating layer IL3 flat than in the display region DA. This is because the peripheral region PA often does not have driving elements, as in the display region DA, and therefore does not have voltage lines, etc., directly connected to the driving elements, etc. Furthermore, the voltage lines, etc., arranged in the peripheral region are often wider than the voltage supply lines (PL1 to PL3), etc., arranged in the display region DA, and are therefore less likely to break. Therefore, even if the top surface of the insulating layer is not flat, the occurrence of defects in the elements and wirings caused by the overlapping arrangement of the external contact hole CNTo and the external via hole VHo can be minimized.

[0117] 10 is a schematic layout diagram illustrating the locations of transistors and storage capacitors in a pixel circuit according to an embodiment of the present invention, and FIGS. 11 to 20 are schematic layout diagrams illustrating the components of the pixel circuit shown in FIG. 10 by layer.

[0118] As shown in Figures 11 to 20, the display device may include a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3. The first pixel circuit PC1 is a pixel circuit that drives the first pixel PX1 (Figure 2), the second pixel circuit PC2 is a pixel circuit that drives the second pixel PX2 (Figure 2), and the third pixel circuit PC3 is a pixel circuit that drives the third pixel PX3 (Figure 2). For convenience of explanation, some conductive patterns will be described below based on the first pixel circuit PC1, but the components thereof may also be arranged in the second pixel circuit PC2 and the third pixel circuit PC3. The structures shown in Figures 11 to 20 may be repeatedly arranged in the x direction and / or y direction.

[0119] FIG. 11 illustrates the first driving voltage line PL1.

[0120] 10 and 11, a portion of the first driving voltage line PL1 has a shape corresponding to the driving transistor T1 and serves as a lower protective metal that protects a portion of the first semiconductor layer 1100 overlapping with the first driving voltage line PL1. In each of the first to third pixels P1, P2, and P3, the first driving voltage line PL1 may be provided in a mesh structure by including a portion extending in a first direction (e.g., the x-direction) and a portion extending in a second direction (e.g., the y-direction). The first driving voltage line PL1 may be provided integrally in the first to third pixel circuits PC1, PC2, and PC3 or the entire display area.

[0121] The first driving voltage line PL1 may be electrically connected to the second driving voltage line PL2 (FIG. 19) and the third driving voltage line PL3 (FIG. 20), so that the same electrical signal as that applied to the second driving voltage line PL2 and the third driving voltage line PL3 may be applied to the first driving voltage line PL1.

[0122] The first driving voltage line PL1 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. For example, the first driving voltage line PL1 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0123] Fig. 12 illustrates the first semiconductor layer 1100 on the first driving voltage line PL1, and Fig. 13 illustrates the first conductive layer 1200 on the first semiconductor layer 1100. Fig. 14 illustrates both the first semiconductor layer 1100 and the first conductive layer 1200, and illustrates the arrangement of the driving transistor T1, the switching transistor T2, the operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8.

[0124] A first interlayer insulating layer 102 (see FIG. 22), which will be described later, may be disposed between the first driving voltage line PL1 and the first semiconductor layer 1100. A first gate insulating layer 103 (see FIG. 22) may be disposed between the first semiconductor layer 1100 and the first conductive layer 1200.

[0125] 10 and 12 to 14, the first semiconductor layer 1100 may include a first semiconductor pattern 1110 and a second semiconductor pattern 1120. That is, the first semiconductor pattern 1110 and the second semiconductor pattern 1120 may be disposed on the same layer. Each of the first semiconductor pattern 1110 and the second semiconductor pattern 1120 may be disposed for each pixel circuit. For example, one first semiconductor pattern 1110 and one second semiconductor pattern 1120 may be disposed for each of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3.

[0126] The driving transistor T1, the switching transistor T2, the operation control transistor T5, the emission control transistor T6, the second initialization transistor T7, and the bias transistor T8 may be located along the first semiconductor layer 1100. The driving transistor T1, the switching transistor T2, the operation control transistor T5, the emission control transistor T6, and the second initialization transistor T7 may be located in the first semiconductor pattern 1110. The bias transistor T8 may be located in the second semiconductor pattern 1120.

[0127] The first semiconductor layer 1100 may include a silicon semiconductor material. For example, the first semiconductor layer 1100 may include amorphous silicon or polysilicon. For example, the first semiconductor layer 1100 may include polysilicon crystallized at a low temperature. The first semiconductor layer 1100 may include a channel region overlapping the gate electrode and source and drain regions disposed on both sides of the channel region. The source and drain regions may also be regions doped with impurities.

[0128] The first conductive layer 1200 may be disposed on the first semiconductor layer 1100. The first conductive layer 1200 may include a first conductive pattern 1210, a second conductive pattern 1220, an emission control line EML, a second initialization control line GBL, and a second-second initialization voltage line VL2-2. That is, the first conductive pattern 1210, the second conductive pattern 1220, the emission control line EML, the second initialization control line GBL, and the second-second initialization voltage line VL2-2 may be disposed on the same layer. The first conductive layer 1200 may be referred to as a first gate layer. The first conductive pattern 1210 and the second conductive pattern 1220 may each have an isolated shape.

[0129] The first conductive pattern 1210, the second conductive pattern 1220, the light emitting control line EML, the second initialization control line GBL, and the 2-2nd initialization voltage line VL2-2 overlap the first semiconductor layer 1100 and serve as gate electrodes of transistors.

[0130] The portion of the first conductive pattern 1210 overlapping with the first semiconductor pattern 1110 also serves as the gate electrode of the driving transistor T1. The first conductive pattern 1210 may overlap with a portion of an electrode of a second conductive layer 1300 (see FIG. 15), which will be described later, thereby forming the storage capacitor Cst shown in FIG. 10. That is, the first conductive pattern 1210 also serves as one electrode of the storage capacitor Cst. For example, the first conductive pattern 1210 also serves as a lower electrode of the storage capacitor Cst.

[0131] The portion of the second conductive pattern 1220 overlapping the first semiconductor pattern 1110 also serves as the gate electrode of the switching transistor T2. The second conductive pattern 1220 is electrically connected to a scan line GWL (FIG. 19) described below and may receive a scan signal GW. That is, the scan signal GW may be applied to the pixel via the second conductive pattern 1220.

[0132] The light emitting control line EML, the second initialization control line GBL, and the 2-2 initialization voltage line VL2-2 may extend in the x-direction. The light emitting control line EML may transmit a light emitting control signal EM to each pixel. The second initialization control line GBL may transmit a second initialization control signal GB to each pixel circuit. The 2-2 initialization voltage line VL2-2 may transmit a 2-2 initialization voltage Vaint2 to the second pixel circuit PC2 and the third pixel circuit PC3.

[0133] A part of the emission control line EML that overlaps with the first semiconductor pattern 1110 is the gate electrode of the operation control transistor T5, and the other part of the emission control line EML that overlaps with the first semiconductor pattern 1110 is also the gate electrode of the emission control transistor T6.

[0134] The portion where the second initialization control line GBL overlaps with the first semiconductor pattern 1110 also serves as the gate electrode of the second initialization transistor T7.

[0135] In one embodiment, the second initialization transistor T7 of the first pixel circuit PC1 may receive a 2-1 initialization voltage Vaint1 via a 2-1 initialization voltage line VL2-1 of the third conductive layer 1500 (described below). In one embodiment, the second initialization transistor T7 of the second pixel circuit PC2 may receive a 2-2 initialization voltage Vaint2 via a 2-2 initialization voltage line VL2-2 of the first conductive layer 1200. In one embodiment, the second initialization transistor T7 of the third pixel circuit PC3 may receive a 2-2 initialization voltage Vaint2 via a 2-2 initialization voltage line VL2-2 of the first conductive layer 1200.

[0136] The portion where the second initialization control line GBL overlaps with the second semiconductor pattern 1120 is also the gate electrode of the bias transistor T8.

[0137] The first conductive layer 1200 may include a metal, an alloy, or a conductive metal oxide. For example, the first conductive layer 1200 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first conductive layer 1200 may be a single layer or multiple layers.

[0138] Figure 15 illustrates a second conductive layer 1300 on the first conductive layer 1200, Figure 16 illustrates a second semiconductor layer 1400 on the second conductive layer 1300, and Figure 17 illustrates a third conductive layer 1500 on the second semiconductor layer 1400. Figure 18 illustrates the second conductive layer 1300, the second semiconductor layer 1400, and the third conductive layer 1500 together, and illustrates the arrangement of the compensation transistor T3 and the first initialization transistor T4.

[0139] A second gate insulating layer 104 (see FIG. 22) may be disposed between the first conductive layer 1200 and the second conductive layer 1300. A second interlayer insulating layer 105 (see FIG. 22) may be disposed between the second conductive layer 1300 and the second semiconductor layer 1400, and a third gate insulating layer 106 (see FIG. 22) may be disposed between the second semiconductor layer 1400 and the third conductive layer 1500.

[0140] 10 and 15 to 18, the second conductive layer 1300 may include a third conductive pattern 1310, a fourth conductive pattern 1320, and a fifth conductive pattern 1330. That is, the third conductive pattern 1310, the fourth conductive pattern 1320, and the fifth conductive pattern 1330 may be disposed in the same layer. The second conductive layer 1300 is also referred to as a second gate layer. The third conductive pattern 1310 may be disposed to overlap the first conductive pattern 1210. The third conductive pattern 1310 may be disposed on top of the first conductive pattern 1210. In an embodiment, the third conductive pattern 1310 overlaps the first conductive pattern 1210 disposed in each of the first to third pixel circuits PC1, PC2, and PC3, and may be integrally provided in the first to third pixel circuits PC1, PC2, and PC3.

[0141] The third conductive pattern 1310 may overlap the first conductive pattern 1210 to form a storage capacitor Cst (see FIG. 10). That is, the third conductive pattern 1310 also serves as one electrode of the storage capacitor Cst shown in FIG. 10. For example, the third conductive pattern 1310 also serves as an upper electrode of the storage capacitor Cst.

[0142] The third conductive pattern 1310 may have a closed opening 1310OP. The first conductive pattern 1210 may be electrically connected to a first connecting electrode 1630 (see FIG. 20) described below through the opening 1310OP of the third conductive pattern 1310.

[0143] The fourth conductive pattern 1320 and the fifth conductive pattern 1330 may each have an isolated shape, and may be disposed for each pixel circuit.

[0144] The fourth conductive pattern 1320 may be electrically connected to a compensation scan line GCL (see FIG. 19) described below. A compensation scan signal GC may be transmitted to the fourth conductive pattern 1320 through the compensation scan line GCL. The portion where the fourth conductive pattern 1320 overlaps with the third semiconductor pattern 1410 also serves as a lower gate electrode of the compensation transistor T3.

[0145] The fifth conductive pattern 1330 may be electrically connected to a first initialization control line GIL (see FIG. 19), which will be described later. A first initialization control signal GI may be transmitted to the fifth conductive pattern 1330 through the first initialization control line GIL. The portion of the fifth conductive pattern 1330 overlapping with the third semiconductor pattern 1410 also serves as a lower gate electrode of the first initialization transistor T4.

[0146] The second conductive layer 1300 may include a metal, an alloy, or a conductive metal oxide. For example, the second conductive layer 1300 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second conductive layer 1300 may be a single layer or multiple layers.

[0147] The second semiconductor layer 1400 may be disposed on the second conductive layer 1300. The second semiconductor layer 1400 may include a third semiconductor pattern 1410. The third semiconductor pattern 1410 may be disposed for each pixel. For example, one third semiconductor pattern 1410 may be disposed for each pixel circuit. A compensation transistor T3 and a first initialization transistor T4 may be located in the third semiconductor pattern 1410.

[0148] The second semiconductor layer 1400 may include an oxide semiconductor material. For example, the second semiconductor layer 1400 may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the second semiconductor layer 1400 may be an ITZO (InSnZnO) semiconductor layer or an IGZO (InGaZnO) semiconductor layer. Oxide semiconductors have a wide band gap (approximately 3.1 eV), high carrier mobility, and low leakage current. Therefore, they have the advantages of not causing a large voltage drop even with long operating times and not causing a large change in brightness due to the voltage drop even when operating at low frequencies. The second semiconductor layer 1400 may include a channel region overlapping the gate electrode, and a source region and a drain region disposed on both sides of the channel region.

[0149] The third conductive layer 1500 may be disposed on the second semiconductor layer 1400. The third conductive layer 1500 may include a sixth conductive pattern 1510, a seventh conductive pattern 1520, a repair line RL, and a 2-1 initialization voltage line VL2-1. That is, the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1 initialization voltage line VL2-1 may be disposed in the same layer. The third conductive layer 1500 may be referred to as a third gate layer.

[0150] The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may each have an isolated shape. The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may each be disposed for each pixel circuit. The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may each overlap the second semiconductor layer 1400 to serve as a gate electrode of a transistor.

[0151] The portion of the sixth conductive pattern 1510 overlapping with the third semiconductor pattern 1410 also serves as the gate electrode of the compensation transistor T3. For example, the portion of the sixth conductive pattern 1510 overlapping with the third semiconductor pattern 1410 also serves as the upper gate electrode of the compensation transistor T3. The sixth conductive pattern 1510 is electrically connected to a compensation scan line GCL (see FIG. 19) described below and may receive a compensation scan signal GC.

[0152] The overlapping portion of the seventh conductive pattern 1520 with the third semiconductor pattern 1410 also serves as the gate electrode of the first initialization transistor T4. For example, the overlapping portion of the seventh conductive pattern 1520 with the third semiconductor pattern 1410 also serves as the upper gate electrode of the first initialization transistor T4. The seventh conductive pattern 1520 is electrically connected to a first initialization control line GIL (see FIG. 19) described below and may receive a first initialization control signal GI.

[0153] The repair line RL may extend in the x-direction. The repair line RL may be connected to a dummy pixel circuit (not shown) and connected to a light-emitting element of a defective pixel circuit among the pixel circuits PC. For example, if the first pixel circuit PC1 is a defective pixel circuit, a laser may be irradiated onto an area where the repair line RL and the first pixel connecting electrode 1620 of the first pixel circuit PC1 overlap, thereby connecting the repair line RL to the first pixel connecting electrode 1620 of the first pixel circuit PC1.

[0154] The 2-1st initialization voltage line VL2-1 may extend in a first direction (eg, the x-direction) and may transmit a 2-1st initialization voltage Vaint1 to the first pixel P1.

[0155] The third conductive layer 1500 may include a metal, an alloy, or a conductive metal oxide. For example, the third conductive layer 1500 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The third conductive layer 1500 may be a single layer or multiple layers.

[0156] Figure 19 illustrates a fourth conductive layer 1600 on the third conductive layer 1500. Figure 20 illustrates a fifth conductive layer 1700 on the fourth conductive layer 1600. A first planarization layer 108 (see Figure 22) may be disposed between the third conductive layer 1500 and the fourth conductive layer 1600. A second planarization layer 109 (see Figure 22) may be disposed between the fourth conductive layer 1600 and the fifth conductive layer 1700.

[0157] 10 and 19, the fourth conductive layer 1600 may include a second driving voltage line PL2, a first pixel connecting electrode 1620, a first connecting electrode 1630, a second connecting electrode 1640, a third connecting electrode 1650, a fourth connecting electrode 1660, a fifth connecting electrode 1670, a first initialization voltage line VL1, a first initialization control line GIL, a scan line GWL, a compensation scan line GCL, and a bias voltage line VL3. That is, the components included in the fourth conductive layer 1600 may be arranged on the same layer. The fourth conductive layer 1600 may be referred to as a first source / drain layer or a first connecting electrode layer.

[0158] The second driving voltage line PL2 may extend in the x-direction and be electrically connected to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3, respectively, and may transmit a driving voltage ELVDD.

[0159] The second driving voltage line PL2 may be electrically connected to the first driving voltage line PL1 (see FIG. 11) through the first-1 contact hole CNTi. The first-1 contact hole CNTi is also referred to as an internal contact hole CNTi. The second driving voltage line PL2 may be electrically connected to the third conductive pattern 1310 (see FIG. 15) through the first-2 contact hole CNT1b. The second driving voltage line PL2 may be electrically connected to the first semiconductor pattern 1110 (see FIG. 12) through the first-3 contact hole CNT1c. A driving voltage ELVDD may be transmitted to the storage capacitor Cst and the operation control transistor T5 through the second driving voltage line PL2.

[0160] The first pixel connecting electrode 1620 may be disposed apart from the second driving voltage line PL2. The first pixel connecting electrode 1620 may be electrically insulated from the second driving voltage line PL2. The first pixel connecting electrode 1620 may be disposed apart from the second driving voltage line PL2. The first pixel connecting electrode 1620 may be disposed for each pixel circuit.

[0161] The first pixel connecting electrode 1620 may be electrically connected to a pixel electrode of the organic light emitting device and may be electrically connected to the first semiconductor pattern 1110 through a second contact hole CNT2.

[0162] The first linking electrode 1630, the second linking electrode 1640, the third linking electrode 1650, the fourth linking electrode 1660, and the fifth linking electrode 1670 may each have an isolated shape. The first linking electrode 1630, the second linking electrode 1640, the third linking electrode 1650, the fourth linking electrode 1660, and the fifth linking electrode 1670 may each be disposed for each pixel circuit.

[0163] The first connecting electrode 1630 may electrically connect the first conductive pattern 1210 and the third semiconductor pattern 1410. The first connecting electrode 1630 may be electrically connected to the first conductive pattern 1210 through a 3-1 contact hole CNT3a. The first connecting electrode 1630 may be electrically connected to the third semiconductor pattern 1410 through a 3-2 contact hole CNT3b. The first connecting electrode 1630 may electrically connect the driving transistor T1 and the compensation transistor T3. The first connecting electrode 1630 may electrically connect the storage capacitor Cst and the compensation transistor T3.

[0164] The second connecting electrode 1640 may electrically connect the first semiconductor pattern 1110 and the third semiconductor pattern 1410. The second connecting electrode 1640 may be electrically connected to the first semiconductor pattern 1110 through a 4-1 contact hole CNT4a. The second connecting electrode 1640 may be electrically connected to the third semiconductor pattern 1410 through a 4-2 contact hole CNT4b. The second connecting electrode 1640 may electrically connect the driving transistor T1 and the compensation transistor T3. The second connecting electrode 1640 may electrically connect the emission control transistor T6 and the compensation transistor T3.

[0165] The third connecting electrode 1650 may be electrically connected to the first semiconductor pattern 1110 (see FIG. 12) through a fifth contact hole CNT5. For example, in the first pixel circuit PC1, the third connecting electrode 1650 may be electrically connected to a first data line DL1 (described below). That is, in the first pixel circuit PC1, the third connecting electrode 1650 may transfer a data signal Dm applied through the first data line DL1 to the first semiconductor pattern 1110.

[0166] The fourth connecting electrode 1660 may electrically connect the first semiconductor pattern 1110 and the second semiconductor pattern 1120. The fourth connecting electrode 1660 may be electrically connected to the first semiconductor pattern 1110 through a 6-1 contact hole CNT6a. The fourth connecting electrode 1660 may be electrically connected to the second semiconductor pattern 1120 through a 6-2 contact hole CNT6b. The fourth connecting electrode 1660 may electrically connect the bias transistor T8 and the operation control transistor T5.

[0167] In the first pixel circuit PC1, the fifth connecting electrode 1670 may electrically connect the first semiconductor pattern 1110 and the 2-1 initialization voltage line VL2-1. In the second pixel circuit PC2 and the third pixel circuit PC3, the fifth connecting electrode 1670 may electrically connect the first semiconductor pattern 1110 and the 2-2 initialization voltage line VL2-2.

[0168] In the first pixel circuit PC1, the fifth connecting electrode 1670 may be electrically connected to the first semiconductor pattern 1110 through a 7-1 contact hole CNT7a and may be electrically connected to a 2-1 initialization voltage line VL2-1 through a 7-2 contact hole CNT7b. A 2-1 initialization voltage Vaint1 may be transmitted to the first semiconductor pattern 1110 of the first pixel circuit PC1 via a fourth connecting electrode 1660. The fourth connecting electrode 1660 may transmit the 2-1 initialization voltage Vaint1 to the second initialization transistor T7 of the first pixel circuit PC1.

[0169] In each of the second pixel circuit PC2 and the third pixel circuit PC3, the fifth connecting electrode 1670 may be electrically connected to the first semiconductor pattern 1110 through a 7-1 contact hole CNT7a and may be electrically connected to the 2-2 initialization voltage line VL2-2 through a 7-2 contact hole CNT7b. In each of the second pixel P2 and the third pixel P3, the 2-2 initialization voltage Vaint2 may be transmitted to the first semiconductor pattern 1110 via the fourth connecting electrode 1660. The fifth connecting electrode 1670 may transmit the 2-2 initialization voltage Vaint2 to the second initialization transistor T7 of the second pixel circuit PC2 and the third pixel circuit PC3.

[0170] The first initialization control line GIL, the compensation scan line GCL, the bias voltage line VL3, and the first initialization voltage line VL1 may extend in the x direction.

[0171] The first initialization control line GIL may transmit a first initialization control signal GI. The first initialization control line GIL may electrically connect the fifth conductive pattern 1330 and the seventh conductive pattern 1520. The first initialization control line GIL may be electrically connected to the fifth conductive pattern 1330 through an 8-1 contact hole CNT8a. The first initialization control line GIL may be electrically connected to the seventh conductive pattern 1520 through an 8-2 contact hole CNT8b. That is, the first initialization control signal GI may be transmitted to each of the fifth conductive pattern 1330 and the seventh conductive pattern 1520.

[0172] The scan line GWL may transmit a scan signal GW to each pixel. The scan line GWL may be electrically connected to the second conductive pattern 1220 through a ninth contact hole CNT9. That is, the scan signal GW may be transmitted to the second conductive pattern 1220. The scan line GWL may transmit a scan signal G2 to the gate electrode of the switching transistor T2.

[0173] The compensation scan line GCL may transmit a compensation scan signal GC to each pixel. The compensation scan line GCL may electrically connect the fourth conductive pattern 1320 and the sixth conductive pattern 1510. The compensation scan line GCL may be electrically connected to the fourth conductive pattern 1320 through a 10-1 contact hole CNT10a. The compensation scan line GCL may be electrically connected to the sixth conductive pattern 1510 through a 10-2 contact hole CNT10b. That is, the compensation scan signal GC may be transmitted to each of the fourth conductive pattern 1320 and the sixth conductive pattern 1510.

[0174] A bias voltage Vobs may be applied to the bias voltage line VL3. The bias voltage line VL3 may be electrically connected to the second semiconductor pattern 1120 through the eleventh contact hole CNT11. That is, the bias voltage Vobs may be transmitted to the second semiconductor pattern 1120.

[0175] A first initialization voltage Vint may be applied to the first initialization voltage line VL1. The first initialization voltage line VL1 may be electrically connected to the third semiconductor pattern 1410 through the twelfth contact hole CNT12. That is, the first initialization voltage Vint may be applied to the third semiconductor pattern 1410.

[0176] The fourth conductive layer 1600 may include a metal, an alloy, a conductive metal oxide, or the like. For example, the fourth conductive layer 1600 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), or the like. Such a fourth conductive layer 1600 may be composed of a single layer or multiple layers.

[0177] 10 and 20, the fifth conductive layer 1700 may be disposed on the fourth conductive layer 1600. The fifth conductive layer 1700 may include a second pixel connecting electrode 1710, a driving voltage line PL, a first data line DL1, a second data line DL2, and a third data line DL3. That is, the second pixel connecting electrode 1710, the driving voltage lines PL (PL1 to PL3), the first data line DL1, the second data line DL2, and the third data line DL3 may be disposed on the same layer. The fifth conductive layer 1700 may be referred to as a second source / drain layer or a second connecting electrode layer. The second pixel connecting electrode 1710 may be disposed for each pixel circuit. At least a portion of the second pixel connecting electrode 1710 may overlap the first pixel connecting electrode 1620.

[0178] The second pixel connecting electrode 1710 may be electrically connected to an organic light emitting element driven by each pixel circuit and may be electrically connected to the first pixel connecting electrode 1620 through a thirteenth contact hole CNT13.

[0179] The third driving voltage line PL3 may apply a driving voltage ELVDD to each pixel circuit, may extend in the y direction, and may be electrically connected to the second driving voltage line PL2 through an internal via hole VHi.

[0180] The first, second, and third data lines DL1, DL2, and DL3 may be electrically connected to the first, second, and third pixel circuits PC1, PC2, and PC3, respectively. The first, second, and third data lines DL1, DL2, and DL3 may transmit a data signal Dm to the first, second, and third pixel circuits PC1, PC2, and PC3, respectively. The first, second, and third data lines DL1, DL2, and DL3 may extend in the y direction.

[0181] The first data line DL1 extends in the y direction and may be curved at least partially. This arrangement is also intended to minimize interference between other components. Therefore, the shape of the first data line DL1 may be different from the shapes of the second data line DL2 and the third data line DL3. The length of the first data line DL1 may be longer than the lengths of the second data line DL2 and the third data line DL3.

[0182] In the first pixel circuit PC1, the first data line DL1 may be electrically connected to the third connecting electrode 1650 through the fifteenth contact hole CNT15. ​​Similarly, in the second pixel circuit PC2, the second data line DL2 may be electrically connected to the third connecting electrode 1650 of the second pixel circuit PC2, and in the third pixel circuit PC3, the third data line DL3 may be electrically connected to the third connecting electrode 1650 of the third pixel circuit PC3. Since the third connecting electrode 1650 is electrically connected to the first semiconductor pattern 1110 (see FIG. 12), a data signal Dm applied to the first data line DL1 may be transmitted to the first semiconductor pattern 1110. The third connecting electrode 1650 may transmit the data signal Dm to the switching transistor T2.

[0183] An additional wiring WL may be further provided between the second pixel circuit PC2 and the third pixel circuit PC3, extending in the y-direction. The additional wiring WL may function as a wiring having a different role for each unit pixel area PU. For example, the additional wiring WL may function as a first initialization voltage line transmitting a first initialization voltage Vint, a second initialization voltage line transmitting a second initialization voltage Vaint, or a common voltage line transmitting a common voltage ELVSS.

[0184] The fifth conductive layer 1700 may include a metal, an alloy, a conductive metal oxide, or the like. For example, the fifth conductive layer 1700 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The fourth conductive layer 1600 may be a single layer or multiple layers.

[0185] 21 is a plan view illustrating a portion of the configuration of a display device according to an embodiment of the present invention, specifically illustrating a first driving voltage line PL1, a second driving voltage line PL2, and a third driving voltage line PL3 superimposed on each other.

[0186] 21, the first driving voltage line PL1 may be arranged in a mesh structure extending in the x and y directions. The second driving voltage line PL2 may extend in the x direction and overlap with the portion of the first driving voltage line PL1 extending in the x direction. The third driving voltage line PL3 may extend in the y direction and overlap with the portion of the first driving voltage line PL1 extending in the y direction.

[0187] The first driving voltage line PL1 and the second driving voltage line PL2 may be connected via an internal contact hole CNTi. At least one internal contact hole CNTi may be arranged for each unit pixel region PU. For example, as shown in FIG. 21, two internal contact holes CNTi may be arranged corresponding to the first pixel circuit PC1 and the third pixel circuit PC3 in the unit pixel region PU. However, this is not limiting. Various modifications are possible, such as an internal contact hole CNTi arranged corresponding to only the first pixel circuit PC1 in the unit pixel region PU, or three internal contact holes CNTi arranged corresponding to the first, second, and third pixel circuits PC1, PC2, and PC3.

[0188] The second driving voltage line PL2 and the third driving voltage line PL3 may be connected via an internal via hole VHi. At least one internal via hole VHi may be arranged for each unit pixel region PU. For example, as shown in FIG. 21, two internal via holes VHi may be arranged corresponding to the second pixel circuit PC2 and the third pixel circuit PC3 in the unit pixel region PU. However, this is not limiting. Various modifications are possible, such as an internal via hole VHi arranged corresponding to only the first pixel circuit PC1 in the unit pixel region PU, or three internal via holes VHi arranged corresponding to the first, second, and third pixel circuits PC1, PC2, and PC3.

[0189] Meanwhile, when both the internal contact hole CNTi and the internal via hole VHi are disposed in one pixel circuit, the internal contact hole CNTi and the internal via hole VHi may be disposed apart from each other in a plan view, in order to minimize process defects when forming the internal via hole VHi and the third driving voltage line PL3.

[0190] FIG. 22 is a cross-sectional view schematically illustrating a cross section of a display device according to one embodiment of the present invention.

[0191] 22, the display device may include a substrate 100, at least one thin film transistor TFT1, TFT2 disposed on the substrate 100, a driving voltage line PL, an organic light emitting element OLED, and a thin film encapsulation layer 300.

[0192] The substrate 100 may be made of glass or a polymer resin and may be formed into multiple layers. For example, the substrate 100 may include a base layer made of a polymer resin and an inorganic layer.

[0193] A buffer layer 101 may be disposed on the substrate 100. The buffer layer 101 may prevent metal atoms, impurities, etc. from diffusing from the substrate 100 into the semiconductor layer located thereon. The buffer layer 101 may be formed of silicon oxide (SiO2), silicon nitride (SiN X ), and / or silicon oxynitride (SiON), or a single or multilayer.

[0194] The first driving voltage line PL1 may be disposed on the buffer layer 101. The first driving voltage line PL1 may be disposed overlapping at least one thin film transistor TFT1, TFT2. In the drawings, the first driving voltage line PL1 is illustrated overlapping the first thin film transistor TFT1, but is not limited thereto. The first driving voltage line PL1 may be variously modified, such as overlapping with the second thin film transistor TFT2.

[0195] A first interlayer insulating layer 102 may be disposed on the first driving voltage line PL1. The first interlayer insulating layer 102 may cover the first driving voltage line PL1 and may be disposed on the buffer layer 101. The first interlayer insulating layer 102 may include an insulating material. For example, the first interlayer insulating layer 102 may be made of silicon oxide (SiO2), silicon nitride (SiN x ), and / or inorganic insulating materials such as silicon oxynitride (SiON).

[0196] The first thin film transistor TFT1 may be disposed on the first interlayer insulating layer 102. The first thin film transistor TFT1 may include a first active layer Act1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. The first thin film transistor TFT1 may be electrically connected to the organic light emitting element OLED. In one embodiment, the first thin film transistor TFT1 also serves as an emission control transistor.

[0197] The first active layer Act1 of the first thin film transistor TFT1 may be disposed on the first interlayer insulating layer 102. In one embodiment, the first active layer Act1 of the first thin film transistor TFT1 may correspond to the first semiconductor pattern 1110 of the first semiconductor layer 1100. The first active layer Act1 of the first thin film transistor TFT1 may include a silicon semiconductor material. For example, the first active layer Act1 may include amorphous silicon or polysilicon. For example, the first active layer Act1 may include polysilicon crystallized at a low temperature. The first active layer Act1 may include a channel region overlapping the first gate electrode GE1 and source and drain regions disposed on either side of the channel region.

[0198] A first gate insulating layer 103 may be disposed on the first active layer Act1. The first gate insulating layer 103 may cover the first active layer Act1 and be disposed on the first interlayer insulating layer 102. The first gate insulating layer 103 may include an insulating material. For example, the first gate insulating layer 103 may be made of silicon oxide (SiO2), silicon nitride (SiN x ), and / or inorganic insulating materials such as silicon oxynitride (SiON).

[0199] The first gate electrode GE1 of the first thin film transistor TFT1 may be disposed on the first gate insulating layer 103. The first gate electrode GE1 is covered by the second gate insulating layer 104. The second gate insulating layer 104 may include an insulating material. For example, the second gate insulating layer 104 may be made of silicon oxide (SiO2), silicon nitride (SiN x ), and / or inorganic insulating materials such as silicon oxynitride (SiON).

[0200] The second thin film transistor TFT2 may be disposed on the second gate insulating layer 104. The second thin film transistor TFT2 may include a second active layer Act2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2. In one embodiment, the second thin film transistor TFT2 also serves as a compensation transistor or a first initialization transistor.

[0201] The fourth conductive pattern 1320 may be disposed on the second gate insulating layer 104. The fourth conductive pattern 1320 may function as a lower gate electrode of the second thin film transistor TFT2.

[0202] The second interlayer insulating layer 105 may cover the fourth conductive pattern 1320 and may be disposed on the second gate insulating layer 104. The second interlayer insulating layer 105 may include an insulating material. For example, the second interlayer insulating layer 105 may be made of silicon oxide (SiO2), silicon nitride (SiN x ), and / or inorganic insulating materials such as silicon oxynitride (SiON).

[0203] A second active layer Act2 of the second thin film transistor TFT2 may be disposed on the second interlayer insulating layer 105. The second active layer Act2 of the second thin film transistor TFT2 may include an oxide semiconductor material. For example, the second active layer Act2 may include an oxide of at least one material selected from the group including indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0204] The third gate insulating layer 106 may cover the second semiconductor layer 1400 (see FIG. 14) and may be disposed on the second interlayer insulating layer 105. The third gate insulating layer 106 may include an insulating material. For example, the third gate insulating layer 106 may be made of silicon oxide (SiO), silicon nitride (SiN), or the like. x ), and / or inorganic insulating materials such as silicon oxynitride (SiON).

[0205] The second gate electrode GE2 of the second thin film transistor TFT2 may be disposed on the third gate insulating layer 106. The third interlayer insulating layer 107 may cover the second gate electrode GE2 and be disposed on the third gate insulating layer 106. The third interlayer insulating layer 107 may include an insulating material. For example, the third interlayer insulating layer 107 may be made of silicon oxide (SiO2), silicon nitride (SiN x ), and / or inorganic insulating materials such as silicon oxynitride (SiON).

[0206] 22 shows the top surfaces of the first interlayer insulating layer 102, the first gate insulating layer 103, the second gate insulating layer 104, the second interlayer insulating layer 105, the third gate insulating layer 106, and the third interlayer insulating layer 107 as flat, but the present invention is not limited thereto. For example, the first interlayer insulating layer 102, the first gate insulating layer 103, the second gate insulating layer 104, the second interlayer insulating layer 105, the third gate insulating layer 106, and the third interlayer insulating layer 107 may each be an inorganic insulating layer containing an inorganic material and disposed with a substantially uniform thickness along the profile of the component. In other words, the insulating layer is disposed on the component with a uniform thickness along the profile of the component, thereby allowing the insulating layer to have a step along the profile of the component.

[0207] The first source electrode SE1 and the first drain electrode DE1 of the first thin film transistor TFT1 may be disposed on the third interlayer insulating layer 107. In one embodiment, the first drain electrode DE1 of the first thin film transistor TFT1 may correspond to the first pixel connecting electrode 1620. The second source electrode SE2 and the second drain electrode DE2 of the second thin film transistor TFT2 may be disposed on the third interlayer insulating layer 107.

[0208] The second driving voltage line PL2 may be disposed on the third interlayer insulating layer 107. The second driving voltage line PL2 may be disposed in the same layer as the first source / drain electrodes SE1, DE1 of the first thin film transistor TFT1, the second source / drain electrodes SE2, DE2 of the second thin film transistor TFT2, and the first pixel connecting electrode 1620.

[0209] The second driving voltage line PL2 may be connected to the first driving voltage line PL1 through an internal contact hole CNTi, which may be formed by overlapping through holes of a plurality of insulating layers.

[0210] Meanwhile, the first interlayer insulating layer 102, the first gate insulating layer 103, the second gate insulating layer 104, and the second interlayer insulating layer 105 may be commonly referred to as a first insulating layer IL1, and the third gate insulating layer 106 and the third interlayer insulating layer 107 may be commonly referred to as a second insulating layer IL2. The internal contact hole CNTi may be formed by overlapping a through hole of the first insulating layer IL1 and a through hole of the second insulating layer IL2.

[0211] The through-holes in the first insulating layer IL1 may be formed simultaneously with the through-holes for connecting the source electrode and first drain electrode DE1 of the first thin film transistor TFT1 to the first active layer Act1. The through-holes in the second insulating layer IL2 may be formed simultaneously with the through-holes for connecting the second source electrode SE2 and second drain electrode DE2 of the second thin film transistor TFT2 to the second active layer Act2. The inner contact hole CNTi may have a step-like step on its sidewall. However, this is not limitative. The inner contact hole CNTi may have no step on its sidewall.

[0212] The first planarization layer 108 covers the second driving voltage line PL2, the first source / drain electrodes SE1, DE1 of the first thin film transistor TFT1, the second source / drain electrodes SE2, DE2 of the second thin film transistor TFT2, and the first pixel connecting electrode 1620, and may be disposed on the third interlayer insulating layer 107.

[0213] The first planarization layer 108 may provide a flat upper surface. The first planarization layer 108 may include an organic insulating material. For example, the first planarization layer 108 may include photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), polymethyl methacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a mixture thereof. The first planarization layer 108 is also referred to as a third insulating layer IL3.

[0214] The third driving voltage line PL3 and the second pixel connecting electrode 1710 may be disposed on the first planarization layer 108. The second pixel connecting electrode 1710 may be electrically connected to the first pixel connecting electrode 1620 and may electrically connect the first thin film transistor TFT1 to the organic light emitting element OLED.

[0215] The third driving voltage line PL3 may be connected to the second driving voltage line PL2 through an internal via hole VHi defined in the first planarization layer 108. The third driving voltage line PL3 is electrically connected to the second driving voltage line PL2 and may transmit a driving voltage ELVDD to the pixel circuit together with the second driving voltage line PL2 and the first driving voltage line PL1. The internal via hole VHi may be disposed apart from the internal contact hole CNTi so as not to overlap with it, in order to reduce process defects.

[0216] The second planarization layer 109 may cover the third driving voltage line PL3 and the second pixel connecting electrode 1710 and may be disposed on the first planarization layer 108. The second planarization layer 109 may provide a flat upper surface.

[0217] The second planarization layer 109 may include an organic insulating material, such as photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), polymethyl methacrylate (PMMA), polystyrene, a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a mixture thereof.

[0218] An organic light emitting element OLED may be located on the second planarization layer 109. The organic light emitting element OLED may include a pixel electrode PE, an emission layer EL, and a counter electrode CE.

[0219] A pixel defining layer 110 may be disposed on the second planarization layer 109. The pixel defining layer 110 increases the distance between the edge of the pixel electrode PE and the counter electrode CE on the pixel electrode PE, thereby preventing arcing or the like from occurring at the edge of the pixel electrode PE. The pixel defining layer 110 may be made of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin, and may be formed by a method such as spin coating.

[0220] A separator SPR may be defined in the pixel defining layer 110. The separator SPR may be a recess of a predetermined depth formed by removing a portion or the entirety of the pixel defining layer 110. In one embodiment, the separator SPR may be formed by etching a portion of the pixel defining layer 110 after the counter electrode CE is formed. In this case, a portion of the counter electrode CE disposed on the pixel defining layer PDL may also be removed, and the counter electrode CE may include a hole corresponding to the separator SPR. The cross section of the separator SPR may have a U-shape, a triangle, a square, a trapezoid, a polygon, or the like. In the drawings, the separator SPR is shown tapered in a direction upward (z-direction), but the present invention is not limited thereto. The separator SPR may also be tapered in a direction downward (z-direction). The separator SPR may be a hole penetrating the pixel defining layer 110 or a groove that does not penetrate the pixel defining layer 110. Alternatively, the separator SPR may be provided as a hole or groove penetrating the pixel defining layer 110 and the second planarization layer 109 thereunder.

[0221] At least a portion of the light-emitting layer EL of the organic light-emitting element OLED may be located within the opening OP formed by the pixel defining layer 110. The light-emitting layer EL may include an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light-emitting layer EL may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be optionally disposed below and above the light-emitting layer.

[0222] In one embodiment, the organic light emitting device OLED is also a tandem light emitting device. The tandem light emitting device may include two or more light emitting units between a pixel electrode PE and a counter electrode CE, and a charge generation layer (CGL) disposed between the two light emitting units. The organic light emitting device OLED has a stacked structure of multiple light emitting units, which may improve color purity and luminous efficiency. The charge generation layer may be separated by a separator SPR, which prevents leakage current from the charge generation layer.

[0223] The counter electrode CE may be a translucent electrode or a reflective electrode. For example, the counter electrode CE may be a transparent or semi-transparent electrode and may include a metal thin film with a low work function, such as Li, Ca, LiF, Al, Ag, Mg, or a compound thereof. The counter electrode CE may further include a TCO (transparent conductive oxide) film, such as ITO, IZO, ZnO, or In2O3, disposed on the metal thin film. The counter electrode CE may be integrally formed over the entire display area and disposed on the light-emitting layer EL and the pixel defining film 110.

[0224] The thin film encapsulation layer 300 may be disposed on the organic light-emitting element OLED to seal the organic light-emitting element OLED. The thin film encapsulation layer 300 may include at least one inorganic film layer and at least one organic film layer. For example, the thin film encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330, which are stacked in sequence.

[0225] The first inorganic sealing layer 310 and the second inorganic sealing layer 330 are made of silicon oxide (SiO2), silicon nitride (SiN X The first inorganic sealing layer 310 and the second inorganic sealing layer 330 may have a single layer or multi-layer structure including the inorganic insulating material.

[0226] The organic encapsulating layer 320 can relieve internal stress in the first inorganic encapsulating layer 310 and / or the second inorganic encapsulating layer 330. The organic encapsulating layer 320 can include a polymer-based material, such as polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof.

[0227] The organic encapsulation layer 320 may be formed by applying a flowable material containing a monomer and then reacting the monomer to form a polymer using heat or light such as ultraviolet light, or by applying a polymer material.

[0228] Various components such as a touch screen layer, a color filter layer, a polarizing film layer, and a window may be further disposed on the thin film encapsulation layer 300 .

[0229] Display devices according to embodiments of the present invention may be included in electronic devices. The electronic device according to an embodiment of the present invention is a device for displaying moving or still images, and may be used as a display screen for a variety of products, including portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), as well as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices. The electronic device according to an embodiment may be used in wearable devices such as smart watches, watch phones, eyeglass displays, and head-mounted displays (HMDs). The electronic device according to an embodiment may be used as a center information display (CID) located in an automobile's dashboard, a room mirror display replacing an automobile's side mirrors, or a display located behind the front seats for rear-seat entertainment in an automobile.

[0230] In the above embodiment, the first driving voltage line PL1 is disposed below the second driving voltage line PL2 via an insulating layer, and extends in a mesh pattern in the x and y directions in the display area. The portions of the first driving voltage line PL1 extending in the x direction are connected to the first power supply voltage supply lines 11 disposed on the left and right sides of the display area, and the portions of the first driving voltage line PL1 extending in the y direction are connected to the first power supply voltage supply lines 11 disposed above and below the display area. The second driving voltage line PL2, which is disposed above the first driving voltage line PL1 via an insulating layer, extends in the x-direction in the display area DA and can overlap with the portion of the first driving voltage line PL1 that extends in the x-direction. The third drive voltage line PL3, which is disposed above the second drive voltage line PL2 via an insulating layer, extends in the y direction in the display area DA and can overlap with the portion of the first drive voltage line PL1 extending in the y direction. The first to third power supply voltage supply lines 11 to 13 are arranged in different layers in the peripheral region. The first power supply voltage supply line 11 and the first driving voltage line PL1 may be integrally formed. The first power supply voltage supply line 11 and the second power supply voltage supply line 12 may be connected to each other through at least one external contact hole CNTo. The second power supply voltage supply line 12 and the third power supply voltage supply line 13 may be connected to each other through at least one external via hole VHo. The third power supply voltage supply line 13 and the third driving voltage line PL3 may be integrally formed. As described above, the first power supply voltage supply line 11, the second power supply voltage supply line 12, and the third power supply voltage supply line 13 are electrically connected to each other and may all supply a driving voltage ELVDD. The driving voltage ELVDD may be used as a driving voltage for a pixel circuit as shown in FIG. 4. In this embodiment, the first drive voltage line PL1 is connected to the second drive voltage line PL2 for each unit pixel region via at least one internal contact hole CNTi, which allows the drive voltages supplied to the pixel circuits arranged in the display region DA to be roughly uniform even if the size of the display region DA increases. Furthermore, the third driving voltage line PL3 is connected to the second driving voltage line PL2 for each of the plurality of unit pixel regions through at least one internal via hole VHi, which makes it possible to more uniformly distribute the driving voltages supplied to the plurality of pixel circuits arranged in the display region DA even if the size of the display region DA increases. In the above embodiment, the configurations of the first and second drive voltage lines PL1, PL2 and the associated first and second power supply voltage supply lines 11, 12, etc. may remain the same, while the configurations of the third drive voltage line PL3 and the associated third power supply voltage supply line 13 and internal via hole VHi, etc. may be omitted. In this case, as described above, the first drive voltage line PL1 is connected to the second drive voltage line PL2 for each unit pixel region via at least one internal contact hole CNTi.

[0231] As described above, the present invention has been described based on the embodiments shown in the drawings, but this is merely an example, and those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical spirit of the claims. [Explanation of symbols]

[0232] 10 Display device PX pixels PL1 First drive voltage line PL2 Second drive voltage line PL3 Third drive voltage line 1100 First semiconductor layer 1200 First conductive layer 1300 Second conductive layer 1400 Second semiconductor layer 1500 Third conductive layer 1600 4th conductive layer 1700 5th conductive layer 2000 pixel electrode layer 1620 First pixel connecting electrode 1710 Second pixel connecting electrode

Claims

1. a substrate including a display area and a peripheral area; a plurality of unit pixel regions arranged in the display region, each of the unit pixel regions including a first pixel circuit, a second pixel circuit, and a third pixel circuit; a power supply voltage supply line disposed in the peripheral region; first driving voltage lines electrically connected to the power supply voltage lines and arranged in a mesh structure in the display area; a second driving voltage line electrically connected to the power supply voltage supply line, disposed in a layer different from the first driving voltage line, and extending in a first direction from the display area; The first driving voltage line is connected to the second driving voltage line for each of the plurality of unit pixel regions through at least one internal contact hole.

2. The display device according to claim 1 , wherein a step-like difference is provided on a side surface of the inner contact hole.

3. The semiconductor device further includes a first insulating layer and a second insulating layer stacked between the first driving voltage line and the second driving voltage line, 2. The display device of claim 1, wherein the internal contact hole is formed by overlapping a first through hole of the first insulating layer and a second through hole of the second insulating layer, and the width of the first through hole is different from the width of the second through hole.

4. the first driving voltage line includes a portion extending in the first direction and a portion extending in a second direction intersecting the first direction; The display device of claim 1 , wherein the second driving voltage line overlaps with a portion of the first driving voltage line extending in the first direction.

5. a third driving voltage line electrically connected to the power supply voltage line and disposed in a layer different from the first driving voltage line and the second driving voltage line; the third driving voltage line extends in a second direction intersecting the first direction in the display area; The display device of claim 1 , wherein the third driving voltage line is connected to the second driving voltage line for each of the plurality of unit pixel regions through at least one internal via hole.

6. further including a third insulating layer disposed between the second driving voltage line and the third driving voltage line; The display device of claim 5 , wherein the internal via hole is defined in the third insulating layer and does not overlap the internal contact hole.

7. the first driving voltage line includes a portion extending in the first direction and a portion extending in a second direction intersecting the first direction; The display device of claim 5 , wherein the third driving voltage line overlaps with a portion of the first driving voltage line extending in the second direction.

8. the power supply voltage supply lines are arranged in the peripheral region and include a first power supply voltage supply line provided in the same layer as the first driving voltage line, a second power supply voltage supply line provided in the same layer as the second driving voltage line, and a third power supply voltage supply line arranged in a layer different from the first power supply voltage supply line and the second power supply voltage supply line; The display device according to claim 1 , wherein the first power supply voltage supply line is arranged so as to surround the display area.

9. The display device according to claim 8 , wherein the second power supply voltage supply line extends along the first direction in the peripheral region.

10. The display device of claim 8 , wherein the first power supply line and the second power supply line are connected to each other through a plurality of external contact holes in the peripheral region.

11. The display device according to claim 10 , wherein a step-like difference is provided on a side surface of the external contact hole.

12. 11. The display device of claim 10, wherein the third power supply voltage supply line is connected to the second power supply voltage supply line through a plurality of external via holes, and at least one of the plurality of external via holes at least partially overlaps with the plurality of external contact holes.

13. The display device according to claim 8 , wherein the first power supply voltage supply line is provided integrally with the first driving voltage line.

14. the first pixel circuit includes a first thin film transistor including a silicon semiconductor layer and a second thin film transistor including an oxide semiconductor layer; The display device of claim 1 , wherein the first driving voltage line overlaps at least one of the first thin film transistor and the second thin film transistor.

15. a substrate including a display area and a peripheral area; a first thin film transistor disposed in the display area and including a first semiconductor layer; and a pixel circuit including a second thin film transistor having a second semiconductor layer disposed in a layer different from the first semiconductor layer; a display element coupled to the pixel circuit; a first driving voltage line disposed between the substrate and the first semiconductor layer; a first insulating layer covering the first semiconductor layer and disposed below the second semiconductor layer; a second insulating layer disposed on the first insulating layer and covering the second semiconductor layer; a second driving voltage line disposed on the second insulating layer; a third insulating layer disposed on the second insulating layer and covering the second driving voltage line; a third driving voltage line disposed on the third insulating layer; The second driving voltage line is connected to the first driving voltage line through an internal contact hole in the display area.

16. The display device of claim 15 , wherein the internal contact hole is formed by overlapping the first through hole of the first insulating layer and the second through hole of the second insulating layer.

17. The display device of claim 16 , wherein a width of the first through-hole is different from a width of the second through-hole.

18. 16. The display device of claim 15, wherein the third driving voltage line is connected to the second driving voltage line through an internal via hole defined in the third insulating layer in the display region.

19. The display device of claim 15, wherein the first driving voltage line overlaps at least one of the first thin film transistor and the second thin film transistor.

20. 16. The display device according to claim 15, wherein the display elements are organic light-emitting elements in a tandem structure, and a pixel defining film defining a light-emitting region of the organic light-emitting element is disposed between the organic light-emitting elements and includes a separator having a concave structure.

21. In an electronic device including a display device, The display device includes: a substrate including a display area and a peripheral area; a plurality of unit pixel regions arranged in the display region, each of the unit pixel regions including a first pixel circuit, a second pixel circuit, and a third pixel circuit; a power supply voltage supply line disposed in the peripheral region; first driving voltage lines electrically connected to the power supply voltage lines and arranged in a mesh structure in the display area; a second driving voltage line electrically connected to the power supply voltage supply line, disposed in a layer different from the first driving voltage line, and extending in a first direction from the display area; The first driving voltage line is connected to the second driving voltage line for each of the plurality of unit pixel regions through at least one internal contact hole.

22. The electronic device according to claim 21 , wherein a step-like difference is provided on a side surface of the inner contact hole.

23. The semiconductor device further includes a first insulating layer and a second insulating layer stacked between the first driving voltage line and the second driving voltage line, 22. The electronic device of claim 21, wherein the internal contact hole is formed by overlapping a first through hole of the first insulating layer and a second through hole of the second insulating layer, and the width of the first through hole is different from the width of the second through hole.

24. a third driving voltage line electrically connected to the power supply voltage line and disposed in a layer different from the first driving voltage line and the second driving voltage line; the third driving voltage line extends in a second direction intersecting the first direction in the display area; The electronic device of claim 21 , wherein the third driving voltage line is connected to the second driving voltage line for each of the plurality of unit pixel regions through at least one internal via hole.

25. further including a third insulating layer disposed between the second driving voltage line and the third driving voltage line; 25. The electronic device of claim 24, wherein the internal via hole is defined in the third insulating layer and does not overlap with the internal contact hole.

26. a first display element, a second display element, and a third display element disposed in the display area and coupled to the first pixel circuit, the second pixel circuit, and the third pixel circuit, respectively; 22. The electronic device of claim 21, wherein the first display element, the second display element, and the third display element are included in an organic light-emitting element in a tandem structure.

27. The electronic device of claim 26 , wherein the pixel defining film that defines the light-emitting region of the organic light-emitting element comprises a separator disposed between the organic light-emitting elements and having a concave structure.

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