Image sensor

Abstract

To provide an image sensor capable of maintaining high-speed operation characteristics.SOLUTION: An image sensor includes a first pixel PX1 sensing a first color, a second pixel PX2 sensing a second color different from the first color, a first active region AR located in the first pixel, and a second active region AR located in the second pixel, and the first active region and the second active region may be directly connected to each other.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to image sensors. [Background technology]

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors can be classified into CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor).

[0003] CIS (CMOS image sensor) has the advantages of lower manufacturing costs, smaller element size, and lower power consumption compared to CCD image sensors that use high-voltage analog circuits, and is therefore mainly used in home appliances, including mobile devices such as smartphones and digital cameras.

[0004] A pixel array that constitutes a CMOS image sensor includes a photoelectric conversion unit such as a photodiode for each pixel. The photoelectric conversion unit generates a variable electrical signal depending on the amount of incident light, and the CMOS image sensor processes the electrical signal to synthesize an image.

[0005] The CMOS image sensor may include a plurality of transistors for driving the photoelectric conversion unit. Summary of the Invention [Problem to be solved by the invention]

[0006] In recent years, the demand for high-resolution images has led to a decrease in pixel size and an increase in the number of pixels in image sensors, which requires high-speed operation characteristics of transistors in image sensors. [Means for solving the problem]

[0007] The embodiment provides an image sensor that can maintain high-speed operating characteristics.

[0008] However, the problems to be solved by the embodiments are not limited to the above problems, and can be variously expanded within the scope of the technical ideas included in the embodiments.

[0009] The image sensor according to the embodiment may include a first pixel sensing a first color, a second pixel sensing a second color different from the first color, a first active region located in the first pixel, and a second active region located in the second pixel, and the first active region and the second active region may be directly connected to each other.

[0010] An image sensor according to an embodiment may include a first pixel group that senses a first color and includes a plurality of pixels including a first pixel, and a second pixel group that senses a second color different from the first color and includes a plurality of pixels including a second pixel adjacent to the first pixel group, wherein the first pixel group and the second pixel group may share a reset transistor, a source follower transistor, and a selection transistor, and the source follower transistor may include a first source follower transistor located in the first pixel and a second source follower transistor located in the second pixel, and the first source follower transistor and the second source follower transistor may be directly connected.

[0011] According to the embodiment, it is possible to provide an image sensor capable of maintaining high-speed operation characteristics.

[0012] However, it is obvious that the effects of the embodiments are not limited to the above-described effects, but can be variously expanded within the scope of the present invention. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram illustrating an image sensor according to an embodiment; [Figure 2] 1 is a plan view illustrating a portion of an image sensor according to an embodiment; [Figure 3] FIG. 1 is a circuit diagram of an image sensor according to an embodiment. [Figure 4] FIG. 1 is a plan view of an image sensor according to an embodiment. [Figure 5] FIG. 5 is a cross-sectional view taken along line II' in FIG. [Figure 6] FIG. 2 is a plan view illustrating a pixel separating structure of an image sensor according to an embodiment. [Figure 7] FIG. 7 is a cross-sectional view taken along line II-II' in FIG. 6. [Figure 8] FIG. 10 is a plan view of an image sensor according to another embodiment. [Figure 9] FIG. 10 is a plan view of an image sensor according to another embodiment. [Figure 10] FIG. 2 is a plan view illustrating a pixel separating structure of an image sensor according to an embodiment. [Figure 11] FIG. 10 is a plan view of an image sensor according to another embodiment. [Figure 12] FIG. 10 is a plan view showing a pixel separating structure of an image sensor according to another embodiment. [Figure 13] FIG. 10 is a plan view of an image sensor according to another embodiment. [Figure 14] FIG. 10 is a plan view showing a pixel separating structure of an image sensor according to another embodiment. [Figure 15] FIG. 10 is a plan view of an image sensor according to another embodiment. [Figure 16] FIG. 10 is a plan view showing a pixel separating structure of an image sensor according to another embodiment. [Figure 17] FIG. 10 is a circuit diagram of an image sensor according to another embodiment. [Figure 18] FIG. 10 is a plan view of an image sensor according to another embodiment. [Figure 19]FIG. 10 is a plan view of an image sensor according to another embodiment. [Figure 20] FIG. 10 is a plan view of an image sensor according to another embodiment. [Figure 21] FIG. 10 is a plan view of an image sensor according to another embodiment. [Figure 22] FIG. 10 is a plan view of an image sensor according to another embodiment. [Figure 23] 10 shows a simplified stack structure of an image sensor according to another embodiment. [Figure 24] 10 shows a simplified stack structure of an image sensor according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0015] In order to clearly explain the present invention, parts not necessary for the explanation will be omitted and the same reference numerals will be used throughout the specification to refer to the same or similar components.

[0016] Furthermore, the attached drawings are intended to facilitate understanding of the embodiments disclosed in this specification, and it should be understood that the attached drawings do not limit the technical ideas disclosed in this specification, and include all modifications, equivalents, and alternatives that fall within the idea and technical scope of the present invention.

[0017] Furthermore, the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation, and the present invention is not necessarily limited to those shown. In the drawings, thicknesses are exaggerated to clearly show some layers and regions. In the drawings, thicknesses of some layers and regions are exaggerated for the convenience of explanation.

[0018] Furthermore, when a layer, film, region, plate, or other part is said to be "on" or "above" another part, this includes not only the case where it is "directly above" that part, but also the case where there are other parts between them. Conversely, when a part is said to be "directly above" another part, it means that there are no other parts between them. Furthermore, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" or "above" the direction opposite to gravity.

[0019] Furthermore, throughout the specification, when a part is said to "comprise" a certain element, this means that it may further include other elements, rather than excluding other elements, unless otherwise specified.

[0020] Also, throughout the specification, "on a plane" means a view of the subject part from above, and "on a cross section" means a view of the subject part cut vertically from the side.

[0021] Furthermore, throughout the specification, when the term "connected" is used, it does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected through other components, or that two or more components are not only physically connected but also electrically connected, or that two or more components are referred to by different names depending on their position or function but are nonetheless one unit.

[0022] Various embodiments and modifications will be described in detail below with reference to the drawings.

[0023] An image sensor according to an embodiment will be briefly described with reference to Fig. 1. Fig. 1 is a block diagram showing an image sensor according to an embodiment.

[0024] Referring to FIG. 1, an image sensor 1000 according to an embodiment may include a pixel array 140 and a logic circuit that controls the pixel array 140.

[0025] The logic circuit is a circuit for controlling the pixel array 140, and may include, for example, a controller 110, a timing generator 120, a row driver 130, a readout circuit 150, a ramp signal generator 160, a data buffer 170, and the like.

[0026] The image sensor 1000 may further include an image signal processor 180, and in another embodiment, the image signal processor 180 may be located outside the image sensor 1000. The image sensor 1000 may convert light received from outside into an electrical signal to generate an image signal. The image signal may be provided to the image signal processor 180.

[0027] The image sensor 1000 may be mounted in an electronic device having an image or light sensing function. For example, the image sensor 1000 may be mounted in an electronic device such as a camera, a smartphone, a wearable device, an Internet of Things (IoT) device, a home appliance, a tablet PC (Personal Computer), a navigation system, a drone, an advanced driver assistance system (ADAS), etc. The image sensor 1000 may also be mounted in an electronic device provided as a component in a vehicle, furniture, manufacturing equipment, a door, various measuring instruments, etc.

[0028] The pixel array 140 may include a plurality of pixels (PX), a plurality of row lines (RL) respectively connected to the plurality of pixels (PX), and a plurality of column lines (CL).

[0029] In one embodiment, each pixel (PX) may include at least one photoelectric converter that can sense incident light and convert the incident light into an electrical signal corresponding to the amount of light, i.e., a plurality of analog pixel signals.

[0030] The photoelectric conversion unit may be a photodiode, a field diode, etc. Furthermore, the photoelectric conversion unit may be a SPAD (Single-Photon Avalanche Diode) applied to a 3D sensor pixel.

[0031] The level of the analog pixel signal output from the photoelectric conversion unit may be proportional to the amount of charge output from the photoelectric conversion unit, i.e., the level of the analog pixel signal output from the photoelectric conversion unit may be determined by the amount of light received at the pixel array 140.

[0032] A plurality of row lines (RL) may be connected to a plurality of pixels (PX). For example, a control signal output from the row driver 130 to a row line (RL) may be transmitted to gates of transistors of a plurality of pixels (PX) connected to the row line (RL). A column line (CL) may be disposed across the row lines (RL) and connected to a plurality of pixels (PX). A plurality of pixel signals output from the plurality of pixels (PX) may be transmitted to the readout circuit 150 through a plurality of column lines (CL).

[0033] The controller 110 may use control signals to control the operation timing of each of the above-mentioned components 120, 130, 150, 160, and 170.

[0034] In one embodiment, the controller 110 can receive a mode signal indicating an imaging mode from the application processor and generally control the image sensor 1000 based on the received mode signal. For example, the application processor can determine the imaging mode of the image sensor 1000 according to various scenarios such as the illuminance of the imaging environment, a user's resolution setting, and a sensed or learned state, and provide the determined result to the controller 110 via a mode signal.

[0035] The controller 110 controls the plurality of pixels (PX) of the pixel array 140 to output pixel signals according to an imaging mode, the pixel array 140 outputs pixel signals for each of the plurality of pixels (PX) or for a portion of the plurality of pixels (PX), and the readout circuit 150 can sample and process the pixel signals transmitted from the pixel array 140.

[0036] The timing generator 120 can generate a signal that serves as a reference for the operation timing of the components of the image sensor 1000. The timing generator 120 can control the timing of the row driver 130, the readout circuit 150, and the ramp signal generator 160. The timing generator 120 can provide control signals that control the timing of the row driver 130, the readout circuit 150, and the ramp signal generator 160.

[0037] The row driver 130 generates control signals for driving the pixel array 140 in response to control signals from the timing generator 120, and can provide control signals to multiple pixels (PX) of the pixel array 140 through multiple row lines (RL).

[0038] In one embodiment, the row driver 130 may control the pixels (PX) in row line units so that they can sense incident light. A row line unit may include at least one row line (RL). For example, the row driver 130 may generate a transmission signal for controlling a transmission transistor, a reset control signal for controlling a reset transistor, a selection control signal for controlling a selection transistor, and the like, and provide these signals to the pixel array 140.

[0039] The readout circuit 150 can convert pixel signals (or electrical signals) from pixels (PX) connected to a row line (RL) selected from a plurality of pixels (PX) into pixel values ​​indicating the amount of light in response to a control signal from the timing generator 120.

[0040] The readout circuit 150 can convert the pixel signal output through the corresponding column line (CL) into a pixel value. For example, the readout circuit 150 can convert the pixel signal into a pixel value by comparing the pixel signal with a ramp signal. The pixel value may be image data having multiple bits. Specifically, the readout circuit 150 may include a selector, multiple comparators, and multiple counter circuits.

[0041] The ramp signal generator 160 can generate a reference signal and transmit it to the readout circuit 150. The ramp signal generator 160 may include a current source, a resistor, and a capacitor. The ramp signal generator 160 can generate a plurality of ramp signals that rise or fall at a slope determined by the magnitude of the current of the variable current source or the resistance value of the variable resistor by adjusting the ramp voltage, which is the voltage applied to the ramp resistor, by adjusting the magnitude of the current of the variable current source or the resistance value of the variable resistor.

[0042] The data buffer 170 stores pixel values ​​of a plurality of pixels (PX) connected to a selected column line (CL) transmitted from the readout circuit 150, and can output the stored pixel values ​​in response to an enable signal from the controller 110.

[0043] The image signal processor 180 may perform image signal processing on the image signal received from the data buffer 170. For example, the image signal processor 180 may receive a plurality of image signals from the data buffer 170 and combine the received image signals to generate one image.

[0044] A pixel arrangement of an image sensor according to an embodiment will be described with reference to Fig. 2. Fig. 2 is a plan view showing a part of an image sensor according to an embodiment.

[0045] Referring to FIG. 2, an image sensor 1000 according to one embodiment may include pixel groups (PG1, PG2, PG3, PG4), photodiodes (PD), color filters (CF), and other circuits necessary for the operation of the image sensor 1000.

[0046] Each of the plurality of pixels (PX) may include one photodiode (PD).

[0047] A plurality of pixels (PX) can be grouped into a plurality of columns and a plurality of rows to form pixel groups (PG1, PG2, PG3, PG4).

[0048] The first pixel group (PG1) overlapping with the first color filter (CF1) can absorb and sense light of a first color, the second pixel group (PG2) overlapping with the second color filter (CF2) and the third pixel group (PG3) overlapping with the second color filter (CF2) can absorb and sense light of a second color different from the first color, and the fourth pixel group (PG4) overlapping with the third color filter (CF3) can absorb and sense light of a third color different from the first and second colors.

[0049] According to another embodiment, the image sensor 1000 may further include a fourth pixel group that absorbs and senses all visible light.

[0050] Each of the pixel groups (PG1, PG2, PG3, PG4) may include N×M pixels (PX) in an N×M array. N and M may each independently be an integer greater than 1. For example, when N and M are each 2, each of the pixel groups (PG1, PG2, PG3, PG4) may have a pixel array with a 2×2 Tetra structure on a plane. That is, each of the pixel groups (PG1, PG2, PG3, PG4) may include pixels (PX) arranged in a 2×2 form on a plane.

[0051] More specifically, a plurality of pixels (PX) arranged along the first direction (DR1) and a plurality of pixels (PX) arranged along the second direction (DR2) may constitute pixel groups (PG1, PG2, PG3, PG4), respectively. However, the embodiment is not limited thereto, and the number of pixels (PX) included in each of the pixel groups (PG1, PG2, PG3, PG4) may be variously changed.

[0052] The image sensor 1000 according to this embodiment may include a first pixel row in which a first pixel group (PG1) corresponding to a first color filter (CF1) and a third pixel group (PG3) corresponding to a second color filter (CF2) are alternately arranged along a first direction (DR1), and a second pixel row in which a second pixel group (PG2) corresponding to a second color filter (CF2) and a fourth pixel group (PG4) corresponding to a third color filter (CF3) are alternately arranged along the first direction (DR1), and the first pixel row and the second pixel row may be alternately arranged along the second direction (DR2).

[0053] The image sensor 1000 according to this embodiment may include a plurality of pixel regions (PG), each including two pixel groups from among a first pixel group (PG1), a second pixel group (PG2), a third pixel group (PG3), and a fourth pixel group (PG4). The two pixel groups included in each pixel region (PG) may be adjacent to each other along the second direction (DR2), but this embodiment is not limited thereto, and the two pixel groups included in each pixel region (PG) may be adjacent to each other along the first direction (DR1).

[0054] The image sensor 1000 according to the embodiment may further include a microlens, and at least one microlens may be located in each of the pixel groups PG1, PG2, PG3, and PG4.

[0055] The image sensor 1000 according to the embodiment may further include a photodiode (PD) located in each of the plurality of pixels (PX).

[0056] One pixel region of an image sensor according to an embodiment will be described with reference to Figures 3 to 7 together with Figure 2. Figure 3 is a circuit diagram of the image sensor according to an embodiment, Figure 4 is a plan view of the image sensor according to an embodiment, Figure 5 is a cross-sectional view taken along line II' of Figure 4, Figure 6 is a plan view showing a pixel separating structure of the image sensor according to an embodiment, and Figure 7 is a cross-sectional view taken along line II-II' of Figure 6.

[0057] 3 together with FIG. 2, the image sensor 1000 according to an embodiment includes a first pixel group (PG1) and a second pixel group (PG2), and the first pixel group (PG1) and the second pixel group (PG2) may include pixels (PX1-PX8), photoelectric conversion units (PD1-PD8), transfer transistors (T1-T8), reset transistors (RX1, RX2), dual conversion transistors (DCX), source follower transistors (S1-S3), and a selection transistor (SE). As described above, the first pixel group (PG1) and the second pixel group (PG2) are illustrated as each including four pixels (PX1-PX4 or PX5-PX8) each including a photoelectric conversion unit (PD1-PD4 or PD5-PD8), but the embodiment is not limited thereto.

[0058] The first pixel (PX1) may include a first photoelectric conversion unit (PD1) and a first transfer transistor (T1), the second pixel (PX2) may include a second photoelectric conversion unit (PD2) and a second transfer transistor (T2), the third pixel (PX3) may include a third photoelectric conversion unit (PD3) and a third transfer transistor (T3), and the fourth pixel (PX4) may include a fourth photoelectric conversion unit (PD4) and a fourth transfer transistor (T4).

[0059] The fifth pixel (PX5) may include a fifth photoelectric conversion unit (PD5) and a fifth transfer transistor (T5), the sixth pixel (PX6) may include a sixth photoelectric conversion unit (PD6) and a sixth transfer transistor (T6), the seventh pixel (PX7) may include a seventh photoelectric conversion unit (PD7) and a seventh transfer transistor (T7), and the eighth pixel (PX8) may include an eighth photoelectric conversion unit (PD8) and an eighth transfer transistor (T8).

[0060] The pixels PX1 to PX4 of the first pixel group PG1 may share a first floating diffusion region FD1.

[0061] The pixels (PX5 to PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0062] The first pixel group (PG1) and the second pixel group (PG2) can share the reset transistors (RX1, RX2), the dual conversion transistor (DCX), the source follower transistors (S1 to S3), and the select transistor (SE). The first floating diffusion region (FD1) or the second floating diffusion region (FD2) can accumulate a charge corresponding to the amount of incident light.

[0063] While the transmission transistors T1 to T4 are turned on by a transmission signal, the first floating diffusion region FD1 or the second floating diffusion region FD2 can receive and store charges from the photoelectric conversion units PD1 to PD4.

[0064] The reset transistors (RX1, RX2) are driven by a reset signal (VRX) to provide a power supply voltage to the first floating diffusion region (FD1) or the second floating diffusion region (FD2). Therefore, charges stored in the first floating diffusion region (FD1) or the extended second floating diffusion region (FD2) can be transferred to the power supply voltage (VPIX) terminal, and the voltage of the first floating diffusion region (FD1) or the second floating diffusion region (FD2) may be reset.

[0065] The source follower transistors S1, S2, and S3 are connected between the power supply voltage VPIX and the selection transistor SE. The source follower transistors S1, S2, and S3 can output an output signal Vout to the selection transistor SE based on the voltage level of the first floating diffusion region FD1 or the second floating diffusion region FD2. The selection transistor SE is driven by a selection signal VSE, and when the selection transistor SE is turned on, the output signal Vout is output to the readout circuit 150 through the column line CL.

[0066] The dual conversion transistor (DCX) may be connected between the first floating diffusion region (FD1), the second floating diffusion region (FD2), and the reset transistors (RX1, RX2). When the dual conversion transistor (DCX) is turned off by the dual conversion signal (VDC), the full well capacity (FWC) of each pixel (PX1 to PX8) may be the capacitance of the first floating diffusion region (FD1) and the second floating diffusion region (FD2). When the dual conversion transistor (DCX) is turned on by the dual conversion signal (VDC), the full well capacity (FWC) of each pixel (PX1 to PX8) increases more than the capacitance of the first floating diffusion region (FD1). The conversion gain of each pixel (PX1 to PX8) is varied by turning on / off the dual conversion transistor (DCX).

[0067] The structures of the first pixel group PG1 and the second pixel group PG2 of the image sensor 1000 according to an embodiment will be described in more detail with reference to FIGS. 4 and 5 in addition to FIGS. 2 and 3.

[0068] As described above, the image sensor 1000 according to an embodiment may include a pixel region PG including a first pixel group PG1 and a second pixel group PG2 that absorb and sense different colors.

[0069] The first pixel group (PG1) may include a first pixel (PX1), a second pixel (PX2), a third pixel (PX3) and a fourth pixel (PX4) arranged along a clockwise direction, and the second pixel group (PG2) may include a fifth pixel (PX5), a sixth pixel (PX6), a seventh pixel (PX7) and an eighth pixel (PX8) arranged along a clockwise direction.

[0070] A pixel separating structure (DTI) may be located between multiple pixels (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8).

[0071] The pixel separating structure (DTI) may be positioned to surround at least a portion of the periphery of the first pixel group (PG1) and the second pixel group (PG2). The pixel separating structure (DTI) may also surround at least a portion of the periphery of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and may also surround at least a portion of the periphery of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2).

[0072] The pixel isolation structure (DTI) can prevent crosstalk between multiple pixels (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8).

[0073] The image sensor 1000 may include a substrate 200. The substrate 200 may include silicon (Si), germanium (Ge), or silicon (Si)-germanium (Ge). The substrate 200 may include gallium arsenide (GaAs), indium (InP), gallium (GaP), indium arsenide (InAs), indium antimony (InSb), or indium gallium arsenide (InGaAs). The substrate 200 may include zinc telluride (ZnTe) or cadmium sulfide (CdS).

[0074] The substrate 200 may be bulk silicon or silicon-on-insulator (SOI). The substrate 200 may be a silicon substrate or may comprise other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 200 may comprise an epitaxial layer formed on a base substrate.

[0075] The substrate 200 may be doped with impurities of a first conductivity type, for example, the first conductivity type may be P-type.

[0076] The substrate 200 may include a first surface (SFA) and a second surface (SFB) that face each other.

[0077] The substrate 200 includes a deep trench (DT) within which a pixel isolation structure (DTI) can be located.

[0078] The pixel isolation structure (DTI) can be located in a deep trench (DT), and at least a portion of the deep trench (DT) may be surrounded by a device isolation portion (STL) located in a shallow trench (ST).

[0079] As previously described, the pixel separating structure (DTI) may be positioned to surround at least a portion of the periphery of the first pixel group (PG1) and the second pixel group (PG2). The pixel separating structure (DTI) may also surround at least a portion of the periphery of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and may also surround at least a portion of the periphery of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2).

[0080] Deep trenches (DT) and pixel isolation structures (DTI) may penetrate the substrate 200 from the first side (SFA) to the second side (SFB) of the substrate 200.

[0081] The pixel isolation structure (DTI) may include a first pattern (DTI1), a second pattern (DTI2), and a third pattern (DTI3). The first pattern (DTI1) may cover the inner wall of the deep trench (DT). The third pattern (DTI3) may fill the upper part of the deep trench (DT). The second pattern (DTI2) may fill the lower part of the deep trench (DT).

[0082] The first pattern (DTI1) may extend from the first side (SFA) to the second side (SFB) of the substrate 200. The second pattern (DTI2) may be separated from the substrate 200 by the first pattern (DTI1). In other embodiments, the third pattern (DTI3) may be omitted.

[0083] The first pattern (DTI1) and the third pattern (DTI3) may include silicon oxide, silicon nitrate, or silicon acid nitrate. The first pattern (DTI1) may include a metal oxide such as hafnium oxide, aluminum oxide, or tantalum oxide, in which case the first pattern (DTI1) can act as a negative fixed charge layer. The second pattern (DTI2) may include a semiconductor material such as polysilicon doped with n-type or p-type.

[0084] Photoelectric conversion regions (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) corresponding to each pixel (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8) may be located within the substrate 200.

[0085] Light incident from the outside may be converted into an electrical signal in the photoelectric conversion regions (PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8). The photoelectric conversion regions (PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8) may include photodiodes formed inside the substrate 200. The photoelectric conversion regions (PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8) may be doped with conductive impurities different from the conductive impurities doped into the substrate 200.

[0086] The photoelectric conversion regions (PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8) may be doped with impurities of a second conductivity type different from the first conductivity type impurities doped into the substrate 200. For example, the substrate 200 may be doped with P-type impurities, and the photoelectric conversion regions (PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8) may be doped with N-type impurities.

[0087] The N-type impurity regions of the photoelectric conversion regions (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) form PN junctions with the surrounding P-type impurity regions of the substrate 200 to form photodiodes, and when light is incident, electron-hole pairs can be generated by the PN junctions.

[0088] Pixel isolation structures (DTIs) are located between photoelectric conversion regions (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) corresponding to the plurality of pixels (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8), and the photoelectric conversion regions (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) corresponding to each of the plurality of pixels (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8) can be isolated from each other by the pixel isolation structures (DTIs). The pixel isolation structures (DTIs) can electrically and optically isolate the adjacent photoelectric conversion regions (PD1, PD2, PD3, PD4).

[0089] The substrate 200 may include a shallow trench (ST), and an isolation region (STL) may be located in the shallow trench (ST) of the substrate 200. The shallow trench (ST) may not penetrate the substrate 200 from the first surface (SFA) of the substrate 200, but may be located in a portion of the substrate 200. The depth of the shallow trench (ST) along the third direction (DR3) of the height direction may be smaller than the depth of the deep trench (DT). The isolation region (STL) may include silicon oxide, silicon nitride, or a combination thereof.

[0090] Alternatively, the isolation region (STL) may be a region doped with the same first conductivity type impurities as those doped into the substrate 200 at a higher concentration than the doping concentration of the impurities doped into the substrate 200.

[0091] The pixel isolation structure (DTI) can penetrate the shallow trench isolation (STI).

[0092] A plurality of gates (TG1 to TG8, RG1, SF1, SEL, GE1, and GE2) may be located on the first surface (SFA) of the substrate 200.

[0093] Each of the plurality of pixels (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8) may include an active region (AR) located in the substrate 200 adjacent to a first surface (SFA) of the substrate 200. Each of the active regions (AR) may be separated by a device isolation region (STL).

[0094] The substrate 200 may include a plurality of floating diffusion regions (FD1, FD2) and ground regions (not shown) located adjacent to the first surface (SFA).

[0095] The first floating diffusion region (FD1) may be adjacent to the transmission gates (TG1, TG2, TG3, TG4), and the second floating diffusion region (FD2) may be adjacent to the transmission gates (TG5, TG6, TG7, TG8). The floating diffusion regions (FD1, FD2) may be doped with impurities of a second conductivity type different from the impurities of the first conductivity type doped into the substrate 200.

[0096] The ground region may be doped with conductive impurities, such as the conductive impurities doped into the substrate 200, and the concentration of the doped conductive impurities may be higher than the concentration of the rest of the substrate 200.

[0097] The active areas (AR) of the plurality of pixels (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8) may be active areas for the operation of a plurality of transistors.

[0098] A plurality of gates (TG1 to TG8, RG1, SF1, SEL, GE) may be located on the active regions (AR) of the plurality of pixels (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8).

[0099] The plurality of gates (TG1 to TG8, RG1, SF1, SEL, GE) and floating diffusion regions (FD1, FD2) may form transfer transistors (T1 to T8), source follower transistors (S1 to S3), select transistor (SE), reset transistors (RX1, RX2), and dual conversion transistor (DCX). The ground region may be a ground pattern for grounding at least one of the transfer transistors (T1 to T8), select transistors (S1 to S3), reset transistors (RX1, RX2), and dual conversion transistor (DCX).

[0100] A first structure 300 may be disposed on the first surface (SFA) of the substrate 200. The first structure 300 may include a plurality of vias (ML1), a plurality of wiring layers (ML2, ML3), and a plurality of insulating layers (IL1, IL2, IL3). The plurality of insulating layers (IL1, IL2, IL3) can electrically isolate the plurality of vias (ML1) and the plurality of wiring layers (ML2, ML3).

[0101] A plurality of vias (ML1) and a plurality of wiring layers (ML2, ML3) may be electrically coupled to transistors on the first surface (SFA) of the substrate 200.

[0102] The vias (ML1) and wiring layers (ML2, ML3) may include tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitrate, titanium nitrate, doped polysilicon, or the like.

[0103] The insulating layers (IL1, IL2, IL3) may include insulating materials such as silicon oxide, silicon nitrate, silicon oxide nitrate, low-k materials, etc. The low-k materials may include, for example, at least one of flowable oxide (FOX), torene silica zene (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphosilica glass (PSG), borophosphosilica glass (BPSG), plasma enhanced tetra ethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), parylene, bis-benzocyclobutenes (BCB), SiLK, polyimide, porous polymeric material, and combinations thereof.

[0104] The image sensor 1000 may further include a support substrate 400 positioned on the first structure 300, but the support substrate 400 is optional. An adhesive member (not shown) may be further positioned between the support substrate 400 and the first structure 300.

[0105] An anti-reflection layer (PRL) may be positioned on the second surface (SFB) of the substrate 200. The anti-reflection layer (PRL) may cover the second surface (SFB) of the substrate 200 and the pixel separating structure (DTI).

[0106] Anti-reflective layers (PRLs) are made of hafnium oxide (HfO2), silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), cerium oxide (CeO2), neodymium oxide (Nd2O3), promethium oxide (Pm2 O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), gadolinium oxide (Gd2O3), terbium oxide (Tb2O3), dysprosium oxide (Dy2O3), holmium oxide (Ho2O3), thulium oxide (Tm2O3), ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3), yttrium oxide (Y2O3), or combinations thereof.

[0107] In one embodiment, the anti-reflective layer (PRL) may include multiple layers containing different materials and having different thicknesses. For example, the anti-reflective layer (PRL) may include first to third anti-reflective layers sequentially stacked on the second surface (SFB) of the substrate 200.

[0108] The first antireflection layer may be a fixed charge layer having a negative fixed charge, which can generate hole accumulation around the fixed charge layer, thereby effectively reducing dark current and white spots.

[0109] The third anti-reflection layer may include a metal oxide or metal fluoride containing at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), and yttrium (Y). For example, the first and third anti-reflection layers may include hafnium oxide layers, and the second anti-reflection layer may include silicon oxide and / or silicon nitride. However, in other embodiments, the number and relative thicknesses of layers constituting the anti-reflection layer (PRL) may vary.

[0110] In another embodiment, the anti-reflective layer (PRL) may further include a silicon nitride layer disposed between the second anti-reflective layer and the third anti-reflective layer.

[0111] The fence pattern (IS) may surround the color filter (CF).

[0112] The fence pattern (IS) may include a low refractive index material. The low refractive index material may have a refractive index greater than about 1.0 and less than or equal to about 1.4. For example, the low refractive index material may include PMMA (polymethylmetacrylate), silicon acrylate, CAB (cellulose acetate butyrate), silica, or FSA (fluoro-silicon acrylate). For example, the low refractive index material may include a polymer material with silica (SiOx) particles dispersed therein.

[0113] When the fence pattern (IS) comprises a low refractive index material having a relatively low refractive index, light incident on the fence pattern (IS) may be totally reflected and directed toward the center of each pixel area (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8).

[0114] The fence pattern (IS) can prevent light that is obliquely incident inside a color filter (CF) placed in one of the multiple pixel regions (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8) from entering a color filter (CF) placed over another adjacent pixel region, thereby preventing crosstalk between the multiple pixel regions (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8).

[0115] A plurality of color filters (CF) may be disposed on the anti-reflection layer (PRL) and may be separated from each other by a fence pattern (IS). The plurality of color filters (CF) may include, for example, a green filter, a blue filter, and a red filter. The plurality of color filters (CF) may include, for example, cyan, magenta, or yellow.

[0116] A microlens (ML) may be disposed above the color filter (CF) and the fence pattern (IS).

[0117] The microlenses (ML) may be transparent. The microlenses (ML) may be made of a resin material such as a styrene resin, an acrylic resin, a styrene-acrylic copolymer resin, or a siloxane resin.

[0118] The microlenses (ML) collect incident light, and the collected light can be incident on the photoelectric conversion regions (PD1, PD2, PD3, PD4, PD5, PD6, PD8) via the color filters (CF).

[0119] A capping layer (CPL) can be disposed on the microlens (ML) to protect the microlens (ML).

[0120] Referring to FIG. 4, the image sensor 1000 may further include a third pixel group (PG3) and a fourth pixel group (PG4) adjacent to the first pixel group (PG1) and the second pixel group (PG2) along the first direction (DR1).

[0121] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0122] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0123] The first floating diffusion region (FD1) does not have to overlap with the pixel separating structure (DTI) along the third direction (DR3), which is the height direction.

[0124] That is, the pixel separating structure (DTI) does not have to be formed in the region corresponding to the first floating diffusion region (FD1).

[0125] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may include a first transmission gate electrode (TG1), a second transmission gate electrode (TG2), a third transmission gate electrode (TG3), and a fourth transmission gate electrode (TG4) located on the active region (AR), and the first floating diffusion region (FD1) may be formed in a portion of the active region (AR) and located on one side of the first transmission gate electrode (TG1), the second transmission gate electrode (TG2), the third transmission gate electrode (TG3), and the fourth transmission gate electrode (TG4).

[0126] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0127] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed as a single unit.

[0128] The second floating diffusion region (FD2) does not have to overlap with the pixel separating structure (DTI) along the third direction (DR3), which is the height direction.

[0129] That is, the pixel separating structure (DTI) does not have to be formed in the region corresponding to the second floating diffusion region (FD2).

[0130] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may include a fifth transmission gate electrode (TG5), a sixth transmission gate electrode (TG6), a seventh transmission gate electrode (TG7), and an eighth transmission gate electrode (TG8) located on the active region (AR), and the second floating diffusion region (FD2) may be formed in a portion of the active region (AR) and located on one side of the fifth transmission gate electrode (TG5), the sixth transmission gate electrode (TG6), the seventh transmission gate electrode (TG7), and the eighth transmission gate electrode (TG8).

[0131] A first reset gate electrode (RG1) may be located on the active region (AR) of the first pixel (PX1) of the first pixel group (PG1), and a second reset gate electrode (RG2) may be located on the active region (AR) of the second pixel (PX2) of the third pixel group (PG3), which is adjacent to the first pixel group (PG1) along the first direction (DR1) and absorbs and senses light of a different color from the first pixel group (PG1).

[0132] A first source follower gate electrode SF1 may be located on the active region AR of the fourth pixel PX4 of the first pixel group PG1.

[0133] A second source follower gate electrode (SF2) may be located on the active region (AR) of the third pixel (PX3) of the third pixel group (PG3), which is adjacent to the first pixel group (PG1) along the first direction (DR1) and absorbs and senses light of a different color from the first pixel group (PG1).

[0134] A third source follower gate electrode (SF3) may be located on the active region (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4), which is adjacent to the second pixel group (PG2) along the first direction (DR1) and absorbs and senses light of a different color from the second pixel group (PG2).

[0135] A select gate electrode (SEL) may be located on the active region (AR) of the fifth pixel (PX5) of the second pixel group (PG2).

[0136] However, in another embodiment, the third source follower gate electrode (SF3) may be located on the active region (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the select gate electrode (SEL) may be located on the active region (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4).

[0137] The active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) may be connected to each other via a first connecting portion (CP1) and formed as an integral unit. The first connecting portion (CP1) between the active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0138] That is, the pixel separating structure (DTI) does not have to be formed in the region corresponding to the first connecting portion (CP1).

[0139] The active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the third pixel (PX3) of the third pixel group (PG3), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active area (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4) may be connected via a second connecting part (CP2) to be integrally formed.

[0140] That is, the pixel separating structure (DTI) does not have to be formed in the region corresponding to the second connecting portion (CP2).

[0141] The active region (AR) and the first reset gate electrode (RG1) of the first pixel (PX1) of the first pixel group (PG1) may form a first reset transistor (RX1), and the active region (AR) and the second reset gate electrode (RG2) of the second pixel (PX2) of the third pixel group (PG3) may form a second reset transistor (RX2).

[0142] The active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3), which absorbs and senses light of a color different from that of the first pixel group (PG1), are connected to each other via a first connection part (CP1) and formed as a single unit, and the first reset transistor (RX1) and the second reset transistor (RX2) may be directly connected to each other without going through the multiple vias (ML1) and multiple wiring layers (ML2, ML3) of the first structure 300.

[0143] The reset transistors (RX1, RX2) of the image sensor 1000 according to the embodiment include a first reset transistor (RX1) and a second reset transistor (RX2) that are directly connected without an additional wiring layer, thereby improving the performance of the reset transistors (RX1, RX2) without increasing the area occupied by the reset transistors (RX1, RX2).

[0144] Similarly, the active region (AR) and the first source follower gate electrode (SF1) of the fourth pixel (PX4) of the first pixel group (PG1) may form a first source follower transistor (S1), the active region (AR) and the second source follower gate electrode (SF2) of the third pixel (PX3) of the third pixel group (PG3) may form a second source follower transistor (S2), the active region (AR) and the third source follower gate electrode (SF3) of the sixth pixel (PX6) of the fourth pixel group (PG4) may form a third source follower transistor (S3), and the active region (AR) and the selection gate electrode (SEL) of the fifth pixel (PX5) of the second pixel group (PG2) may form a selection transistor (SE).

[0145] The active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the third pixel (PX3) of the third pixel group (PG3) that absorbs and senses light of a color different from that of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a color different from that of the first pixel group (PG1), and the active area (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4) that absorbs and senses light of a color different from that of the second pixel group (PG2) may be connected to each other via the second connecting part (CP2) and formed as an integral unit, and the first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the selection transistor (SE) may be directly connected without using the multiple vias (ML1) and multiple wiring layers (ML2, ML3) of the first structure 300.

[0146] The source follower transistors (S1, S2, S3) of the image sensor 1000 according to the embodiment may include a first source follower transistor (S1), a second source follower transistor (S2) and a third source follower transistor (S3) that are directly connected without an additional wiring layer.

[0147] Source-follower transistors may be more susceptible to the effects of thermal noise and flicker noise inherent to transistor elements than other transistors, such as transfer transistors, reset transistors, and select transistors. Noise induced in source-follower transistors is directly transmitted to internal circuits, resulting in reduced image quality. By including a first source-follower transistor (S1), a second source-follower transistor (S2), and a third source-follower transistor (S3), the effects of thermal noise and flicker noise inherent to transistor elements can be reduced and the amount of current flowing through the source-follower transistors can be increased. This improves the linearity of the voltage-current graph of the source-follower transistors, thereby reducing source-follower transistor noise.

[0148] The first source follower transistor (S1), the second source follower transistor (S2), and the third source follower transistor (S3) of the source follower transistors (S1, S2, S3) can be directly connected without an additional wiring layer, preventing unnecessary coupling and resistance due to the additional wiring layer. Also, the performance of the source follower transistors (S1, S2, S3) can be improved without increasing the area occupied by the source follower transistors (S1, S2, S3).

[0149] The source follower transistors (S1, S2, S3) and the selection transistor (SE) are also directly connected without an additional wiring layer, which can prevent unnecessary coupling and resistance due to the additional wiring layer.

[0150] Either the first gate electrode (GE1) located on the active area (AR) of the seventh pixel (PX7) of the second pixel group (PG2) or the second gate electrode (GE2) located on the active area (AR) of the eighth pixel (PX8) of the second pixel group (PG2) may be a dual conversion gate electrode (DCG).

[0151] In addition, a gate electrode may not be located in either the seventh pixel (PX7) or the eighth pixel (PX8) of the second pixel group (PG2), and the active area that does not overlap with the gate electrode may be a ground area (not shown).

[0152] The transistors (RX1, RX2, S1, S2, S3, SE, DCX) formed by the gates (RG1, RG2, SF1, SF2, SF3, SEL, GE) and active regions (AR) of the image sensor 1000 according to the embodiment may have a fingered type including one source region and two drain regions. Therefore, the transistors (RX1, RX2, S1, S2, S3, SE, DCX) can operate like two transistors connected in parallel, thereby improving the performance of the transistors (RX1, RX2, S1, S2, S3, SE, DCX) without increasing the area occupied by the transistors (RX1, RX2, S1, S2, S3, SE, DCX).

[0153] As explained above, one pixel area including two pixel groups shares the reset transistors (RX1, RX2), dual conversion transistor (DCX), source follower transistors (S1 to S3), and select transistor (SE), which allows for efficient arrangement of transistors for driving the image sensor even if the size of the image sensor is reduced.

[0154] The positions of the source follower transistors (S1 to S3), the selection transistor (SE), the reset transistors (RX1, RX2), and the dual conversion transistor (DCX) are not limited to the positions shown in Figures 4 and 5, and the positions of the source follower transistors (S1 to S3), the selection transistor (SE), the reset transistors (RX1, RX2), and the dual conversion transistor (DCX) can be changed in various ways so that multiple pixels (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8) can share the source follower transistors (S1 to S3), the selection transistor (SE), the reset transistors (RX1, RX2), and the dual conversion transistor (DCX).

[0155] The arrangement of the pixel separating structures (DTIs) of the image sensor 1000 according to one embodiment will be described in more detail with reference to FIGS.

[0156] The pixel separating structure (DTI) may surround at least a portion of the periphery of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3) and fourth pixel (PX4) of the first pixel group (PG1), and may surround at least a portion of the periphery of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7) and eighth pixel (PX8) of the second pixel group (PG2).

[0157] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0158] The pixel separating structure (DTI) may have a first open portion (OPN1) formed in an area corresponding to a first floating diffusion region (FD1) shared by the first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4), and the first floating diffusion region (FD1) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0159] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed integrally.

[0160] The pixel separating structure (DTI) may have a second open portion (OPN2) formed in an area corresponding to a second floating diffusion region (FD2) shared by the fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8), and the second floating diffusion region (FD2) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0161] A first floating diffusion region (FD1) shared by the first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) and a second floating diffusion region (FD2) shared by the fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) are connected to a first floating diffusion region (FD1) of the substrate 200 through regions corresponding to the first open portion (OPN1) and the second open portion (OPN2) of the pixel isolation structure (DTI). The floating diffusion regions (FD1) of the first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) can be connected to each other without using an additional interconnection wiring layer, and the floating diffusion regions (FD2) of the fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) can be connected to each other.

[0162] The active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3), which absorbs and senses light of a different color from that of the first pixel group (PG1), may be integrally formed by being connected to each other via a first connecting part (CP1).

[0163] The pixel separating structure (DTI) may have a third open portion (OPN3) formed in a region corresponding to the first connecting portion (CP1) between the active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3), and the first connecting portion (CP1) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0164] The active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the third pixel (PX3) of the third pixel group (PG3) that absorbs and senses light of a color different from that of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a color different from that of the first pixel group (PG1), and the active area (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4) that absorbs and senses light of a color different from that of the second pixel group (PG2) may be connected to each other via a second connecting part (CP2) and formed as a single unit.

[0165] The pixel separating structure (DTI) may have a fourth open portion (OPN4) formed in a region corresponding to the second connecting portion (CP2) between the active region (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active region (AR) of the third pixel (PX3) of the third pixel group (PG3), the active region (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active region (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4), and the second connecting portion (CP2) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0166] The active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) are connected to each other through the first connecting portion (CP1) located in an area corresponding to the third opening portion (OPN3) of the pixel separating structure (DTI) and are integrally formed adjacent to the first surface (SFA) of the substrate 200, so that the first reset transistor (RX1) and the second reset transistor (RX2) are directly connected to each other without using an additional connecting wiring layer.

[0167] The active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the third pixel (PX3) of the third pixel group (PG3), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active area (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4) are connected to each other via the second connecting portion (CP2) located in an area corresponding to the fourth open portion (OPN4) of the pixel separating structure (DTI), and are integrally formed adjacent to the first surface (SFA) of the substrate 200. This makes it possible to directly connect the first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the select transistor (SE) to each other without using an additional interconnection layer.

[0168] In addition, the pixel separating structure (DTI) surrounding the periphery of the plurality of pixels (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8) of the first pixel group (PG1) and the second pixel group (PG2) may have a first open portion (OPN1) located at the center of the first pixel group (PG1), a second open portion (OPN2) located at the center of the second pixel group (PG2), and a third open portion (OPN3) and a fourth open portion (OPN4) located at the corners of the first pixel group (PG1) and the second pixel group (PG2). Therefore, the shape of the pixel separating structure (DTI) has a symmetric shape, which allows the pixel separating structure (DTI) to be stably formed and maintained and prevents the pixel separating structure (DTI) from tilting in any direction.

[0169] An image sensor 1001 according to another embodiment will be described below with reference to Fig. 8. Fig. 8 is a plan view of the image sensor according to another embodiment.

[0170] 8, an image sensor 1001 according to this embodiment is similar to the image sensor 1000 according to the previously described embodiment, and a detailed description of the same components will be omitted.

[0171] The image sensor 1001 may further include a third pixel group (PG3) and a fourth pixel group (PG4) adjacent to the first pixel group (PG1) and the second pixel group (PG2) along the first direction (DR1).

[0172] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0173] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0174] The pixel separating structure (DTI) may have a first open portion (OPN1) formed in an area corresponding to a first floating diffusion region (FD1) shared by the first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4), and the first floating diffusion region (FD1) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0175] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0176] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed integrally.

[0177] The pixel separating structure (DTI) may have a second open portion (OPN2) formed in an area corresponding to a second floating diffusion region (FD2) shared by the fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8), and the second floating diffusion region (FD2) may not overlap with the pixel separating structure (DTI) along a third direction (DR3) in the height direction.

[0178] The active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3), which absorbs and senses light of a different color from that of the first pixel group (PG1), may be connected to each other via a first connecting part (CP1) and formed as a single unit.

[0179] The pixel separating structure (DTI) may have a third open portion (OPN3) formed in a region corresponding to the first connecting portion (CP1) between the active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3), and the first connecting portion (CP1) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0180] The active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the third pixel (PX3) of the third pixel group (PG3) that absorbs and senses light of a color different from that of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a color different from that of the first pixel group (PG1), and the active area (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4) that absorbs and senses light of a color different from that of the second pixel group (PG2) may be connected to each other via a second connecting part (CP2) and formed as a single unit.

[0181] The pixel separating structure (DTI) may have a fourth open portion (OPN4) formed in a region corresponding to the second connecting portion (CP2) between the active region (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active region (AR) of the third pixel (PX3) of the third pixel group (PG3), the active region (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active region (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4), and the second connecting portion (CP2) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0182] In the image sensor 1001 according to this embodiment, the ground region (GNL) of the eighth pixel (PX8) of the second pixel group (PG2) and the ground region (GNL) of the seventh pixel (PX7) of the fourth pixel group (PG4), which absorbs and senses light of a color different from that of the second pixel group (PG2), may be connected via a third connection part (CP3) and formed integrally adjacent to the first surface (SFA) of the substrate 200.

[0183] The pixel separating structure (DTI) may have a fifth open portion (OPN5) formed in a region corresponding to the third connecting portion (CP3) between the ground region (GNL) of the eighth pixel (PX8) of the second pixel group (PG2) and the ground region (GNL) of the seventh pixel (PX7) of the fourth pixel group (PG4), and the third connecting portion (CP3) may not overlap with the pixel separating structure (DTI) along the third direction (DR3), which is the height direction.

[0184] The ground region (GNL) of the eighth pixel (PX8) of the second pixel group (PG2) and the ground region (GNL) of the seventh pixel (PX7) of the fourth pixel group (PG4) may be connected to each other via a third connection part (CP3) located in an area corresponding to the fifth opening part (OPN5) of the pixel separating structure (DTI), and may be integrally formed adjacent to the first surface (SFA) of the substrate 200.

[0185] Many of the features of the image sensor 1000 according to the embodiment described above are all applicable to the image sensor 1001 according to this embodiment.

[0186] An image sensor 1002 according to another embodiment will be described with reference to Figures 9 and 10. Figure 9 is a plan view of an image sensor according to another embodiment, and Figure 10 is a plan view showing a pixel separating structure of an image sensor according to one embodiment.

[0187] 9, an image sensor 1002 according to this embodiment is similar to the image sensors 1000 and 1001 according to the previously described embodiments, and a detailed description of the same components will be omitted.

[0188] The image sensor 1002 may further include a third pixel group (PG3) and a fourth pixel group (PG4) adjacent to the first pixel group (PG1) and the second pixel group (PG2) along the first direction (DR1).

[0189] A first reset gate electrode (RG1) may be located over the active area (AR) of the first pixel (PX1) of the first pixel group (PG1), a second reset gate electrode (RG2) may be located over the active area (AR) of the second pixel (PX2) of the first pixel group (PG1), and a first source follower gate electrode (SF1) may be located over the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1).

[0190] A select gate electrode (SEL) may be located on the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2).

[0191] A second source follower gate electrode (SF2) may be located over the active area (AR) of the third pixel (PX3) of the third pixel group (PG3) adjacent to the first pixel group (PG1) along the first direction (DR1), and a third source follower gate electrode (SF3) may be located over the active area (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4) adjacent to the second pixel group (PG2).

[0192] However, in another embodiment, the third source follower gate electrode (SF3) may be located over the active region (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the select gate electrode (SEL) may be located over the active region (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4).

[0193] Either the first gate electrode (GE1) located on the active area (AR) of the seventh pixel (PX7) of the second pixel group (PG2) or the second gate electrode (GE2) located on the active area (AR) of the eighth pixel (PX8) of the second pixel group (PG2) may be a dual conversion gate electrode (DCG).

[0194] In addition, a gate electrode may not be disposed in either the seventh pixel (PX7) or the eighth pixel (PX8) of the second pixel group (PG2), and the active area that does not overlap with the gate electrode may be a ground area (not shown).

[0195] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0196] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0197] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0198] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed integrally.

[0199] The active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the third pixel (PX3) of the third pixel group (PG3) that absorbs and senses light of a color different from that of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a color different from that of the first pixel group (PG1), and the active area (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4) that absorbs and senses light of a color different from that of the second pixel group (PG2) may be connected to each other via the second connecting part (CP2) and formed as a single unit, and the first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the selection transistor (SE) may be directly connected without using the multiple vias (ML1) and multiple wiring layers (ML2, ML3) of the first structure 300.

[0200] The source follower transistors (S1, S2, S3) of the image sensor 1002 according to the embodiment may include a first source follower transistor (S1), a second source follower transistor (S2) and a third source follower transistor (S3) that are directly connected without using an additional wiring layer.

[0201] The first source follower transistor (S1), the second source follower transistor (S2), and the third source follower transistor (S3) of the source follower transistors (S1, S2, S3) may be directly connected without using an additional wiring layer, which can prevent unnecessary coupling and resistance due to the additional wiring layer. Also, the performance of the source follower transistors (S1, S2, S3) can be improved without increasing the area occupied by the source follower transistors (S1, S2, S3).

[0202] The source follower transistors (S1, S2, S3) and the select transistor (SE) are also directly connected without using an additional wiring layer, which can prevent unnecessary coupling and resistance due to the additional wiring layer.

[0203] Unlike the image sensors 1000 and 1001 according to the previously described embodiments, the first reset gate electrode (RG1) and the second reset gate electrode (RG2) of the image sensor 1002 according to this embodiment are located on the active areas (AR) of the first pixel (PX1) and the second pixel (PX2) of the first pixel group (PG1), and the first reset transistor (RX1) and the second reset transistor (RX2) may not be directly connected.

[0204] Referring to FIG. 10, the pixel separating structure (DTI) of the image sensor 1002 according to this embodiment may have a first open portion (OPN1) formed in an area corresponding to a first floating diffusion region (FD1) shared by a first pixel (PX1), a second pixel (PX2), a third pixel (PX3), and a fourth pixel (PX4), and the first floating diffusion region (FD1) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0205] The pixel separating structure (DTI) may have a second open portion (OPN2) formed in an area corresponding to a second floating diffusion region (FD2) shared by the fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8), and the second floating diffusion region (FD2) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0206] The pixel separating structure (DTI) may have a fourth open portion (OPN4) formed in a region corresponding to the second connecting portion (CP2) between the active region (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active region (AR) of the third pixel (PX3) of the third pixel group (PG3), the active region (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active region (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4), and the second connecting portion (CP2) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0207] Unlike the image sensors 1000 and 1001 according to the previously described embodiments, the pixel separating structure (DTI) of the image sensor 1002 according to this embodiment may not have the third open portion (OPN3).

[0208] Therefore, the pixel separating structure (DTI) can be stably formed and maintained, and the pixel separating structure (DTI) can be prevented from tilting in any direction.

[0209] Many of the features of the image sensors 1000 and 1001 according to the previously described embodiments are all applicable to the image sensor 1002 according to this embodiment.

[0210] An image sensor 1003 according to another embodiment will be described with reference to Figures 11 and 12. Figure 11 is a plan view of the image sensor according to the other embodiment, and Figure 12 is a plan view showing a pixel separating structure of the image sensor according to the other embodiment.

[0211] 11, an image sensor 1003 according to this embodiment is similar to the image sensors 1000, 1001, and 1002 according to the previously described embodiments, and a detailed description of the same components will be omitted.

[0212] The image sensor 1003 may further include a third pixel group (PG3) and a fourth pixel group (PG4) adjacent to the first pixel group (PG1) and the second pixel group (PG2) along the first direction (DR1).

[0213] A first reset gate electrode (RG1) may be located over the active region (AR) of the first pixel (PX1) of the first pixel group (PG1), and a second reset gate electrode (RG2) may be located over the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) adjacent to the first pixel group (PG1) along the first direction (DR1) and absorbing and sensing light of a different color from that of the first pixel group (PG1).

[0214] A first source follower gate electrode (SF1) may be located over the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), and a second source follower gate electrode (SF2) may be located over the active area (AR) of the third pixel (PX3) of the first pixel group (PG1).

[0215] A third source follower gate electrode (SF3) may be located on the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and a select gate electrode (SEL) may be located on the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2).

[0216] Either the first gate electrode (GE1) located on the active area (AR) of the seventh pixel (PX7) of the second pixel group (PG2) or the second gate electrode (GE2) located on the active area (AR) of the eighth pixel (PX8) of the second pixel group (PG2) may be a dual conversion gate electrode (DCG).

[0217] In addition, a gate electrode may not be arranged in either the seventh pixel (PX7) or the eighth pixel (PX8) of the second pixel group (PG2), and the active area that does not overlap with the gate electrode may be a ground area (not shown).

[0218] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0219] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0220] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0221] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed integrally.

[0222] The active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) may be connected via a first connecting portion (CP1) and formed as an integral unit. The first connecting portion (CP1) between the active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0223] Referring to FIG. 12, the pixel separating structure (DTI) of the image sensor 1003 according to this embodiment may have a first open portion (OPN1) formed in an area corresponding to a first floating diffusion region (FD1) shared by the first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4), and the first floating diffusion region (FD1) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0224] The pixel separating structure (DTI) may have a second open portion (OPN2) formed in an area corresponding to a second floating diffusion region (FD2) shared by the fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8), and the second floating diffusion region (FD2) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0225] The pixel separating structure (DTI) may have a third open portion (OPN3) formed in a region corresponding to the first connecting portion (CP1) between the active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3), and the first connecting portion (CP1) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0226] Unlike the image sensors 1000, 1001, and 1002 according to the previously described embodiments, the pixel separating structure (DTI) of the image sensor 1002 according to this embodiment may not have the fourth open portion (OPN4).

[0227] Therefore, the pixel separating structure (DTI) can be stably formed and maintained, and the pixel separating structure (DTI) can be prevented from tilting in any direction.

[0228] An image sensor 1004 according to another embodiment will be described with reference to Figures 13 and 14. Figure 13 is a plan view of the image sensor according to the other embodiment, and Figure 14 is a plan view showing a pixel separating structure of the image sensor according to the other embodiment.

[0229] 13, an image sensor 1004 according to this embodiment is similar to the image sensors 1000, 1001, 1002, and 1003 according to the previously described embodiments, and a detailed description of the same components will be omitted.

[0230] The image sensor 1004 may further include a third pixel group (PG3) and a fourth pixel group (PG4) adjacent to the first pixel group (PG1) and the second pixel group (PG2) along the first direction (DR1).

[0231] A first reset gate electrode (RG1) may be located over the active region (AR) of the first pixel (PX1) of the first pixel group (PG1), and a second reset gate electrode (RG2) may be located over the active region (AR) of the second pixel (PX2) of the first pixel group (PG1).

[0232] A first source follower gate electrode (SF1) may be located over the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), and a second source follower gate electrode (SF2) may be located over the active area (AR) of the third pixel (PX3) of the first pixel group (PG1).

[0233] A third source follower gate electrode (SF3) may be located on the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and a select gate electrode (SEL) may be located on the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2).

[0234] Either the first gate electrode (GE1) located on the active area (AR) of the seventh pixel (PX7) of the second pixel group (PG2) or the second gate electrode (GE2) located on the active area (AR) of the eighth pixel (PX8) of the second pixel group (PG2) may be a dual conversion gate electrode (DCG).

[0235] In addition, a gate electrode may not be arranged in either the seventh pixel (PX7) or the eighth pixel (PX8) of the second pixel group (PG2), and the active area that does not overlap with the gate electrode may be a ground area (not shown).

[0236] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0237] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0238] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0239] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed as a single unit.

[0240] The fourth connecting portion (CP4) between the active area (AR) of the third pixel (PX3) of the first pixel group (PG1), the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2) may not overlap with the pixel separating structure (DTI) along the third direction (DR3), which is the height direction.

[0241] The active area (AR) of the third pixel (PX3) of the first pixel group (PG1), the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a color different from that of the first pixel group (PG1), and the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2) may be connected to each other and formed as a single unit through the fourth connecting part (CP4), and the first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the selection transistor (SE) may be directly connected without using additional wiring.

[0242] The source follower transistors (S1, S2, S3) of the image sensor 1004 according to the embodiment may include a first source follower transistor (S1), a second source follower transistor (S2), and a third source follower transistor (S3) that are directly connected without using an additional wiring layer.

[0243] The first source follower transistor (S1), the second source follower transistor (S2), and the third source follower transistor (S3) of the source follower transistors (S1, S2, S3) may be directly connected without using an additional wiring layer, which can prevent unnecessary coupling and resistance due to the additional wiring layer. Also, the performance of the source follower transistors (S1, S2, S3) can be improved without increasing the area occupied by the source follower transistors (S1, S2, S3).

[0244] The source follower transistors (S1, S2, S3) and the selection transistor (SE) are also directly connected without using an additional wiring layer, thereby preventing unnecessary coupling and resistance due to the additional wiring layer.

[0245] The first reset gate electrode (RG1) and the second reset gate electrode (RG2) of the image sensor 1004 according to this embodiment are located on the active regions (AR) of the first pixel (PX1) and the second pixel (PX2) of the first pixel group (PG1), and the first reset transistor (RX1) and the second reset transistor (RX2) may not be directly connected.

[0246] Referring to FIG. 14, the pixel separating structure (DTI) of the image sensor 1004 according to this embodiment may have a first open portion (OPN1) formed in an area corresponding to a first floating diffusion region (FD1) shared by the first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4), and the first floating diffusion region (FD1) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0247] The pixel separating structure (DTI) may have a second open portion (OPN2) formed in an area corresponding to a second floating diffusion region (FD2) shared by the fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8), and the second floating diffusion region (FD2) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0248] The pixel separating structure (DTI) may have a sixth open portion (OPN6) formed in a region corresponding to a fourth connecting portion (CP4) between the active region (AR) of the third pixel (PX3) of the first pixel group (PG1), the active region (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active region (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a color different from that of the first pixel group (PG1), and the active region (AR) of the sixth pixel (PX6) of the second pixel group (PG2), and the fourth connecting portion (CP4) may not overlap the pixel separating structure (DTI) along the third direction (DR3), which is the height direction.

[0249] The pixel separating structure (DTI) of the image sensor 1004 according to this embodiment may not have the third open portion (OPN3), which allows the pixel separating structure (DTI) to be stably formed and maintained and prevents the pixel separating structure (DTI) from tilting in any direction.

[0250] Many of the features of the image sensors 1000, 1001, 1002, and 1003 according to the previously described embodiments are all applicable to the image sensor 1004 according to this embodiment.

[0251] An image sensor 1005 according to another embodiment will be described with reference to Fig. 15 and Fig. 16. Fig. 15 is a plan view of the image sensor according to the another embodiment, and Fig. 16 is a plan view showing a pixel separating structure of the image sensor according to the another embodiment.

[0252] 15, an image sensor 1005 according to this embodiment is similar to the image sensors 1000, 1001, 1002, 1003, and 1004 according to the previously described embodiments, and a detailed description of the same components will be omitted.

[0253] The image sensor 1005 may further include a third pixel group (PG3) and a fourth pixel group (PG4) adjacent to the first pixel group (PG1) and the second pixel group (PG2) along the first direction (DR1).

[0254] A first reset gate electrode (RG1) may be located over the active region (AR) of the first pixel (PX1) of the first pixel group (PG1), and a second reset gate electrode (RG2) may be located over the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) adjacent to the first pixel group (PG1) along the first direction (DR1) and absorbing and sensing light of a different color from that of the first pixel group (PG1).

[0255] A first source follower gate electrode (SF1) may be located over the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), and a second source follower gate electrode (SF2) may be located over the active area (AR) of the third pixel (PX3) of the first pixel group (PG1).

[0256] A third source follower gate electrode (SF3) may be located on the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2), and a select gate electrode (SEL) may be located on the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2).

[0257] Either the first gate electrode (GE1) located on the active area (AR) of the seventh pixel (PX7) of the second pixel group (PG2) or the second gate electrode (GE2) located on the active area (AR) of the eighth pixel (PX8) of the second pixel group (PG2) may be a dual conversion gate electrode (DCG).

[0258] In addition, a gate electrode may not be arranged in either the seventh pixel (PX7) or the eighth pixel (PX8) of the second pixel group (PG2), and the active area that does not overlap with the gate electrode may be a ground area (not shown).

[0259] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0260] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0261] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0262] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed as a single unit.

[0263] The active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) may be connected via a first connecting portion (CP1) and formed as an integral unit. The first connecting portion (CP1) between the active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0264] The active area (AR) of the third pixel (PX3) of the first pixel group (PG1), the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a different color from that of the first pixel group (PG1), and the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2) may be connected to each other via a fourth connecting part (CP4) and formed as a single unit.

[0265] The fourth connecting portion (CP4) between the active area (AR) of the third pixel (PX3) of the first pixel group (PG1), the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2) may not overlap with the pixel separating structure (DTI) along the third direction (DR3), which is the height direction.

[0266] The active area (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active area (AR) of the second pixel (PX2) of the third pixel group (PG3), which absorbs and senses light of a color different from that of the first pixel group (PG1), are connected via a first connection part (CP1) and formed as a single unit, and the first reset transistor (RX1) and the second reset transistor (RX2) may be directly connected without going through the multiple vias (ML1) and multiple wiring layers (ML2, ML3) of the first structure 300.

[0267] The active area (AR) of the third pixel (PX3) of the first pixel group (PG1), the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a color different from that of the first pixel group (PG1), and the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2) may be connected via a fourth connecting part (CP4) and formed as a single unit, and the first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the selection transistor (SE) may be directly connected without using additional wiring.

[0268] The reset transistors (RX1, RX2) of the image sensor 1005 according to the embodiment include a first reset transistor (RX1) and a second reset transistor (RX2) that are directly connected without using an additional wiring layer, thereby improving the performance of the reset transistors (RX1, RX2) without increasing the area occupied by the reset transistors (RX1, RX2).

[0269] The source follower transistors (S1, S2, S3) may include a first source follower transistor (S1), a second source follower transistor (S2), and a third source follower transistor (S3) that are directly coupled without using an additional wiring layer.

[0270] The first source follower transistor (S1), the second source follower transistor (S2), and the third source follower transistor (S3) of the source follower transistors (S1, S2, S3) are directly connected without using an additional wiring layer, which can prevent unnecessary coupling and resistance due to the additional wiring layer. Also, the performance of the source follower transistors (S1, S2, S3) can be improved without increasing the area occupied by the source follower transistors (S1, S2, S3).

[0271] The source follower transistors (S1, S2, S3) and the select transistor (SE) are also directly connected without using an additional wiring layer, which can prevent unnecessary coupling and resistance due to the additional wiring layer.

[0272] Referring to FIG. 16, the pixel separating structure (DTI) of the image sensor 1005 according to this embodiment may have a first open portion (OPN1) formed in an area corresponding to a first floating diffusion region (FD1) shared by the first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4), and the first floating diffusion region (FD1) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0273] The pixel separating structure (DTI) may have a second open portion (OPN2) formed in an area corresponding to a second floating diffusion region (FD2) shared by the fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8), and the second floating diffusion region (FD2) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0274] The pixel separating structure (DTI) may have a third open portion (OPN3) formed in a region corresponding to the first connecting portion (CP1) between the active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3), and the first connecting portion (CP1) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0275] The pixel separating structure (DTI) may have a sixth open portion (OPN6) formed in a region corresponding to a fourth connecting portion (CP4) between the active region (AR) of the third pixel (PX3) of the first pixel group (PG1), the active region (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active region (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a color different from that of the first pixel group (PG1), and the active region (AR) of the sixth pixel (PX6) of the second pixel group (PG2), and the fourth connecting portion (CP4) may not overlap the pixel separating structure (DTI) along the third direction (DR3), which is the height direction.

[0276] Many of the features of the image sensors 1000, 1001, 1002, 1003, and 1004 according to the previously described embodiments are all applicable to the image sensor 1005 according to this embodiment.

[0277] An image sensor 2000 according to another embodiment will be described with reference to Figures 17 and 18. Figure 17 is a circuit diagram of the image sensor according to the another embodiment, and Figure 18 is a plan view of the image sensor according to the another embodiment.

[0278] 17, the image sensor 2000 according to this embodiment includes a first pixel group (PG1) and a second pixel group (PG2), and the first pixel group (PG1) and the second pixel group (PG2) may include pixels (PX1-PX8), photoelectric conversion units (PD1-PD8), transfer transistors (T1-T8), reset transistors (RX1, RX2), dual conversion transistors (DCX), source follower transistors (S1-S4), and a selection transistor (SE). As described above, each of the first pixel group (PG1) and the second pixel group (PG2) is illustrated as including four pixels (PX1-PX4) or (PX5-PX8), each including a photoelectric conversion unit (PD1-PD4 or PD5-PD8), but this is not a limitation of the embodiment.

[0279] The first pixel (PX1) may include a first photoelectric conversion unit (PD1) and a first transfer transistor (T1), the second pixel (PX2) may include a second photoelectric conversion unit (PD2) and a second transfer transistor (T2), the third pixel (PX3) may include a third photoelectric conversion unit (PD3) and a third transfer transistor (T3), and the fourth pixel (PX4) may include a fourth photoelectric conversion unit (PD4) and a fourth transfer transistor (T4).

[0280] The fifth pixel (PX5) may include a fifth photoelectric conversion unit (PD5) and a fifth transfer transistor (T5), the sixth pixel (PX6) may include a sixth photoelectric conversion unit (PD6) and a sixth transfer transistor (T6), the seventh pixel (PX7) may include a seventh photoelectric conversion unit (PD7) and a seventh transfer transistor (T7), and the eighth pixel (PX8) may include an eighth photoelectric conversion unit (PD8) and an eighth transfer transistor (T8).

[0281] The pixels (PX1 to PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0282] The pixels (PX5 to PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0283] The first pixel group (PG1) and the second pixel group (PG2) can share the reset transistors (RX1, RX2), the dual conversion transistor (DCX), the source follower transistors (S1 to S4), and the select transistor (SE). The first floating diffusion region (FD1) or the second floating diffusion region (FD2) can accumulate a charge corresponding to the amount of incident light.

[0284] While the transmission transistors (T1 to T8) are turned on by a transmission signal, the first floating diffusion region (FD1) and the second floating diffusion region (FD2) can receive and store charges from the photoelectric conversion units (PD1 to PD4) and (PD5 to PD8).

[0285] The reset transistors (RX1, RX2) are driven by a reset signal to provide a power supply voltage to the first floating diffusion region (FD1) or the second floating diffusion region (FD2). Therefore, charges stored in the first floating diffusion region (FD1) or the extended second floating diffusion region (FD2) can be transferred to the power supply voltage (VPIX) terminal, and the voltage of the first floating diffusion region (FD1) or the second floating diffusion region (FD2) can be reset.

[0286] The source follower transistors (S1, S2, S3, S4) may be connected between the power supply voltage (VPIX) and the selection transistor (SE). The source follower transistors (S1, S2, S3, S4) may output an output signal (Vout) to the selection transistor (SE) based on the voltage level of the first floating diffusion region (FD1) or the second floating diffusion region (FD2).

[0287] The dual conversion transistor (DCX) may be connected between the first floating diffusion region (FD1) and the second floating diffusion region (FD2) and the reset transistors (RX1, RX2). When the dual conversion transistor (DCX) is turned off, the full well capacity (FWC) of each pixel (PX1 to PX8) may be the capacitance of the first floating diffusion region (FD1) and the second floating diffusion region (FD2). When the dual conversion transistor (DCX) is turned on, the FWC of each pixel (PX1 to PX8) may be greater than the capacitance of the first floating diffusion region (FD1). The conversion gain of each pixel (PX1 to PX8) may be variable by turning on / off the dual conversion transistor (DCX).

[0288] Unlike the image sensors 1000, 1001, 1002, 1003, 1004, and 1005 according to the previously described embodiments, the image sensor 2000 according to this embodiment may include four source follower transistors (S1, S2, S3, and S4).

[0289] The source follower transistor includes a first source follower transistor (S1), a second source follower transistor (S2), a third source follower transistor (S3), and a fourth source follower transistor (S4), which can reduce the effects of thermal noise and flicker noise inherent to the source follower transistor element and increase the amount of current flowing through the source follower transistor during operation. This improves the linearity of the voltage-current graph of the source follower transistor and reduces source follower transistor noise.

[0290] 18, an image sensor 2000 according to this embodiment is similar to the image sensor 1000 according to the embodiment shown in Figures 4 to 7. A detailed description of the same components will be omitted.

[0291] Referring to FIG. 18, the image sensor 2000 according to this embodiment may further include a third pixel group (PG3) and a fourth pixel group (PG4) adjacent to the first pixel group (PG1) and the second pixel group (PG2) along the first direction (DR1).

[0292] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0293] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0294] The pixel separating structure (DTI) is removed from the area corresponding to the first floating diffusion region (FD1) shared by the first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4), and the pixel separating structure (DTI) may have a first open portion (OPN1) as shown in FIG. 6, and the first floating diffusion region (FD1) may not overlap with the pixel separating structure (DTI) along the third direction (DR3), which is the height direction.

[0295] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may include a first transmission gate electrode (TG1), a second transmission gate electrode (TG2), a third transmission gate electrode (TG3), and a fourth transmission gate electrode (TG4) located on the active region (AR), and the first floating diffusion region (FD1) may be formed in a portion of the active region (AR) and located on one side of the first transmission gate electrode (TG1), the second transmission gate electrode (TG2), the third transmission gate electrode (TG3), and the fourth transmission gate electrode (TG4).

[0296] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0297] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed integrally.

[0298] The pixel separating structure (DTI) is removed from the area corresponding to the second floating diffusion region (FD2) shared by the fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8), and the pixel separating structure (DTI) may have a second open portion (OPN2) as shown in FIG. 6, and the second floating diffusion region (FD2) may not overlap with the pixel separating structure (DTI) along the third direction (DR3), which is the height direction.

[0299] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may include a fifth transmission gate electrode (TG5), a sixth transmission gate electrode (TG6), a seventh transmission gate electrode (TG7), and an eighth transmission gate electrode (TG8) located on the active region (AR), and the second floating diffusion region (FD2) may be formed in a portion of the active region (AR) and located on one side of the fifth transmission gate electrode (TG5), the sixth transmission gate electrode (TG6), the seventh transmission gate electrode (TG7), and the eighth transmission gate electrode (TG8).

[0300] A first reset gate electrode (RG1) may be located over the active region (AR) of the first pixel (PX1) of the first pixel group (PG1), and a second reset gate electrode (RG2) may be located over the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) that is adjacent to the first pixel group (PG1) along the first direction (DR1) and absorbs and senses light of a different color from the first pixel group (PG1).

[0301] A first source follower gate electrode (SF1) may be located on the active region (AR) of the fourth pixel (PX4) of the first pixel group (PG1).

[0302] A second source follower gate electrode (SF2) may be located on the active region (AR) of the third pixel (PX3) of the third pixel group (PG3), which is adjacent to the first pixel group (PG1) along the first direction (DR1) and absorbs and senses light of a different color from the first pixel group (PG1).

[0303] A third source follower gate electrode (SF3) may be located on the active region (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4), which is adjacent to the second pixel group (PG2) along the first direction (DR1) and absorbs and senses light of a different color from the second pixel group (PG2).

[0304] A fourth source follower gate electrode (SF4) may be located on the active region (AR) of the fifth pixel (PX5) of the second pixel group (PG2).

[0305] The active area (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active area (AR) of the second pixel (PX2) of the third pixel group (PG3) may be connected via a first connecting part (CP1) and formed as a single unit.

[0306] The pixel separating structure (DTI) is removed from a region corresponding to the first connecting portion (CP1) between the active area (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active area (AR) of the second pixel (PX2) of the third pixel group (PG3), and the pixel separating structure (DTI) may have a third open portion (OPN3) as shown in FIG. 6, and the first connecting portion (CP1) may not overlap the pixel separating structure (DTI) along the third direction (DR3) in the height direction.

[0307] The active area (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active area (AR) of the second pixel (PX2) of the third pixel group (PG3) are connected to each other via a first connecting portion (CP1) that does not overlap with the pixel separating structure (DTI) and are integrally formed adjacent to the first surface (SFA) of the substrate 200, so that the first reset transistor (RX1) and the second reset transistor (RX2) may be directly connected to each other without using an additional wiring layer for connection.

[0308] The reset transistors (RX1, RX2) include a first reset transistor (RX1) and a second reset transistor (RX2) that are directly connected without using an additional wiring layer, thereby improving the performance of the reset transistors (RX1, RX2) without increasing the area occupied by the reset transistors (RX1, RX2).

[0309] The active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the third pixel (PX3) of the third pixel group (PG3), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active area (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4) may be connected via a second connecting part (CP2) and formed as a single unit.

[0310] The pixel separating structure (DTI) is removed from a region corresponding to a second connecting portion (CP2) between the active region (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active region (AR) of the third pixel (PX3) of the third pixel group (PG3), the active region (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active region (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4), and the pixel separating structure (DTI) may have a fourth open portion (OPN4) as shown in FIG. 6, and the second connecting portion (CP2) may not overlap the pixel separating structure (DTI) along the third direction (DR3), which is the height direction.

[0311] The active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the third pixel (PX3) of the third pixel group (PG3), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active area (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4) are connected to each other through the second connecting portion (CP2) that does not overlap with the pixel separating structure (DTI), and are integrally formed adjacent to the first surface (SFA) of the substrate 200, so that the first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the fourth source follower transistor (S4) may be directly connected to each other without using an additional wiring layer for connection.

[0312] The first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the fourth source follower transistor (S4) of the source follower transistors (S1, S2, S3, S4) may be directly connected without using an additional wiring layer, thereby preventing unnecessary coupling and resistance due to the additional wiring layer. Also, the performance of the source follower transistors (S1, S2, S3, S4) can be improved without increasing the area occupied by the source follower transistors (S1, S2, S3, S4).

[0313] Either one of the first gate electrode (GE1) located on the active area (AR) of the seventh pixel (PX7) of the second pixel group (PG2) and the second gate electrode (GE2) located on the active area (AR) of the eighth pixel (PX8) of the second pixel group (PG2) may be a selection gate electrode (SEL), and the other may be a dual conversion gate electrode (DCG).

[0314] The positions of the source follower transistors (S1 to S4), the selection transistor (SE), the reset transistors (RX1, RX2), and the dual conversion transistor (DCX) are not limited to these positions, and the positions of the source follower transistors (S1 to S4), the selection transistor (SE), the reset transistors (RX1, RX2), and the dual conversion transistor (DCX) can be changed in various ways so that multiple pixels (PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8) can share the source follower transistors (S1 to S4), the selection transistor (SE), the reset transistors (RX1, RX2), and the dual conversion transistor (DCX).

[0315] An image sensor 2001 according to another embodiment will be described with reference to Fig. 19. Fig. 19 is a plan view of the image sensor according to another embodiment.

[0316] 19, an image sensor 2001 according to this embodiment is similar to the image sensor 1002 according to the embodiment shown in Figures 9 and 10. A detailed description of the same components will be omitted.

[0317] The image sensor 2001 according to this embodiment may further include a third pixel group (PG3) and a fourth pixel group (PG4) adjacent to the first pixel group (PG1) and the second pixel group (PG2) along the first direction (DR1).

[0318] A first reset gate electrode (RG1) may be located over the active region (AR) of the first pixel (PX1) of the first pixel group (PG1), and a second reset gate electrode (RG2) may be located over the active region (AR) of the second pixel (PX2) of the first pixel group (PG1).

[0319] A first source follower gate electrode (SF1) may be located over the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), a second source follower gate electrode (SF2) may be located over the active area (AR) of the third pixel (PX3) of the third pixel group (PG3) adjacent to the first pixel group (PG1) along the first direction (DR1), and a third source follower gate electrode (SF3) may be located over the active area (AR) of the sixth pixel (PX6) of the fourth pixel group (PG4) adjacent to the second pixel group (PG2).

[0320] A fourth source follower gate electrode (SF4) may be located on the active region (AR) of the fifth pixel (PX5) of the second pixel group (PG2).

[0321] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0322] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0323] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0324] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed integrally.

[0325] an active area (AR) of a fourth pixel (PX4) of the first pixel group (PG1); an active area (AR) of a third pixel (PX3) of a third pixel group (PG3) that absorbs and senses light of a different color than that of the first pixel group (PG1); an active area (AR) of a fifth pixel (PX5) of a second pixel group (PG2) that absorbs and senses light of a different color than that of the first pixel group (PG1); and a fourth pixel group (PG2) that absorbs and senses light of a different color than that of the second pixel group (PG2). The active area (AR) of the sixth pixel (PX6) of (PG4) may be connected to the pixel separating structure (DTI) via a second connecting portion (CP2) that does not overlap with the pixel separating structure (DTI) and may be formed as one unit, and the first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the fourth source follower transistor (S4) may be directly connected without using the multiple vias (ML1) and wiring layers (ML2, ML3) of the first structure 300.

[0326] The source follower transistors (S1, S2, S3, S4) of the image sensor 2001 according to the embodiment may include a first source follower transistor (S1), a second source follower transistor (S2), a third source follower transistor (S3) and a fourth source follower transistor (S4) that are directly connected without using an additional wiring layer.

[0327] The first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the fourth source follower transistor (S4) of the source follower transistors (S1, S2, S3, S4) may be directly connected without using an additional wiring layer, thereby preventing unnecessary coupling and resistance due to the additional wiring layer. Also, the performance of the source follower transistors (S1, S2, S3, S4) can be improved without increasing the area occupied by the source follower transistors (S1, S2, S3, S4).

[0328] Unlike the image sensor 2000 according to the embodiment shown in FIG. 18, the first reset gate electrode (RG1) and the second reset gate electrode (RG2) of the image sensor 2001 according to the embodiment are located on the active areas (AR) of the first pixel (PX1) and the second pixel (PX2) of the first pixel group (PG1), and the first reset transistor (RX1) and the second reset transistor (RX2) may not be directly connected but may be connected by an additional wiring layer.

[0329] Many of the features of the image sensor according to the embodiment described above are all applicable to the image sensor according to this embodiment.

[0330] An image sensor 2002 according to another embodiment will be described with reference to Fig. 20. Fig. 20 is a plan view of the image sensor according to another embodiment.

[0331] 20, an image sensor 2002 according to this embodiment is similar to the image sensor 1003 according to the embodiment shown in Figures 11 and 12. A detailed description of the same components will be omitted.

[0332] The image sensor 2002 according to this embodiment may further include a third pixel group (PG3) and a fourth pixel group (PG4) adjacent to the first pixel group (PG1) and the second pixel group (PG2) along the first direction (DR1).

[0333] A first reset gate electrode (RG1) may be located over the active region (AR) of the first pixel (PX1) of the first pixel group (PG1), and a second reset gate electrode (RG2) may be located over the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) adjacent to the first pixel group (PG1) along the first direction (DR1) and absorbing and sensing light of a different color from that of the first pixel group (PG1).

[0334] A first source follower gate electrode (SF1) may be located over the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), and a second source follower gate electrode (SF2) may be located over the active area (AR) of the third pixel (PX3) of the first pixel group (PG1).

[0335] A third source follower gate electrode (SF3) may be located over the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and a fourth source follower gate electrode (SF4) may be located over the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2).

[0336] Either one of the first gate electrode (GE1) located on the active area (AR) of the seventh pixel (PX7) of the second pixel group (PG2) and the second gate electrode (GE2) located on the active area (AR) of the eighth pixel (PX8) of the second pixel group (PG2) may be a selection gate electrode (SEL), and the other may be a dual conversion gate electrode (DCG).

[0337] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0338] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0339] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0340] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed integrally.

[0341] The active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) may be connected via a first connecting portion (CP1) and formed as an integral unit. The first connecting portion (CP1) between the active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0342] The active area (AR) of the third pixel (PX3) of the first pixel group (PG1), the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2) may not be directly connected to each other, but may be connected by using an additional wiring layer.

[0343] Many of the features of the image sensor according to the embodiment described above are all applicable to the image sensor according to this embodiment.

[0344] An image sensor 2003 according to another embodiment will be described with reference to Fig. 21. Fig. 21 is a plan view of the image sensor according to another embodiment.

[0345] 21, an image sensor 2003 according to this embodiment is similar to the image sensor 1004 according to the embodiment shown in Figures 13 and 14. A detailed description of the same components will be omitted.

[0346] The image sensor 2003 according to this embodiment may further include a third pixel group (PG3) and a fourth pixel group (PG4) adjacent to the first pixel group (PG1) and the second pixel group (PG2) along the first direction (DR1).

[0347] A first reset gate electrode (RG1) may be located over the active region (AR) of the first pixel (PX1) of the first pixel group (PG1), and a second reset gate electrode (RG2) may be located over the active region (AR) of the second pixel (PX2) of the first pixel group (PG1).

[0348] A first source follower gate electrode (SF1) may be located over the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), and a second source follower gate electrode (SF2) may be located over the active area (AR) of the third pixel (PX3) of the first pixel group (PG1).

[0349] A third source follower gate electrode (SF3) may be located over the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and a fourth source follower gate electrode (SF4) may be located over the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2).

[0350] Either one of the first gate electrode (GE1) located on the active area (AR) of the seventh pixel (PX7) of the second pixel group (PG2) and the second gate electrode (GE2) located on the active area (AR) of the eighth pixel (PX8) of the second pixel group (PG2) may be a selection gate electrode (SEL), and the other may be a dual conversion gate electrode (DCG).

[0351] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0352] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0353] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0354] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed integrally.

[0355] The active area (AR) of the third pixel (PX3) of the first pixel group (PG1), the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a color different from that of the first pixel group (PG1), and the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2) may be connected via a fourth connecting part (CP4) and formed as a single unit, and the first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the fourth source follower transistor (S4) may be directly connected without using additional wiring.

[0356] The source follower transistors (S1, S2, S3, S4) of the image sensor 2003 according to the embodiment may include a first source follower transistor (S1), a second source follower transistor (S2), a third source follower transistor (S3) and a fourth source follower transistor (S4) that are directly connected without using an additional wiring layer.

[0357] The first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the fourth source follower transistor (S4) of the source follower transistors (S1, S2, S3, S4) may be directly connected without using an additional wiring layer, thereby preventing unnecessary coupling and resistance due to the additional wiring layer. Also, the performance of the source follower transistors (S1, S2, S3, S4) can be improved without increasing the area occupied by the source follower transistors (S1, S2, S3, S4).

[0358] The first reset gate electrode (RG1) and the second reset gate electrode (RG2) of the image sensor 2003 according to this embodiment are located on the active regions (AR) of the first pixel (PX1) and the second pixel (PX2) of the first pixel group (PG1), and the first reset transistor (RX1) and the second reset transistor (RX2) may not be directly connected.

[0359] Many of the features of the image sensor according to the embodiment described above are all applicable to the image sensor according to this embodiment.

[0360] An image sensor 2004 according to another embodiment will be described with reference to Fig. 22. Fig. 22 is a plan view of the image sensor according to another embodiment.

[0361] 22, an image sensor 2004 according to this embodiment is similar to the image sensor 1005 according to the embodiment shown in Figures 15 and 16. A detailed description of the same components will be omitted.

[0362] The image sensor 2004 according to this embodiment may further include a third pixel group (PG3) and a fourth pixel group (PG4) adjacent to the first pixel group (PG1) and the second pixel group (PG2) along the first direction (DR1).

[0363] A first reset gate electrode (RG1) may be located over the active region (AR) of the first pixel (PX1) of the first pixel group (PG1), and a second reset gate electrode (RG2) may be located over the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) adjacent to the first pixel group (PG1) along the first direction (DR1) and absorbing and sensing light of a different color from that of the first pixel group (PG1).

[0364] A first source follower gate electrode (SF1) may be located over the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), and a second source follower gate electrode (SF2) may be located over the active area (AR) of the third pixel (PX3) of the first pixel group (PG1).

[0365] A third source follower gate electrode (SF3) may be located over the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and a fourth source follower gate electrode (SF4) may be located over the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2).

[0366] Either one of the first gate electrode (GE1) located on the active area (AR) of the seventh pixel (PX7) of the second pixel group (PG2) and the second gate electrode (GE2) located on the active area (AR) of the eighth pixel (PX8) of the second pixel group (PG2) may be a selection gate electrode (SEL), and the other may be a dual conversion gate electrode (DCG).

[0367] The first pixel (PX1), the second pixel (PX2), the third pixel (PX3), and the fourth pixel (PX4) of the first pixel group (PG1) may share a first floating diffusion region (FD1).

[0368] The first floating diffusion region (FD1) may be located in a portion of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) of the first pixel group (PG1), and the first floating diffusion region (FD1) of each of the first pixel (PX1), second pixel (PX2), third pixel (PX3), and fourth pixel (PX4) may be formed integrally.

[0369] The fifth pixel (PX5), the sixth pixel (PX6), the seventh pixel (PX7), and the eighth pixel (PX8) of the second pixel group (PG2) may share the second floating diffusion region (FD2).

[0370] The second floating diffusion region (FD2) may be located in a portion of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) of the second pixel group (PG2), and the second floating diffusion region (FD2) of each of the fifth pixel (PX5), sixth pixel (PX6), seventh pixel (PX7), and eighth pixel (PX8) may be formed integrally.

[0371] The active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) may be connected via a first connecting portion (CP1) and formed as an integral unit. The first connecting portion (CP1) between the active region (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active region (AR) of the second pixel (PX2) of the third pixel group (PG3) may not overlap with the pixel separating structure (DTI) along a third direction (DR3), which is the height direction.

[0372] The active area (AR) of the third pixel (PX3) of the first pixel group (PG1), the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a different color from that of the first pixel group (PG1), and the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2) may be connected to each other via a fourth connecting part (CP4) and formed as a single unit.

[0373] The fourth connecting portion (CP4) between the active area (AR) of the third pixel (PX3) of the first pixel group (PG1), the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2), and the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2) may not overlap with the pixel separating structure (DTI) along the third direction (DR3), which is the height direction.

[0374] The active area (AR) of the first pixel (PX1) of the first pixel group (PG1) and the active area (AR) of the second pixel (PX2) of the third pixel group (PG3), which absorbs and senses light of a different color from that of the first pixel group (PG1), are connected via a first connecting part (CP1) and formed as a single unit, and the first reset transistor (RX1) and the second reset transistor (RX2) may be directly connected without using the multiple vias (ML1) and multiple wiring layers (ML2, ML3) of the first structure 300.

[0375] The active area (AR) of the third pixel (PX3) of the first pixel group (PG1), the active area (AR) of the fourth pixel (PX4) of the first pixel group (PG1), the active area (AR) of the fifth pixel (PX5) of the second pixel group (PG2) that absorbs and senses light of a color different from that of the first pixel group (PG1), and the active area (AR) of the sixth pixel (PX6) of the second pixel group (PG2) are connected via a fourth connecting part (CP4) and formed as a single unit, and the first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the fourth source follower transistor (S4) may be directly connected without using an additional wiring layer.

[0376] The reset transistors (RX1, RX2) include a first reset transistor (RX1) and a second reset transistor (RX2) that are directly connected without using an additional wiring layer, thereby improving the performance of the reset transistors (RX1, RX2) without increasing the area occupied by the reset transistors (RX1, RX2).

[0377] The source follower transistors (S1, S2, S3, S4) may include a first source follower transistor (S1), a second source follower transistor (S2), a third source follower transistor (S3) and a fourth source follower transistor (S4) that are directly coupled without using an additional wiring layer.

[0378] The first source follower transistor (S1), the second source follower transistor (S2), the third source follower transistor (S3), and the fourth source follower transistor (S4) of the source follower transistors (S1, S2, S3, S4) may be directly connected without using an additional wiring layer, thereby preventing unnecessary coupling and resistance due to the additional wiring layer. Also, the performance of the source follower transistors (S1, S2, S3, S4) can be improved without increasing the area occupied by the source follower transistors (S1, S2, S3, S4).

[0379] Many of the features of the image sensor according to the previously described embodiments are all applicable to the image sensor according to this embodiment.

[0380] The stacked structure of the image sensor 3000 according to the embodiment will be briefly described with reference to Fig. 23. Fig. 23 shows a simplified stacked structure of an image sensor according to another embodiment.

[0381] 23 , an image sensor 3000 according to some embodiments may include a first semiconductor chip 10 and a second semiconductor chip 20. The first semiconductor chip 10 and the second semiconductor chip 20 may overlap each other along the height direction. The first semiconductor chip 10 and the second semiconductor chip 20 may be stacked in the vertical direction.

[0382] The photoelectric conversion layers (PD1 to PD8), transfer transistors (T1 to T8), reset transistors (RX1, RX2), source follower transistors (S1 to S4), selection transistors (SE), and dual conversion transistors (DCX) of the image sensors according to the previously described embodiments may be formed on the first semiconductor chip 10.

[0383] The second semiconductor chip 20 may include the logic circuit of FIG.

[0384] Although not shown, an image sensor according to another embodiment may further include a memory cell array in the second semiconductor chip 20. The memory cell array can store data based on digital signals.

[0385] Many of the features of the image sensor according to the embodiment described above are all applicable to the stacked structure of the image sensor according to this embodiment.

[0386] The stacked structure of the image sensor 4000 according to the embodiment will be briefly described with reference to Fig. 24. Fig. 24 shows a simplified stacked structure of an image sensor according to another embodiment.

[0387] 24 , an image sensor 4000 according to some embodiments may include a first semiconductor chip 10, a second semiconductor chip 20, and a third semiconductor chip 30. The first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 may be stacked in the height direction. The first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 may be stacked sequentially in the vertical direction. The first semiconductor chip 10 may be an upper plate, the second semiconductor chip 20 may be a middle plate, and the third semiconductor chip 30 may be a lower plate.

[0388] The photoelectric conversion units (PD1 to PD8) and transfer transistors (T1 to T8) of the image sensor according to the previously described embodiments may be formed on the first semiconductor chip 10, and the reset transistors (RX1, RX2), dual conversion transistor (DCX), source follower transistors (S1 to S4), and selection transistor (SE) may be formed on the second semiconductor chip 20.

[0389] The third semiconductor chip 30 may include the logic circuit of FIG.

[0390] Alternatively, the first semiconductor chip 10 and the second semiconductor chip 20 may be formed in one chip.

[0391] The first semiconductor chip 10 and the second semiconductor chip 20 may each include a pixel array, or may be a 3-stack image sensor formed on different chips and stacked together.

[0392] Many of the features of the image sensor according to the embodiment described above are all applicable to the stacked structure of the image sensor according to this embodiment.

[0393] Although the preferred embodiment of the present invention has been described above, the present invention is not limited to this, and various modifications are possible within the scope of the claims, the detailed description of the invention, and the accompanying drawings, and it is natural that these modifications are also included within the scope of the present invention.

[0394] [Explanation of symbols] 1000, 1001, 1002, 1003, 1004, 1005, 2000, 2001, 2002, 2003, 2004 Image Sensors PX, PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8 pixels PG1, PG2, PG3, PG4 pixel groups CF, CF1, CF2, CF3 color filters PD, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8 photoelectric conversion unit FD1, FD2 floating diffusion regions AR active area DTI pixel isolation structure OPN1, OPN2, OPN3, OPN4, OPN5, OPN6 Open section TG1 to TG8, RG1, RG2, SF1, SF2, SF3, SF4, SEL, GE1, GE2 gate electrodes GNL ground area T1, T2, T3, T4, T5, T6, T7, T8 transfer transistors RX1, RX2 reset transistors S1, S2, S3, S4 Source follower transistors SE select transistor DCX Dual Conversion Transistor

Claims

1. An image sensor, the image sensor comprising: a first pixel that senses a first color; a second pixel sensing a second color different from the first color; a first active area located in the first pixel; and a second active region located in the second pixel; the first active region and the second active region are directly connected to each other; Image sensor.

2. further comprising a pixel separating structure located between the first pixel and the second pixel and in the substrate; the first active region and the second active region are connected to each other via a connection portion; The image sensor of claim 1 , wherein the first active region, the second active region, and the connecting portion do not overlap the pixel separating structure along a height direction.

3. the substrate includes a first surface and a second surface facing each other; the pixel separating structure extends through the second surface; The image sensor of claim 2 , wherein the first active region, the second active region, and the connecting portion are positioned adjacent to the first surface of the substrate.

4. a first gate electrode located over the first active region; and a second gate electrode located over the second active region; the first gate electrode is a first source follower gate electrode, The image sensor of claim 2 , wherein the second gate electrode is a second source follower gate electrode.

5. a third pixel adjacent to the first pixel along a first direction and sensing a color different from the first color; a fourth pixel adjacent to the second pixel along the first direction and sensing a color different from the second color; a third active region located in the third pixel; and a fourth active region located in the fourth pixel; The image sensor of claim 4 , wherein the first active region and the second active region are directly connected to the third active region and the fourth active region.

6. a third gate electrode located over the third active region; and a fourth gate electrode located over the fourth active region; 6. The image sensor of claim 5, wherein one of the third gate electrode and the fourth gate electrode is a third source follower gate electrode.

7. The image sensor of claim 6 , wherein the remaining one of the third gate electrode and the fourth gate electrode is a select gate electrode.

8. The image sensor of claim 6 , wherein the remaining one of the third gate electrode and the fourth gate electrode is a fourth source follower gate electrode.

9. a third pixel adjacent to the first pixel along a first direction and sensing the first color; a fourth pixel adjacent to the second pixel along the first direction and sensing the second color; a third active region located in the third pixel; and a fourth active region located in the fourth pixel; The image sensor of claim 4 , wherein the first active region and the second active region are directly connected to the third active region and the fourth active region.

10. a third gate electrode located over the third active region; and a fourth gate electrode located over the fourth active region; 10. The image sensor of claim 9, wherein one of the third gate electrode and the fourth gate electrode is a third source follower gate electrode.

11. The image sensor of claim 10 , wherein the remaining one of the third gate electrode and the fourth gate electrode is a select gate electrode.

12. The image sensor of claim 10 , wherein the remaining one of the third gate electrode and the fourth gate electrode is a fourth source follower gate electrode.

13. a first gate electrode located over the first active region; and a second gate electrode located over the second active region; the first gate electrode is a first reset gate electrode, The image sensor of claim 2 , wherein the second gate electrode is a second reset gate electrode.

14. An image sensor, the image sensor comprising: a first pixel group including a plurality of pixels including a first pixel and sensing a first color; and a second pixel group including a plurality of pixels including a second pixel adjacent to the first pixel group, the second pixel group sensing a second color different from the first color; the first pixel group and the second pixel group share a reset transistor, a source follower transistor, and a selection transistor; the source follower transistors include a first source follower transistor located in the first pixel and a second source follower transistor located in the second pixel; the first source follower transistor and the second source follower transistor are directly connected; Image sensor.

15. a third pixel group including a plurality of pixels including a third pixel, the third pixel group being adjacent to the first pixel group along a first direction and sensing a color different from the first color; and a fourth pixel group including a plurality of pixels including a fourth pixel, the fourth pixel group being adjacent to the second pixel group along the first direction and sensing a color different from the second color; the source follower transistor further includes a third source follower transistor located in the third pixel; The image sensor of claim 14 , wherein the third source follower transistor is directly coupled to the first source follower transistor and the second source follower transistor.

16. the selection transistor is located in the fourth pixel; The image sensor of claim 15 , wherein the source follower transistor is directly coupled to the select transistor.

17. the source follower transistor further includes a fourth source follower transistor located in the fourth pixel; The image sensor of claim 15 , wherein the fourth source follower transistor is directly coupled to the first source follower transistor, the second source follower transistor, and the third source follower transistor.

18. a third pixel included in the first pixel group; a fourth pixel included in the second pixel group; the source follower transistor further includes a third source follower transistor located in the third pixel; The image sensor of claim 14 , wherein the third source follower transistor is directly coupled to the first source follower transistor and the second source follower transistor.

19. the selection transistor is located in the fourth pixel; The image sensor of claim 18 , wherein the source follower transistor is directly coupled to the select transistor.

20. the source follower transistor further includes a fourth source follower transistor located in the fourth pixel; 20. The image sensor of claim 18, wherein the fourth source follower transistor is directly coupled to the first source follower transistor, the second source follower transistor, and the third source follower transistor.

Images