Computation apparatus, test apparatus, computation method, and computation program

Abstract

SOLUTION: A computation apparatus comprises a plurality of memory banks and a computation processing unit that generates a result data sequence obtained by computation of a plurality of data sequences by repeating processes of reading the data sequence from a source memory bank among the plurality of memory banks, performing computation between the read data sequence and the next data sequence, and writing the data sequence obtained as a result of the computation into a destination memory bank among the plurality of memory banks while alternately switching the source memory bank and the destination memory bank.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a computing device, a test device, a computing method, and a computing program. [Background technology]

[0002] Patent Document 1 describes an image sensor tester that "takes in image signals output from terminals in contact with the image sensor under test, processes the images, and determines whether the sensor is good or bad" (Claim 1 of Patent Document 1). [Prior art document] [Patent documents] [Patent Document 1] Japanese Patent Application Laid-Open No. 4-3686 Summary of the Invention

[0003] In a first aspect of the present invention, there is provided an arithmetic device comprising a plurality of memory banks and an arithmetic processing unit that generates a data string as a result of calculating a plurality of data strings by repeating the process of reading a data string from a source memory bank among the plurality of memory banks, calculating it with a next data string, and writing the data string obtained as a result of the calculation to a destination memory bank among the plurality of memory banks while alternating between the source memory bank and the destination memory bank.

[0004] In the above-mentioned calculation device, the calculation processing unit may perform parallel processing of reading a data string from the source memory bank, performing an operation between the data string read from the source memory bank and the next data string, and writing the data string obtained as a result of the operation to the destination memory bank.

[0005] Any of the above arithmetic devices may include a result output section that reads and outputs the result data string from a result memory bank that is the destination memory bank that stores the result data string among the plurality of memory banks.

[0006] In any of the above-mentioned calculation devices, the calculation processing unit may generate the result data string by summing the multiple data strings for each corresponding data element, and the result output unit may divide the result data string for each data element by the number of data strings included in the multiple data strings and output the result data string.

[0007] In any of the above-mentioned arithmetic devices, the arithmetic processing unit may write the first result data string obtained by operating on the first of the plurality of data strings to the result memory bank, and then perform an operation on the second of the plurality of data strings using two memory banks among the plurality of memory banks different from the result memory bank as the source memory bank and the destination memory bank, and the result output unit may read out the first result data string from the result memory bank in parallel with the operation of the second of the plurality of data strings by the arithmetic processing unit.

[0008] In any of the above-mentioned arithmetic devices, the arithmetic processing unit may use the first memory bank and the second memory bank among the plurality of memory banks as the result memory bank, and may not select the third memory bank among the plurality of memory banks as the write destination for the result data string.

[0009] In any of the above-mentioned computing devices, in response to a failure of at least one memory bank among the plurality of memory banks, the computing processing unit may assign the source memory bank and the destination memory bank to the same memory bank.

[0010] In any of the above-described computing devices, each of the plurality of data strings may include image data.

[0011] In a second aspect of the present invention, there is provided a test apparatus for testing a device under test which is an imaging device, comprising: an image data receiving unit that receives a plurality of data strings each containing image data captured by the device under test; an arithmetic device as described in claim 1 that generates a result data string by calculating the plurality of data strings; and an image processing device that inspects the result data string.

[0012] In a third aspect of the present invention, there is provided an arithmetic method in which an arithmetic device having a plurality of memory banks reads a data string from a source memory bank among the plurality of memory banks, performs an operation with a next data string, and writes the data string obtained as a result of the operation to a destination memory bank among the plurality of memory banks, repeating this process while alternating between the source memory bank and the destination memory bank, thereby generating a data string as a result of operating on a plurality of data strings.

[0013] In a fourth aspect of the present invention, there is provided an arithmetic program that is executed by a computer and causes the computer to function as an arithmetic processing unit that generates a data string as a result of calculating a plurality of data strings by repeating the process of reading a data string from a source memory bank among a plurality of memory banks, calculating it with a next data string, and writing the data string obtained as a result of the calculation to a destination memory bank among the plurality of memory banks, while alternating between the source memory bank and the destination memory bank.

[0014] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0015] [Figure 1] 1 shows the configuration of a test device 10 according to this embodiment. [Figure 2] 1 shows the configuration of a capture module 200 and an image processing device 194 according to this embodiment. [Figure 3] 1 shows a test flow of the test device 10 according to the present embodiment. [Figure 4] 1 shows the configuration of a calculation device 300 according to this embodiment. [Figure 5] 3 shows a calculation flow of the calculation device 300 according to the present embodiment. [Figure 6] 2 shows an operating state of the arithmetic device 300 according to the present embodiment. [Figure 7] 2 shows an operating state of the arithmetic device 300 according to the present embodiment. [Figure 8] 22 illustrates an example computer 2200 in which aspects of the present invention may be embodied, in whole or in part. DETAILED DESCRIPTION OF THE INVENTION

[0016] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0017] 1 shows the configuration of a test apparatus 10 according to this embodiment, together with a device under test 20. The device under test 20 includes one or more devices, each of which has a circuit to be tested by the test apparatus 10, formed therein, as a device under test (DUT). The DUT according to this embodiment is a photoelectric conversion device that detects light and converts it into an electrical signal. The DUT may be an imaging device such as a CMOS image sensor or other image sensor that converts an incident optical image into image data.

[0018] The device under test 20 may be a wafer on which a circuit is formed, each IC / LSI chip circuit formed on the wafer, an IC / LSI chip obtained by dividing the wafer, or an IC / LSI package in which IC / LSI chips are packaged. In the example shown in the figure, the test apparatus 10 mounts the device under test 20, which is a wafer on which multiple imaging devices are formed, and tests each imaging device. The test apparatus 10 may test each imaging device one by one, or may test two or more imaging devices simultaneously.

[0019] The test apparatus 10 performs an optical input test on the DUT. Alternatively, or in addition, the test apparatus 10 may perform an electrical test on the DUT. In this embodiment, an example will be described in which the test apparatus 10 performs an imaging test on the DUT, which is an imaging device.

[0020] The test apparatus 10 includes a prober apparatus 100, a test head 150, a rotation device 180, and a main frame 190. The prober apparatus 100 includes a stage 102, a probe card 104, and a connection unit 120.

[0021] The stage 102 places the DUT 20 on it. The stage 102 may have a vacuum chuck, an electrostatic chuck, or the like on its upper surface to fix the DUT 20 in place.

[0022] The probe card 104 is provided above the stage 102. The probe card 104 includes one or more probes 106 and a light-shielding unit 108. The one or more probes 106 are provided on the surface of the probe card 104 facing the stage 102, and are connected to respective electrodes of the DUT to be tested on the device under test 20. The probe card 104 includes one or more connectors connected to a connection unit 120 on the surface opposite the stage 102, and each probe 106 is electrically connected to a performance board 130 on the test head 150 side via the corresponding connector and connection unit 120.

[0023] The light-shielding unit 108 is disposed in an opening provided in the probe card 104. The light-shielding unit 108 may have an opening through which test light to be irradiated onto the DUT passes, and a light-shielding wall disposed around the opening to block stray light.

[0024] The connection unit 120 is provided above the probe card 104. The connection unit 120 has an opening that allows the test light to pass through. The connection unit 120 electrically connects one or more connectors of the probe card 104 to the performance board 130 of the test head 150. The probe card 104 and connection unit 120 described above may be interchangeable depending on the type of device under test 20 or DUT, etc.

[0025] The test head 150 tests a DUT on a device under test 20 placed on a stage 102 of the prober apparatus 100. The test head 150 includes a performance board 130, a HiFix 140, one or more test modules 160a-d (also referred to as "test modules 160"), a light source 170, and a lens barrel 175.

[0026] The performance board 130 and the HiFix 140 are provided on the surface of the test head 150 facing the connection unit 120. The performance board 130 and the HiFix 140 have openings that allow test light to pass through. The performance board 130 and the HiFix 140 electrically connect the connection unit 120 and each test module 160, thereby electrically connecting the terminals of each test module 160 to corresponding electrodes of the DUT via the connection unit 120, the probe card 104, and each probe 106. The performance board 130 includes one or more connectors connected to the connection unit 120 and one or more connectors on the HiFix 140 side. The HiFix 140 accommodates cables and the like that connect each of the multiple terminals of the connectors on the HiFix 140 side of the performance board 130 to the terminals of the corresponding test modules 160.

[0027] Each of the one or more test modules 160 is inserted into a slot in the test head 150 and removably connected to the backplane (upper side in the figure) of the test head 150. The test modules 160 may also be referred to as "pin electronics cards" or "tester boards." Each test module 160 is electrically connected to a DUT on the device under test 20 via a HIFIX 140 and a performance board 130 mounted on the test head 150, and a connection unit 120 and a probe card 104 mounted on the prober device 100, or other connection devices. The one or more test modules 160 input and output signals to and from the DUT, and test the DUT by inspecting signals input from the DUT.

[0028] At least one test module 160 exchanges signals with the DUT, which is an imaging device, via electrical signal lines to configure the DUT and capture the image of the test light. At least one test module 160 receives image data of an image captured by the DUT from the DUT and supplies the image data to an image processing device 194 in the mainframe 190. In addition, at least one test module 160 may function as a power supply that supplies power to the DUT.

[0029] The light source 170 is disposed on the surface of the test head 150 opposite to the surface on which the performance board 130 and the HiFix 140 are placed. The light source 170 emits test light to irradiate the DUT. The lens barrel 175 is provided in the range from the light source 170 to the performance board 130, and guides the test light from the light source 170 to the opening of the performance board 130.

[0030] The rotation device 180 holds the test head 150 rotatably around a rotation axis. When testing a DUT, the rotation device 180 rotates the test head 150 to a test position where the performance board 130 of the test head 150 is electrically connected to the connection unit 120 of the prober device 100, as shown in the figure. Furthermore, when installing or replacing the performance board 130 and the HiFix 140, or inserting or removing a test module 160, the rotation device 180 rotates the test head 150 to a maintenance position where the surface of the test head 150 on which the performance board 130 and the HiFix 140 are placed faces upward.

[0031] The mainframe 190 is connected to the prober apparatus 100 and the test head 150. The mainframe 190 has a system controller 192 and an image processing device 194. The system controller 192 is connected to the prober apparatus 100, the test head 150, and the image processing device 194, and controls the testing of the DUT. In response to receiving a signal from the prober apparatus 100 indicating that the DUT of the device under test 20 has been contacted with one or more probes 106, the system controller 192 controls each part of the test head 150, including one or more test modules 160, to test the DUT.

[0032] The system controller 192 may be a personal computer (PC), workstation, server computer, general-purpose computer, or other computer, or may be a computer system in which multiple computers are connected. Such a computer system is also considered a computer in the broad sense. The system controller 192 may also be implemented by one or more virtual computer environments executable within a computer. Alternatively, the system controller 192 may be a dedicated computer designed for test control, or may be dedicated hardware implemented using dedicated circuitry.

[0033] The image processing device 194 is connected to the system controller 192 and the test head 150. The image processing device 194 receives, from the test module 160 in the test head 150, image data of an image captured by the DUT capturing test light, or image data of an image captured when the DUT is not receiving light. The image processing device 194 processes the received image data to determine whether the captured image meets the image quality standards of the imaging device as the DUT. Note that the image processing device 194 may be connected to one test head 150 as shown in this figure, or may be connected to multiple test heads 150. When the image processing device 194 is connected to multiple test heads 150, the image processing device 194 receives image data from each DUT being tested in the multiple test heads 150 and inspects the image data.

[0034] The image processing device 194 may be a PC (personal computer), a workstation, a server computer, a general-purpose computer, or any other computer, or may be a computer system in which multiple computers are connected. Such a computer system is also considered a computer in a broad sense. The image processing device 194 may also be implemented as one or more virtual computer environments executable within a computer. Alternatively, the image processing device 194 may be a dedicated computer designed for image processing, or may be dedicated hardware realized by dedicated circuitry.

[0035] 2 shows the configuration of a capture module 200 and an image processing device 194 according to this embodiment. Of the multiple test modules 160 shown in FIG. 1, the capture module 200 functions as a test module 160 (e.g., test module 160c) that captures image data of an image captured by the DUT from the DUT. The test head 150 may be equipped with one or more capture modules 200. Here, the image data of the captured image includes multiple data elements with a predetermined bit width, and is therefore also referred to as an "image data string" or simply a "data string."

[0036] The capture module 200 includes one or more capture blocks 210 (in the example of this figure, "capture blocks 210-1 to 210-4"), one or more signal transmitters 250 (in the example of this figure, "signal transmitters 250-1 to 2"), and a module IF (module interface) 255.

[0037] Each capture block 210 is provided corresponding to one or more DUTs to be tested. The capture block 210 is electrically connected to the DUT to be tested and captures image data streams from the DUT. The capture block 210 includes an image data receiving section 220, a capture unit 230, and one or more memory banks 240a-c (also referred to as "memory banks 240").

[0038] The image data receiving unit 220 is electrically connected to the DUT under test. The image data receiving unit 220 receives a data stream from the DUT. The image data receiving unit 220 may receive multiple data streams, each containing image data captured by the DUT. The image data receiving unit 220 has an image input interface that matches an image output interface implemented in the DUT under test. The image data receiving unit 220 may be a PHY chip or PHY board that complies with a physical layer (PHY) standard such as MIPI (Mobile Industry Processor Interface, registered trademark). In this case, the image data receiving unit 220 can receive an image data stream from a DUT that has an interface that complies with such a PHY standard.

[0039] The capture unit 230 is connected to the image data receiving section 220 and one or more memory banks 240. The capture unit 230 receives a data stream from the image data receiving section 220 and temporarily stores it in one or more memory banks 240. In response to a request from the image processing device 194, the capture unit 230 transmits the data stream stored in the one or more memory banks 240 to the image processing device 194.

[0040] The capture unit 230 may sequentially receive multiple data sequences corresponding to multiple captured images captured by the DUT under the same or different test light. The capture unit 230 may generate a data sequence by aggregating the multiple data sequences through calculations and transmit the resulting data sequence to the image processing device 194 as the data sequence to be inspected. For example, the capture unit 230 may generate the data sequence to be inspected by calculating the sum, average, maximum value, minimum value, or other statistical quantity for each corresponding pixel of the data sequences of the multiple captured images, or by performing a pre-specified filter process on the data sequences of the multiple captured images. The capture unit 230 may temporarily store intermediate data sequences in one or more memory banks 240 while calculating the data sequence to be inspected from the image data sequences of the multiple captured images.

[0041] One or more memory banks 240 are connected to the capture unit 230. Each memory bank 240 may be a memory device or a memory module such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). Each memory bank 240 may be composed of two or more memory devices or memory modules.

[0042] One or more signal transmitters 250 are connected to one or more capture blocks 210. Each signal transmitter 250 may be connected to all capture blocks 210 in the capture module 200, may be connected to two or more capture blocks 210 in the capture module 200, or may be connected to one capture block 210. In the example shown in the figure, the capture module 200 has four capture blocks 210 and two signal transmitters 250, and each signal transmitter 250 is connected to the four capture blocks 210.

[0043] The signal transmitter 250 is connected to a signal transmitter 290 in the oppositely connected image processing device 194 via a communication cable, and transmits and receives signals such as electrical signals or optical signals to and from the signal transmitter 290. As an example, the signal transmitter 250 may be an optical transceiver conforming to the QSFP (Quad Small Form-factor Pluggable) standard or the like. When the signal transmitter 250 is an optical transceiver conforming to the QSFP standard, the signal transmitter 250 is connected to the opposite signal transmitter 290 via a four-lane optical fiber.

[0044] The module IF 255 is connected to each capture block 210 and other circuits in the capture module 200, and to the system controller 192. The module IF 255 relays access from the system controller 192 to each circuit in the capture module 200, thereby enabling the system controller 192 to control each circuit in the capture module 200.

[0045] The image processing device 194 includes an image processing engine 270 and one or more CAPIFs 280-1 to 280-8 (also referred to as "CAPIF 280"). The image processing engine 270 inspects the image data stream of each DUT received from the capture module 200. The image processing engine 270 may be a computer main body including a CPU, memory, and input / output devices, and may also include an external storage device as needed. The image processing engine 270 may be equipped with one or more image processing accelerators, such as a graphics processing unit (GPU), to speed up image processing. The image processing engine 270 may be equipped with one or more image processing accelerators on a peripheral bus, such as PCI Express (registered trademark). Alternatively, the image processing engine 270 may be a dedicated computer or dedicated circuit designed specifically for image processing of the test apparatus 10.

[0046] The CAPIF (capture interface) 280 is an interface device for communicatively connecting the image processing engine 270 to the capture block 210 in the capture module 200. The CAPIF 280 may be mounted on a peripheral bus such as PCI Express (registered trademark) that the image processing engine 270 has. Each of one or more CAPIFs 280-1 to 280-8 includes one or more signal transmitters 290-1 to 290-8, and communicates with the capture unit 230 in the capture block 210 via the corresponding signal transmitter 290 and the signal transmitter 250 connected opposite to the signal transmitter 290.

[0047] 1 and 2 are merely examples. The test apparatus 10 may have a structure suited to the test method (wafer test, chip test, IC / LSI test, etc.), the type of test (functional test, parametric test, etc.), and the scale of the test. For example, instead of being located within the mainframe 190, the image processing device 194 may be installed in a location remote from the main body of the test apparatus 10 and connected to the main body of the test apparatus 10 via a communications network. The image processing device 194 may be realized by a cloud server capable of communicating with the main body of the test apparatus 10 via the Internet.

[0048] FIG. 3 shows a test flow of the test apparatus 10 according to this embodiment. In step 300 (S300), the test apparatus 10 is configured according to the DUT. Specifically, the rotation device 180 rotates the test head 150 to the maintenance position. The test head 150 is equipped with a light source 170 corresponding to the DUT. Various test modules 160 selected according to the type and number of DUTs are inserted into the test head 150 from the top side in the maintenance position. In addition, a HiFix 140 and a performance board 130 corresponding to the DUT are placed and fixed on the top surface of the test head 150. A probe card 104 and a connection unit 120 corresponding to the DUT are placed on the prober apparatus 100. Once the configuration of the test apparatus 10 is complete, the rotation device 180 rotates the test head 150 to the test position.

[0049] In S310, the prober apparatus 100 connects one or more DUTs to be tested among the DUTs formed on the device under test 20 to the probe card 104 of the test apparatus 10. Specifically, the prober apparatus 100 transports the device under test 20 and places it on the stage 102. The prober apparatus 100 moves the stage 102 in the horizontal direction (also referred to as the "XY direction") to align the DUT to be tested on the device under test 20 with the probe card 104, and then moves the stage 102 upward in the vertical direction (also referred to as the "Z direction") to electrically connect each electrode of the DUT to be tested with each probe 106 of the probe card 104.

[0050] In S320, the light source 170 emits test light under the control of the system controller 192. The test light passes through the lens barrel 175, the HiFix 140, the performance board 130, the connection unit 120, and the probe card 104. In this way, the test apparatus 10 irradiates the test light onto the DUT.

[0051] In S330, the test module 160 used to control the DUT instructs the DUT to set up for imaging and capture the image of the test light under the control of the system controller 192. As a result, the DUT captures an image of the test light.

[0052] In S340, the test module 160 used to control the DUT outputs a data string of captured images from the DUT under the control of the system controller 192. The capture block 210 in the capture module 200 receives and captures the data string of the captured images. When testing a plurality of captured images in a consolidated manner, the test apparatus 10 repeats the processes from S320 to S340 while changing at least one of the light intensity, color, or light emission pattern of the test light as necessary. The capture block 210 in the capture module 200 sequentially receives and consolidates the data strings of each captured image.

[0053] In S350, the image processing device 194 receives the image data sequence captured by the capture module 200 and tests the DUT by inspecting the captured image data sequence or the aggregated result data sequence. Specifically, the image processing device 194 performs image processing on the captured data sequence or the result data sequence according to an algorithm predetermined by a test program or the like, thereby determining whether the captured image satisfies an image quality standard. Note that the test apparatus 10 may also perform an electrical test on the DUT in addition to the optical input test on the DUT.

[0054] In S360, the test apparatus 10 determines whether the test of the DUT under test has been completed. If the test of the DUT has not been completed (NO in S360), the test apparatus 10 proceeds to S320 and performs the test process from S320 to S350 for the next test item. If the test of the DUT has been completed (YES in S360), the test apparatus 10 proceeds to S370.

[0055] In S370, the test apparatus 10 determines whether testing of all DUTs of the device under test 20 has been completed. If testing of all DUTs has not been completed (NO in S370), the test apparatus 10 proceeds to S310 and performs the test processing from S310 to S360. If testing of all DUTs has been completed (YES in S370), the test apparatus 10 ends the test processing of the device under test 20. Note that the prober apparatus 100 may remove the device under test 20 that has been tested and place the next device under test 20 on the stage 102. In response to this, the test apparatus 10 may perform the test processing shown in this figure for the next device under test 20.

[0056] FIG. 4 shows the configuration of a computing device 300 according to this embodiment. The computing device 300 according to this embodiment may be used as a component including the capture unit 230 and the multiple memory banks 240 shown in FIG. 2. Alternatively, the computing device 300 may be applied to various application fields in which various operations are performed between data strings other than image data strings. The computing device 300 may be realized by one or more devices such as ICs or LSIs, or may be realized by executing an operation program on a general computer, a DSP (Digital Signal Processor), a microcontroller, or the like.

[0057] In the example shown in the figure, the computing device 300 includes three memory banks 240a to 240c. Alternatively, the computing device 300 may include two, four, or more memory banks 240 depending on the required memory bandwidth and capacity.

[0058] The capture unit 230 includes an arithmetic processing unit 402, a result output unit 404, a bank selector 440, and an arithmetic control unit 470. Under the control of the arithmetic control unit 470, the arithmetic processing unit 402 performs an arithmetic operation on a plurality of data strings sequentially input from the image data receiving unit 220. The arithmetic processing unit 402 then stores the resulting data string, obtained by performing an arithmetic operation on the plurality of data strings, in a result memory bank selected from the plurality of memory banks 240. The arithmetic processing unit 402 includes a data input unit 400, an input buffer 405, a source address generation unit 410, a read buffer 415, a destination address generation unit 420, a write buffer 425, and an arithmetic unit 450.

[0059] The data input section 400 is communicatively connected to the image data receiving section 220. The data input section 400 may be an input circuit, and receives from the image data receiving section 220 the data stream received from the DUT.

[0060] The input buffer 405 is connected to the data input unit 400. The input buffer 405 temporarily buffers at least a portion of the data sequence received by the data input unit 400 and transmits it to the calculation unit 450. The input buffer 405 may be capable of buffering up to a portion of the data sequence, for example, one to several tens of data elements. In another embodiment, the input buffer 405 may temporarily store the entire data sequence for one image.

[0061] The source address generation unit 410 generates an address (source address) for reading data from a memory bank selected as a source memory bank among the multiple memory banks 240. The source address generation unit 410 may generate a read command for reading data from an address in the source memory bank specified by the source address. The read buffer 415 temporarily buffers at least a portion of the data sequence read from the source memory bank. The read buffer 415 may be capable of buffering up to a portion of the data sequence, for example, one to several tens of data elements. In another embodiment, the read buffer 415 may temporarily store the entire data sequence for one image.

[0062] The destination address generation unit 420 generates an address (destination address) for writing data to a memory bank selected as the destination memory bank from among the multiple memory banks 240. The destination address generation unit 420 may generate a write command for writing data stored in the write buffer 425 to an address in the destination memory bank specified by the destination address. The write buffer 425 is connected to the calculation unit 450. The write buffer 425 temporarily buffers at least a portion of the data sequence to be written to the destination bank. The write buffer 425 may be capable of buffering, for example, one to several tens of data elements in the data sequence. In another embodiment, the write buffer 425 may temporarily store the entire data sequence for one image.

[0063] The arithmetic unit 450 performs a pre-specified operation between a data string read from a source memory bank among the plurality of memory banks 240 and a data string input via the input buffer 405. The arithmetic unit 450 stores the data string obtained as a result of the operation in the write buffer 425, thereby causing the data string to be written to a destination memory bank among the plurality of memory banks 240.

[0064] The result output unit 404, under the control of the calculation control unit 470, reads out a result data string obtained as a result of the calculation by the calculation processing unit 402 from a result memory bank selected from the plurality of memory banks 240, and outputs the read data to the signal transmitter 250. The result output unit 404 has a result address generation unit 430, an output buffer 435, and a data output unit 460.

[0065] The result address generation unit 430 generates an address (result address) for reading data from a result memory bank that stores the calculation result by the calculation device 300, among the multiple memory banks 240. The result address generation unit 430 may generate a read command for reading data from an address specified by the result address in the result memory bank.

[0066] The output buffer 435 temporarily buffers at least a portion of the result data string read from the result memory bank. The output buffer 435 may be capable of buffering, for example, one to several tens of data elements in the result data string. In another embodiment, the output buffer 435 may temporarily store the entire result data string having a size equivalent to one image.

[0067] The data output unit 460 is connected to the output buffer 435. The data output unit 460 receives, from the output buffer 435, the result data string that has been read out from the result memory bank among the plurality of memory banks 240, and outputs it to the signal transmitter 250.

[0068] The bank selector 440 is connected to the source address generation unit 410, the read buffer 415, the destination address generation unit 420, the write buffer 425, the result address generation unit 430, the output buffer 435, the multiple memory banks 240, and the arithmetic control unit 470. Under the control of the arithmetic control unit 470, the bank selector 440 selects which of the multiple memory banks 240 to connect each of the pair of the source address generation unit 410 and the read buffer 415, the pair of the destination address generation unit 420 and the write buffer 425, and the pair of the result address generation unit 430 and the output buffer 435 to. In this way, the bank selector 440 connects the pair of the source address generation unit 410 and the read buffer 415 to the memory bank 240 selected as the source memory bank from among the multiple memory banks 240. The bank selector 440 also connects the set of the destination address generation unit 420 and the write buffer 425 to the memory bank 240 selected as the destination memory bank from among the multiple memory banks 240. The bank selector 440 also connects the set of the result address generation unit 430 and the output buffer 435 to the memory bank 240 selected as the result memory bank from among the multiple memory banks 240. The arithmetic control unit 470 controls each unit within the capture unit 230.

[0069] 5 shows a calculation flow of the calculation device 300 according to this embodiment. According to this calculation flow, the calculation device 300 sequentially inputs a plurality of data strings for a plurality of captured images from the image data receiving unit 220, calculates the plurality of data strings, and outputs the resulting data strings to the signal transmitter 250.

[0070] In step S500, the data input unit 400 in the capture unit 230 inputs the next data string from the image data receiving unit 220 and stores it in the input buffer 405. In S510, the calculation control unit 470 selects, as a source memory bank, one of the multiple memory banks 240 in which the data string (also referred to as the "intermediate data string") resulting from the calculations performed up to that point is stored, and instructs the bank selector 440 to connect the pair of the source address generation unit 410 and the read buffer 415 to the source memory bank. The calculation control unit 470 sets the starting address of the data string resulting from the calculations performed up to that point as the source address in the source address generation unit 410, and instructs it to read the data string. As a result, the calculation device 300 reads the data from the source memory bank by reading the data from the source memory bank while sequentially incrementing the source address using the source address generation unit 410, and buffers the data string in the read buffer 415.

[0071] In S520, the arithmetic unit 450, under the control of the arithmetic control unit 470, performs an operation designated in advance by the test program or the user of the test apparatus 10, between a data sequence read from the source memory bank and sequentially buffered in the read buffer 415 and a next data sequence sequentially buffered in the input buffer 405. For example, when the arithmetic unit 300 is instructed to calculate the sum or average of corresponding data elements of multiple data sequences (e.g., data elements at the same data position in the data sequences), the arithmetic unit 450 adds each data element received from the read buffer 415 to the corresponding data element received from the input buffer 405, and outputs the data element resulting from the addition. When the arithmetic unit 300 is instructed to output the maximum or minimum value of each corresponding data element of multiple data sequences, the arithmetic unit 450 selects and outputs the larger or smaller value of each data element received from the read buffer 415 and the corresponding data element received from the input buffer 405. The calculation unit 450 may perform other calculations between corresponding data elements received from the read buffer 415 and the input buffer 405. The calculation unit 450 buffers each data element of the data string obtained as a result of the calculation in the write buffer 425.

[0072] In addition, if the data string input to the data input unit 400 and sequentially buffered in the input buffer 405 is the first image data string among multiple image data strings to be calculated, the calculation unit 450 may output the data elements from the input buffer 405 as is, or may perform a calculation between a data element with a value of 0 or the like and the data element from the input buffer 405 instead of the data element from the read buffer 415 and output the result.

[0073] In S530, the calculation control unit 470 selects, as a destination memory bank, one of the multiple memory banks 240 that is different from the source memory bank and that allows data to be overwritten. The calculation control unit 470 does not select, as a destination memory bank, any memory bank 240 that stores a result data string that has not yet been output to the signal transmitter 250. The calculation control unit 470 instructs the bank selector 440 to connect a pair of the destination address generation unit 420 and the write buffer 425 to the selected destination memory bank. The calculation control unit 470 sets the starting address to which the data string resulting from the calculation should be written as the destination address in the destination address generation unit 420, and instructs the destination address generation unit 420 to write the data string. As a result, the calculation device 300 writes the data string resulting from the calculation to the destination memory bank by writing the data in the write buffer 425 to the destination memory bank while sequentially incrementing the destination address using the destination address generation unit 420.

[0074] Here, the arithmetic processing unit 402 may perform parallel processing of reading a data string from a source memory bank (S510), performing an operation between the data string read from the source memory bank and the next data string (S520), and writing the data string obtained as a result of the operation to a destination memory bank (S530). Here, "parallel processing" refers to a processing method in which two or more processes proceed with overlapping time by starting a second or subsequent process before the first of the two or more processes is completed to the end.

[0075] For example, if the communication interface between the image data receiving unit 220 and the capture unit 230 and the data bus between each memory bank 240 and the capture unit 230 are 64 bits wide, an image data sequence of several megabytes to several tens of megabytes is transmitted over hundreds of thousands to millions or more data cycles. The arithmetic processing unit 402 starts reading the data sequence resulting from the calculation so far from the source memory bank in response to input of the leading portion of the next data sequence from the image data receiving unit 220, and performs calculation as soon as corresponding data elements from the data sequence resulting from the calculation so far and the next data sequence are available. This allows parallel processing of reading the data sequence from the source memory bank (S510) and calculation (S520) between the data sequence read from the source memory bank and the next data sequence. Furthermore, the arithmetic processing unit 402 writes the calculation result from the calculation unit 450 to the destination memory bank as soon as it is output, allowing parallel processing of writing the data sequence resulting from the calculation to the destination memory bank.

[0076] In S540, the calculation control unit 470 in the calculation device 300 determines whether all data strings to be calculated have been input. For example, the calculation control unit 470 determines that all data strings have been input when a number of data strings designated in advance by the test program or the user of the test device 10 have been input and calculated. If all data strings have been input ("YES" in S540), the calculation device 300 proceeds to S550.

[0077] If not all data strings have been input (NO in S540), the calculation control unit 470 in the calculation device 300 swaps the source memory bank and the destination memory bank in S550. By swapping ("swapping") the source memory bank and the destination memory bank, the calculation control unit 470 sets the memory bank that was the source memory bank as the next destination memory bank, and the memory bank that was the destination memory bank as the next source memory bank. For example, if memory bank 240a was the source memory bank and memory bank 240b was the destination memory bank in the calculation process for the third data string, the calculation control unit 470 sets memory bank 240b as the source memory bank and memory bank 240a as the destination memory bank in the calculation process for the fourth data string. The calculation processing unit 402 generates a result data string by calculating multiple data strings by repeating the processes of S510, S520, and S530 in accordance with instructions from the calculation control unit 470, while alternately swapping the source memory bank and the destination memory bank. The final resultant data string obtained by computing the multiple data strings is stored in the memory bank 240 selected as the destination memory bank.

[0078] If all data strings have been input and calculated ("YES" in S540), in S560, the calculation control unit 470 in the calculation device 300 selects a result memory bank that is a destination memory bank that stores the result data string from among the multiple memory banks 240. The result output unit 404 reads out and outputs the result data string from the result memory bank that is a destination memory bank that stores the result data string from among the multiple memory banks 240.

[0079] Specifically, the arithmetic control unit 470 in the arithmetic device 300 instructs the bank selector 440 to connect a set of the result address generation unit 430 and the output buffer 435 to the selected result memory bank. The arithmetic control unit 470 sets the starting address from which the result data string should be read as a result address in the result address generation unit 430 and instructs the result address generation unit 430 to read the result data string. As a result, the result output unit 404 reads the result memory bank while the result address generation unit 430 sequentially increments the result address, and outputs the result data string sequentially buffered in the output buffer 435 to the signal transmitter 250 via the data output unit 460.

[0080] 6 shows the operating state of the arithmetic device 300 according to this embodiment. In the example of this figure, the arithmetic device 300 receives three data sequences 1, 2, and 3 (shown in solid line frames) as examples of the first plurality of data sequences from the image data receiving unit 220.

[0081] In the calculation process of data sequence 1 (left side in the figure), the calculation control unit 470 in the calculation device 300 selects memory bank 240c as the source memory bank ("S" in the figure) and memory bank 240a as the destination memory bank ("D" in the figure). Then, the calculation processing unit 402 in the calculation device 300 performs calculations for each data element between the data sequence read from the source memory bank 240c and the data sequence input from the image data receiving unit 220, and writes the result to the destination memory bank 240a (see S510 to S530 in FIG. 5). Furthermore, if the results of calculations between multiple data sequences performed before the calculation of the first multiple data sequences are stored in memory bank 240b, the result output unit 404 in the calculation device 300 outputs the result data sequence from result memory bank 240b ("R" in the figure) to the signal transmitter 250 (see S560 in FIG. 5). Here, if the calculation processing unit 402 has generated a result data string by summing multiple data strings for each corresponding data element as the result of the previous calculation, the result output unit 404 may output a result data string that is the average of the multiple data strings by dividing the result data string for each data element by the number of data strings contained in the multiple data strings ("÷" in the figure).

[0082] In the calculation process for data sequence 2, which is the next data sequence after data sequence 1 (center of the figure), the calculation control unit 470 selects memory bank 240a as the source memory bank and memory bank 240c as the destination memory bank. Then, the calculation processing unit 402 in the calculation device 300 performs calculations for each data element between the data sequence read from the source memory bank 240a and the data sequence input from the image data receiving unit 220, and writes the results to the destination memory bank 240c. Furthermore, if the results of calculations between multiple data sequences performed before the calculation of the first multiple data sequences remain in memory bank 240b, the result output unit 404 in the calculation device 300 continues to output the result data sequence from result memory bank 240b to the signal transmitter 250.

[0083] In the calculation process for data sequence 3, which is the next data sequence after data sequence 2 (right side in the figure), the calculation control unit 470 selects memory bank 240c as the source memory bank and memory bank 240a as the destination memory bank. Then, the calculation processing unit 402 in the calculation device 300 performs calculations for each data element between the data sequence read from the source memory bank 240c and the data sequence input from the image data receiving unit 220, and writes the result to the destination memory bank 240a. As a result, the result data sequence obtained by calculating the first plurality of data sequences 1, 2, and 3 is stored in memory bank 240a. Furthermore, if the results of calculations performed between multiple data sequences performed before the calculation of the first plurality of data sequences remain in memory bank 240b, the result output unit 404 in the calculation device 300 continues to output the result data sequence from result memory bank 240b to the signal transmitter 250.

[0084] The arithmetic device 300 described above can generate results of operations on multiple data strings by alternately switching the source and destination memory banks, performing an operation between the next data string and the data string read from the source memory bank, and writing the resulting data string to the destination memory bank. While the read and write bandwidths of a memory bank are limited by the bit width and data transmission frequency of the memory bank's data bus (e.g., a bidirectional data bus), the arithmetic device 300 can read data from the source memory bank and write data to the destination memory bank with maximum throughput. By using two memory banks, the arithmetic device 300 can achieve twice the operation speed compared to using a single memory bank to both read and write data strings during an operation.

[0085] Fig. 7 shows the operating state of the arithmetic device 300 according to this embodiment. In the example of this figure, the arithmetic device 300 performs calculations on the first plurality of data strings as shown in Fig. 6, and then inputs three data strings 1, 2, and 3 enclosed by dashed lines as examples of the second plurality of data strings from the image data receiving unit 220.

[0086] The calculation control unit 470 in the calculation device 300 selects memory bank 240c as the source memory bank ("S" in the figure) and memory bank 240b as the destination memory bank ("D" in the figure) in the calculation process of data string 1 (left side in the figure). Because the calculation results of the first plurality of data strings are stored in memory bank 240a, the calculation control unit 470 selects memory banks other than memory bank 240a as the source memory bank and destination memory bank.

[0087] The arithmetic processing unit 402 in the arithmetic device 300 performs an operation for each data element between the data sequence read from the source memory bank 240c and the data sequence input from the image data receiving unit 220, and writes the operation result to the destination memory bank 240b. Furthermore, when the operation results of the first plurality of data sequences are stored in the memory bank 240a, the result output unit 404 in the arithmetic device 300 outputs the result data sequence from the result memory bank 240a ("R" in the figure) to the signal transmitter 250. Here, when the arithmetic processing unit 402 has generated a result data sequence by summing the plurality of data sequences for each corresponding data element as the result of the previous operation, the result output unit 404 may output a result data sequence that is an average of the plurality of data sequences by dividing the result data sequence for each data element by the number of data sequences included in the plurality of data sequences ("÷" in the figure).

[0088] In the calculation process for data sequence 2, which is the next data sequence after data sequence 1 (center of the figure), the calculation control unit 470 selects memory bank 240b as the source memory bank and memory bank 240c as the destination memory bank. Then, the calculation processing unit 402 in the calculation device 300 performs calculations for each data element between the data sequence read from the source memory bank 240b and the data sequence input from the image data receiving unit 220, and writes the result to the destination memory bank 240c. Furthermore, if the calculation results between the first plurality of data sequences remain in memory bank 240a, the result output unit 404 in the calculation device 300 continues to output the result data sequence from result memory bank 240a to the signal transmitter 250.

[0089] In the calculation process for data sequence 3, which is the next data sequence after data sequence 2 (right side in the figure), the calculation control unit 470 selects memory bank 240c as the source memory bank and memory bank 240b as the destination memory bank. Then, the calculation processing unit 402 in the calculation device 300 performs calculations for each data element between the data sequence read from the source memory bank 240c and the data sequence input from the image data receiving unit 220, and writes the result to the destination memory bank 240b. As a result, the result data sequence obtained by calculating the second plurality of data sequences 1, 2, and 3 is stored in memory bank 240b. Furthermore, if the calculation results between the first plurality of data sequences remain in memory bank 240a, the result output unit 404 in the calculation device 300 continues to output the result data sequence from result memory bank 240a to the signal transmitter 250.

[0090] 6 and 7, the arithmetic processing unit 402 writes a first result data string obtained by computing a first plurality of data strings into the result memory bank 240a, and then performs computation on a second plurality of data strings using two memory banks 240b and 240c, which are different from the result memory bank 240a, as the source and destination memory banks. This allows the computation device 300 to start computing the next plurality of data strings before outputting the computation results of the previous plurality of data strings. The result output unit 404 can then read the first result data string from the result memory bank 240a and output it to the signal transmitter 250 in parallel with the computation of the second plurality of data strings by the arithmetic processing unit 402.

[0091] 6 and 7, the arithmetic processing unit 402 may also use the first memory bank 240a and the second memory bank 240b of the multiple memory banks 240 as result memory banks, but may not select the third memory bank 240c of the multiple memory banks 240 as a write destination for the result data sequence. To achieve this, the arithmetic control unit 470 in the arithmetic device 300 may determine to which of the first memory bank 240a, the second memory bank 240b, and the third memory bank 240c an initially input data sequence of the multiple data sequences is written, so that a result data sequence that is the result of the arithmetic operation on the multiple data sequences is written to either the first memory bank 240a or the second memory bank 240b.

[0092] For example, when an operation is performed between an odd number of data strings, such as three, as shown in Figures 6 and 7, the memory bank initially selected as the destination memory bank (the first memory bank 240a in Figure 6 and the second memory bank 240b in Figure 7), in other words, the memory bank into which the first data string is written, stores the final result data string. Conversely, when an operation is performed between an even number of data strings, the memory bank initially selected as the source memory bank, in other words, the memory bank into which the first data string is not written, stores the final result data string. Therefore, when the operation control unit 470 selects one of two available memory banks as the source memory bank and the other as the destination memory bank, if the number of data strings to be operated is odd, the operation control unit 470 may first select the memory bank available as the result memory bank as the destination memory bank, and if the number of data strings to be operated is even, the operation control unit 470 may first select the memory bank available as the result memory bank as the source memory bank. In this way, the calculation processing unit 402 and the calculation control unit 470 may select the source memory bank or destination memory bank to be used for processing the initial data string depending on the number of data strings to be calculated, in order to avoid the result memory bank that ultimately stores the result data string being a predetermined memory bank (e.g., the third memory bank 240c).

[0093] This allows the arithmetic device 300 to avoid using at least one of the multiple memory banks as a result memory bank, which eliminates the need for the arithmetic device 300 to connect the result address generation unit 430 and the output buffer 435 to the memory bank that is not used as a result memory bank, thereby reducing the circuit size.

[0094] In the calculation device 300 described above, the calculation processing unit 402 may be controlled by the calculation control unit 470 to assign the source memory bank and the destination memory bank to the same memory bank 240 in response to a failure in at least one of the memory banks 240. This allows the calculation device 300 to continue calculation processing even if one of the memory banks 240 fails, although the calculation speed will be halved.

[0095] Furthermore, when the throughput of the data sequence input from the image data receiving unit 220 is high, the arithmetic device 300 may write the data sequence in parallel to three or more of the multiple memory banks 240. This allows the arithmetic device 300 to utilize the multiple memory banks 240 to handle faster data input.

[0096] Various embodiments of the present invention may be described with reference to flowcharts and block diagrams, where the blocks may represent (1) stages of a process in which operations are performed or (2) sections of an apparatus responsible for performing the operations. Particular stages and sections may be implemented by dedicated circuitry, programmable circuitry provided with computer-readable instructions stored on a computer-readable medium, and / or a processor provided with computer-readable instructions stored on a computer-readable medium. Dedicated circuitry may include digital and / or analog hardware circuitry, and may include integrated circuits (ICs) and / or discrete circuits. Programmable circuitry may include reconfigurable hardware circuitry, including logical AND, OR, XOR, NAND, NOR, and other logical operations, flip-flops, registers, memory elements such as field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), and the like.

[0097] A computer-readable medium may include any tangible device capable of storing instructions that are executed by an appropriate device, such that the computer-readable medium having instructions stored thereon comprises an article of manufacture containing instructions that can be executed to create means for performing the operations specified in the flowcharts or block diagrams. Examples of computer-readable media may include electronic, magnetic, optical, electromagnetic, and semiconductor storage media. More specific examples of computer-readable media may include floppy disks, diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), electrically erasable programmable read-only memory (EEPROM), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disc (DVD), Blu-ray disc, memory stick, integrated circuit card, and the like.

[0098] The computer readable instructions may include either assembler instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, JAVA®, C++, etc., and conventional procedural programming languages ​​such as the “C” programming language or similar programming languages.

[0099] The computer-readable instructions may be provided to a processor or programmable circuitry of a programmable data processing apparatus, such as a general-purpose computer, special-purpose computer, or other computer, either locally or over a wide-area network (WAN) such as a local area network (LAN), the Internet, etc., which executes the computer-readable instructions to create means for performing the operations specified in the flowcharts or block diagrams. Examples of processors include computer processors, processing units, microprocessors, digital signal processors, controllers, microcontrollers, etc.

[0100] 8 illustrates an example of a computer 2200 in which aspects of the present invention may be embodied, in whole or in part. Programs installed on the computer 2200 may cause the computer 2200 to function as or perform operations associated with an apparatus or one or more sections of the apparatus according to embodiments of the present invention, and / or to perform a process or steps of a process according to embodiments of the present invention. Such programs may be executed by the CPU 2212 to cause the computer 2200 to perform specific operations associated with some or all of the blocks in the flowcharts and block diagrams described herein.

[0101] A computer 2200 according to this embodiment includes a CPU 2212, a RAM 2214, a graphics controller 2216, and a display device 2218, which are interconnected by a host controller 2210. The computer 2200 also includes input / output units such as a communication interface 2222, a hard disk drive 2224, a DVD-ROM drive 2226, and an IC card drive, which are connected to the host controller 2210 via an input / output controller 2220. The computer also includes legacy input / output units such as a ROM 2230 and a keyboard 2242, which are connected to the input / output controller 2220 via an input / output chip 2240.

[0102] The CPU 2212 operates according to programs stored in the ROM 2230 and RAM 2214, thereby controlling each unit. The graphics controller 2216 acquires image data generated by the CPU 2212 into a frame buffer or the like provided in the RAM 2214 or into the graphics controller 2216 itself, and causes the image data to be displayed on the display device 2218.

[0103] The communications interface 2222 communicates with other electronic devices via a network. The hard disk drive 2224 stores programs and data used by the CPU 2212 in the computer 2200. The DVD-ROM drive 2226 reads programs or data from the DVD-ROM 2201 and provides the programs or data to the hard disk drive 2224 via the RAM 2214. The IC card drive reads programs and data from an IC card and / or writes programs and data to an IC card.

[0104] The ROM 2230 stores therein a boot program or the like that is executed by the computer 2200 upon activation, and / or programs that depend on the hardware of the computer 2200. The input / output chip 2240 may also connect various input / output units to the input / output controller 2220 via a parallel port, a serial port, a keyboard port, a mouse port, etc.

[0105] The programs are provided by a computer-readable medium such as a DVD-ROM 2201 or an IC card. The programs are read from the computer-readable medium, installed in the hard disk drive 2224, RAM 2214, or ROM 2230, which are also examples of computer-readable media, and executed by the CPU 2212. Information processing described in these programs is read by the computer 2200, and brings about cooperation between the programs and the various types of hardware resources described above. An apparatus or method may be configured by realizing information manipulation or processing in accordance with the use of the computer 2200.

[0106] For example, when communication is performed between the computer 2200 and an external device, the CPU 2212 may execute a communication program loaded into the RAM 2214 and instruct the communication interface 2222 to perform communication processing based on the processing described in the communication program. Under the control of the CPU 2212, the communication interface 2222 reads transmission data stored in a transmission buffer processing area provided in the RAM 2214, the hard disk drive 2224, the DVD-ROM 2201, or a recording medium such as an IC card, and transmits the read transmission data to the network, or writes reception data received from the network to a reception buffer processing area or the like provided on the recording medium.

[0107] The CPU 2212 may also cause all or a necessary portion of a file or database stored on an external recording medium such as the hard disk drive 2224, the DVD-ROM drive 2226 (DVD-ROM 2201), an IC card, etc. to be read into the RAM 2214, and perform various types of processing on the data on the RAM 2214. The CPU 2212 then writes back the processed data to the external recording medium.

[0108] Various types of information, such as various types of programs, data, tables, and databases, may be stored on the recording medium and may undergo information processing. The CPU 2212 may perform various types of processing on data read from the RAM 2214, including various types of operations, information processing, conditional judgment, conditional branching, unconditional branching, information search / replacement, etc., as described throughout this disclosure and specified by the instruction sequences of the programs, and write the results back to the RAM 2214. The CPU 2212 may also search for information in a file, database, etc. on the recording medium. For example, if multiple entries each having an attribute value of a first attribute associated with an attribute value of a second attribute are stored on the recording medium, the CPU 2212 may search for an entry that matches a condition specified by the attribute value of the first attribute from among the multiple entries, read the attribute value of the second attribute stored in the entry, and thereby obtain the attribute value of the second attribute associated with the first attribute that satisfies a predetermined condition.

[0109] The above-described programs or software modules may be stored in a computer-readable medium on or near the computer 2200. A recording medium such as a hard disk or RAM provided in a server system connected to a dedicated communication network or the Internet can also be used as a computer-readable medium, thereby providing the programs to the computer 2200 via the network.

[0110] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0111] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0112] 10 test equipment, 20 test object, 100 prober device, 102 stage, 104 probe card, 106 probe, 108 light shielding unit, 120 connection unit, 130 performance board, 140 HiFix, 150 test head, 160a to d test module, 170 light source, 175 lens barrel, 180 rotation device, 190 mainframe, 192 system controller, 194 image processing device, 200 capture module, 210-1 to 4 capture block, 220 image data receiving unit, 230 capture unit, 240a to c memory bank, 250-1 to 2 signal transmitter, 255 module IF, 270 image processing engine, 280-1 to 8 CAPIF, 290-1 to 8 signal transmitter, 300 arithmetic unit, 400 data input unit, 402 arithmetic processing unit, 404 Result output unit, 405 input buffer, 410 source address generation unit, 415 read buffer, 420 destination address generation unit, 425 write buffer, 430 result address generation unit, 435 output buffer, 440 bank selector, 450 arithmetic unit, 460 data output unit, 470 arithmetic control unit, 2200 computer, 2201 DVD-ROM, 2210 host controller, 2212 CPU, 2214 RAM, 2216 graphics controller, 2218 display device, 2220 input / output controller, 2222 communication interface, 2224 hard disk drive, 2226 DVD-ROM drive, 2230 ROM, 2240 input / output chip, 2242 keyboard

Claims

1. A plurality of memory banks; an arithmetic processing unit that generates a data string as a result of arithmetic operations on the plurality of data strings by repeating a process of reading a data string from a source memory bank among the plurality of memory banks, performing an operation between the data string and a next data string, and writing the data string obtained as a result of the operation into a destination memory bank among the plurality of memory banks while alternately switching between the source memory bank and the destination memory bank; A computing device comprising:

2. 2. The arithmetic device according to claim 1, wherein the arithmetic processing unit performs parallel processing of reading a data sequence from the source memory bank, performing an operation between the data sequence read from the source memory bank and a next data sequence, and writing the data sequence obtained as a result of the operation to the destination memory bank.

3. 3. The arithmetic device according to claim 2, further comprising a result output section that reads out and outputs the result data string from a result memory bank that is the destination memory bank that stores the result data string among the plurality of memory banks.

4. the arithmetic processing unit generates the resultant data string by summing the plurality of data strings for each corresponding data element; The arithmetic device according to claim 3 , wherein the result output unit divides the result data string by the number of data strings included in the plurality of data strings for each data element, and outputs the result data string.

5. the arithmetic processing unit writes the first result data string obtained by operating the first plurality of data strings into the result memory bank, and then performs an operation on the second plurality of data strings using two memory banks different from the result memory bank among the plurality of memory banks as the source memory bank and the destination memory bank; The result output unit reads the first result data string from the result memory bank in parallel with the operation of the second plurality of data strings by the operation processing unit. The computing device according to claim 3 .

6. 4. The arithmetic device according to claim 3, wherein the arithmetic processing unit uses the first memory bank and the second memory bank among the plurality of memory banks as the result memory bank, and does not select the third memory bank among the plurality of memory banks as the write destination for the result data string.

7. 2. The arithmetic device according to claim 1, wherein, in response to a failure in at least one memory bank among the plurality of memory banks, the arithmetic processing unit assigns the source memory bank and the destination memory bank to the same memory bank.

8. The computing device according to claim 1 , wherein each of the plurality of data strings includes image data.

9. A test apparatus for testing a device under test that is an imaging device, comprising: an image data receiving unit that receives a plurality of data strings each including image data captured by the device under test; the computing device according to claim 1 , which generates a data string as a result of computing the plurality of data strings; an image processing device that inspects the result data string; A test device comprising:

10. An arithmetic method in which an arithmetic device having a plurality of memory banks reads a data string from a source memory bank among the plurality of memory banks, performs an operation with a next data string, and writes the data string obtained as a result of the operation to a destination memory bank among the plurality of memory banks, repeating this process while alternating between the source memory bank and the destination memory bank, thereby generating a data string as a result of operating on a plurality of data strings.

11. The method is executed by a computer, causing the computer to: a calculation processing unit that reads a data string from a source memory bank among a plurality of memory banks, calculates the data string with a next data string, and writes the data string obtained as a result of the calculation into a destination memory bank among the plurality of memory banks, repeating this process while alternating between the source memory bank and the destination memory bank, thereby generating a data string as a result of calculating the plurality of data strings; A calculation program that functions as a

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