Semiconductor device and method for manufacturing the same

Abstract

To prevent abnormal growth of a contact plug.SOLUTION: A semiconductor device comprises a semiconductor substrate, a barrier metal layer, and a contact plug. The semiconductor substrate includes a metal silicide region. A contact trench is provided in the semiconductor substrate. The barrier metal layer is formed inside the contact trench, and the contact plug is formed on the barrier metal layer. The metal silicide region is in contact with the barrier metal layer and includes a first metal silicide region, a second metal silicide region, and a third metal silicide region. A first thickness of the first metal silicide region is smaller than a second thickness of the second metal silicide region and also smaller than a third thickness of the third metal silicide region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and is suitably applicable to, for example, a semiconductor device including a barrier metal layer and a contact plug formed in a contact hole, and a manufacturing method thereof. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2024-1723 (Patent Document 1) discloses a semiconductor device including a barrier metal layer and a contact plug formed in a contact hole. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2024-1723 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device disclosed in Patent Document 1, a part of the barrier metal layer is broken when forming the contact plug, causing the contact plug to grow abnormally. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a semiconductor substrate, a barrier metal layer, and a contact plug. The semiconductor substrate has a first main surface. The barrier metal layer includes a first barrier metal layer and a second barrier metal layer. The semiconductor substrate includes a source region, a body region, and a metal silicide region. The source region has a first conductivity type. The body region is in contact with the source region and has a second conductivity type opposite to the first conductivity type. The semiconductor substrate is provided with a contact trench extending from the first main surface to the body region. The first barrier metal layer is formed in the contact trench. The second barrier metal layer is formed on the first barrier metal layer. The contact plug is formed on the second barrier metal layer. The metal silicide region is in contact with the first barrier metal layer and includes a first metal silicide region, a second metal silicide region, and a third metal silicide region. The first metal silicide region is formed in the body region and the source region. The second metal silicide region is connected to the first metal silicide region and is formed in the source region, the third metal silicide region is connected to the first metal silicide region and is formed in the body region, and the first thickness of the first metal silicide region is smaller than the second thickness of the second metal silicide region and smaller than the third thickness of the third metal silicide region.

[0006] According to one embodiment, a method for manufacturing a semiconductor device includes the steps of: preparing a semiconductor substrate having a first main surface. The semiconductor substrate includes a source region and a body region. The source region has a first conductivity type. The body region is in contact with the source region and has a second conductivity type different from the first conductivity type. The method for manufacturing a semiconductor device includes the steps of: forming a hole in the semiconductor substrate, the hole extending from the first main surface to the body region; forming a base barrier metal layer in the hole; and forming a first barrier metal layer on the base barrier metal layer. The method for manufacturing a semiconductor device includes the steps of: annealing the semiconductor substrate on which the base barrier metal layer and the first barrier metal layer are formed, to form a metal silicide region from the base barrier metal layer and the semiconductor substrate. The metal silicide region is in contact with the first barrier metal layer. A contact trench is defined by the interface between the metal silicide region and the first barrier metal layer. The method for manufacturing a semiconductor device includes the steps of: forming a second barrier metal layer on the first barrier metal layer; and forming a contact plug on the second barrier metal layer. The metal silicide region includes a first metal silicide region, a second metal silicide region, and a third metal silicide region. The first metal silicide region is formed in the body region and the source region. The second metal silicide region is connected to the first metal silicide region and is formed in the source region. The third metal silicide region is connected to the first metal silicide region and is formed in the body region. A first thickness of the first metal silicide region is smaller than a second thickness of the second metal silicide region and smaller than a third thickness of the third metal silicide region. [Effects of the Invention]

[0007] According to the embodiment, it is possible to provide a semiconductor device capable of preventing abnormal growth of contact plugs. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic partial cross-sectional view of a semiconductor device according to an embodiment; [Figure 2]2 is a schematic enlarged partial cross-sectional view of a region II shown in FIG. 1 of the semiconductor device according to the embodiment. [Figure 3] 1 is a schematic partial cross-sectional view showing one step of a method for manufacturing a semiconductor device according to an embodiment; [Figure 4] 4 is a schematic partial cross-sectional view showing a step subsequent to the step shown in FIG. 3 in the method for manufacturing the semiconductor device according to the embodiment. [Figure 5] 5 is a schematic partial enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 4 in the method for manufacturing the semiconductor device according to the embodiment. [Figure 6] 6 is a schematic partial enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 5 in the method for manufacturing the semiconductor device according to the embodiment. [Figure 7] 7 is a schematic partial enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 6 in the method for manufacturing the semiconductor device according to the embodiment. [Figure 8] 8 is a schematic partial enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 7 in the method for manufacturing the semiconductor device according to the embodiment. [Figure 9] 9 is a schematic partial enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 8 in the method for manufacturing the semiconductor device according to the embodiment. [Figure 10] 10 is a schematic partial enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 9 in the method for manufacturing the semiconductor device according to the embodiment. [Figure 11] 11 is a schematic partial enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 10 in the method for manufacturing the semiconductor device according to the embodiment. [Figure 12] 12 is a schematic partial cross-sectional view showing a step subsequent to the step shown in FIG. 11 in the method for manufacturing the semiconductor device according to the embodiment. [Figure 13] 13 is a schematic partial cross-sectional view showing a step subsequent to the step shown in FIG. 12 in the method for manufacturing the semiconductor device according to the embodiment. [Figure 14] 14 is a schematic partial cross-sectional view showing a step subsequent to the step shown in FIG. 13 in the method for manufacturing the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The semiconductor device according to the embodiment will be described below, with the same reference numerals being used to designate the same components, and description thereof will not be repeated.

[0010] The configuration of a semiconductor device SD according to an embodiment will be described with reference to Figures 1 and 2. The semiconductor device SD according to this embodiment is a trench-gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In particular, the MOSFET according to this embodiment has a split-gate structure including a gate electrode GE and a field plate electrode FP. The semiconductor device SD includes a semiconductor substrate SUB, a gate insulating film GI, a gate electrode GE, a field plate electrode FP, an interlayer insulating film IL, a barrier metal layer BM, a contact plug CP, a source electrode SE, a drain electrode DE, and a passivation film PV.

[0011] The semiconductor substrate SUB has a first main surface SF1 and a second main surface SF2 opposite to the first main surface SF1. The thickness direction of the semiconductor substrate SUB is the direction in which the first main surface SF1 and the second main surface SF2 are spaced apart from each other. The semiconductor substrate SUB is formed of, for example, single-crystal silicon (Si).

[0012] In the semiconductor substrate SUB, a drift region DRF, a source region SR, a body region BR, a drain region DRR, a contact region CR, and a metal silicide region SIL are formed.

[0013] The source region SR is formed in the first main surface SF1. The body region BR is in contact with the source region SR and is located on the second main surface SF2 side of the source region SR. A channel is formed in a portion of the body region BR facing the gate electrode GE with the gate insulating film GI interposed therebetween. The drift region DRF is in contact with the body region BR and is located on the second main surface SF2 side of the body region BR. The drain region DRR is formed in the second main surface SF2. The drift region DRF is in contact with the drain region DRR and is located on the first main surface SF1 side of the drain region DRR. The contact region CR is formed in the body region BR and the drift region DRF. The contact region CR is formed from the bottom surface of the contact trench TR2 to the drift region DRF.

[0014] The conductivity type of the source region SR, the drift region DRF, and the drain region DRR is a first conductivity type. The conductivity type of the body region BR and the contact region CR is a second conductivity type. The second conductivity type is the opposite conductivity type of the first conductivity type. For example, if the first conductivity type is n-type, the second conductivity type is p-type.

[0015] The concentration of the first conductivity type impurity in the source region SR is higher than the concentration of the first conductivity type impurity in the drift region DRF. + and the drift region DRF is n - The drain region DRR has a higher concentration of impurities of the first conductivity type than the drift region DRF. The source region SR and the drain region DRR have an impurity of the second conductivity type, such as arsenic (As).

[0016] The concentration of the second conductive type impurity in the contact region CR is higher than the concentration of the second conductive type impurity in the body region BR. For example, the contact region CR is p + region, and the body region BR is p -The impurity of the second conductivity type in the body region BR and the contact region CR is, for example, boron (B). The contact region CR may contain fluorine atoms.

[0017] The metal silicide region SIL is formed by a reaction between the base barrier metal layer BBM and silicon in the semiconductor substrate SUB. The metal silicide region SIL is formed of a metal silicide such as titanium silicide. The metal silicide region SIL does not need to contain chlorine atoms. The metal silicide region SIL is conductive. The metal silicide region SIL is formed in a portion of the semiconductor substrate SUB that contacts the side and bottom surfaces of the contact trench TR2. The metal silicide region SIL is in contact with the first barrier metal layer BM1. Referring to FIG. 2, the metal silicide region SIL includes a first metal silicide region SIL1, a second metal silicide region SIL2, a third metal silicide region SIL3, a fourth metal silicide region SIL4, and a fifth metal silicide region SIL5.

[0018] The first metal silicide region SIL1 is formed in a portion of the semiconductor substrate SUB that contacts the side surface of the contact trench TR2. The first metal silicide region SIL1 is in contact with the first barrier metal layer BM1. The first metal silicide region SIL1 is formed in the source region SR and the body region BR. The first metal silicide region SIL1 is formed in a part of the interface between the source region SR and the body region BR. The first thickness of the first metal silicide region SIL1 is smaller than the second thickness of the second metal silicide region SIL2 and smaller than the third thickness of the third metal silicide region SIL3.

[0019] The second metal silicide region SIL2 is formed in a portion of the semiconductor substrate SUB that contacts the side surface of the contact trench TR2. The second metal silicide region SIL2 contacts the first barrier metal layer BM1. The second metal silicide region SIL2 is formed in the source region SR. The second metal silicide region SIL2 is connected to the first metal silicide region SIL1. The second metal silicide region SIL2 is formed from the first metal silicide region SIL1 to the first main surface SF1.

[0020] The third metal silicide region SIL3 is formed in a portion of the semiconductor substrate SUB that contacts the side surface of the contact trench TR2. The third metal silicide region SIL3 contacts the first barrier metal layer BM1. The third metal silicide region SIL3 is formed in the body region BR. The third metal silicide region SIL3 is connected to the first metal silicide region SIL1.

[0021] The fourth metal silicide region SIL4 is formed in a portion of the semiconductor substrate SUB that is in contact with the bottom surface of the contact trench TR2. The fourth metal silicide region SIL4 is in contact with the first barrier metal layer BM1. The fourth metal silicide region SIL4 is formed in the body region BR.

[0022] The fifth metal silicide region SIL5 is formed in the body region BR and the contact region CR. The fifth metal silicide region SIL5 is formed in a part of the interface between the body region BR and the contact region CR. The fifth metal silicide region SIL5 is in contact with the first barrier metal layer BM1. The fifth metal silicide region SIL5 is connected to the third metal silicide region SIL3 and the fourth metal silicide region SIL4. The fifth thickness of the fifth metal silicide region SIL5 is smaller than the third thickness of the third metal silicide region SIL3 and smaller than the fourth thickness of the fourth metal silicide region SIL4.

[0023] The fifth metal silicide region SIL5 may be formed, for example, in a portion of the semiconductor substrate SUB that contacts a corner of the contact trench TR2. At the corner of the contact trench TR2, the side surface of the contact trench TR2 and the bottom surface of the contact trench TR2 are connected to each other. At the corner of the contact trench TR2, the side surface of the contact trench TR2 and the bottom surface of the contact trench TR2 form a gap.

[0024] A gate trench TR1 is formed in the first main surface SF1. The gate trench TR1 extends from the first main surface SF1 toward the second main surface SF2. The gate trench TR1 penetrates the source region SR and the body region BR and extends to the drift region DRF.

[0025] A contact trench TR2 is formed in the first main surface SF1. The contact trench TR2 extends from the first main surface SF1 toward the second main surface SF2. The contact trench TR2 penetrates the source region SR and extends to the body region BR. The contact trench TR2 is formed between two adjacent gate trenches TR1. In a cross section along the thickness direction of the semiconductor substrate SUB, the contact trench TR2 may have a bow shape.

[0026] The gate insulating film GI is formed in the gate trench TR1. The gate insulating film GI is formed on the side surface and bottom surface of the gate trench TR1. The gate insulating film GI separates the gate electrode GE and the field plate electrode FP from the source region SR, the body region BR, and the drift region DRF. The gate insulating film GI is formed of, for example, silicon oxide (SiO2).

[0027] The gate electrode GE is disposed in a portion of the gate trench TR1 that is proximate to the first main surface SF1. The gate electrode GE is formed on the gate insulating film GI. The gate electrode GE faces the body region BR via the gate insulating film GI. The gate electrode GE is formed of, for example, polycrystalline silicon doped with impurities.

[0028] The field plate electrode FP is disposed in a portion of the gate trench TR1 that is close to the second main surface SF2. The field plate electrode FP is separated from the gate electrode GE via the gate insulating film GI. The field plate electrode FP is electrically connected to the source electrode SE. This allows a depletion layer to expand from the field plate electrode FP when the MOSFET is turned off. This improves the breakdown voltage characteristics of the semiconductor device SD.

[0029] The source region SR, drain region DRR, drift region DRF, body region BR, gate insulating film GI, gate electrode GE, and field plate electrode FP constitute a transistor that is a trench gate type MOSFET having a split gate structure.

[0030] The interlayer insulating film IL is formed on the first main surface SF1. The interlayer insulating film IL separates the adjacent gate trenches TR1. The interlayer insulating film IL is formed of, for example, silicon oxide. The interlayer insulating film IL is formed of, for example, non-doped silicon oxide, i.e., NSG (Non-doped Silicon Glass). The interlayer insulating film IL may be formed of silicon oxide doped with impurities, for example, BPSG (Boron Phosphorous Silicon Glass).

[0031] A contact hole CH is formed in the interlayer insulating film IL. The contact hole CH is connected to the contact trench TR2. The side surface of the contact hole CH may be flush with the side surface of the contact trench TR2.

[0032] The barrier metal layer BM is formed on the interlayer insulating film IL, on the side surfaces of the contact holes CH, and on the side surfaces and bottom surfaces of the contact trenches TR2. The barrier metal layer BM is separated between adjacent contact trenches TR2. The barrier metal layer BM is conductive. The barrier metal layer BM prevents the metal material (e.g., tungsten (W)) constituting the contact plug CP from diffusing into the semiconductor substrate SUB. Referring to FIG. 2, the barrier metal layer BM includes a base barrier metal layer BBM, a first barrier metal layer BM1, and a second barrier metal layer BM2.

[0033] The base barrier metal layer BBM is formed on the side surface of the contact hole CH and on the interlayer insulating film IL. The base barrier metal layer BBM is conductive. The base barrier metal layer BBM is, for example, a Ti layer. The base barrier metal layer BBM is formed by a physical vapor deposition (PVD) method such as a sputtering method, and is a PVD-Ti layer. Since the base barrier metal layer BBM is formed by a PVD method rather than a chemical vapor deposition (CVD) method, it does not contain chlorine atoms contained in gases used in the CVD method.

[0034] The first barrier metal layer BM1 is formed on the base barrier metal layer BBM and on the side and bottom surfaces of the contact trench TR2. The first barrier metal layer BM1 improves adhesion of the second barrier metal layer BM2 to the metal silicide region SIL. The first barrier metal layer BM1 is conductive. The first barrier metal layer BM1 is, for example, a TiN layer. The first barrier metal layer BM1 is formed by the PVD method and is a PVD-TiN layer. The first barrier metal layer BM1 is formed by the PVD method rather than the CVD method, and therefore does not contain chlorine atoms contained in the gas used in the CVD method. The PVD method is a highly directional film formation method, and a film is more likely to be formed on the bottom surface of the trench than on the side surface of the trench. Therefore, the thickness of the first barrier metal layer BM1 on the bottom surface of the contact trench TR2 is greater than the thickness of the first barrier metal layer BM1 on the side surface of the contact trench TR2.

[0035] The second barrier metal layer BM2 is formed on the first barrier metal layer BM1. The second barrier metal layer BM2 is conductive. The second barrier metal layer BM2 is, for example, a TiN layer. The second barrier metal layer BM2 is formed by a CVD method and is a CVD-TiN layer. In the CVD method, TiCl4 gas and N2 are reacted to form a CVD-TiN film. Therefore, the second barrier metal layer BM2 contains chlorine atoms. The second barrier metal layer BM2 has a higher chlorine atom concentration than the first barrier metal layer BM1. The thickness of the second barrier metal layer BM2 is greater than the thickness of the first barrier metal layer BM1. Since the second barrier metal layer BM2 is formed by a CVD method, it has better step coverage than the first barrier metal layer BM1 formed by a PVD method. Therefore, the side and bottom surfaces of the contact trench TR2 are reliably covered by the second barrier metal layer BM2.

[0036] The contact plug CP is disposed inside the contact hole CH and the contact trench TR2. The contact plug CP is made of, for example, tungsten (W). The contact plug CP is electrically connected to the source region SR, the body region BR, and the contact region CR through the first barrier metal layer BM1, the second barrier metal layer BM2, and the metal silicide region SIL.

[0037] The source electrode SE is formed on the interlayer insulating film IL, the barrier metal layer BM (more specifically, the second barrier metal layer BM2), and the contact plug CP. The source electrode SE is made of, for example, aluminum (Al). The source electrode SE is in contact with the contact plug CP and is electrically connected to the contact plug CP.

[0038] The drain electrode DE is formed on the second main surface SF2. The drain electrode DE is formed of, for example, a metal stack of Ag / Ni / Ti. The drain electrode DE is in contact with the drain region DRR and is electrically connected to the drain region DRR.

[0039] The passivation film PV is formed on the source electrode SE. The passivation film PV protects the source electrode SE, the gate electrode GE, the field plate electrode FP, the contact plug CP, and the semiconductor substrate SUB from moisture. The passivation film PV includes, for example, a first passivation film PV1 and a second passivation film PV2. The first passivation film PV1 is formed on the source electrode SE. The first passivation film PV1 is, for example, a silicon oxide film. The second passivation film PV2 is formed on the first passivation film PV1. The second passivation film PV2 is, for example, a silicon nitride film.

[0040] When a voltage is applied to the drain electrode DE, holes and electrons are generated between the drain region DRR and the channel of the body region BR. The holes flow into the channel, turning the transistor on. Current flows intensively through the transistor, which can cause electrical breakdown of the transistor. By forming a contact region CR that has a higher concentration of second-conductivity-type impurities and a lower electrical resistivity than the body region BR, the holes can be discharged to the outside of the semiconductor device SD through the contact region CR, the metal silicide region SIL, the contact plug CP, and the source electrode SE. This can prevent electrical breakdown of the transistor.

[0041] In the above description, the semiconductor device SD of the present embodiment is a trench-gate MOSFET having a split-gate structure. However, the semiconductor device SD may be a trench-gate MOSFET that does not have a split-gate structure (i.e., does not have a field plate electrode FP), or may be a trench-gate IGBT (Insulated Gate Bipolar Transistor).

[0042] An example of a method for manufacturing the semiconductor device SD of this embodiment will be described with reference to FIGS.

[0043] Referring to FIG. 3, a semiconductor substrate SUB is prepared. The semiconductor substrate SUB includes a source region SR, a drain region DRR, a drift region DRF, and a body region BR. A gate insulating film GI, a gate electrode GE, a field plate electrode FP, and a drain electrode DE are formed in the semiconductor substrate SUB. A gate trench TR1 is formed in the semiconductor substrate SUB. The gate trench TR1 extends from a first main surface SF1 of the semiconductor substrate SUB, passing through the source region SR and the body region BR, to the drift region DRF. A gate insulating film GI is formed on the side and bottom surfaces of the gate trench TR1. The gate electrode GE is disposed in a portion of the gate trench TR1 close to the first main surface SF1. The gate electrode GE faces the body region BR via the gate insulating film GI. The field plate electrode FP is disposed in a portion of the gate trench TR1 close to the second main surface SF2. The field plate electrode FP is separated from the gate electrode GE via the gate insulating film GI.

[0044] The semiconductor substrate SUB, on which the gate insulating film GI, gate electrode GE, field plate electrode FP, and drain electrode DE are formed, is obtained by a known method. For example, an impurity having a second conductivity type (e.g., boron (B)) is implanted from the first main surface SF1 by ion implantation, followed by annealing, to form the body region BR. An impurity having a first conductivity type (arsenic (As)) is implanted from the first main surface SF1 by ion implantation, followed by annealing, to form the source region SR.

[0045] Referring to FIG. 4, an interlayer insulating film IL is formed on the first main surface SF1 of the semiconductor substrate SUB. The interlayer insulating film IL is separated between adjacent gate trenches TR1. For example, a material constituting the interlayer insulating film IL is deposited on the first main surface SF1. Then, portions of the interlayer insulating film IL between adjacent gate trenches TR1 are removed by etching or the like. In this manner, the interlayer insulating film IL is formed.

[0046] Referring to FIG. 5, a hole HL is formed in the semiconductor substrate SUB. The hole HL is formed, for example, by etching the first main surface SF1 of the semiconductor substrate SUB using the interlayer insulating film IL as a mask. The hole HL extends from the first main surface SF1 toward the second main surface SF2. The hole HL penetrates the source region SR and extends to the body region BR. The hole HL is formed between two adjacent gate trenches TR1. In a cross section along the thickness direction of the semiconductor substrate SUB, the hole HL may have a bow shape.

[0047] Referring to FIG. 6, the contact region CR is formed. The concentration of the second conductivity type impurity in the contact region CR is higher than the concentration of the second conductivity type impurity in the body region BR. For example, by ion implantation, the impurity having the second conductivity type is implanted into the body region BR and the drift region DRF through the holes HL. Then, the semiconductor substrate SUB is annealed. In this way, the contact region CR is formed.

[0048] The impurity implanted to form the contact region CR may be a fluoride of an impurity having the second conductivity type (e.g., boron fluoride (BF)). The mass of the impurity implanted to form the contact region CR (e.g., boron fluoride (BF)) may be greater than the mass of the impurity implanted to form the body region BR (e.g., boron (B)). The ion acceleration voltage used to form the contact region CR may be lower than the ion acceleration voltage used to form the body region BR.

[0049] 7, a base barrier metal layer BBM is formed on the side and bottom surfaces of the hole HL and on the interlayer insulating film IL. The base barrier metal layer BBM is, for example, a Ti layer. The base barrier metal layer BBM is formed by a PVD (Physical Vapor Deposition) method such as a sputtering method, and is a PVD-Ti layer.

[0050] 8, a first barrier metal layer BM1 is formed on the base barrier metal layer BBM. The first barrier metal layer BM1 is, for example, a TiN layer. The first barrier metal layer BM1 is formed by a PVD method and is a PVD-TiN layer.

[0051] 9 and 10, the semiconductor substrate SUB on which the base barrier metal layer BBM and the first barrier metal layer BM1 are formed is annealed. This annealing is, for example, lamp annealing. The annealing temperature is, for example, 600 degrees Celsius or higher and 750 degrees Celsius or lower. This annealing causes the base barrier metal layer BBM to react with silicon in the semiconductor substrate SUB, forming a metal silicide region SIL. The metal silicide region SIL is in contact with the first barrier metal layer BM1. A contact trench TR2 is defined by the interface between the first barrier metal layer BM1 and the metal silicide region SIL. A portion of the hole HL that was formed in the interlayer insulating film IL becomes a contact hole CH.

[0052] The base barrier metal layer BBM and the first barrier metal layer BM1 are formed by the PVD method, not the CVD method, and therefore do not contain chlorine atoms resulting from the CVD method. As a result, a metal silicide region SIL that does not contain chlorine atoms is formed. This reduces the contact resistance between the contact plug CP and the semiconductor substrate SUB.

[0053] As shown in FIG. 9, at the beginning of the annealing, the thickness of the metal silicide region SIL is substantially uniform.

[0054] As shown in FIG. 10, as annealing continues, a portion of the metal silicide region SIL aggregates to form a second metal silicide region SIL2, a third metal silicide region SIL3, and a fourth metal silicide region SIL4. The non-aggregated portions of the metal silicide region SIL become a first metal silicide region SIL1 and a fifth metal silicide region SIL5. The first thickness of the first metal silicide region SIL1 is smaller than the second thickness of the second metal silicide region SIL2 and smaller than the third thickness of the third metal silicide region SIL3. The fifth thickness of the fifth metal silicide region SIL5 is smaller than the third thickness of the third metal silicide region SIL3 and smaller than the fourth thickness of the fourth metal silicide region SIL4. The first metal silicide region SIL1 is formed in a portion of the interface between the body region BR and the source region SR. The fifth metal silicide region SIL5 is formed in a portion of the interface between the body region BR and the contact region CR.

[0055] The region near the interface (pn junction) between the body region BR and the source region SR contains the second conductivity type impurities implanted to form the body region BR and the first conductivity type impurities implanted to form the source region SR. Therefore, the impurity concentration in the region near the interface between the body region BR and the source region SR is high. As a result, migration of metal silicide from the portion of the metal silicide region SIL where the interface between the body region BR and the source region SR is located to the portion of the metal silicide region SIL adjacent to that portion is promoted. In this way, the metal silicide region SIL aggregates to form a first metal silicide region SIL1, a second metal silicide region SIL2, and a third metal silicide region SIL3.

[0056] Furthermore, the region near the interface between the body region BR and the contact region CR contains the second-conductivity-type impurities implanted to form the body region BR and the second-conductivity-type impurities implanted to form the contact region CR. Therefore, the impurity concentration in the region near the interface between the body region BR and the contact region CR is high. As a result, migration of metal silicide from the portion of the metal silicide region SIL where the interface between the body region BR and the contact region CR is located to the portion of the metal silicide region SIL adjacent to that portion is promoted. In this way, the metal silicide region SIL aggregates to form a third metal silicide region SIL3, a fourth metal silicide region SIL4, and a fifth metal silicide region SIL5.

[0057] When the contact region CR contains fluorine atoms, migration of metal silicide from a portion where the interface between the body region BR and the contact region CR is located to a portion adjacent to that portion is promoted. The aggregation of the metal silicide region SIL is promoted. The aggregation of the metal silicide region SIL is promoted, and the formation of the third metal silicide region SIL3, the fourth metal silicide region SIL4, and the fifth metal silicide region SIL5 is promoted.

[0058] Referring to FIG. 11, a second barrier metal layer BM2 is formed on a first barrier metal layer BM1. The second barrier metal layer BM2 is, for example, a TiN layer. The second barrier metal layer BM2 is formed by a CVD method and is a CVD-TiN layer. In the CVD method, TiCl4 gas is reacted with N2 to form a CVD-TiN film. Therefore, the second barrier metal layer BM2 contains chlorine atoms. The second barrier metal layer BM2 has a higher chlorine atom concentration than the first barrier metal layer BM1. The thickness of the second barrier metal layer BM2 is greater than the thickness of the first barrier metal layer BM1.

[0059] The deposition temperature of the second barrier metal layer BM2 is lower than the annealing temperature for forming the metal silicide region SIL. The deposition temperature of the second barrier metal layer BM2 is, for example, 600°C or higher and 700°C or lower. The agglomeration of the metal silicide region SIL may further progress during the deposition of the second barrier metal layer BM2. The degree of agglomeration of the metal silicide region SIL that progresses during the deposition of the second barrier metal layer BM2 is lower than the degree of agglomeration of the metal silicide region SIL that progresses during the annealing for forming the metal silicide region SIL.

[0060] Referring to FIG. 12, a contact plug CP is formed in the contact hole CH and the contact trench TR2. The contact plug CP is made of, for example, tungsten (W). For example, a tungsten film is formed on the second barrier metal layer BM2 and the interlayer insulating film IL by a CVD method that reduces tungsten fluoride (WF6). The barrier metal layer BM is a barrier against attacks by fluorine contained in WF6. Then, a portion of the material constituting the contact plug CP is removed by etch-back or chemical mechanical polishing (CMP). In this manner, the contact plug CP is formed.

[0061] The deposition temperature of the contact plug CP is lower than the annealing temperature for forming the metal silicide region SIL. The deposition temperature of the contact plug CP is equal to or lower than the deposition temperature of the second barrier metal layer BM2. The deposition temperature of the contact plug CP is, for example, approximately 600 degrees Celsius. The agglomeration of the metal silicide region SIL may further progress during the deposition of the contact plug CP. The degree of agglomeration of the metal silicide region SIL that progresses during the deposition of the contact plug CP is lower than the degree of agglomeration of the metal silicide region SIL that progresses during the annealing for forming the metal silicide region SIL.

[0062] 13, a source electrode SE is formed on the contact plug CP, the barrier metal layer BM (more specifically, the second barrier metal layer BM2), and the interlayer insulating film IL. For example, a material constituting the source electrode SE is deposited on the contact plug CP, the barrier metal layer BM (more specifically, the second barrier metal layer BM2), and the interlayer insulating film IL by, for example, a sputtering method. The deposited material constituting the source electrode SE is patterned by a photolithography process and an etching process. In this way, the source electrode SE is formed.

[0063] Referring to FIG. 14, a drain electrode DE is formed. The drain electrode DE is formed by, for example, a sputtering method. Then, a passivation film PV is formed on the source electrode SE. Specifically, a first passivation film PV1 is formed on the source electrode SE. A second passivation film PV2 is formed on the first passivation film PV1. In this way, the semiconductor device of the present embodiment shown in FIGS. 1 and 2 is obtained.

[0064] The operation of the semiconductor device SD of this embodiment and the manufacturing method thereof will be described in comparison with the semiconductor devices of the first and second comparative examples.

[0065] The semiconductor device of the first comparative example has the same configuration as the semiconductor device SD of the present embodiment, but differs from the semiconductor device SD of the present embodiment in the following respects: The metal silicide region SIL in the semiconductor device of the first comparative example has a substantially uniform thickness, as shown in Fig. 9. For example, the annealing time for forming the metal silicide region SIL in the manufacturing method for the semiconductor device of the first comparative example is shorter than the annealing time for forming the metal silicide region SIL in the manufacturing method for the semiconductor device SD of the present embodiment.

[0066] In the semiconductor device of the first comparative example, the metal silicide region SIL has a substantially uniform thickness. Therefore, when forming the contact plug CP, a high thermal stress is applied from the metal silicide region SIL to the first barrier metal layer BM1 and the second barrier metal layer BM2, causing the first barrier metal layer BM1 and the second barrier metal layer BM2 to break. The contact plug CP grows abnormally from the breakage points of the first barrier metal layer BM1 and the second barrier metal layer BM2.

[0067] The semiconductor device of the second comparative example has the same configuration as the semiconductor device SD of the present embodiment, but differs from it in the following respects: The metal silicide region SIL in the semiconductor device of the second comparative example does not have the first metal silicide region SIL1 and the fifth metal silicide region SIL5, and the third metal silicide region SIL3 is separated from the second metal silicide region SIL2 and the fourth metal silicide region SIL4. For example, the annealing time for forming the metal silicide region SIL in the manufacturing method for the semiconductor device of the second comparative example is longer than the annealing time for forming the metal silicide region SIL in the manufacturing method for the semiconductor device SD of the present embodiment.

[0068] In the semiconductor device of the second comparative example, the second metal silicide region SIL2, the third metal silicide region SIL3, and the fourth metal silicide region SIL4 are separated from one another. Therefore, when forming the contact plug CP, high thermal stress is applied to the first barrier metal layer BM1 and the second barrier metal layer BM2 from the silicon of the semiconductor substrate SUB where the metal silicide region SIL is not formed, causing the first barrier metal layer BM1 and the second barrier metal layer BM2 to break. The contact plug CP grows abnormally from the breakage points of the first barrier metal layer BM1 and the second barrier metal layer BM2.

[0069] In contrast, in the semiconductor device SD of this embodiment, the second metal silicide region SIL2 and the third metal silicide region SIL3 are connected by the first metal silicide region SIL1. The third metal silicide region SIL3 and the fourth metal silicide region SIL4 are connected by the fifth metal silicide region SIL5. The thickness of the metal silicide region SIL varies along the side surface and bottom surface of the contact trench TR2. This reduces the thermal stress applied from the metal silicide region SIL to the first barrier metal layer BM1 and the second barrier metal layer BM2 when forming the contact plug CP. Breakage of the first barrier metal layer BM1 and the second barrier metal layer BM2 is prevented when forming the contact plug CP. Abnormal growth of the contact plug CP can be prevented.

[0070] In the semiconductor device SD of this embodiment, the metal element contained in the base barrier metal layer BBM, the metal silicide region SIL, the first barrier metal layer BM1, and the second barrier metal layer BM2 is Ti, but the metal element may also be Co, Ni, Pd, Mo, or W.

[0071] The effects of the semiconductor device SD of this embodiment and the manufacturing method thereof will be described.

[0072] The semiconductor device SD of this embodiment includes a semiconductor substrate SUB, a barrier metal layer BM, and a contact plug CP. The semiconductor substrate SUB has a first main surface SF1 and a second main surface SF2 opposite to the first main surface SF1. The semiconductor substrate SUB includes a source region SR, a body region BR, and a metal silicide region SIL. The source region SR has a first conductivity type. The body region BR is in contact with the source region SR, is located on the second main surface SF2 side of the source region SR, and has a second conductivity type opposite to the first conductivity type. A contact trench TR2 extending from the first main surface SF1 to the body region BR is provided in the semiconductor substrate SUB. The barrier metal layer BM includes a first barrier metal layer BM1 and a second barrier metal layer BM2. The first barrier metal layer BM1 is formed in the contact trench TR2. The second barrier metal layer BM2 is formed on the first barrier metal layer BM1. The contact plug CP is formed on the second barrier metal layer BM2. The metal silicide region SIL is in contact with the first barrier metal layer BM1 and includes a first metal silicide region SIL1, a second metal silicide region SIL2, and a third metal silicide region SIL3. The first metal silicide region SIL1 is formed in the body region BR and the source region SR. The second metal silicide region SIL2 is connected to the first metal silicide region SIL1 and is formed in the source region SR. The third metal silicide region SIL3 is connected to the first metal silicide region SIL1 and is formed in the body region BR. The first thickness of the first metal silicide region SIL1 is smaller than the second thickness of the second metal silicide region SIL2 and smaller than the third thickness of the third metal silicide region SIL3.

[0073] The second metal silicide region SIL2 and the third metal silicide region SIL3 are connected by the first metal silicide region SIL1. The thickness of the metal silicide region SIL varies along the side surface of the contact trench TR2. Therefore, the thermal stress applied from the metal silicide region SIL to the first barrier metal layer BM1 and the second barrier metal layer BM2 when forming the contact plug CP is reduced. Breakage of the first barrier metal layer BM1 and the second barrier metal layer BM2 is prevented when forming the contact plug CP. Abnormal growth of the contact plug CP can be prevented.

[0074] In the semiconductor device SD of this embodiment, the second barrier metal layer BM2 is thicker than the first barrier metal layer BM1.

[0075] Therefore, the inner surface of the contact trench TR2 can be reliably covered with the second barrier metal layer BM2. When the contact plug CP is formed, the second barrier metal layer BM2 is prevented from being broken. Abnormal growth of the contact plug CP can be prevented.

[0076] In the semiconductor device SD of the present embodiment, the second barrier metal layer BM2 has a higher chlorine atom concentration than the first barrier metal layer BM1.

[0077] Therefore, the second barrier metal layer BM2 can be formed by a CVD method with excellent step coverage. The inner surface of the contact trench TR2 can be reliably covered with the second barrier metal layer BM2. Breakage of the second barrier metal layer BM2 is prevented when forming the contact plug CP. Abnormal growth of the contact plug CP can be prevented.

[0078] In the semiconductor device SD of the present embodiment, the metal silicide region SIL does not contain chlorine atoms.

[0079] Therefore, the contact resistance between the contact plug CP and the semiconductor substrate SUB can be reduced.

[0080] In the semiconductor device SD of the present embodiment, the semiconductor substrate SUB includes a drift region DRF and a contact region CR. The drift region DRF is in contact with the body region BR, is located on the second main surface SF2 side of the body region BR, and has a first conductivity type. The contact region CR has a second conductivity type and has a higher second conductivity type impurity concentration than the body region BR. The contact region CR is formed from the bottom surface of the contact trench TR2 to the drift region. The metal silicide region SIL includes a fourth metal silicide region SIL4 and a fifth metal silicide region SIL5. The fourth metal silicide region SIL4 is in contact with the bottom surface of the contact trench TR2 and is formed in the contact region CR. The fifth metal silicide region SIL5 is connected to the third metal silicide region SIL3 and the fourth metal silicide region SIL4, and is formed in the body region BR and the contact region CR. The fifth thickness of the fifth metal silicide region SIL5 is smaller than the third thickness of the third metal silicide region SIL3 and smaller than the fourth thickness of the fourth metal silicide region SIL4.

[0081] The third metal silicide region SIL3 and the fourth metal silicide region SIL4 are connected by a fifth metal silicide region SIL5. The thickness of the metal silicide region SIL varies along the bottom surface of the contact trench TR2. Therefore, the thermal stress applied from the metal silicide region SIL to the first barrier metal layer BM1 and the second barrier metal layer BM2 when forming the contact plug CP is reduced. Breakage of the first barrier metal layer BM1 and the second barrier metal layer BM2 is prevented when forming the contact plug CP. Abnormal growth of the contact plug CP can be prevented.

[0082] In the semiconductor device SD of the present embodiment, the contact region CR contains fluorine atoms.

[0083] Therefore, aggregation of the metal silicide region SIL is promoted. Thermal stress applied from the metal silicide region SIL to the first barrier metal layer BM1 and the second barrier metal layer BM2 when forming the contact plug CP is reduced. Breakage of the first barrier metal layer BM1 and the second barrier metal layer BM2 is prevented when forming the contact plug CP. Abnormal growth of the contact plug CP can be prevented.

[0084] A method for manufacturing a semiconductor device SD according to the present embodiment includes the steps of: preparing a semiconductor substrate SUB having a first main surface SF1 and a second main surface SF2 opposite to the first main surface SF1. The semiconductor substrate SUB includes a source region SR and a body region BR. The source region SR has a first conductivity type. The body region BR is in contact with the source region SR, is located on the second main surface SF2 side of the source region SR, and has a second conductivity type different from the first conductivity type. A method for manufacturing a semiconductor device SD according to the present embodiment includes the steps of: forming a hole HL in the semiconductor substrate SUB, the hole HL extending from the first main surface SF1 to the body region BR; forming a base barrier metal layer BBM in the hole HL; and forming a first barrier metal layer BM1 on the base barrier metal layer BBM. The method for manufacturing a semiconductor device SD according to the present embodiment includes the steps of: annealing the semiconductor substrate SUB on which the base barrier metal layer BBM and the first barrier metal layer BM1 have been formed, to form a metal silicide region SIL from the base barrier metal layer BBM and the semiconductor substrate SUB. The metal silicide region SIL is in contact with the first barrier metal layer BM1. A contact trench TR2 is defined by the interface between the metal silicide region SIL and the first barrier metal layer BM1. The manufacturing method of the semiconductor device SD of this embodiment includes the steps of forming a second barrier metal layer BM2 on the first barrier metal layer BM1 and forming a contact plug CP on the second barrier metal layer BM2. The metal silicide region SIL includes a first metal silicide region SIL1, a second metal silicide region SIL2, and a third metal silicide region SIL3. The first metal silicide region SIL1 is formed in the body region BR and the source region SR. The second metal silicide region SIL2 is connected to the first metal silicide region SIL1 and is formed in the source region SR. The third metal silicide region SIL3 is connected to the first metal silicide region SIL1 and is formed in the body region BR. The first thickness of the first metal silicide region SIL1 is smaller than the second thickness of the second metal silicide region SIL2 and smaller than the third thickness of the third metal silicide region SIL3.

[0085] The second metal silicide region SIL2 and the third metal silicide region SIL3 are connected by the first metal silicide region SIL1. The thickness of the metal silicide region SIL varies along the side surface of the contact trench TR2. Therefore, the thermal stress applied from the metal silicide region SIL to the first barrier metal layer BM1 and the second barrier metal layer BM2 when forming the contact plug CP is reduced. Breakage of the first barrier metal layer BM1 and the second barrier metal layer BM2 is prevented when forming the contact plug CP. Abnormal growth of the contact plug CP can be prevented.

[0086] In the manufacturing method of the semiconductor device SD of the present embodiment, the film formation temperature of the second barrier metal layer BM2 in the step of forming the second barrier metal layer BM2 is lower than the annealing temperature in the step of annealing the semiconductor substrate SUB.

[0087] Therefore, excessive aggregation of the metal silicide region SIL is prevented, which would otherwise cause the second metal silicide region SIL2 and the third metal silicide region SIL3 to separate from each other. The thermal stress applied from the metal silicide region SIL to the first barrier metal layer BM1 and the second barrier metal layer BM2 when forming the contact plug CP is reduced. Breakage of the first barrier metal layer BM1 and the second barrier metal layer BM2 is prevented when forming the contact plug CP. Abnormal growth of the contact plug CP can be prevented.

[0088] In the manufacturing method of the semiconductor device SD of this embodiment, the deposition temperature of the contact plug CP in the step of forming the contact plug CP is lower than the annealing temperature and equal to or lower than the deposition temperature of the second barrier metal layer BM2.

[0089] Therefore, excessive aggregation of the metal silicide region SIL is prevented, which would otherwise cause the second metal silicide region SIL2 and the third metal silicide region SIL3 to separate from each other. The thermal stress applied from the metal silicide region SIL to the first barrier metal layer BM1 and the second barrier metal layer BM2 when forming the contact plug CP is reduced. Breakage of the first barrier metal layer BM1 and the second barrier metal layer BM2 is prevented when forming the contact plug CP. Abnormal growth of the contact plug CP can be prevented.

[0090] In the manufacturing method of the semiconductor device SD of this embodiment, the second barrier metal layer BM2 is thicker than the first barrier metal layer BM1.

[0091] Therefore, the inner surface of the contact trench TR2 can be reliably covered with the second barrier metal layer BM2. When the contact plug CP is formed, the second barrier metal layer BM2 is prevented from being broken. Abnormal growth of the contact plug CP can be prevented.

[0092] In the manufacturing method of the semiconductor device SD of the present embodiment, the second barrier metal layer BM2 has a higher chlorine atom concentration than the first barrier metal layer BM1.

[0093] Therefore, the second barrier metal layer BM2 can be formed by a CVD method with excellent step coverage. The inner surface of the contact trench TR2 can be reliably covered with the second barrier metal layer BM2. Breakage of the second barrier metal layer BM2 is prevented when forming the contact plug CP. Abnormal growth of the contact plug CP can be prevented.

[0094] In the manufacturing method of the semiconductor device SD of the present embodiment, the metal silicide region SIL does not contain chlorine atoms.

[0095] Therefore, the contact resistance between the contact plug CP and the semiconductor substrate SUB can be reduced.

[0096] In the manufacturing method of the semiconductor device SD of the present embodiment, in the step of forming the first barrier metal layer BM1, the first barrier metal layer BM1 is formed by physical vapor deposition, and in the step of forming the second barrier metal layer BM2, the second barrier metal layer BM2 is formed by chemical vapor deposition.

[0097] Since the second barrier metal layer BM2 is formed by a CVD method with excellent step coverage, the inner surface of the contact trench TR2 can be reliably covered with the second barrier metal layer BM2. When the contact plug CP is formed, breakage of the second barrier metal layer BM2 is prevented. Abnormal growth of the contact plug CP can be prevented.

[0098] Since the first barrier metal layer BM1 is formed by the PVD method rather than the CVD method, it does not contain chlorine atoms resulting from the CVD method. As a result, a metal silicide region SIL that does not contain chlorine atoms is formed. This reduces the contact resistance between the contact plug CP and the semiconductor substrate SUB.

[0099] The manufacturing method of the semiconductor device SD of the present embodiment further includes a step of forming a contact region CR. The semiconductor substrate SUB includes a drift region DRF and a contact region CR. The drift region DRF is in contact with the body region BR, is located on the second main surface SF2 side of the body region BR, and has a first conductivity type. The contact region CR has a second conductivity type and has a higher second conductivity type impurity concentration than the body region BR. The contact region CR is formed from the bottom of the hole HL to the drift region. The metal silicide region SIL includes a fourth metal silicide region SIL4 and a fifth metal silicide region SIL5. The fourth metal silicide region SIL4 is in contact with the bottom surface of the contact trench TR2 and is formed in the contact region CR. The fifth metal silicide region SIL5 is connected to the third metal silicide region SIL3 and the fourth metal silicide region SIL4, and is formed in the body region BR and the contact region CR. The fifth thickness of the fifth metal silicide region SIL5 is smaller than the third thickness of the third metal silicide region SIL3 and smaller than the fourth thickness of the fourth metal silicide region SIL4.

[0100] The third metal silicide region SIL3 and the fourth metal silicide region SIL4 are connected by a fifth metal silicide region SIL5. The thickness of the metal silicide region SIL varies along the bottom surface of the contact trench TR2. Therefore, the thermal stress applied from the metal silicide region SIL to the first barrier metal layer BM1 and the second barrier metal layer BM2 when forming the contact plug CP is reduced. Breakage of the first barrier metal layer BM1 and the second barrier metal layer BM2 is prevented when forming the contact plug CP. Abnormal growth of the contact plug CP can be prevented.

[0101] In the manufacturing method of the semiconductor device SD of the present embodiment, the step of forming the contact region CR includes implanting fluoride of an impurity having the second conductivity type into the contact region CR and the drift region DRF.

[0102] Therefore, aggregation of the metal silicide region SIL is promoted. Thermal stress applied from the metal silicide region SIL to the first barrier metal layer BM1 and the second barrier metal layer BM2 when forming the contact plug CP is reduced. Breakage of the first barrier metal layer BM1 and the second barrier metal layer BM2 is prevented when forming the contact plug CP. Abnormal growth of the contact plug CP can be prevented.

[0103] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0104] BBM base barrier metal layer, BM barrier metal layer, BM1 first barrier metal layer, BM2 second barrier metal layer, BR body region, CH contact hole, CP contact plug, CR contact region, DE drain electrode, DRF drift region, DRR drain region, FP field plate electrode, GE gate electrode, GI gate insulating film, HL hole, IL interlayer insulating film, PV passivation film, PV1 first passivation film, PV2 second passivation film, SD semiconductor device, SE source electrode, SF1 first main surface, SF2 second main surface, SIL metal silicide region, SIL1 first metal silicide region, SIL2 second metal silicide region, SIL3 third metal silicide region, SIL4 fourth metal silicide region, SIL5 fifth metal silicide region, SR source region, SUB semiconductor substrate, TR1 gate trench, TR2 contact trench.

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a barrier metal layer including a first barrier metal layer and a second barrier metal layer; a contact plug; the semiconductor substrate includes a source region, a body region, and a metal silicide region, the source region having a first conductivity type, the body region being in contact with the source region, being on the second main surface side of the source region, and having a second conductivity type opposite to the first conductivity type; a contact trench extending from the first main surface to the body region is provided in the semiconductor substrate; the first barrier metal layer is formed in the contact trench; the second barrier metal layer is formed on the first barrier metal layer, the contact plug is formed on the second barrier metal layer, the metal silicide region is in contact with the first barrier metal layer and includes a first metal silicide region, a second metal silicide region, and a third metal silicide region; the first metal silicide region is formed in the body region and the source region; the second metal silicide region is connected to the first metal silicide region and is formed in the source region; the third metal silicide region is connected to the first metal silicide region and is formed in the body region; a first thickness of the first metal silicide region that is smaller than a second thickness of the second metal silicide region and smaller than a third thickness of the third metal silicide region;

2. The semiconductor device according to claim 1 , wherein said second barrier metal layer is thicker than said first barrier metal layer.

3. 2. The semiconductor device according to claim 1, wherein said second barrier metal layer has a higher chlorine atomic concentration than said first barrier metal layer.

4. 2. The semiconductor device according to claim 1, wherein said metal silicide region does not contain chlorine atoms.

5. the semiconductor substrate includes a drift region and a contact region; the drift region is in contact with the body region, is on the second main surface side of the body region, and has the first conductivity type; the contact region has the second conductivity type, has a higher impurity concentration of the second conductivity type than the body region, and is formed from a bottom surface of the contact trench to the drift region; the metal silicide region includes a fourth metal silicide region and a fifth metal silicide region; the fourth metal silicide region is in contact with the bottom surface of the contact trench and is formed in the contact region; the fifth metal silicide region is connected to the third metal silicide region and the fourth metal silicide region, and is formed in the body region and the contact region; 2. The semiconductor device according to claim 1, wherein a fifth thickness of said fifth metal silicide region is smaller than said third thickness of said third metal silicide region and smaller than said fourth thickness of said fourth metal silicide region.

6. The semiconductor device according to claim 5 , wherein said contact region contains fluorine atoms.

7. a step of preparing a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, the semiconductor substrate including a source region and a body region, the source region having a first conductivity type, the body region being in contact with the source region, being on the second main surface side of the source region, and having a second conductivity type different from the first conductivity type; forming a hole in the semiconductor substrate, the hole extending from the first major surface to the body region; forming a base barrier metal layer in the hole; forming a first barrier metal layer on the base barrier metal layer; and annealing the semiconductor substrate on which the base barrier metal layer and the first barrier metal layer are formed to form a metal silicide region from the base barrier metal layer and the semiconductor substrate, the metal silicide region being in contact with the first barrier metal layer, and a contact trench being defined by an interface between the metal silicide region and the first barrier metal layer. forming a second barrier metal layer on the first barrier metal layer; forming a contact plug on the second barrier metal layer; the metal silicide region includes a first metal silicide region, a second metal silicide region, and a third metal silicide region; the first metal silicide region is formed in the body region and the source region; the second metal silicide region is connected to the first metal silicide region and is formed in the source region; the third metal silicide region is connected to the first metal silicide region and is formed in the body region; a first thickness of the first metal silicide region being smaller than a second thickness of the second metal silicide region and smaller than a third thickness of the third metal silicide region;

8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein a film formation temperature of said second barrier metal layer in said step of forming said second barrier metal layer is lower than an annealing temperature in said step of annealing said semiconductor substrate.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein a film formation temperature of the contact plug in the step of forming the contact plug is lower than the annealing temperature and is equal to or lower than the film formation temperature of the second barrier metal layer.

10. 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of annealing the semiconductor substrate, the semiconductor substrate is annealed by lamp annealing.

11. 8. The method for manufacturing a semiconductor device according to claim 7, wherein said second barrier metal layer is thicker than said first barrier metal layer.

12. 8. The method for manufacturing a semiconductor device according to claim 7, wherein said second barrier metal layer has a higher chlorine atomic concentration than said first barrier metal layer.

13. 8. The method for manufacturing a semiconductor device according to claim 7, wherein said metal silicide region does not contain chlorine atoms.

14. In the step of forming the first barrier metal layer, the first barrier metal layer is formed by physical vapor deposition; 8. The method for manufacturing a semiconductor device according to claim 7, wherein in said step of forming said second barrier metal layer, said second barrier metal layer is formed by chemical vapor deposition.

15. forming a contact region; the semiconductor substrate includes a drift region and the contact region; the drift region is in contact with the body region, is on the second main surface side of the body region, and has the first conductivity type; the contact region has the second conductivity type, has a higher impurity concentration of the second conductivity type than the body region, and is formed from a bottom surface of the hole to the drift region; the metal silicide region includes a fourth metal silicide region and a fifth metal silicide region; the fourth metal silicide region is in contact with a bottom surface of the contact trench and is formed in the contact region; the fifth metal silicide region is connected to the third metal silicide region and the fourth metal silicide region, and is formed in the body region and the contact region; 8. The method of manufacturing a semiconductor device according to claim 7, wherein a fifth thickness of said fifth metal silicide region is smaller than said third thickness of said third metal silicide region and smaller than a fourth thickness of said fourth metal silicide region.

16. 16. The method for manufacturing a semiconductor device according to claim 15, wherein the step of forming the contact region includes implanting a fluoride of an impurity having the second conductivity type into the contact region and the drift region.

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