Manufacturing method for display device

Abstract

To provide a manufacturing method for a display device capable improving reliability.SOLUTION: According to one embodiment, a manufacturing method for a display device includes: preparing a process substrate in which a lower electrode, a rib, and a partition wall including a lower part and an upper part are formed at an upper part of the substrate; forming a first organic layer covering the lower electrode and second organic layer that separates from the first organic layer and is positioned above the upper part; forming a first upper electrode covering the first organic layer and contacting the lower part and a second upper electrode that separates from the first upper electrode and is positioned on the second organic layer; forming a sealing layer positioned on the first upper electrode and the second upper electrode; forming a resist covering part of the sealing layer; performing anisotropic dry etching with the resist as a mask; reducing film thickness of the sealing layer exposed from the resist; performing isotropic dry etching with the resist as a mask; and removing the sealing layer exposed from the resist.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a method for manufacturing a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer includes functional layers such as a hole transport layer and an electron transport layer. Such display elements are susceptible to deterioration due to moisture, and therefore a technology for reliably sealing the display elements is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a method for manufacturing a display device that can improve reliability. [Means for solving the problem]

[0005] According to one embodiment, a method for manufacturing a display device includes the steps of: A processing substrate is prepared above a substrate, the processing substrate having a lower electrode, a rib having an opening overlapping the lower electrode, and a partition wall including a lower portion disposed on the rib and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; a first organic layer covering the lower electrode and a second organic layer spaced from the first organic layer and positioned on the upper portion; a first upper electrode covering the first organic layer and contacting the lower portion, and a second upper electrode spaced from the first upper electrode and positioned on the second organic layer; a sealing layer positioned on the first upper electrode and the second upper electrode; a resist covering a portion of the sealing layer; anisotropic dry etching using the resist as a mask to reduce the film thickness of the sealing layer exposed from the resist; and isotropic dry etching using the resist as a mask to remove the sealing layer exposed from the resist. According to another embodiment, a method for manufacturing a display device includes: A processing substrate is prepared above the substrate, on which a lower electrode, a rib having an opening overlapping the lower electrode, and a partition wall including a lower portion disposed on the rib and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion, the partition wall having a shadowed region below the upper portion are formed; an organic layer is formed to cover the lower electrode, the rib, and the partition wall; an upper electrode is formed to cover the organic layer and contact the lower portion; a sealing layer is formed on the upper electrode; a resist is formed to cover a portion of the sealing layer; anisotropic dry etching is performed using the resist as a mask to reduce the film thickness of the sealing layer exposed from the resist; and isotropic dry etching is performed using the resist as a mask to remove the sealing layer exposed from the resist and the sealing layer located in the shadowed region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Figure 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Figure 3]FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line III-III in FIG. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of the display element 20. As shown in FIG. [Figure 5] FIG. 5 is a flow chart for explaining an example of a method for manufacturing the display device DSP. [Figure 6] FIG. 6 is a diagram for explaining the process of preparing a substrate to be processed. [Figure 7] FIG. 7 is a diagram illustrating the step of forming the first thin film. [Figure 8] FIG. 8 is a diagram illustrating the step of forming a resist. [Figure 9] FIG. 9 is a diagram for explaining the first etching (anisotropic dry etching) of the first thin film. [Figure 10] FIG. 10 is a diagram for explaining the second etching (isotropic dry etching) of the first thin film. [Figure 11] FIG. 11 is a diagram for explaining the third etching of the first thin film. [Figure 12] FIG. 12 is a diagram illustrating the step of removing the resist. DETAILED DESCRIPTION OF THE INVENTION

[0007] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that can be easily conceived by a person skilled in the art while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in width, thickness, shape, etc., compared to the actual embodiment for clarity of explanation, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0008] In the drawings, mutually orthogonal X-, Y-, and Z-axes are shown as necessary to facilitate understanding. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis is referred to as the second direction, and the direction along the Z-axis is referred to as the third direction. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0009] The display device according to this embodiment is an organic electroluminescence display device having organic light-emitting diodes (OLEDs) as display elements, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0010] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA, both of which are disposed on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0011] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circle, or ellipse.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a red subpixel SP1, a green subpixel SP2, and a blue subpixel SP3. The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0013] The subpixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0014] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0015] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0016] The display elements 20 are organic light-emitting diodes (OLEDs) that function as light-emitting elements and may be referred to as organic EL elements. For example, the subpixel SP1 includes a display element 20 that emits light in the red wavelength range, the subpixel SP2 includes a display element 20 that emits light in the green wavelength range, and the subpixel SP3 includes a display element 20 that emits light in the blue wavelength range.

[0017] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. 2, the subpixels SP1 and SP2 are aligned in the second direction Y. Furthermore, the subpixels SP1 and SP2 are aligned in the first direction X with the subpixel SP3.

[0018] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple subpixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0019] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0020] In the display area DA, ribs 5 and partition walls 6 are arranged. The ribs 5 have openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, opening AP2 is larger than opening AP1, and opening AP3 is larger than opening AP2.

[0021] The partitions 6 overlap the ribs 5 in a plan view. The partitions 6 have a plurality of first partitions 6x extending in the first direction X and a plurality of second partitions 6y extending in the second direction Y. The plurality of first partitions 6x are respectively arranged between the openings AP1 and AP2 adjacent to each other in the second direction Y and between two openings AP3 adjacent to each other in the second direction Y. The second partitions 6y are respectively arranged between the openings AP1 and AP3 adjacent to each other in the first direction X and between the openings AP2 and AP3 adjacent to each other in the first direction X.

[0022] 2, the first partition 6x and the second partition 6y are connected to each other. As a result, the partition 6 as a whole is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition 6 has openings in the subpixels SP1, SP2, and SP3, similar to the rib 5.

[0023] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with aperture AP3.

[0024] In the example of FIG. 2, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed-dotted lines. The peripheral edges of the lower electrodes LE1, LE2, and LE3 overlap the ribs 5. The outline of the upper electrode UE1 roughly matches the outline of the organic layer OR1, and the peripheral edges of the upper electrode UE1 and the organic layer OR1 overlap the partition walls 6. The outline of the upper electrode UE2 roughly matches the outline of the organic layer OR2, and the peripheral edges of the upper electrode UE2 and the organic layer OR2 overlap the partition walls 6. The outline of the upper electrode UE3 roughly matches the outline of the organic layer OR3, and the peripheral edges of the upper electrode UE3 and the organic layer OR3 overlap the partition walls 6.

[0025] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 constitute the display element 20 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 constitute the display element 20 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 constitute the display element 20 of the subpixel SP3. The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of the display element 20. The upper electrodes UE1, UE2, and UE3 correspond to, for example, the cathode of the display element 20, or a common electrode.

[0026] The lower electrode LE1 is connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1) through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0027] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line III-III in FIG. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0028] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12. The rib 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5.

[0029] The partition wall 6 includes a lower portion 61 disposed on the rib 5 and an upper portion 62 covering the upper surface of the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61 in FIG. 3. Such a shape of the partition wall 6 can also be said to be an overhanging shape.

[0030] The organic layer OR1 shown in FIG. 2 includes a first organic layer OR1a and a second organic layer OR1b spaced apart from each other. The upper electrode UE1 shown in FIG. 2 also includes a first upper electrode UE1a and a second upper electrode UE1b spaced apart from each other. As shown in FIG. 3, the first organic layer OR1a contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1, and also covers a portion of the rib 5. The second organic layer OR1b is located on the upper portion 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Furthermore, the first upper electrode UE1a contacts the side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0031] The organic layer OR2 shown in FIG. 2 includes a first organic layer OR2a and a second organic layer OR2b that are spaced apart from each other. The upper electrode UE2 shown in FIG. 2 also includes a first upper electrode UE2a and a second upper electrode UE2b that are spaced apart from each other. As shown in FIG. 3, the first organic layer OR2a contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2, and also covers a portion of the rib 5. The second organic layer OR2b is located on the upper portion 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. Furthermore, the first upper electrode UE2a contacts the side surface of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0032] The organic layer OR3 shown in FIG. 2 includes a first organic layer OR3a and a second organic layer OR3b that are spaced apart from each other. The upper electrode UE3 shown in FIG. 2 also includes a first upper electrode UE3a and a second upper electrode UE3b that are spaced apart from each other. As shown in FIG. 3, the first organic layer OR3a contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3, and also covers a portion of the rib 5. The second organic layer OR3b is located on the upper portion 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. Furthermore, the first upper electrode UE3a contacts the side surface of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0033] In the example shown in FIG. 3, the subpixels SP1, SP2, and SP3 include cap layers CP1, CP2, and CP3 for adjusting the optical properties of the light emitted from the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0034] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b spaced apart from each other. The first cap layer CP1a is located in the opening AP1 and is disposed on the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and is disposed on the second upper electrode UE1b.

[0035] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b spaced apart from each other. The first cap layer CP2a is located in the opening AP2 and is disposed on the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and is disposed on the second upper electrode UE2b.

[0036] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b spaced apart from each other. The first cap layer CP3a is located in the opening AP3 and is disposed on the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and is disposed on the second upper electrode UE3b.

[0037] Sealing layers 71, 72, and 73 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer 71 continuously covers the components of the subpixel SP1, including the first cap layer CP1a, the partition wall 6, and the second cap layer CP1b. The sealing layer 72 continuously covers the components of the subpixel SP2, including the first cap layer CP2a, the partition wall 6, and the second cap layer CP2b. The sealing layer 73 continuously covers the components of the subpixel SP3, including the first cap layer CP3a, the partition wall 6, and the second cap layer CP3b.

[0038] 3, the second organic layer OR1b, the second upper electrode UE1b, the second cap layer CP1b, and the sealing layer 71 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the second organic layer OR3b, the second upper electrode UE3b, the second cap layer CP3b, and the sealing layer 73 on the partition wall 6. In addition, the second organic layer OR2b, the second upper electrode UE2b, the second cap layer CP2b, and the sealing layer 72 on the partition wall 6 between the subpixels SP2 and SP3 are spaced apart from the second organic layer OR3b, the second upper electrode UE3b, the second cap layer CP3b, and the sealing layer 73 on the partition wall 6.

[0039] The sealing layers 71, 72, and 73 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. Furthermore, the sealing layer 14 is covered with a resin layer 15.

[0040] The insulating layer 12 is made of an organic material. The rib 5 and the sealing layers 14, 71, 72, and 73 are made of an inorganic material such as silicon nitride (SiNx). The thickness of the rib 5 made of an inorganic material is sufficiently smaller than the thickness of the partition wall 6 and the insulating layer 12. In one example, the thickness of the rib 5 is 200 nm or more and 400 nm or less.

[0041] The lower portion 61 of the partition wall 6 is electrically conductive. The upper portion 62 of the partition wall 6 may also be electrically conductive.

[0042] The lower electrodes LE1, LE2, and LE3 may be formed of a transparent conductive material such as ITO, or may have a laminated structure of a metal material such as silver (Ag) and a transparent conductive material. The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). The upper electrodes UE1, UE2, and UE3 may be formed of a transparent conductive material such as ITO.

[0043] When the potential of the lower electrodes LE1, LE2, LE3 is relatively higher than the potential of the upper electrodes UE1, UE2, UE3, the lower electrodes LE1, LE2, LE3 correspond to anodes and the upper electrodes UE1, UE2, UE3 correspond to cathodes. Also, when the potential of the upper electrodes UE1, UE2, UE3 is relatively higher than the potential of the lower electrodes LE1, LE2, LE3, the upper electrodes UE1, UE2, UE3 correspond to anodes and the lower electrodes LE1, LE2, LE3 correspond to cathodes.

[0044] The organic layers OR1, OR2, and OR3 each include a plurality of functional layers and a light-emitting layer.

[0045] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. These thin films have different refractive indices. The material of the thin films constituting the multilayer structure is different from the material of the upper electrodes UE1, UE2, and UE3 and also different from the material of the sealing layers 71, 72, and 73. The cap layers CP1, CP2, and CP3 may be omitted.

[0046] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the first upper electrodes UE1a, UE2a, and UE3a in contact with the side surfaces of the lower portion 61. A pixel voltage is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 included in the subpixels SP1, SP2, and SP3, respectively.

[0047] When a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength range.

[0048] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0049] FIG. 4 is a diagram showing an example of the configuration of the display element 20. As shown in FIG. The lower electrode LE shown in Fig. 4 corresponds to each of the lower electrodes LE1, LE2, and LE3 in Fig. 3. The organic layer OR shown in Fig. 4 corresponds to each of the organic layers OR1, OR2, and OR3 in Fig. 3. The upper electrode UE shown in Fig. 4 corresponds to each of the upper electrodes UE1, UE2, and UE3 in Fig. 3.

[0050] The organic layer OR includes a carrier adjustment layer CA1, an emitting layer EM, and a carrier adjustment layer CA2. The carrier adjustment layer CA1 is located between the lower electrode LE and the emitting layer EM, and the carrier adjustment layer CA2 is located between the emitting layer EM and the upper electrode UE. The carrier adjustment layers CA1 and CA2 each include multiple functional layers. The following description will be given taking as an example a case where the lower electrode LE corresponds to the anode and the upper electrode UE corresponds to the cathode.

[0051] The carrier adjustment layer CA1 includes, as functional layers, a hole injection layer F11, a hole transport layer F12, an electron blocking layer F13, etc. The hole injection layer F11 is disposed on the lower electrode LE, the hole transport layer F12 is disposed on the hole injection layer F11, the electron blocking layer F13 is disposed on the hole transport layer F12, and the light-emitting layer EM is disposed on the electron blocking layer F13.

[0052] The carrier adjustment layer CA2 includes, as functional layers, a hole blocking layer F21, an electron transport layer F22, an electron injection layer F23, etc. The hole blocking layer F21 is disposed on the light-emitting layer EM, the electron transport layer F22 is disposed on the hole blocking layer F21, the electron injection layer F23 is disposed on the electron transport layer F22, and the upper electrode UE is disposed on the electron injection layer F23.

[0053] In addition to the above-mentioned functional layers, the carrier adjustment layers CA1 and CA2 may include other functional layers such as a carrier generation layer as necessary, or at least one of the above-mentioned functional layers may be omitted.

[0054] Next, an example of a method for manufacturing the display device DSP will be described with reference to FIGS.

[0055] FIG. 5 is a flow chart for explaining an example of a method for manufacturing the display device DSP. The manufacturing method shown here roughly includes a step of preparing a processing substrate SUB that serves as a base for the subpixels (step ST1), and a step of forming the subpixels SPα (step ST2). After step ST2, a step of forming the subpixels SPβ, which is similar to the step of forming the subpixels SPα, is performed, and then a step of forming the subpixels SPγ is performed. Note that the subpixels SPα, SPβ, and SPγ here are any of the subpixels SP1, SP2, and SP3 described above.

[0056] In step ST2, first, a first thin film is formed on the processing substrate SUB (step ST21). Then, a resist patterned into a predetermined shape is formed on the first thin film (step ST22). Then, the first thin film is etched using the resist as a mask (step ST23). Then, the resist is removed (step ST24). As a result, a sub-pixel SPα having a first thin film of a predetermined shape is formed. The process of forming the sub-pixel SPβ and the process of forming the sub-pixel SPγ include the same processes as steps ST21 to ST24.

[0057] Steps ST1 and ST2 will be specifically described below.

[0058] First, in step ST1, as shown in Fig. 6, a process substrate SUB is prepared above a substrate 10, on which are formed lower electrodes LEα, LEβ, and LEγ, ribs 5 having openings APα, APβ, and APγ overlapping with the lower electrodes LEα, LEβ, and LEγ, respectively, and partition walls 6 including a lower portion 61 arranged on the rib 5 and an upper portion 62 arranged on the lower portion 61 and protruding from a side surface of the lower portion 61. Note that in Figs. 7 to 12, the substrate 10 and the circuit layer 11 below the insulating layer 12 are not shown.

[0059] 7, an organic layer OR10 is formed on the processing substrate SUB, an upper electrode UE10 is formed on the organic layer OR10, a cap layer CP10 is formed on the upper electrode UE10, and a sealing layer 70 is formed on the cap layer CP10. That is, in the example shown in FIG. 7, the first thin film includes the organic layer OR10, the upper electrode UE10, the cap layer CP10, and the sealing layer 70.

[0060] The organic layer OR10 includes a first organic layer OR11, a second organic layer OR12, a third organic layer OR13, a fourth organic layer OR14, and a fifth organic layer OR15. The first organic layer OR11, the second organic layer OR12, the third organic layer OR13, the fourth organic layer OR14, and the fifth organic layer OR15 each include a first light-emitting layer that emits light of a first color. The first organic layer OR11 is formed so as to cover the lower electrode LEα. The second organic layer OR12 is spaced apart from the first organic layer OR11 and is located on an upper portion 62 of the partition wall 6 between the lower electrode LEα and the lower electrode LEβ. The third organic layer OR13 is spaced apart from the second organic layer OR12 and is formed so as to cover the lower electrode LEβ. The fourth organic layer OR14 is spaced apart from the third organic layer OR13 and is located on an upper portion 62 of the partition wall 6 between the lower electrode LEβ and the lower electrode LEγ. The fifth organic layer OR15 is spaced apart from the fourth organic layer OR14 and is formed so as to cover the lower electrode LEγ.

[0061] The upper electrode UE10 includes a first upper electrode UE11, a second upper electrode UE12, a third upper electrode UE13, a fourth upper electrode UE14, and a fifth upper electrode UE15. The first upper electrode UE11 covers the first organic layer OR11 and is in contact with the lower portion 61 of the partition wall 6 between the lower electrode LEα and the lower electrode LEβ. The second upper electrode UE12 is spaced apart from the first upper electrode UE11 and is located on the second organic layer OR12 between the lower electrode LEα and the lower electrode LEβ. The third upper electrode UE13 is spaced apart from the second upper electrode UE12 and covers the third organic layer OR13. In the illustrated example, the third upper electrode UE13 is in contact with the lower portion 61 of the partition wall 6 between the lower electrode LEα and the lower electrode LEβ and is in contact with the lower portion 61 of the partition wall 6 between the lower electrode LEβ and the lower electrode LEγ, but may be in contact with either of the lower portions 61. The fourth upper electrode UE14 is spaced apart from the third upper electrode UE13 and is located on the fourth organic layer OR14 between the lower electrode LEβ and the lower electrode LEγ. The fifth upper electrode UE15 is spaced apart from the fourth upper electrode UE14, covers the fifth organic layer OR15, and is in contact with the lower portion 61 of the partition wall 6 between the lower electrode LEβ and the lower electrode LEγ.

[0062] The cap layer CP10 includes a first cap layer CP11, a second cap layer CP12, a third cap layer CP13, a fourth cap layer CP14, and a fifth cap layer CP15. The first cap layer CP11 is located on the first upper electrode UE11. The second cap layer CP12 is spaced apart from the first cap layer CP11 and located on the second upper electrode UE12. The third cap layer CP13 is spaced apart from the second cap layer CP12 and located on the third upper electrode UE13. The fourth cap layer CP14 is spaced apart from the third cap layer CP13 and located on the fourth upper electrode UE14. The fifth cap layer CP15 is spaced apart from the fourth cap layer CP14 and located on the fifth upper electrode UE15.

[0063] The sealing layer 70 is made of an inorganic material. The sealing layer 70 is formed to cover the first cap layer CP11, the second cap layer CP12, the third cap layer CP13, the fourth cap layer CP14, the fifth cap layer CP15, and the partition wall 6. The sealing layer 70 has a thickness Tα in the subpixel SPα, a thickness Tβ in the subpixel SPβ, and a thickness Tγ in the subpixel SPγ. Here, the thicknesses Tα, Tβ, and Tγ are approximately equal.

[0064] 8, a resist is applied onto the sealing layer 70 and then patterned. The patterned resist 30 covers the subpixel SPα. That is, the resist 30 is disposed directly above the lower electrode LEα, the first organic layer OR11, the first upper electrode UE11, and the first cap layer CP11. The resist 30 also extends above the partition wall 6 from the subpixel SPα. Between the subpixels SPα and SPβ, the resist 30 is disposed on the subpixel SPα side (left side of the figure) and exposes the sealing layer 70 on the subpixel SPβ side (right side of the figure). In the example shown, the resist 30 exposes the sealing layer 70 in the subpixels SPβ and SPγ.

[0065] The thickness T1 of the sealing layer 70 between the upper portion 62 of the partition wall 6 and the resist 30 is larger than the thickness T2 of the lower portion 61 thereof.

[0066] The width W1 of the resist 30 directly above the upper portion 62 is larger than the width W2 of the upper portion 62 protruding from the side surface of the lower portion 61 and smaller than the overall width W3 of the upper portion 62. In one example, the width W1 of the resist 30 is 1 μm or more.

[0067] Then, in step ST23, as shown in FIG. 9 , anisotropic dry etching is performed as a first etching of the first thin film using the resist 30 as a mask to reduce the film thickness of the sealing layer 70 exposed from the resist 30. Compared to isotropic dry etching, anisotropic dry etching is less prone to side etching. Therefore, side etching of the sealing layer 70 between the upper portion 62 and the resist 30 is suppressed, and the film thickness T1 of the sealing layer 70 is maintained. Note that the film thickness T3 of the sealing layer 70 in the portion exposed from the resist 30 directly above the upper portion 62 is smaller than the film thickness T1. However, the film thickness T3 is greater than 0 μm. The partition wall 6 between the subpixels SPα and SPβ, the second organic layer OR12, the second upper electrode UE12, and the second cap layer CP12 located on the partition wall 6 are all covered by the sealing layer 70.

[0068] The thickness Tβ of the sealing layer 70 in the subpixel SPβ is smaller than the thickness Tα of the sealing layer 70 in the subpixel SPα. In the example shown, the thickness Tγ of the sealing layer 70 in the subpixel SPγ is also smaller than the thickness Tα. In one example, the thicknesses Tβ and Tγ are approximately equal to the thickness T3. Note that the thicknesses Tβ and Tγ are larger than 0 μm. In other words, the sealing layer 70 remains in the subpixels SPβ and SPγ, and the third cap layer CP13 and the fifth cap layer CP15 are covered by the sealing layer 70.

[0069] The partition wall 6 between the subpixels SPβ and SPγ, the fourth organic layer OR14 located on the partition wall 6, the fourth upper electrode UE14, and the fourth cap layer CP14 are all covered with the sealing layer 70.

[0070] 10, isotropic dry etching is performed as the second etching of the first thin film using the resist 30 as a mask to remove the sealing layer 70 exposed from the resist 30. This isotropic dry etching exposes the third cap layer CP13 of the subpixel SPβ and the fifth cap layer CP15 of the subpixel SPγ from the sealing layer 70. A sealing layer 7α is formed in the subpixel SPα.

[0071] Furthermore, the lower portion 61, upper portion 62, and second cap layer CP12 between the subpixels SPα and SPβ are covered with the sealing layer 7α on the subpixel SPα side, while the subpixel SPβ side is exposed from the sealing layer. The lower portion 61, upper portion 62, and fourth cap layer CP14 between the subpixels SPβ and SPγ are exposed from the sealing layer on the subpixel SPβ side, and the subpixel SPγ side is exposed from the sealing layer. Such cap layer CP10 functions as an etching stopper layer.

[0072] The processing conditions for the above anisotropic dry etching and isotropic dry etching are as follows.

[0073] The anisotropic dry etching is performed for a predetermined time so that the thickness of the sealing layer 70 is sufficiently reduced. On the other hand, the isotropic dry etching is performed until an endpoint is detected. The endpoint can be detected, for example, by monitoring the spectrum of the plasma in the chamber.

[0074] The processing time of isotropic dry etching is shorter than that of anisotropic dry etching. That is, the amount of sealing layer 70 removed by anisotropic dry etching is greater than the amount of sealing layer 70 removed by isotropic dry etching. In other words, the processing time of isotropic dry etching is shortened, thereby suppressing side etching of the sealing layer 70.

[0075] The pressure in the chamber where anisotropic dry etching is performed is lower than the pressure in the chamber where isotropic dry etching is performed.

[0076] The bias power of the stage on which the substrate to be processed is placed when anisotropic dry etching is performed is greater than the bias power of the stage on which the substrate to be processed is placed when isotropic dry etching is performed.

[0077] The flow rate of the fluorine-based gas introduced into the chamber where anisotropic dry etching is performed is lower than the flow rate of the fluorine-based gas introduced into the chamber where isotropic dry etching is performed. Examples of gas species that can be introduced when performing anisotropic dry etching and isotropic dry etching include fluorine-based gases such as sulfur hexafluoride (SF), tetrafluoromethane (CF), hexafluoroethane (C2F6), trifluoromethane (CHF3), and nitrogen trifluoride (NF3).

[0078] In this way, the sealing layer 70 of the first thin film is formed to have a predetermined shape by performing anisotropic dry etching and then isotropic dry etching. In Comparative Example 1, when the sealing layer 70 is patterned only by isotropic dry etching, side etching proceeds excessively. As a result, when the sealing layer 70 of the subpixels not covered with the resist 30 is completely removed, there is a risk that the region near the partition wall of the subpixels covered with the resist 30 will be exposed from the sealing layer 70.

[0079] Furthermore, in Comparative Example 2, when the sealing layer 70 is patterned only by anisotropic dry etching, side etching does not progress easily. Therefore, when the sealing layer 70 in the region near the partition wall of the subpixel covered with the resist 30 is completely removed, there is a risk that the sealing layer 70 will remain in the region near the partition wall of the subpixel that is not covered with the resist 30 (particularly the region in the shadow of the upper portion 62). If a portion of the sealing layer 70 remains, further anisotropic dry etching will be performed to remove this sealing layer, which may damage the elements of the subpixel that were previously exposed from the sealing layer.

[0080] According to this embodiment, the sealing layer 70 of the sub-pixels not covered with the resist 30 is reliably removed, suppressing damage to the sub-pixel elements exposed from the sealing layer. Furthermore, the sub-pixels covered with the resist 30 are reliably covered with the sealing layer 70, suppressing the formation of undesired moisture penetration paths. Therefore, reliability can be improved.

[0081] 11, a third etching of the first thin film is performed using the resist 30 as a mask. In this third etching, a part of the second organic layer OR12, the entire third organic layer OR13, the entire fourth organic layer OR14, the entire fifth organic layer OR15, a part of the second upper electrode UE12, the entire third upper electrode UE13, the entire fourth upper electrode UE14, the entire fifth upper electrode UE15, a part of the second cap layer CP12, the entire third cap layer CP13, the entire fourth cap layer CP14, and the entire fifth cap layer CP15, which are exposed from the resist 30, are removed. As a result, the lower electrode LEβ is exposed in the subpixel SPβ, and the lower electrode LEγ is exposed in the subpixel SPγ. Furthermore, for the partition wall 6 between the subpixels SPα and SPβ, the second organic layer OR12, the second upper electrode UE12, and the second cap layer CP12 are formed on the subpixel SPα side directly above the upper portion 62, and the second organic layer OR12, the second upper electrode UE12, and the second cap layer CP12 are removed on the subpixel SPβ side, so that the upper portion 62 is exposed on the subpixel SPβ side. Furthermore, the rib 5 between the subpixels SPα and SPβ is exposed on the side of the subpixel SPβ. Furthermore, the lower portion 61 and the upper portion 62 of the partition wall 6 between the subpixels SPβ and SPγ are exposed. Furthermore, the rib 5 between the subpixels SPβ and SPγ is exposed on both the subpixel SPβ side and the subpixel SPγ side.

[0082] 12, the resist 30 is removed in step ST24, thereby forming the sub-pixel SPα. The subpixel SPα is any one of the subpixels SP1, SP2, and SP3. For example, when the subpixel SPα corresponds to the subpixel SP1, the lower electrode LEα corresponds to the lower electrode LE1, the first organic layer OR11 corresponds to the first organic layer OR1a, the second organic layer OR12 corresponds to the second organic layer OR1b, the first upper electrode UE11 corresponds to the first upper electrode UE1a, the second upper electrode UE12 corresponds to the second upper electrode UE1b, the first cap layer CP11 corresponds to the first cap layer CP1a, the second cap layer CP12 corresponds to the second cap layer CP1b, and the sealing layer 7α corresponds to the sealing layer 71.

[0083] The sub-pixels SPβ and SPγ can be formed by performing steps similar to steps ST21 to ST24 described above. In the step of forming the sub-pixel SPβ, an organic layer including a second light-emitting layer that emits light of a second color is formed on the processing substrate SUB as the organic layer. In the step of forming the sub-pixel SPγ, an organic layer including a third light-emitting layer that emits light of a third color is formed on the processing substrate SUB as the organic layer. The first color, second color, and third color are different from each other.

[0084] As described above, according to this embodiment, it is possible to provide a method for manufacturing a display device that can improve reliability and manufacturing yield.

[0085] All display device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display device manufacturing method described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0086] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0087] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0088] DSP…display device SP1, SP2, SP3... Sub-pixels 20... Display element (organic EL element) LE, LE1, LE2, LE3...lower electrode (anode) UE, UE1, UE2, UE3...Upper electrode (cathode) OR,OR1,OR2,OR3…Organic layer CP, CP1, CP2, CP3...cap layer 10...Base plate 5...Rib 6...Bulkhead 61...Lower portion 62...Upper portion 7, 71, 72, 73...Sealing layers

Claims

1. a processing substrate is provided above the substrate, the processing substrate having a lower electrode, a rib having an opening overlapping with the lower electrode, and a partition wall including a lower portion disposed on the rib and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion, the partition wall having a shadowed region below the upper portion; forming an organic layer covering the lower electrode, the rib, and the partition wall; forming an upper electrode covering the organic layer and in contact with the lower portion; forming a sealing layer located on the upper electrode; forming a resist that covers a part of the sealing layer; performing anisotropic dry etching using the resist as a mask to reduce the film thickness of the sealing layer exposed from the resist; a method for manufacturing a display device, comprising: performing isotropic dry etching using the resist as a mask to remove the sealing layer exposed from the resist and the sealing layer located in the shadow region.

2. The method for manufacturing a display device according to claim 1 , wherein a thickness of the sealing layer between the upper portion and the resist is greater than a thickness of the lower portion before the anisotropic dry etching is performed.

3. The method for manufacturing a display device according to claim 1 , wherein, before the anisotropic dry etching, a width of the resist directly above the upper portion is larger than a width of the upper portion protruding from the side surface and smaller than an overall width of the upper portion.

4. The method for manufacturing a display device according to claim 3 , wherein the width of the resist is 1 μm or more.

5. The anisotropic dry etching is performed for a predetermined time, The method for manufacturing a display device according to claim 1 , wherein the isotropic dry etching is performed until an end point is detected.

6. The method for manufacturing a display device according to claim 5 , wherein a processing time of the isotropic dry etching is shorter than a processing time of the anisotropic dry etching.

7. 2. The method for manufacturing a display device according to claim 1, wherein a pressure in a chamber in which the anisotropic dry etching is performed is lower than a pressure in a chamber in which the isotropic dry etching is performed.

8. The method for manufacturing a display device according to claim 1 , wherein a bias power of a stage on which the processing substrate is placed when the anisotropic dry etching is performed is greater than a bias power of a stage on which the processing substrate is placed when the isotropic dry etching is performed.

9. 2. The method for manufacturing a display device according to claim 1, wherein a flow rate of the fluorine-based gas introduced into the chamber where the anisotropic dry etching is performed is lower than a flow rate of the fluorine-based gas introduced into the chamber where the isotropic dry etching is performed.

10. The method for manufacturing a display device according to claim 1 , further comprising forming a cap layer located on the upper electrode before forming the sealing layer.

11. 11. The method for manufacturing a display device according to claim 10, further comprising, after removing the sealing layer, performing etching using the resist as a mask to remove a part of the cap layer, a part of the upper electrode, and a part of the organic layer.

12. The method for manufacturing a display device according to claim 11 , wherein the cap layer is an etching stopper layer used in the isotropic dry etching.

13. The method for manufacturing a display device according to claim 1 , wherein the resist does not overlap the shadow area.

Images