Status setting circuit

Abstract

To provide a status setting circuit capable of reducing a circuit scale.SOLUTION: A current generating circuit 2 generates a current Imode corresponding to a resistance value of an external resistor Rmode. A first comparing unit 31 compares a current Iref2 with the current Imode. A second comparing unit 32 compares the current Imode with a current Iref3, current Iref3+current ref4, which are switched depending on the comparison result of the first comparing unit 31. A third comparing unit 33 compares the current Imode with a current Iref7, current Iref5+current Iref7, current Iref6+current Iref7, and current Iref5+current Iref6+current Iref7, which are switched depending on the comparison results of the first and second comparing units 31 and 32. The comparison results of the first to third comparing units 31 to 33 are output to a decoder 4.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a state setting circuit. [Background technology]

[0002] Versatile power supplies can be set to multiple operating modes. Users can select a combination of these operating modes that best suits their application. Examples of combinations include power supply methods (switching power supply or series regulator) and overcurrent protection methods (timer latch or automatic recovery).

[0003] It has been proposed to set the internal operating mode according to the resistance value of an external resistor (Patent Document 1). The power supply device described in Patent Document 1 is shown in Fig. 5. As shown in the figure, a state setting circuit 100 built into the power supply device includes a current generating circuit 2 that generates a current Imode according to the resistance value of an external resistor Rmode, and first to seventh comparing units 301 to 307.

[0004] The first to seventh comparators 301 to 307 include transistors MP2 to MP8 that form a current mirror circuit with transistor MP1 through which current Imode flows and that reflect a current of the same value as current Imode, and transistors MN2 to MN8 that form a current mirror circuit with transistor MN1 through which current Iref1 flows and that receive currents Iref2 to Iref8 that are the current Iref1 reflected at a predetermined ratio. The first to seventh comparators 301 to 307 compare current Imode flowing in transistors MP2 to MP8 with currents Iref2 to Iref8 flowing in transistors MN2 to MN8, and output signals OUT1 to OUT7 that are the comparison results to decoder 4.

[0005] Fig. 6 is a table showing the relationship between the operation mode, the resistance value of the external resistor Rmode, the current Imode, and the signals OUT1 to OUT7 in the state setting circuit 100 shown in Fig. 5. As shown in the figure, the conventional power supply device 100 had to provide the same number of comparison units for each mode, which increased the number of transistors and resulted in a problem of an increase in circuit size. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6799398 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a state setting circuit that can reduce the circuit scale. [Means for solving the problem]

[0008] In order to achieve the above-mentioned object, the state setting circuit according to the present invention is characterized by the following [1] to [3]. [1] a current generating circuit that generates a resistance current according to the resistance value of the external resistor; a current source that generates a first reference current; a first reference side transistor to which the first reference current is supplied; a first comparison unit including a second reference side transistor that forms a current mirror circuit together with the first reference side transistor and through which a second reference current, which is obtained by reflecting the first reference current at a predetermined ratio, flows, and a second resistance side transistor that forms a current mirror circuit together with the first resistance side transistor through which the resistance current flows and reflects a current having the same current value as the resistance current, and that outputs a result of comparing the second reference current with the resistance current; a third reference transistor and a fourth reference transistor which form a current mirror circuit together with the first reference transistor, and through which a third reference current and a fourth reference current which are obtained by reflecting the first reference current at a predetermined ratio flow, respectively; a third resistance transistor which forms a current mirror circuit together with the first resistance transistor, and reflects a current of the same current value as the resistance current; and a second comparison unit which has a first switch which cuts off the third reference current flowing through the third reference transistor in accordance with a comparison result of the first comparison unit, and which outputs a result of comparing the resistance current with one of the fourth reference current and (the third reference current+the fourth reference current) in accordance with an on / off state of the first switch. It is a state-setting circuit. [2] In the state setting circuit according to [1], a fifth reference transistor, a sixth reference transistor, and a seventh reference transistor which form a current mirror circuit together with the first reference transistor and through which a fifth reference current, a sixth reference current, and a seventh reference current which are obtained by reflecting the first reference current at a predetermined ratio flow, respectively; a fourth resistor transistor which forms a current mirror circuit together with the first resistor transistor and reflects a current of the same current value as the resistor current; a second switch which cuts off the fifth reference current flowing to the fifth reference transistor in accordance with a comparison result of the first comparator; and a third switch which cuts off the sixth reference current flowing to the sixth reference transistor in accordance with a comparison result of the second comparator, and a third comparator which outputs a result of comparing the resistor current with one of the seventh reference current, (the fifth reference current+the seventh reference current), (the sixth reference current+the seventh reference current), and (the fifth reference current+the sixth reference current+the seventh reference current) in accordance with an on / off state of the second switch and the third switch. It is a state-setting circuit. [3] In the state setting circuit according to [1], a decoder that outputs a state setting signal according to the comparison results of the first comparator and the second comparator; A timer that measures a certain period of time from startup, a fourth switch that cuts off the current flowing through the first reference-side transistor; a fifth switch that cuts off a current flowing through the first resistor-side transistor, the current generating circuit is powered off after the timer has timed out the predetermined period of time, the decoder latches the state setting signal after the timer has timed the predetermined period of time; the fourth switch and the fifth switch cut off the current after the timer has measured the certain period of time. It is a state-setting circuit. [Effects of the Invention]

[0009] The state setting circuit according to the present invention has the effect of reducing the circuit scale.

[0010] The present invention has been briefly described above. The details of the present invention will become clearer by reading the following detailed description of the invention (hereinafter referred to as "embodiments") with reference to the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a circuit diagram showing a state setting circuit according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a table showing the relationship between the operation mode in the state setting circuit of FIG. 1, the resistance value of the external resistor Rmode, the current Imode, the signals OUT1 to OUT3, and the voltages V1 to V3. [Figure 3] FIG. 3 is a table showing the relationship between the operating mode, the resistance value of the external resistor Rmode, the current Imode, the signals OUT1 to OUT3, and the voltages V1 to V3 when Iref1:Iref2:Iref3:Iref4:Iref5:Iref6:Iref7=1:4:4:2:4:2:1 in the state setting circuit of FIG. 1. [Figure 4]FIG. 4 is a circuit diagram showing a state setting circuit according to the second embodiment of the present invention. [Figure 5] FIG. 5 is a circuit diagram showing an example of a conventional state setting circuit. [Figure 6] FIG. 6 is a table showing the relationship between the operation mode in the state setting circuit of FIG. 5, the resistance value of the external resistor Rmode, the current Imode, and the signals OUT1 to OUT7. DETAILED DESCRIPTION OF THE INVENTION

[0012] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0013] (First embodiment) 1 is a circuit diagram showing a state setting circuit of the present invention in a first embodiment. The state setting circuit 1 shown in the figure is built into a power supply device that is configured so that multiple operating modes can be set. The power supply device is made up of a semiconductor chip, and the semiconductor chip is provided with a mode setting terminal T1, a power supply terminal T21 to which a voltage Vreg is supplied, and a ground terminal T22 to which a ground voltage Vgnd is supplied.

[0014] The status setting circuit 1 outputs a status setting signal S1 that corresponds to the resistance value of an external resistor Rmode connected between the mode setting terminal T1 and the ground terminal T22. The power supply device is set to an operating mode that corresponds to the status setting signal S1. A user can set the power supply device to a desired operating mode by connecting an external resistor Rmode having a resistance value that corresponds to the desired operating mode to the mode setting terminal T1.

[0015] The state setting circuit 1 includes a current generating circuit 2, a current source CS1, a transistor MN1 (=first reference side transistor), a first comparing unit 31, a second comparing unit 32, a third comparing unit 33, and a decoder 4.

[0016] The current generating circuit 2 is a circuit that generates a current Imode (=resistor current) having a current value corresponding to the resistance value of the external resistor Rmode. The current generating circuit 2 has an amplifier OP1, a voltage source 21, and a transistor MP1 (=first resistor-side transistor). The amplifier OP1 has an inverting input connected to the voltage source 21 and a non-inverting input connected to a mode setting terminal T1. The transistor MP1 is composed of a P-channel field-effect transistor.

[0017] The transistor MP1 has a gate connected to the output of the amplifier OP1, a source connected to a power supply terminal T21, and a drain connected to the non-inverting input of the amplifier OP1 and a mode setting terminal T1. With the above configuration, the amplifier OP1 controls the current Imode flowing through the transistor MP1 so that the voltage of the mode setting terminal T1 becomes equal to the voltage Vref0 output from the voltage source 21. The current Imode is given by the following equation (1) and is a current that depends on the resistance value of the external resistor Rmode. Imode=Vref0 / Rmode …(1)

[0018] The current source CS1 is connected between the power supply terminal T21 and the transistor MN1. The transistor MN1 is composed of an N-channel field effect transistor. The gate and drain of the transistor MN1 are connected to the current source CS1, and the source is connected to the ground terminal T22. The current Iref1 (=first reference current) supplied from the current source CS1 is supplied to the transistor MN1.

[0019] The first comparison unit 31 compares the current Imode with the current Iref2 (=second reference current) and outputs the comparison result to the decoder 4. The first comparison unit 31 has a transistor MN2 (=second reference side transistor), a transistor MP2 (=second resistor side transistor), and NOT circuits 311 and 312. The transistor MN2 is composed of an N-channel field effect transistor. The transistor MP2 is composed of a P-channel field effect transistor.

[0020] The gate of transistor MN2 is connected to the gate and drain of transistor MN1, and the source is connected to ground terminal T22. The gate of transistor MP2 is connected to the gate of transistor MP1, and the source is connected to power supply terminal T21. The drains of transistors MP2 and MN2 are connected to each other, and this connection point is connected to the input of NOT circuit 311. The output of NOT circuit 311 is connected to the input of NOT circuit 312, and the output of NOT circuit 312 is connected to decoder 4.

[0021] Transistors MN1 and MN2 form a current mirror circuit, and current Iref2, which is a current Iref1 supplied to transistor MN1 mirrored at a predetermined ratio, flows through transistor MN2. The ratio between current Iref1 and current Iref2 can be changed according to the size ratio of transistors MN1 and MN2.

[0022] The transistors MP1 and MP2 form a current mirror circuit. The transistors MP1 and MP2 are provided with the same size, and a current Imode having the same current value as the current Imode flowing through the transistor MP1 is reflected back to the transistor MP2. When the current Imode is greater than the current Iref2, the voltage V1, which is the drain voltage of the transistors MP2 and MN2, becomes H level (=voltage Vreg), and the first comparator 31 outputs an H level signal OUT1 to the decoder 4. When the current Imode is less than the current Iref2, the voltage V1 becomes L level (=voltage Vgnd), and the first comparator 31 outputs an L level signal OUT1 to the decoder 4.

[0023] The second comparing unit 32 compares the current Imode with one of the current Iref4 and (current Iref3+current Iref4) depending on the on / off state of a switch SW1 (described later), and outputs the comparison result to the decoder 4. The switch SW1 (=first switch) is turned on and off depending on the comparison result of the first comparing unit 31.

[0024] The second comparator 32 includes a transistor MN3 (third reference-side transistor), a transistor MN4 (fourth reference-side transistor), a transistor MP3 (third resistor-side transistor), NOT circuits 321 and 322, and a switch SW1. The transistors MN3 and MN4 are configured as N-channel field-effect transistors. The transistor MP3 is configured as a P-channel field-effect transistor.

[0025] The gates of transistors MN3 and MN4 are connected to the gate and drain of transistor MN1, and the sources are connected to ground terminal T22. The gate of transistor MP3 is connected to the gate of transistor MP1, and the source is connected to power supply terminal T21. The drains of transistor MP3 and transistors MN3 and MN4 are connected to each other, and this connection point is connected to the input of NOT circuit 321. The output of NOT circuit 321 is connected to the input of NOT circuit 322, and the output of NOT circuit 322 is connected to decoder 4.

[0026] Transistors MN1, MN3, and MN4 form a current mirror circuit, and current Iref3 (=third reference current) and current Iref4 (=fourth reference current), which are obtained by mirroring current Iref1 supplied to transistor MN1 at a predetermined ratio, flow through transistors MN3 and MN4, respectively. The ratio between current Iref1 and currents Iref3 and Iref4 can be changed according to the size ratio of transistors MN1, MN3, and MN4.

[0027] The switch SW1 is connected between the drain of the transistor MP3 and the drain of the transistor MN3, and cuts off the current Iref3 flowing through the transistor MN3. The control terminal of the switch SW1 (not shown) is connected to the connection point between the drains of the transistors MN2 and MP2.

[0028] The transistors MP1 and MP3 form a current mirror circuit. The transistors MP1 and MP3 are provided with the same size, and the transistor MP3 mirrors back a current Imode having the same current value as the current Imode flowing through the transistor MP1. The switch SW1 is turned on when the voltage V1 is at H level. The switch SW1 is turned off when the voltage V1 is at L level. When the switch SW1 is on, the second comparison unit 32 compares the current Imode with (current Iref3 + current Iref4). When the switch SW1 is off, the second comparison unit 32 compares the current Imode with current Iref4.

[0029] When current Imode>current Iref4 or (current Iref3+current Iref4), voltage V2, which is the drain voltage of transistors MP3, MN3, and MN4, becomes H level, and an H level signal OUT2 is output from the second comparing unit 32 to the decoder 4. When current Imode<current Iref4 or (current Iref3+current Iref4), voltage V2 becomes L level, and an L level signal OUT2 is output from the second comparing unit 32 to the decoder 4.

[0030] The third comparing unit 33 compares the current Imode with one of current Iref7 (=seventh reference current), (current Iref5 (=fifth reference current)+current Iref7), (current Iref6 (=sixth reference current)+current Iref7), and (current Iref5+current Iref6+current Iref7) depending on the on / off states of switches SW2 (=second switch) and SW3 (=third switch), which will be described later, and outputs the comparison result to the decoder 4. The switches SW2 and SW3 are turned on and off depending on the comparison results of the first comparing unit 31 and the second comparing unit 32.

[0031] The third comparing unit 33 includes a transistor MN5 (=fifth reference side transistor), a transistor MN6 (=sixth reference side transistor), a transistor MN7 (=seventh reference side transistor), a transistor MP4 (=fourth resistor side transistor), NOT circuits 331 and 332, and switches SW2 and SW3. The transistors MN5 to MN7 are configured as N-channel field effect transistors. The transistor MP4 is configured as a P-channel field effect transistor.

[0032] The gates of transistors MN5 to MN7 are connected to the gate and drain of transistor MN1, and the sources are connected to ground terminal T22. The gate of transistor MP4 is connected to the gate of transistor MP1, and the source is connected to power supply terminal T21. The drains of transistor MP4 and transistors MN5 to MN7 are connected to each other, and this connection point is connected to the input of NOT circuit 331. The output of NOT circuit 331 is connected to the input of NOT circuit 332, and the output of NOT circuit 332 is connected to decoder 4.

[0033] Transistors MN1, MN5 to MN7 form a current mirror circuit, and currents Iref5 to Iref7, which are the mirrored version of current Iref1 supplied to transistor MN1, flow through transistors MN5 to MN7. The ratio between current Iref1 and currents Iref5 to Iref7 can be changed according to the size ratio between transistors MN1, MN5 to MN7.

[0034] The switch SW2 is connected between the drain of transistor MP4 and the drain of transistor MN5 and cuts off the current Iref5 flowing through transistor MN5. The switch SW3 is connected between the drain of transistor MP4 and the drain of transistor MN6 and cuts off the current Iref6 flowing through transistor MN6. The control terminal of the switch SW2 (not shown) is connected to the connection point between the drains of transistors MN2 and MP2. The control terminal of the switch SW3 (not shown) is connected to the connection point between the drains of transistors MP3, MN3, and MN4.

[0035] Transistors MP1 and MP4 form a current mirror circuit. Transistors MP1 and MP4 are the same size, and transistor MP4 mirrors back a current Imode of the same value as the current Imode flowing through transistor MP1. Switch SW2 turns on when voltage V1 is at H level. Switch SW2 turns off when voltage V1 is at L level. Switch SW3 turns on when voltage V2 is at H level. Switch SW3 turns off when voltage V2 is at L level.

[0036] When switches SW2 and SW3 are off, the third comparing unit 33 compares the current Imode with the current Iref7. When switch SW2 is on and switch SW3 is off, the third comparing unit 33 compares the current Imode with (current Iref5+current Iref7). When switch SW2 is off and switch SW3 is on, the third comparing unit 33 compares the current Imode with (current Iref6+current Iref7). When switches SW2 and SW3 are on, the third comparing unit 33 compares the current Imode with (current Iref5+current Iref6+current Iref7).

[0037] When current Imode>current Iref7, (current Iref5+current Iref7), (current Iref6+current Iref7) or (current Iref5+current Iref6+current Iref7), voltage V3 which is the drain voltage of transistors MP4, MN4 to MN7 becomes H level, and a H level signal OUT3 is output from the third comparing unit 33 to the decoder 4. When current Imode<current Iref7, (current Iref5+current Iref7), (current Iref6+current Iref7) or (current Iref5+current Iref6+current Iref7), voltage V3 becomes L level, and a L level signal OUT3 is output from the third comparing unit 33 to the decoder 4.

[0038] The decoder 4 outputs, for example, a 3-bit state setting signal S1 according to the combination of logic of the signals OUT1 to OUT3.

[0039] The operation of the above-described state setting circuit 1 will be described with reference to the table shown in FIG. 2. Now, assume that Iref7 < Iref4 < Iref6 + Iref7 < Iref2 < Iref5 + Iref7 < Iref3 + Iref4 < Iref5 + Iref6 + Iref7 is set.

[0040] When it is desired to set MODE1, the user connects an external resistor Rmode having a resistance value R1 to the mode setting terminal T1. In the current generation circuit 2, a current Imode lower than the current Iref7 is generated. In the first comparison unit 31, the current Imode and the current Iref2 are compared, and the signal OUT1 becomes the L level. In the second comparison unit 32, the switch SW1 is turned off, the current Imode and the current Iref4 are compared, and the signal OUT2 becomes the L level. In the third comparison unit 33, the switches SW2 and SW3 are turned off, the current Imode and the current Iref7 are compared, and the signal OUT3 becomes the L level.

[0041] When it is desired to set MODE2, the user connects an external resistor Rmode having a resistance value R2 to the mode setting terminal T1. In the current generation circuit 2, a current Imode such that Iref7 < Imode < Iref4 is generated. In the first comparison unit 31, the current Imode and the current Iref2 are compared, and the signal OUT1 becomes the L level. In the second comparison unit 32, the switch SW1 is turned off, the current Imode and the current Iref4 are compared, and the signal OUT2 becomes the L level. In the third comparison unit 33, the switches SW2 and SW3 are turned off, the current Imode and the current Iref7 are compared, and the signal OUT3 becomes the H level.

[0042] When it is desired to set to MODE3, the user connects an external resistor Rmode with a resistance value of R3 to the mode setting terminal T1. In the current generation circuit 2, a current Imode is generated such that Iref4 < Imode < Iref6 + Iref7. In the first comparison unit 31, the current Imode and the current Iref2 are compared, and the signal OUT1 becomes the L level. In the second comparison unit 32, the switch SW1 is turned off, the current Imode and the current Iref4 are compared, and the signal OUT2 becomes the H level. In the third comparison unit 33, the switch SW2 is turned off and the switch SW3 is turned on, the current Imode and (the current Iref6 + the current Iref7) are compared, and the signal OUT3 becomes the L level.

[0043] When it is desired to set to MODE4, the user connects an external resistor Rmode with a resistance value of R4 to the mode setting terminal T1. In the current generation circuit 2, a current Imode is generated such that Iref6 + Iref7 < Imode < Iref2. In the first comparison unit 31, the current Imode and the current Iref2 are compared, and the signal OUT1 becomes the L level. In the second comparison unit 32, the switch SW1 is turned off, the current Imode and the current Iref4 are compared, and the signal OUT2 becomes the H level. In the third comparison unit 33, the switch SW2 is turned off and the switch SW3 is turned on, the current Imode and (the current Iref6 + the current Iref7) are compared, and the signal OUT3 becomes the H level.

[0044] When it is desired to set to MODE5, the user connects an external resistor Rmode with a resistance value of R5 to the mode setting terminal T1. In the current generation circuit 2, a current Imode is generated such that Iref2 < Imode < Iref5 + Iref7. In the first comparison unit 31, the current Imode and the current Iref2 are compared, and the signal OUT1 becomes the H level. In the second comparison unit 32, the switch SW1 is turned on, the current Imode and (the current Iref3 + the current Iref4) are compared, and the signal OUT2 becomes the L level. In the third comparison unit 33, the switch SW3 is turned off and the switch SW2 is turned on, the current Imode and (the current Iref5 + the current Iref7) are compared, and the signal OUT3 becomes the L level.

[0045] When it is desired to set to MODE6, the user connects an external resistor Rmode with a resistance value R6 to the mode setting terminal T1. In the current generation circuit 2, a current Imode is generated such that Iref5 + Iref7 < Imode < Iref3 + Iref4. In the first comparator 31, the current Imode and the current Iref2 are compared, and the signal OUT1 becomes the H level. In the second comparator 32, the switch SW1 is turned on, the current Imode and (the current Iref3 + the current Iref4) are compared, and the signal OUT2 becomes the L level. In the third comparator 33, the switch SW3 is turned off and the switch SW2 is turned on, the current Imode and (the current Iref5 + the current Iref7) are compared, and the signal OUT3 becomes the H level.

[0046] When it is desired to set to MODE7, the user connects an external resistor Rmode with a resistance value R7 to the mode setting terminal T1. In the current generation circuit 2, a current Imode is generated such that Iref3 + Iref4 < Imode < Iref5 + Iref6 + Iref7. In the first comparator 31, the current Imode and the current Iref2 are compared, and the signal OUT1 becomes the H level. In the second comparator 32, the switch SW1 is turned on, the current Imode and (the current Iref3 + the current Iref4) are compared, and the signal OUT2 becomes the H level. In the third comparator 33, the switches SW2 and SW3 are turned on, the current Imode and (the current Iref5 + Iref6 + Iref7) are compared, and the signal OUT3 becomes the L level.

[0047] When it is desired to set to MODE8, the user connects an external resistor Rmode with a resistance value R8 to the mode setting terminal T1. In the current generation circuit 2, a current Imode is generated such that Iref5 + Iref6 + Iref7 < Imode. In the first comparator 31, the current Imode and the current Iref2 are compared, and the signal OUT1 becomes the H level. In the second comparator 32, the switch SW1 is turned on, the current Imode and (the current Iref3 + the current Iref4) are compared, and the signal OUT2 becomes the H level. In the third comparator 33, the switches SW2 and SW3 are turned on, the current Imode and (the current Iref5 + Iref6 + Iref7) are compared, and the signal OUT3 becomes the H level.

[0048] When Iref1:Iref2:Iref3:Iref4:Iref5:Iref6:Iref7=1:4:4:2:4:2:1, the resistance values ​​of the external resistors Rmode, the current Imode, and the signals OUT1 to OUT3 are as shown in FIG.

[0049] According to the above-described embodiment, the second comparison unit 32 can compare the current Imode with two currents Iref4, (current Iref3+current Iref4), and the third comparison unit 33 can compare the current Imode with four currents Iref7, (current Iref5+current Iref7), (current Iref6+current Iref7), and (current Iref5+current Iref6+current Iref7), so that the number of elements (number of transistors) can be reduced and the circuit size can be made smaller.

[0050] In order to set eight operation modes, the conventional state setting circuit 100 shown in Fig. 5 required 16 transistors MP1 to MP8, MN1 to MN8, whereas the state setting circuit 1 of this embodiment shown in Fig. 1 requires only 11 transistors MP1 to MP4, MN1 to MN7, thereby reducing the circuit size. Furthermore, the conventional state setting circuit 100 shown in Fig. 5 required the same number of inputs to the decoder 4 as the number of operation modes, whereas the state setting circuit 1 of this embodiment can reduce this to signals OUT1 to OUT3.

[0051] (Second embodiment) Next, a status setting circuit 1B of the present invention in a second embodiment will be described with reference to Fig. 4. In Fig. 4, parts equivalent to those in the status setting circuit 1 shown in Fig. 1 already described in the first embodiment are given the same reference numerals, and detailed description thereof will be omitted. As shown in Fig. 4, the status setting circuit 1B includes a current generating circuit 2, a current source CS1, a transistor MN1, a first comparator 31, a second comparator 32, a third comparator 33, a decoder 4, a timer 5, a transistor MN10 (=fourth switch), and a transistor MP10 (=fifth switch).

[0052] The current generating circuit 2, current source CS1, transistor MN1, first comparator 31, second comparator 32, third comparator 33, and decoder 4 are the same as those in the state setting circuit 1 shown in FIG. 1 and described in the first embodiment above, and therefore detailed description thereof will be omitted here. The timer 5 measures a fixed time from the start of the state setting circuit 1B and outputs an enable signal EN that remains at an H level for a fixed time from the start. The enable signal EN from the timer 5 is supplied to the decoder 4. The enable signal EN is also supplied to the amplifier OP1.

[0053] The transistor MP10 is composed of a P-channel field effect transistor. The transistor MN10 is composed of an N-channel field effect transistor. The source of the transistor MP10 is connected to the power supply terminal T21, and the drain is connected to the gates of the transistors MP1 to MP4. The gate of the transistor MP10 is connected to the timer 5, and an enable signal EN is supplied to the transistor MP10.

[0054] The source of the transistor MN10 is connected to the ground terminal T22, and the drain is connected to the gates of the transistors MN1 to MN7. An inverted enable signal EN is supplied to the gate of the transistor MN10.

[0055] The operation of the state setting circuit 1B configured as described above will now be described. After startup, the timer 5 outputs an H-level enable signal EN, power is supplied to the amplifier OP1, and the transistors MP10 and MN10 are turned off. After a certain time has passed since startup, the timer 5 stops outputting the H-level enable signal EN. This causes the decoder 4 to latch the output state of the state setting signal S1. Furthermore, the power supply to the amplifier OP1 is cut off. Furthermore, the transistor MP10 is turned on, cutting off the current IMode, and the transistor MN10 is turned on, cutting off the currents Iref1 to Iref7. According to the embodiment described above, it is possible to reduce current consumption after a certain time has passed since startup.

[0056] The present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. Furthermore, the material, shape, size, number, location, etc. of each component in the above-described embodiments are arbitrary and not limited as long as they can achieve the present invention.

[0057] According to the above-described embodiment, the status setting circuits 1, 1B include the third comparator 33, but this is not limiting. The third comparator 33 is not essential and may be omitted. Alternatively, two second comparators 32 may be provided instead of the third comparator 33. In this case, the currents Iref3 flowing through the two second comparators 32 must be different from each other, and the currents Iref4 must be different from each other. [Explanation of symbols]

[0058] 1. Status setting circuit 2 Current generation circuit 4 Decoder 31 First comparison section 32 Second comparison section 33 Third Comparison Section CS1 current source Imode current (resistance current) Iref1 current (first reference current) Iref2 current (second reference current) Iref3 current (third reference current) Iref4 current (fourth reference current) Iref5 current (fifth reference current) Iref6 Current (6th reference current) Iref7 current (7th reference current) MN1 transistor (first reference side transistor) MN2 transistor (second reference transistor) MN3 transistor (third reference transistor) MN4 transistor (fourth reference transistor) MN5 transistor (fifth reference transistor) MN6 transistor (sixth reference transistor) MN7 transistor (seventh reference transistor) MN10 transistor (fourth switch) MP1 transistor (first resistor side transistor) MP2 transistor (second resistor-side transistor) MP3 transistor (third resistor side transistor) MP4 transistor (fourth resistor-side transistor) MP10 Transistor (5th Switch) Rmode external resistor S1 Status setting signal SW1 switch (first switch) SW2 switch (second switch) SW3 switch (third switch)

Claims

1. a current generating circuit that generates a resistance current according to the resistance value of the external resistor; a current source that generates a first reference current; a first reference side transistor to which the first reference current is supplied; a first comparison unit including a second reference side transistor which forms a current mirror circuit together with the first reference side transistor and through which a second reference current obtained by reflecting the first reference current at a predetermined ratio flows, and a second resistance side transistor which forms a current mirror circuit together with the first resistance side transistor through which the resistance current flows and reflects a current having the same current value as the resistance current, and which outputs a result of comparing the second reference current with the resistance current; a third reference transistor and a fourth reference transistor which form a current mirror circuit together with the first reference transistor, and through which a third reference current and a fourth reference current which are obtained by reflecting the first reference current at a predetermined ratio flow, respectively; a third resistance transistor which forms a current mirror circuit together with the first resistance transistor, and reflects a current of the same current value as the resistance current; and a second comparison unit which has a first switch which cuts off the third reference current flowing through the third reference transistor in accordance with a comparison result of the first comparison unit, and which outputs a result of comparing the resistance current with one of the fourth reference current and (the third reference current + the fourth reference current) in accordance with an on / off state of the first switch. State setting circuit.

2. 2. The state setting circuit according to claim 1, a fifth reference transistor, a sixth reference transistor, and a seventh reference transistor which form a current mirror circuit together with the first reference transistor and through which a fifth reference current, a sixth reference current, and a seventh reference current which are obtained by reflecting the first reference current at a predetermined ratio flow, respectively; a fourth resistance transistor which forms a current mirror circuit together with the first resistance transistor and reflects a current having the same current value as the resistance current; a second switch which cuts off the fifth reference current flowing through the fifth reference transistor in accordance with a comparison result of the first comparison unit; and a third switch which cuts off the sixth reference current flowing through the sixth reference transistor in accordance with a comparison result of the second comparison unit, and a third comparison unit which outputs a result of comparing the resistance current with one of the seventh reference current, (the fifth reference current+the seventh reference current), (the sixth reference current+the seventh reference current), and (the fifth reference current+the sixth reference current+the seventh reference current) in accordance with an on / off state of the second switch and the third switch. State setting circuit.

3. 2. The state setting circuit according to claim 1, a decoder that outputs a state setting signal according to the comparison results of the first comparator and the second comparator; A timer that measures a certain period of time from startup, a fourth switch that cuts off a current flowing through the first reference-side transistor; a fifth switch that cuts off a current flowing through the first resistor-side transistor, the current generating circuit is powered off after the timer has timed out the predetermined period of time, the decoder latches the state setting signal after the timer has timed the predetermined period of time; the fourth switch and the fifth switch cut off the current after the timer has measured the certain period of time. State setting circuit.

Images