Compilation program and compilation method

Abstract

To reduce performance deterioration due to SFI.SOLUTION: An information processing device 101 detects target loop processing 111 from a program 110 to be optimized. The information processing device 101 also changes the target loop processing 111 to first loop processing 111a, second loop processing 111b, and third loop processing 111c. The first loop processing 111a is loop processing which executes a store instruction in advance so that access addresses of the store instruction and a load instruction do not become the same access unit from the processor to the memory for a first number of repetitions among the number of repetitions of the target loop processing 111. The second loop processing 111b is loop processing which executes the store instruction and the load instruction for a second number of repetitions obtained by subtracting the first number of times from the number of repetitions of the target loop processing 111 after the first loop processing 111a. The third loop processing 111c is loop processing which executes the load instruction for the first number of repetitions after the second loop processing 111b.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a compilation program and a compilation method. [Background technology]

[0002] Conventionally, compiler optimization methods for arrays and loops have been devised for executing programs on computers, such as loop unrolling, software pipelining, loop merging, and loop joining to speed up loop processing, as well as array merging and array dimension reduction to speed up array processing.

[0003] One prior art example is one that performs optimization processing on a program to be optimized that has a loop with vector store instructions and vector load instructions for an array variable. The optimization processing unrolls the vector store instructions and vector load instructions in the loop by a first unroll number or a second unroll number that is one less than the first unroll number, and schedules the vector load instructions that are after the first vector store instruction among the unrolled multiple vector load instructions to be moved before the first vector store instruction. The first unroll number is the number obtained by dividing the vector length by the array size of the array variable and rounding up the remainder. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-196637 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the conventional technology has a problem in that program performance may be degraded due to a Store Fetch Interlock (SFI) that occurs between a preceding store instruction and a subsequent load instruction.

[0006] In one aspect, the present invention aims to reduce performance degradation due to SFI. [Means for solving the problem]

[0007] In one embodiment, a compilation program is provided that detects, from a program to be optimized, a target loop process that includes a store instruction and a load instruction following the store instruction, and modifies the detected target loop process into a first loop process that executes the store instruction first for a first number of iterations of the target loop process, a second loop process that executes the store instruction and the load instruction after the first loop process for a second number of iterations obtained by subtracting the first number from the number of iterations, so that the access address of the store instruction and the access address of the load instruction are not the same unit of access from the processor to memory, and a third loop process that executes the load instruction for the first number of iterations after the second loop process. [Effects of the Invention]

[0008] Advantageous Effects of Invention According to one aspect of the present invention, an effect is achieved in that performance degradation due to SFI can be reduced. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is an explanatory diagram illustrating an example of a compiling method according to an embodiment. [Figure 2] FIG. 2 is an explanatory diagram showing a first example program. [Figure 3] FIG. 3 is an explanatory diagram showing a second program example. [Figure 4] FIG. 4 is a block diagram showing an example of the hardware configuration of the information processing device 101. [Figure 5] FIG. 5 is a block diagram showing an example of the functional configuration of the information processing device 101. [Figure 6] FIG. 6 is an explanatory diagram showing the relationship between store and load. [Figure 7] FIG. 7 is an explanatory diagram showing an example of a program after the loop has been restructured. [Figure 8] FIG. 8 is an explanatory diagram showing the relationship between instructions in the initial loop. [Figure 9A] FIG. 9A is an explanatory diagram (part 1) showing the relationship between instructions in a kernel loop. [Figure 9B] FIG. 9B is an explanatory diagram (part 2) showing the relationship between instructions in a kernel loop. [Figure 10] FIG. 10 is an explanatory diagram showing the relationship between instructions in the end loop. [Figure 11] FIG. 11 is a flowchart showing an example of a compilation procedure of the information processing device 101. [Figure 12] FIG. 12 is an explanatory diagram illustrating an example of the target program. [Figure 13] FIG. 13 is an explanatory diagram of an example of the contents of the DO loop management table. [Figure 14A] FIG. 14A is an explanatory diagram (part 1) showing an example of the stored contents of array definition information. [Figure 14B] FIG. 14B is a diagram (part 2) illustrating an example of the stored contents of the array definition information. [Figure 14C] FIG. 14C is an explanatory diagram (part 3) showing an example of the stored contents of the array definition information. [Figure 15] FIG. 15 is an explanatory diagram showing an example of loop division. [Figure 16] FIG. 16 is an explanatory diagram showing an example of dividing source code. [Figure 17] FIG. 17 is an explanatory diagram showing an example of the initial loop. [Figure 18] FIG. 18 is an explanatory diagram illustrating an example of a kernel loop. [Figure 19] FIG. 19 is an explanatory diagram showing an example of changing the subscripts of an array. [Figure 20] FIG. 20 is an explanatory diagram showing an example of the end loop. [Figure 21]FIG. 21 is an explanatory diagram showing assembler expansion of the kernel loop after the loop configuration has been changed. [Figure 22] FIG. 22 is an explanatory diagram showing an example of a program including an ocl statement. [Figure 23] FIG. 23 is an explanatory diagram showing an example of operation using profile information and the like. [Figure 24] FIG. 24 is a flowchart illustrating an example of a procedure for profile information acquisition processing performed by the information processing device 101. [Figure 25] FIG. 25 is an explanatory diagram showing a specific example of profile information. [Figure 26] FIG. 26 is a flowchart illustrating an example of an event information acquisition process performed by the information processing device 101. [Figure 27] FIG. 27 is an explanatory diagram illustrating an example of the configuration of a compiler. [Figure 28] FIG. 28 is a flowchart showing an example of a specific processing procedure of the compilation process of the information processing device 101. [Figure 29] FIG. 29 is a flowchart illustrating an example of a specific processing procedure of the first target loop detection processing. [Figure 30] FIG. 30 is a flowchart illustrating an example of a specific processing procedure of the second target loop detection processing. [Figure 31] FIG. 31 is a flowchart illustrating an example of a specific processing procedure for changing the loop configuration. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a compilation program and a compilation method according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0011] (Embodiment) Fig. 1 is an explanatory diagram showing an example of a compiling method according to an embodiment. In Fig. 1, an information processing device 101 is a computer that optimizes a program. The program to be optimized is a source program written in a programming language. Examples of programming languages ​​include C, FORTRAN, Java, COBOL, and shell.

[0012] The program to be optimized includes a loop including a store instruction and a load instruction following the store instruction. The store instruction is an instruction for performing a store operation, such as an instruction to write data about an array to memory. The load operation is an instruction for performing a load operation, such as an instruction to read data about an array from memory.

[0013] The information processing device 101 is, for example, a server (such as a general-purpose computer or a supercomputer). The information processing device 101 may also be a PC (Personal Computer). The program to be optimized may be, for example, an application for an HPC (High Performance Computer) or an application for business use.

[0014] Generally, when a processor reads data (load instruction, fetch) after a memory rewrite store instruction, if the write address and read address are the same, a logical contradiction occurs if the data read is executed before the preceding store instruction. For this reason, the subsequent load instruction must wait for the memory rewrite of the preceding store instruction.

[0015] On the other hand, if the addresses are different, no inconsistency occurs even if a load instruction is executed before a store instruction in a certain instruction execution group. For this reason, recent processors have an out-of-order mechanism that allows a load instruction to be executed without waiting for the preceding store instruction if the addresses of the preceding store instruction and the subsequent load instruction are different. This broadens the scope of instruction scheduling and is expected to improve performance.

[0016] In this way, when the memory rewrite address of the preceding store instruction has been determined, if the subsequent load instruction is input into the pipeline and the write address and read address for the memory match, the logic will break down if the load instruction is executed ahead of the store instruction, and therefore the load instruction cannot be executed ahead.

[0017] Therefore, data is written to memory and then read from the same memory area. From a hardware perspective, reading cannot begin until the write to the same memory area is complete, and it is not possible to execute a load instruction in parallel with a store instruction or to execute a load instruction that overtakes a store instruction. This has traditionally caused SFIs, making it impossible to avoid performance degradation. SFIs are internal delays that occur during data transfer caused by hardware.

[0018] Therefore, some recent processors are equipped with a store data forwarding function, which alleviates performance degradation by bypassing the preceding store data flowing in the store pipeline directly to the pipeline of the subsequent load instruction, rather than reading it from memory.

[0019] However, with the store data forwarding function, when a store instruction and a load instruction are issued consecutively to the same address, the subsequent load instruction must wait for the execution of the preceding store instruction, so it only reduces internal delays and still makes it difficult to avoid performance degradation.

[0020] One way to avoid this delay using software is to schedule the insertion of an operation instruction, etc., that is independent of the store instruction and the load instruction, between them in order to conceal the internal delay that occurs between the preceding store instruction and the subsequent load instruction. However, if there is no instruction that can be inserted between the store instruction and the load instruction, it is impossible to avoid a decrease in performance.

[0021] Here, an example of a program in which a load instruction is expanded immediately after a store instruction will be described with reference to FIGS.

[0022] 2 is an explanatory diagram showing a first example program. In FIG. 2, program 200 includes a loop (loop process 210) described by a do statement. In program 200, store instructions and load instructions for a(i) are deployed at close intervals during the repeatedly executed process. Moreover, because the memory address accessed is the same, an SFI occurs, and with conventional technology, performance degradation cannot be avoided even when the store data forwarding function is activated.

[0023] FIG. 3 is an explanatory diagram showing a second example program. In FIG. 3, program 300 includes a repetition (loop process 310) described by a do statement. S in program 300 is an integer variable and corresponds to the number of elements in the array. In the example of FIG. 3, "S=1". Note that the example of FIG. 2 corresponds to the case of "S=0".

[0024] Here, the access addresses of the preceding store instruction and the subsequent load instruction are different (S=1). However, SFI can occur even if the address difference between the store instruction and the load instruction does not match exactly, as long as they are within the same cache line. For example, suppose the processor's cache line size is 256 bytes.

[0025] In this case, data is transferred between memory and cache in 256-byte cache line size units, with the memory address at 256-byte boundaries. Here, the length of one element is 8 bytes, so one cache line size can store 32 (=256 / 8) elements of array a. Therefore, if S is in the range of -31 to 31, there is a possibility that a(i+S) and a(i) are located in memory at addresses that are on the same cache line, in which case an SFI will occur.

[0026] More specifically, the access addresses of the store and load instructions do not match, and because the address difference is "S=1," they are separated by one element size (8 bytes). Therefore, the store data forwarding function does not work. Furthermore, the unit of data memory write and read in a processor is generally the cache line size, which is larger than the processing unit of the store / load instructions (8 bytes in the example in Figure 3).

[0027] Therefore, in the conventional technology, even if the access addresses of the store instruction and the load instruction do not match, the write / read operations are performed on the same cache line, which causes an internal SFI and a significant degradation in performance.

[0028] Therefore, in this embodiment, a compilation method for reducing the performance degradation due to SFI occurring between a preceding store instruction and a subsequent load instruction will be described.

[0029] Here, an example of processing by the information processing device 101 will be described.

[0030] (1) The information processing device 101 detects a target loop from a program 110 to be optimized. The target loop includes a store instruction and a load instruction following the store instruction. The target loop is, for example, a high-cost loop that may cause an SFI and result in performance degradation.

[0031] Specifically, for example, the information processing device 101 may detect, as the target loop, a loop including a store instruction and a load instruction that cause an SFI by statically analyzing the program 110. Furthermore, the information processing device 101 may detect, as the target loop, a loop specified by a directive in the program 110.

[0032] In the example of FIG. 1, it is assumed that a target loop process 111 is detected from a program 110.

[0033] (2) The information processing device 101 changes the detected target loop process 111 to a first loop process 111a, a second loop process 111b, and a third loop process 111c. Here, the first loop process 111a is a loop process in which a store instruction is executed first for a first number of iterations of the target loop process 111 so that the access address of the store instruction and the access address of the load instruction do not have the same unit of access from the processor to the memory.

[0034] The access address of a store instruction is a write address for memory. The access address of a load instruction is a read address for memory. The unit of access from the processor to memory is the unit (block unit) in which reading and writing to memory is performed, such as a cache line.

[0035] The second loop processing 111b is a loop processing that executes, after the first loop processing 111a, a store instruction and a load instruction a second number of times obtained by subtracting the first number of times from the number of iterations of the target loop processing 111. In the second loop processing 111b, the access addresses of the store instruction and the load instruction are adjusted so that they do not have the same access unit (for example, cache line), and therefore the store instruction and the load instruction are each executed without generating an SFI.

[0036] The third loop process 111c is a loop process that executes the load instruction a first number of times after the second loop process 111b. In the third loop process 111c, only the remaining load instructions are executed a first number of times, the same as in the first loop process 111a.

[0037] In this way, the information processing device 101 can reduce performance degradation due to SFI that occurs between a preceding store instruction and a subsequent load instruction in the target loop process 111 for the program 110. Specifically, for example, the information processing device 101 can change the high-cost loop (target loop process 111) into three logically equivalent loop configurations (first loop process 111a, second loop process 111b, and third loop process 111c).

[0038] The information processing device 101 can provide an address difference between the store instruction and the load instruction that may cause an SFI by executing the store instruction first in the first loop processing 111a, thereby enabling the information processing device 101 to avoid consecutive area accesses in which the preceding store instruction and the subsequent load instruction access the same cache line.

[0039] In the second loop processing 111b, the access addresses of the preceding store instruction and the subsequent load instruction are in different cache lines, so that SFIs do not occur in the same loop processing, and performance degradation due to SFIs can be avoided. In addition, the information processing device 101 can adjust the overall processing volume by executing the remaining load instructions in the third loop processing 111c.

[0040] This compilation method is independent of the programming language. It is also independent of the number of array dimensions, the number of loop iterations, or the degree of multiplicity. To improve computing performance, some processors provide SIMD instructions that execute multiple pieces of data simultaneously using the same processor. Utilizing SIMD instructions is effective for processors that operate on servers and supercomputers that require high performance. This compilation method is independent of the presence or absence of SIMD (Single Instruction Multiple Data) instructions, and is also independent of the SIMD width.

[0041] In the following explanation, the number of arrays is assumed to be "1" and the programming language may be "FORTRAN" as an example. In addition, the explanation may be given using an example in which SIMD instructions are used. The SIMD instructions are assumed to have a SIMD width of 8, which can process 8 elements simultaneously, each 8 bytes.

[0042] The cache line size will sometimes be described as "256 bytes." However, the cache line size is not limited to 256 bytes and is set according to the processor. The following explanation uses array data as an example of the data to be handled, but this compilation method is not limited to arrays and can also be applied to any language that follows the grammar of a language specification that allows data to be referenced and set, such as pointer variables.

[0043] (Example of hardware configuration of information processing device 101) Next, an example of the hardware configuration of the information processing device 101 will be described.

[0044] Fig. 4 is a block diagram showing an example of the hardware configuration of the information processing device 101. In Fig. 4, the information processing device 101 has a CPU (Central Processing Unit) 401, a memory 402, a disk drive 403, a disk 404, a communication I / F (Interface) 405, a portable recording medium I / F 406, and a portable recording medium 407. Furthermore, each component is connected to each other by a bus 410.

[0045] Here, the CPU 401 controls the entire information processing device 101. The CPU 401 has a cache memory 411. The cache memory 411 is a storage device located between the CPU 401 and the memory 402, and is used as a temporary storage destination for data. The CPU 401 may also have multiple cores. Each core is an arithmetic circuit within the CPU 401.

[0046] The memory 402 includes, for example, a read-only memory (ROM), a random access memory (RAM), etc. A program stored in the memory 402 is loaded into the CPU 401, causing the CPU 401 to execute coded processing.

[0047] The disk drive 403 controls reading / writing of data from / to the disk 404 under the control of the CPU 401. The disk 404 stores data written under the control of the disk drive 403. Examples of the disk 404 include a magnetic disk and an optical disk.

[0048] The communication I / F 405 is connected to a network via a communication line, and is connected to an external computer via the network. The communication I / F 405 serves as an interface between the network and the inside of the device, and controls input and output of data from the external computer. The network may be, for example, the Internet, a LAN (Local Area Network), or a WAN (Wide Area Network). The communication I / F 405 may be, for example, a modem or a LAN adapter.

[0049] The portable recording medium I / F 406 controls reading / writing of data from / to the portable recording medium 407 under the control of the CPU 401. The portable recording medium 407 stores data written under the control of the portable recording medium I / F 406. The portable recording medium 407 is, for example, a CD (Compact Disc)-ROM, a DVD (Digital Versatile Disk), or a USB (Universal Serial Bus) memory.

[0050] In addition to the above-described components, the information processing device 101 may also include, for example, an input device, a display, etc. Furthermore, the information processing device 101 may not necessarily include, for example, the portable recording medium I / F 406 and the portable recording medium 407 among the above-described components.

[0051] (Example of functional configuration of information processing device 101) Next, an example of the functional configuration of the information processing device 101 will be described.

[0052] Fig. 5 is a block diagram showing an example of the functional configuration of the information processing device 101. In Fig. 5, the information processing device 101 includes a reception unit 501, a detection unit 502, a configuration change unit 503, and a translation unit 504. The reception unit 501 to the translation unit 504 are functions that constitute the control unit 500, and specifically, the functions are realized by, for example, having the CPU 401 execute a program stored in a storage device such as the memory 402, the disk 404, or the portable recording medium 407 shown in Fig. 4, or by the communication I / F 405. The processing results of each functional unit are stored in a storage device such as the memory 402 or the disk 404. Specifically, for example, each functional unit is realized by a compiler.

[0053] The receiving unit 501 receives a program to be optimized. Here, the program to be optimized includes a loop process including a preceding store instruction and a subsequent load instruction. The store instruction is, for example, an instruction to write data about an array to the memory 402. The load process is, for example, an instruction to read data about an array from the memory 402.

[0054] Data is exchanged between the CPU 401 and the memory 402, for example, via the cache memory 411 shown in Fig. 4. Access (writing and reading) from the CPU 401 to the memory 402 is performed in predetermined access units. The predetermined access unit is, for example, a cache line.

[0055] Specifically, for example, the reception unit 501 may receive the program to be optimized by receiving it from an external computer via the communication I / F 405. Alternatively, the reception unit 501 may receive the program to be optimized by a user's operation input using an input device (not shown).

[0056] In the following description, a program to be optimized may be referred to as a "target program." A specific example of a target program will be described later with reference to FIG. 5. The unit of access from the CPU 401 to the memory 402 is referred to as a "cache line." However, the unit of access from the CPU 401 to the memory 402 may be, for example, a unit of multiple cache lines, or may be an access unit other than a cache line.

[0057] The detection unit 502 detects a target loop process that includes a store instruction and a load instruction following the store instruction from the target program. Specifically, for example, the detection unit 502 may detect a target loop process that includes a store instruction for the same variable and a load instruction following the store instruction. The variable is, for example, an array. However, the variable may be a single variable. The loop process to be detected is, for example, the innermost loop.

[0058] More specifically, for example, the detection unit 502 detects as a target loop process a loop process that includes a store instruction for the same array and a load instruction following the store instruction, and the value obtained by multiplying the access address difference between the store instruction and the load instruction by the data size of the processing unit is less than the cache line size.

[0059] Here, the processing unit is the processing unit of a store instruction and a load instruction, and is, for example, the element size of an array. The access address difference between a store instruction and a load instruction is expressed, for example, by the number of elements. The cache line size corresponds to the unit of access from a processor (for example, CPU 401) to a memory (for example, memory 402).

[0060] This allows the detection unit 502 to automatically detect, as a target loop, a loop containing a store instruction and a load instruction that cause an SFI. An SFI is an internal delay during data transfer caused by hardware. For example, an SFI can occur when the access addresses of a preceding store instruction and a subsequent load instruction are the same. An SFI can also occur when the access addresses of a preceding store instruction and a subsequent load instruction are close to each other and therefore belong to the same cache line.

[0061] Furthermore, the detection unit 502 may detect a loop specified by a directive in the target program as the target loop. A directive is a directive to a compiler that can be arbitrarily specified by the user in the target program (source program). For example, in the case of FORTRAN, a directive is an ocl statement. In the case of C language, a directive is a character string beginning with "#pragma".

[0062] This allows the detection unit 502 to detect, as a target loop, a loop process that is likely to become a high-cost loop designated in advance by the user.

[0063] The detection unit 502 may also detect the target loop process from the target program based on execution information obtained by executing the target program. Here, the execution information is, for example, profile information or event information.

[0064] The profile information is information obtained by a profiler that indicates the execution cost and data access status, and includes, for example, the number of executions of loop processes and statements included in the target program, the number of array accesses, etc. The event information is information that can be obtained from the performance counter of the CPU 401, and indicates, for example, the number of SFI occurrences and delay cycles.

[0065] The event information is acquired by, for example, a general-purpose tool (performance analysis tool) such as perf. Furthermore, the detection unit 502 may detect the target loop processing from the target program based on information on loop structure and data dependency, static syntax information, etc., obtained when the target program is translated.

[0066] Specifically, for example, the detection unit 502 may detect, as the target loop, a loop that is likely to become a high-cost loop by combining profile information, event information, information on loop structure and data dependency obtained during translation, static syntax information, etc. More specifically, for example, the detection unit 502 may determine, as the target loop, a loop that includes a preceding store instruction and a subsequent load instruction, generates an SFI, and has an execution cost equal to or greater than a threshold, as a high-cost loop, and detect it as the target loop.

[0067] Furthermore, the detection unit 502 may generate a learning model for detecting the target loop processing by performing machine learning on a combination of profile information, event information, information on loop structures and data dependencies obtained during translation, static syntax information, etc. Then, the detection unit 502 may use the generated learning model to detect the target loop processing from the profile information, etc.

[0068] In the following description, of the store instruction and the load instruction following the store instruction included in the target loop processing, the store instruction may be referred to as the "preceding store instruction" and the load instruction may be referred to as the "subsequent load instruction."

[0069] The subsequent load instruction is executed, for example, immediately after the preceding store instruction. However, depending on the scheduling, other instructions such as an arithmetic instruction may be inserted between the preceding store instruction and the subsequent load instruction. For this reason, the following description may take as an example a case where the subsequent load instruction is executed immediately after the preceding store instruction, but is not limited to this.

[0070] The configuration change unit 503 changes the detected target loop processing into an initial loop (first loop processing), a kernel loop (second loop processing), and an end loop (third loop processing). Here, the initial loop is a loop processing in which the preceding store instruction is executed first for a first number of times among the loop rotation numbers (number of iterations) of the target loop processing so that the access address of the preceding store instruction and the access address of the subsequent load instruction do not become the same cache line.

[0071] A cache line corresponds to a unit of access from a processor (e.g., CPU 401) to a memory (e.g., memory 402). The kernel loop is a loop process that executes a preceding store instruction and a subsequent load instruction a second number of times, which is the number of loop rotations of the target loop process minus a first number of times, after the initial loop. The end loop is a loop process that executes a subsequent load instruction a first number of times after the kernel loop.

[0072] Specifically, for example, the configuration change unit 503 calculates the first count based on the access address difference between the preceding store instruction and the subsequent load instruction, the data size of the processing unit, and the cache line size. Here, the processing unit is the processing unit of the preceding store instruction and the subsequent load instruction, such as the element size of an array. The cache line size corresponds to the data size of the unit of access from the processor to the memory.

[0073] More specifically, for example, the configuration change unit 503 may calculate the first number of times by subtracting the size according to the access address difference from the cache line size and dividing the result by the element size. Here, the size according to the access address difference corresponds to, for example, the value obtained by multiplying the access address difference (number of elements) by the element size.

[0074] Furthermore, the configuration change unit 503 sets a control variable for the initial loop, a control variable for the kernel loop, and a control variable for the end loop based on the calculated first count. Here, the control variables include, for example, an initial value, a final value, and an increment value. The initial value is the value of the control variable for the first loop. The final value is the value of the control variable for the last loop. The increment value is the increment value of the control variable that is changed for each loop. The initial value and increment value for the initial loop are identified, for example, from the control variable of the target loop processing.

[0075] The translation unit 504 generates a machine language program corresponding to the changed target program. Here, the changed target program is a target program in which the target loop has been changed to an initial loop, a kernel loop, and an end loop. The machine language program is, for example, object code. Specifically, for example, the machine language program is generated by translating the changed target program.

[0076] The information processing device 101 may execute the target program based on the generated machine language program. Specifically, the information processing device 101 may create an executable file from the machine language program and execute the created executable file.

[0077] Furthermore, the information processing device 101 may output the generated machine language program, for example. The output format may be, for example, storing the program in a storage device such as the memory 402 or the disk 404, or transmitting the program to another computer via the communication I / F 405. This allows the information processing device 101 to make the optimized target program executable on, for example, another computer.

[0078] Furthermore, the information processing device 101 may optimize the target program when it receives an instruction to optimize the target program. Specifically, for example, the receiving unit 501 receives an instruction to optimize the target program. Then, when the detecting unit 502 receives an instruction to optimize the target program, it may detect a target loop process from the target program. This allows the information processing device 101 to optimize the target program using this compiling method only when, for example, a user instructs it to do so.

[0079] Furthermore, the information processing device 101 may use a compiler translation option to change the loop structure for an array in the detected target loop process and expand object code that avoids SFI (-KaviodSFI). Furthermore, the information processing device 101 may use a compiler translation option to change the loop structure for an array (A) in a loop process specified by the user and expand object code that avoids SFI (-KavoidSFI(A)). The keyword of the compiler translation option (for example, KaviodSFI) can be set arbitrarily.

[0080] (Example of operation of information processing device 101) Next, an example of the operation of the information processing device 101 will be described. Here, the program 300 shown in FIG. 3 will be used as an example of the target program.

[0081] In loop processing 310 in program 300, the access addresses of the preceding store instruction and the subsequent load instruction differ by 8 bytes. Specifically, the array subscript of the preceding store processing is "S=1", and the access addresses of the preceding store instruction and the subsequent load instruction differ by only one element. Therefore, the difference in access addresses between the preceding store instruction and the subsequent load instruction is 8 bytes, the equivalent of one element.

[0082] In this case, the preceding store instruction is assumed to be an instruction (store) that stores 64 bytes of data (8 elements) from a register to a continuous memory area, and the subsequent load instruction is assumed to be an instruction (load) that reads 64 bytes (8 elements) from a memory area to a register.

[0083] The relationship between these instructions (store, load) is shown in Figure 6. However, the cache line size is assumed to be 256 bytes.

[0084] 6 is an explanatory diagram showing the relationship between store and load. As shown in FIG. 6, the access addresses of the instruction (store) and the instruction (load) are the same cache line. Therefore, if this continues, an SFI will occur, resulting in a decrease in performance of the program 300.

[0085] Therefore, the information processing device 101 reconfigures the loop structure of the loop process 310 (see FIG. 3) that includes the preceding store instruction and the subsequent load instruction that cause the SFI. Specifically, for example, the information processing device 101 changes the loop process 310 in the program 300 into three logically equivalent loop configurations (initial loop, kernel loop, and end loop) as shown in FIG.

[0086] 7 is an explanatory diagram showing an example of a program after the loop has been restructured. In FIG. 7, the loop processing 310 (see FIG. 3) in the program 300 has been changed to an initial loop 710, a kernel loop 720, and an end loop 730.

[0087] The initial loop 710 is a loop process that executes a store instruction first to set an access address difference between the preceding store instruction and the subsequent load instruction, which may cause an SFI, so that the access addresses of the preceding store instruction and the subsequent load instruction do not become the same cache line.

[0088] As a result, the information processing device 101 avoids accessing consecutive areas in which the preceding store instruction and the subsequent load instruction access the same cache line.

[0089] Specifically, for example, the information processing device 101 separates the preceding store instruction resulting from the SFI from the subsequent store instruction and divides the loop in the initial loop 710. More specifically, the information processing device 101 extracts an if statement [if(x(i)==0) then a(i+S)=(i+S)*3.14 end if] including the preceding store instruction in the loop processing 310 and an if statement from a transfer statement [b(i)=a(i)] including a subsequent load instruction having an SFI relationship, and configures the preceding store instruction as the initial loop 710.

[0090] This allows the information processing device 101 to avoid access to the same cache line by the preceding store instruction and the subsequent load instruction in the initial loop 710. In this case, the information processing device 101 adjusts the number of rotations (loop rotation number) in the initial loop 710, for example, so that the preceding store instruction is executed one cache line length ahead.

[0091] This number of rotations is the number of times the preceding store instruction is repeatedly executed in the initial loop 710, and corresponds to the above-mentioned "first number of times." Here, the size according to the access address difference between the preceding store instruction and the subsequent load instruction is represented as "A," and the address of array X(i) is represented as &X(i).

[0092] In this case, in the example of the program 300, "A=&a(i+S)-&a(i)=8" is obtained. The cache line size is "256 bytes", and the access address of the preceding store instruction precedes the access address of the subsequent load instruction. The information processing device 101 places the access address of the preceding store instruction in a different cache line from the access address of the subsequent load instruction.

[0093] For this reason, the information processing device 101 executes the preceding store instruction (storing process to the preceding array) in advance for, for example, "31 elements (D)" obtained by dividing the remaining byte length (256-8) to the next cache line size by the element size "8". As a result, in the initial loop 710, the store process to the array is performed with the number of rotations set to "31".

[0094] In the kernel loop 720 to be executed next, the access addresses of the preceding store instruction and the subsequent load instruction are adjusted to be different cache lines, which enables the information processing device 101 to execute the preceding store instruction and the subsequent load instruction without generating an SFI, thereby avoiding performance degradation due to an SFI.

[0095] Specifically, for example, in the kernel loop 720, the access addresses of the preceding store instruction and the subsequent load instruction are separated by one cache line size, so that SFI does not occur and performance degradation can be avoided. Here, the subsequent load instruction is started for the first time in the kernel loop 720. Therefore, the information processing device 101 sets the start position (initial value) of the control variable of the kernel loop 720 to the same start position "1" as before the change.

[0096] However, the preceding store instruction is executed only from 1 to D in the initial loop 710. Therefore, the information processing device 101 shifts the start position of the preceding store instruction by D (S+1+D) in the kernel loop 720. Furthermore, since the information processing device 101 executes only the subsequent load instruction in the end loop 730, the end position of the control variable of the kernel loop 720 is set to a value (nD) obtained by subtracting D, the number of preceding store operations executed in the initial loop 710, from the pre-change rotation speed.

[0097] In the end loop 730 to be executed next, the preceding store instruction is executed in advance, and therefore, by executing only the remaining subsequent load instruction, the overall processing amount is adjusted. Specifically, for example, in the end loop 730, the information processing device 101 executes load processing for the remaining D amount that is shifted in the kernel loop 720. This allows the information processing device 101 to make the execution order and the number of times of execution of the preceding store instruction and the structure load instruction the same before and after changing the loop configuration.

[0098] The relationship between the instructions (store, load) in each loop (initial loop 710, kernel loop 720, end loop 730) after the loop configuration has been changed is shown in Figures 8, 9A, 9B, and 10. However, the cache line size is assumed to be "256 bytes."

[0099] 8 is an explanatory diagram showing the relationship between instructions in an initial loop. As shown in Fig. 8, in an initial loop 710, an instruction (store) is executed first to create an access address difference between a preceding store instruction that may cause an SFI and a subsequent load instruction. In Fig. 8, the instruction (store) corresponds to a store process that writes one element (8 bytes) from a register to a memory area.

[0100] 9A and 9B are explanatory diagrams showing the relationship between instructions in a kernel loop. As shown in Fig. 9A and 9B, in the kernel loop 720, although the preceding store instruction and the subsequent load instruction are each executed, an SFI does not occur because the access addresses of the preceding store instruction and the subsequent load instruction are separated by one cache line size.

[0101] In Figure 9A, the instruction (load) corresponds to a load operation that reads 64 bytes of eight consecutive elements from a memory area into a register. In Figure 9B, the instruction (store) corresponds to a store operation that writes 64 bytes of eight elements of 8-byte data from a register to a consecutive memory area.

[0102] Figure 10 is an explanatory diagram showing the relationship between instructions in the end loop. As shown in Figure 10, in the end loop 730, in order to adjust the overall processing volume, only the remaining subsequent load instructions are executed. In Figure 10, the instruction (load) corresponds to a load process that reads one element (8 bytes) from the memory area into a register.

[0103] In this way, according to the information processing device 101, in the case where an SFI occurs in the high-cost processing (loop processing 310), the loop structure can be reconfigured to provide an access address difference between the preceding store instruction and the subsequent load instruction. This allows the information processing device 101 to avoid access to nearby addresses in the same cache line by the store instruction and the load instruction.

[0104] (Compilation process procedure of information processing device 101) Next, the compilation procedure of the information processing device 101 will be described.

[0105] Fig. 11 is a flowchart showing an example of a compilation procedure of the information processing device 101. In the flowchart of Fig. 11, first, the information processing device 101 receives a program to be optimized (step S1101).

[0106] The information processing device 101 then detects, from the received program, a target loop process that includes a store instruction and a load instruction that follows the store instruction (step S1102). The target loop process is, for example, a loop process that includes a preceding store instruction and a subsequent load instruction for the same array, and in which the value obtained by multiplying the access address difference between the preceding store instruction and the subsequent load instruction by the element size is less than the cache line size.

[0107] Next, the information processing device 101 changes the detected target loop processing to an initial loop, a kernel loop, and an end loop (step S1103). The initial loop is a loop processing in which the preceding store instruction is executed first for the first number of iterations of the target loop processing so that the access addresses of the preceding store instruction and the subsequent load instruction do not become the same cache line.

[0108] The kernel loop is a loop process that executes the preceding store instruction and the subsequent load instruction a second number of times, which is the number of iterations of the target loop process minus the first number of times, after the initial loop. The end loop is a loop process that executes the subsequent load instruction a first number of times, after the kernel loop.

[0109] Then, the information processing apparatus 101 generates a machine language program corresponding to the changed target program (step S1104), and ends the series of processes according to this flowchart.

[0110] As a result, the information processing device 101 can change the high-cost process (target loop process) into three logically equivalent loop configurations, thereby preventing a performance degradation due to SFI.

[0111] Example 1 Next, a first embodiment of the present compiling method will be described. First, the target program (the program to be optimized) will be described with reference to FIG.

[0112] Fig. 12 is an explanatory diagram showing an example of a target program. In Fig. 12, the target program 1200 includes a repetition described by a do statement (for example, a loop process 1210). The loop process 1210 corresponds to the innermost loop. Note that the numbers in the left corner of the target program 1200 indicate line numbers.

[0113] Next, the contents of the DO loop management table will be described with reference to Figure 13. The DO loop management table stores management information related to loop processing for each loop processing corresponding to a source program (for example, the target program 1200). Note that even loop repetitions other than do statements, which are syntactically the same as do statements, are also included in the loop processing. The DO loop management table is created, for example, by syntactically analyzing the target program 1200.

[0114] 13 is an explanatory diagram showing an example of the contents of a DO loop management table. In Fig. 13, the DO loop management table 1300 has fields for loop number, loop nest level, control variable, initial value, end value, increment value, array definition information, and variable definition information. By setting information in each field, DO loop management information (for example, DO loop management information 1300-1 to 1300-3) is stored as records.

[0115] Here, the loop number is a number created for each loop process written in a program. In the target program 1200 shown in Fig. 12, three loop processes appear, so three loop numbers (1, 2, 3) are prepared.

[0116] The loop nest level indicates the multiplicity of loop processing. If there is no nesting, the multiplicity is "1". For example, in the target program 1200, the multiplicity of the loop processing of loop number "2" is "2". The loop nest level corresponding to loop number "2" is "2". Note that the multiplicity of the loop processing of other loop numbers "1, 3" is "1".

[0117] The control variable is the control variable for the loop processing. In the case of a Fortran do statement, if "do i=is,ie,id" is written, the control variable is "i". In the target program 1200, the control variable corresponding to loop number "2" is "i".

[0118] The initial value is the initial value of the control variable for the loop processing. The value of the control variable for the first loop is stored in the initial value. In the case of a Fortran do statement, if "do i=is,ie,id" is written, the initial value is "is". In the target program 1200, the initial value of the control variable corresponding to loop number "2" is "1".

[0119] The end value is the end value of the control variable for the loop processing. The value of the control variable in the last loop processing is stored in the end value. In the case of a Fortran do statement, if "do i=is,ie,id" is written, the end value is "ie". In the target program 1200, the end value of the control variable corresponding to loop number "2" is "n".

[0120] The increment value is the increment value of the control variable for the loop processing. The increment value stores the increment value of the control variable that is changed for each loop. In the case of a Fortran do statement, if "do i=is,ie,id" is written, the increment value is "id". In the target program 1200, the increment value of the control variable corresponding to loop number "2" is "1", and the notation is omitted.

[0121] The array definition information is a pointer to a table of array definition information relating to arrays that appear during loop processing. In the target program 1200, the array definition information corresponding to loop number “2” points to the table of array definition information 2.

[0122] The variable definition information is a pointer to a table of variable definition information relating to variables that appear during loop processing. In the target program 1200, the variable definition information corresponding to loop number “2” points to the table of variable definition information 2.

[0123] 14A, 14B, and 14C, the contents of the array definition information (array definition information 1, 2, 3) will be described. The array definition information (array definition information 1, 2, 3) stores the array definition of the array that appears for each line (statement identification number) that appears during loop processing of the source program (for example, target program 1200).

[0124] 14A, 14B, and 14C are explanatory diagrams showing an example of the stored contents of array definition information. In FIGS. 14A, 14B, and 14C, array definition information 1, 2, and 3 have fields for table number, array name, number of dimensions, first-dimension subscript, element size, definition (1: setting, 2: setting + reference, 0: reference), and statement identification number. By setting information in each field, array definitions (e.g., array definitions 1311, 1321 to 1327, 1331, and 1332) are stored as records.

[0125] Here, the table number is the number of the array created for each line written in the program. If there are multiple arrays on the same line, they are assigned in the order in which they are processed. The array name is the name of the array defined in the program. In the example of array definition information 2, x, a, b, and c are stored for each statement identification number as the array corresponding to loop number "2."

[0126] The number of dimensions indicates the number of dimensions of the array. The first-dimensional subscript indicates the first-dimensional subscript. Here, we assume that we are determining whether the access addresses of a store instruction and a load instruction are the same cache line. In array accesses of two or more dimensions, including one-dimensional arrays, consecutive access occurs during one-dimensional access. Therefore, to check only one-dimensional accesses, the first-dimensional subscript is stored. In the example of array definition information 2, the first-dimensional subscript of array a with identification number "13" corresponding to loop number "2" is "i+S".

[0127] The element size is the size of an array element. It can be defined as "1: Set", "2: Set + Reference", or "0: Reference". For example, when a store operation is performed as a statement, the definition is "1: Set". Also, when a store operation and a load operation for the same array element appear in a single statement, the definition is "2: Set + Reference". In this case, a data write occurs as a store operation, but because it is the same array element, the data read comes first. Since it is a pre-load and a subsequent store, an SFI does not occur. When a load operation is performed as a statement, the definition is "0: Reference".

[0128] Statement identification numbers indicate the corresponding lines in the program. However, statement identification numbers created by the compiler may not strictly correspond to line numbers. For example, "b(i+100)=c(i+2,j)+b(i+100)+b(j*2)" on lines 16 and 17 of target program 1200 is two lines of source code, but as an assignment statement it is one line because it forms one statement. Therefore, in array definition information 2, the statement identification number of arrays b(i+100) and b(j*2) on line 17 is "16," the same as that of b(i+100) and c(i+2,j) defined on line 16, which are the same statements.

[0129] 13, the information processing device 101 detects a target loop process from the target program 1200. Specifically, for example, the information processing device 101 searches for a case that becomes an SFI by referring to array definition information corresponding to each loop number in the DO loop management table 1300.

[0130] Here, an example will be described in which a search for a case that results in SFI is performed by referring to the array definition information 2 shown in Figure 14B. Also, the element size of the array is assumed to be "8 bytes" and the cache line size is assumed to be "256 bytes." The variable S included in the target program 1200 is assumed to be "S=1."

[0131] First, the information processing device 101 identifies table numbers i from the beginning to the end of the array definition information 2. Here, table numbers 1 to 7 (i=1, 2, . . . , 7) are identified.

[0132] Then, the information processing device 101 searches for arrays (from i=1 to the last -1) for consecutive table numbers "i" and "i+1" in the array definition information 2, where an array exists at the access destination in the store process and load process that cause the SFI to occur, and which satisfy all of the following conditions (i) to (iv).

[0133] (i) ARRAY_TBL(i).array = ARRAY_TBL(i+1).array

[0134] Here, ARRAY_TBL(i).array indicates the array of table number i in the array definition information. In the example of array definition information 2, when "i=2", the same array a is obtained, satisfying condition (i). Below, we will explain the case of "i=2", which satisfies condition (i), as an example.

[0135] (ii) |ARRAY_TBL(i).1D index - ARRAY_TBL(i+1).1D index |*element size < cachelinesize

[0136] Here, ARRAY_TBL(i).1st-dimension subscript indicates the 1st-dimension subscript of the array of table number i in the array definition information. In the example of array definition information 2, when "i=2", it is "ARRAY_TBL(2).1st-dimension subscript=i+S" and "ARRAY_TBL(3).1st-dimension subscript=i".

[0137] Furthermore, the element size is "8 bytes." The cachelinesize is "256 bytes." The variable S is "S=1." In this case, "|(i+1)-i|*8<256" holds, which satisfies the condition (ii).

[0138] (iii) ARRAY_TBL(i).definition = 1 (setting), and ARRAY_TBL(i+1).definition = 0 (reference)

[0139] Here, ARRAY_TBL(i).definition indicates the definition of table number i in the array definition information. In the example of array definition information 2, when "i=2", "ARRAY_TBL(2).definition=1 (setting)" and "ARRAY_TBL(3).definition=0 (reference)" are used. In this case, condition (iii) is met.

[0140] (iv)ARRAY_TBL(i).Sentence identification number≦ARRAY_TBL(i+1).Sentence identification number

[0141] Here, ARRAY_TBL(i).statement_id indicates the statement identification number of table number i in the array definition information. In the example of array definition information 2, when "i=2", "ARRAY_TBL(2).statement_id=13" and "ARRAY_TBL(3).statement_id=15" are used. In this case, condition (iv) is met.

[0142] The information processing device 101 detects, as a target loop, a loop including a preceding store instruction and a subsequent load instruction for an array that satisfies all of the conditions (i) to (iv). An array that satisfies all of the conditions (i) to (iv) can be said to be an SFI target array.

[0143] For example, if conditions (i), (iii), and (iv) are met, it can be said that the loop includes a preceding store instruction and a subsequent load instruction for the same array. Also, if condition (ii) is met, it can be said that the loop is one in which the value obtained by multiplying the access address difference between the preceding store instruction and the subsequent load instruction by the element size is less than the cache line size.

[0144] Note that, in some cases, it may be possible to insert another instruction between the store instruction and the load instruction that can hide the interlock cycle of the SFI due to instruction scheduling by the compiler. Therefore, when it is not possible to insert another instruction that can hide the interlock cycle of the SFI, the information processing device 101 may detect, as the target loop, a loop including a preceding store instruction and a subsequent load instruction for an array that satisfies all of the conditions (i) to (iv).

[0145] In the target program 1200, for example, a loop 1210 (see FIG. 12) is detected as the target loop.

[0146] Next, the information processing device 101 changes the detected target loop process (for example, loop process 1210) into three logically equivalent loop configurations (initial loop, kernel loop, and end loop). A specific processing example when changing the loop configuration will be described below with reference to FIGS. 15 to 20.

[0147] 15 is an explanatory diagram showing an example of loop division. In FIG. 15, a loop 1500 is a simplified representation of the target loop processing. First, the information processing device 101 decomposes the loop 1500 into two. Specifically, for example, the information processing device 101 divides the loop 1500 into a loop 1510 including a precedent store processing (PS) and a loop 1520 including a subsequent load processing (PL).

[0148] As a result, the information processing device 101 separates the preceding store operation (PS) that causes the SFI from the subsequent load operation (PL). At this time, logically, the number of revolutions of the two divided loops 1510 and 1520 must be the same as before the division. Note that the loop division method is an existing technology, so a detailed explanation will be omitted.

[0149] Here, an example of dividing source code will be described using the loop process 1210 shown in FIG. 12 as an example.

[0150] Fig. 16 is an explanatory diagram showing an example of dividing source code. In Fig. 16, a loop process 1210 corresponds to a target loop process detected from a target program 1200 (see Fig. 12). The loop process 1210 includes a preceding store process PS and a following load process PL.

[0151] The information processing device 101 divides the loop processing 1210 into a loop processing 1610 including a store processing (PS) and a loop processing 1620 including a load processing (PL). The preceding store processing (PS) corresponds to the preceding store instruction. The subsequent load processing (PL) corresponds to the subsequent load instruction.

[0152] Next, the information processing device 101 changes the divided loop 1510 (for example, loop processing 1610) and loop 1520 (for example, loop processing 1620) into three loop configurations (initial loop, kernel loop, and end loop). In the initial loop, only a store operation (PS) is executed. In the kernel loop, a store operation (PS) and a load operation (PL) are executed. In the end loop, only a load operation (PL) is executed.

[0153] The execution order and execution count of the store operation (PS) and the load operation (PL) remain the same before and after changing the loop configuration. The information processing device 101 adjusts the loop configuration by dividing it into three loop configurations so that the load operation (PL) does not overtake the store operation (PS). Furthermore, in order to make the execution count the same before and after changing the loop configuration, the information processing device 101 sets the control variables (initial value, final value, increment value) of the three loops so that the number of unrolled loops is the same as before the change.

[0154] First, the initial loop will be described with reference to Fig. 17. Note that the number of revolutions before the loop configuration is changed (number of loop revolutions) may be expressed as "n". In the example of loop processing 1210, n is "1024" (see Fig. 12).

[0155] 17 is an explanatory diagram showing an example of an initial loop. In Fig. 17, an initial loop 1700 includes a store operation (PS). The information processing device 101 adjusts the initial loop 1700 so that the store operation (PS) is executed first until the access address difference between the store operation (PS) and the load operation (PL) for the array that is the target of SFI exceeds one cache line size (cachelinesize).

[0156] Specifically, for example, the information processing apparatus 101 calculates the number of array elements (D) in the store operation (PS) executed in advance in the initial loop 1700 using the following formula (1).

[0157] D = (cachelinsize - |ARRAY_TBL(i).1D index - ARRAY_TBL(i+1).1D index |*element size) / element size (1)

[0158] Here, "ARRAY_TBL(2).1st-dimension subscript = i+S" and "ARRAY_TBL(3).1st-dimension subscript = i" are used, and the access address difference between the preceding store operation (PS) and the subsequent load operation (PL) is 8 bytes. The cache line size is 256 bytes.

[0159] Therefore, the number of array elements (D) is "D = (256 - | (i + 1) - i | * 8) / 8 = 31". The access address of the preceding store operation (PS) is 8 bytes larger than the access address of the subsequent load operation (PL). In order to create a separate cache line, the information processing device 101 adjusts the execution of the store instruction for the remaining (256 - 8) / 8 = 31 elements (D) of the array elements in advance.

[0160] In this case, the number of revolutions of the initial loop 1700 (number of loop revolutions) is D. Then, the information processing device 101 calculates the control variables (initial value: is, final value: ie, increment value: id) of the initial loop 1700 as follows: where DO_TBL(l). initial value and DO_TBL(l). increment value are the initial value and increment value corresponding to the loop number: l in the DO loop management table 1300 corresponding to the array definition information that is the target of SFI.

[0161] is=DO_TBL(l).initial value ie=DO_TBL(l).initial value+D-1 id=DO_TBL(l).increment

[0162] Here, the loop number in the DO loop management table 1300 corresponding to the array definition information 2 that is the SFI target is "2." Therefore, the control variables (initial value: is, final value: ie, increment value: id) of the initial loop 1700 are calculated as follows:

[0163] is=DO_TBL(2).initial=1 ie = DO_TBL(2).initial value + D-1 = 1 + 31 - 1 = 31 id=DO_TBL(2).increment=1

[0164] Then, the information processing device 101 sets the calculated values ​​(is, ie, id) as control variables of the initial loop 1700 (see the right side of FIG. 17).

[0165] In the above example, a case where one cache line size (256 bytes) is freed up to avoid an SFI has been described, but this is not limiting. For example, depending on the processor, the access address difference that causes an SFI may be two or more cache line sizes, or may be a different management unit different from the cache line size. In such cases, the information processing device 101 may calculate the number of rotations D of the preceding store operation (PS) according to these sizes.

[0166] Next, the kernel loop will be described with reference to FIG.

[0167] 18 is an explanatory diagram showing an example of a kernel loop. In Fig. 18, a kernel loop 1800 includes a store operation (PS) and a load operation (PL). The preceding store operation (PS) has processed the number of array elements (D) from 1 in the initial loop 1700. Therefore, the store operation (PS) has (nD) elements remaining to be executed (n is the number of rotations before the loop configuration was changed).

[0168] Furthermore, in the kernel loop 1800, a load process (PL) is also executed within the same loop. For this reason, the information processing device 101 sets the number of rotations of the kernel loop 1800 to "nD". Note that when expanding an SIMD instruction, the number of rotations of the kernel loop 1800 may be set to a number of rotations divided into integer multiples of the SIMD width. However, this is not taken into consideration here, and for simplicity, it is set to "nD".

[0169] Furthermore, the information processing apparatus 101 calculates the control variables (initial value: ks, final value: ke, increment value: kd) of the kernel loop 1800 as follows.

[0170] ks=DO_TBL(l).initial value ke= DO_TBL(l).initial value+(nD)-1 kd=DO_TBL(l).increment

[0171] The initial value (ks) is the same as the initial value corresponding to the loop number: l in the DO management table 1300 corresponding to the array definition information that is the target of SFI. On the other hand, the end value (ke) is "DO_TBL(l).initial value + (nD) - 1" using the initial value of the loop number: l in the DO management table 1300, since the number of rotations is "nD". The increment value (kd) is the same as the increment value of the loop number: l in the DO management table 1300 that is the target of SFI.

[0172] Here, the loop number in the DO loop management table 1300 corresponding to the array definition information 2 that is the SFI target is "2." Also, the number of rotations D is "D=31." Therefore, the control variables (initial value: ks, final value: ke, increment value: kd) of the kernel loop 1800 are calculated as follows:

[0173] ks=DO_TBL(2).initial=1 ke=1+n-31-1=n-31 kd=DO_TBL(2).increment=1

[0174] Then, the information processing apparatus 101 sets the calculated values ​​(ks, ke, kd) as control variables of the kernel loop 1800 (see the right side of FIG. 18).

[0175] Here, the initial loop 1700 processes the preceding store operations (PS) from 1 to the number of array elements (D). The initial value of the control variable of the kernel loop 1800 uses the same value as the initial loop 1700. Therefore, the kernel loop 1800 changes the array subscript (i) and variable i in the store operation (PS) so that the store operation (PS) is not executed twice for the same array.

[0176] Figure 19 is an explanatory diagram showing an example of changing an array subscript. In Figure 19, <before change> indicates the store operation (PS) before changing the array subscript (i) and variable i. <after change> indicates the store operation (PS) after changing the array subscript (i) and variable i.

[0177] Here, the information processing device 101 changes the array subscript (i) and the variable i to a value obtained by adding D to the value of the array subscript (i) and the variable i in the store process (PS) to start the store process (PS) from the element next to element D. Specifically, the information processing device 101 changes the "i" in the array subscript (i) and the variable i to "i+D".

[0178] Next, the end loop will be described with reference to FIG.

[0179] Figure 20 is an explanatory diagram showing an example of an end loop. In Figure 20, an end loop 2000 includes a load operation (PL). Before and after the change in loop configuration, the store operation (PS) and the load operation (PL) have the same execution order and execution count. In the initial loop 1700, only the store operation (PS) is executed first, the number of times equal to the number of array elements (D).

[0180] The relationship in which the store operation (PS) accesses the load operation (PL) by the number of array elements (D) is maintained also in the kernel loop 1800. Therefore, in the end loop 2000, the information processing device 101 executes only the load operation (PL), thereby making the total number of executions of the store operation (PS) and the load operation (PL) the same as before the change in the loop configuration.

[0181] The number of times the load process (PL) is executed in the end loop 2000 is the same as the number of array elements (D) for which the store process (PS) has been executed in advance in the initial loop 1700. In addition, the end loop 2000 executes the load process (PL) from the element following the final element of the kernel loop 1800 to the end.

[0182] Specifically, for example, the information processing device 101 sets the number of revolutions of the end loop 2000 to "D", the same as that of the initial loop 1700. Then, the information processing device 101 calculates the control variables (initial value: es, final value: ee, increment value: ed) of the end loop 2000 as follows:

[0183] es= DO_TBL(l).Close-D+1 ee = DO_TBL(l).Close ed=DO_TBL(l).increment

[0184] In the end loop 2000, only the load process (PL) for the last remaining D elements is executed. Therefore, the initial value (es) of the control variable of the end loop 2000 is "DO_TBL(l).end value"-D+1" using the end value of loop number:l in the DO management table 1300 corresponding to the array definition information that is the target of SFI. The end value (ee) is the same as the end value of loop number:l in the DO management table 1300. The increment (ed) is the same as the increment value of loop number:l in the DO management table 1300.

[0185] Here, the loop number in the DO loop management table 1300 corresponding to the array definition information 2 that is the SFI target is "2." Also, the number of rotations D is "D=31." Therefore, the control variables (initial value: es, final value: ee, increment value: ed) of the end loop 2000 are calculated as follows:

[0186] es=DO_TBL(2).Close-D+1=n-31+1=n-30 ee=DO_TBL(2).ClosePrice=n ed=DO_TBL(2).increment=1

[0187] Then, the information processing apparatus 101 sets the calculated values ​​(es, ee, ed) as control variables of the end loop 2000 (see the right side of FIG. 20).

[0188] Here, the assembler expansion of the kernel loop 1800 after the loop configuration change will be described. Note that, as an example of the instruction set, the instruction set of the ARM processor will be described, but it is similar for other processors and is not limited to the ARM processor (ARM is a registered trademark).

[0189] 21 is an explanatory diagram showing the assembler expansion of the kernel loop after the loop configuration has been changed. The access address difference between the store instruction (st1d) and the load instruction (ld1d) in the kernel loop 1800 is 64*4=256 bytes (=1 cache line size). Therefore, in the kernel loop 1800, the access addresses of the store instruction and the load instruction are not the same cache line, and SFI can be avoided.

[0190] Specifically, in the kernel loop 1800, the access addresses of the preceding store process (PS) and the subsequent load process (PL) are separated so that they are in different cache lines. This makes it possible to execute the preceding store process (PS) and the subsequent load process (PL) without generating an SFI, thereby avoiding performance degradation due to an SFI.

[0191] From these factors, the information processing device 101 can change the high-cost loop in the target program 1200 into three logically equivalent loop configurations (initial loop, kernel loop, and end loop). For example, in the initial loop, the information processing device 101 shifts the processing timing of the preceding store instruction and the subsequent load instruction, which are SFI causes, so that the access addresses of the preceding store instruction and the subsequent load instruction do not become the same cache line. In this way, the information processing device 101 avoids consecutive area accesses in which the preceding store instruction and the subsequent load instruction access the same cache line.

[0192] Furthermore, in the kernel loop to be executed next, the information processing device 101 makes it possible to execute the preceding store and the subsequent load without causing an SFI in the same loop processing because the access addresses of the preceding store instruction and the subsequent load instruction are in different cache lines. This enables the information processing device 101 to avoid an interlock due to an SFI and improve the performance of the target program 1200.

[0193] While the above description focuses on a single loop and divides applicable arrays into separate loops, and then changes the loop configuration, the present invention is not limited to this. For example, the information processing device 101 may combine the divided loop with other loops by loop fusion, and then change the loop configuration. Furthermore, the information processing device 101 may apply this compilation method by combining other optimizations, such as loop division, loop fusion, and scheduling, across multiple loops, such as extracting target arrays from multiple loops and then allocating them to applicable arrays and loop configurations.

[0194] Example 2 Next, a second embodiment of the present compiling method will be described. In the second embodiment, a case will be described in which the user explicitly specifies loop locations and arrays that can be SFI targets in the source program (target program) using ocl statements or the like.

[0195] 22 is an explanatory diagram showing an example of a program including an ocl statement. In Fig. 22, a program 2200 includes a repetition (loop processing 2210) described by a do statement. In the program 2200, an ocl statement 2201 explicitly specifies a loop location including an array name (a) for which SFI should be avoided.

[0196] Here, an OCL statement is a compiler directive beginning with !ocl that can be arbitrarily specified by the user in the Fortran source code. In this case, the information processing device 101 avoids an interlock due to an SFI occurrence by changing the loop structure for array a in the specified loop processing 2210. The control directive name (avoidSFI) of the OCL statement can be arbitrarily set.

[0197] Even if the user does not explicitly specify it using an ocl statement or the like, the target loop processing (loop processing or array that is subject to SFI) can be automatically detected using a compiler translation option. However, there may be cases where the compiler cannot automatically detect it using an ocl statement, or where you want to specify only a specific loop location. In such cases, if the user explicitly specifies it using an ocl statement or the like, the information processing device 101 can change the loop structure for the specified loop location and avoid an interlock due to the occurrence of an SFI.

[0198] Example 3 Next, a third embodiment of the present compiling method will be described. In the third embodiment, a case will be described in which a target loop process (a loop process or array that is a target of SFI) is detected based on profile information and event information acquired during execution of the target program.

[0199] Fig. 23 is an explanatory diagram showing an example of operation using profile information, etc. In Fig. 23, a program 300 is an example of a target program. The information processing device 101 executes the program 300 in advance to acquire profile information 2310 and event information 2320.

[0200] Then, the information processing device 101 detects a target loop process from the program 300 based on the acquired profile information 2310 and event information 2320. Here, from the profile information 2310 and event information 2320, for example, a loop process 310 that is determined to be a high-cost loop and a location where SFI should be avoided is detected.

[0201] File output / input of profile information / event information can be specified, for example, using the following translation options:

[0202] Specifically, for example, the information processing device 101 can output profile information to a file (prof1) using "-KavoidSFI_prof.out=prof1". Also, the information processing device 101 can input profile information from a file (prof1) using "-KavoidSFI_prof.in=prof1". Also, the information processing device 101 can input event information from a file (event1) using "-KavoidSFI_event.in=event1".

[0203] Here, the procedure of the profile information acquisition process of the information processing device 101 will be described with reference to FIG.

[0204] Fig. 24 is a flowchart showing an example of a profile information acquisition processing procedure of the information processing device 101. In the flowchart of Fig. 24, first, the information processing device 101 specifies a translation option for profile information acquisition and translates the target program (step S2401).

[0205] Then, the information processing device 101 executes the translated target program to output the profile information (step S2402), and ends the series of processes according to this flowchart. This allows the information processing device 101 to obtain the profile information of the target program.

[0206] Fig. 25 is an explanatory diagram showing a specific example of profile information. In Fig. 25, profile information 2500 includes loop information 2501 and 2502. Each piece of loop information 2501 and 2502 has an array, a loop length, a loop count, an array X reference count, and an array X storage count. The array indicates a loop that includes the array. The loop length indicates the length of the loop. The loop count indicates the number of loop iterations.

[0207] The number of array X references indicates the number of times an array is referenced. The number of array X storages indicates the number of times an array is stored. The information processing device 101, for example, refers to the profile information 2500 to determine a location that is a high-cost loop and should be SFI-avoided. Specifically, for example, the information processing device 101 may determine that a loop with a relatively large number of loops is a location that should be SFI-avoided.

[0208] Next, the event information acquisition process performed by the information processing device 101 will be described with reference to FIG.

[0209] Fig. 26 is a flowchart showing an example of an event information acquisition processing procedure of the information processing device 101. In the flowchart of Fig. 26, first, the information processing device 101 executes a target program using a general-purpose tool (step S2601). The general-purpose tool is, for example, software (e.g., perf) for acquiring performance information.

[0210] Then, the information processing device 101 outputs the event information acquired by the general-purpose tool (step S2602), and ends the series of processes according to this flowchart. This allows the information processing device 101 to acquire the event information of the target program.

[0211] Example 4 Next, a fourth embodiment of the compiling method will be described. In the fourth embodiment, a case will be described in which the functional units of the information processing device 101 (for example, the detection unit 502, the configuration change unit 503, and the translation unit 504 shown in FIG. 5) are realized by a compiler.

[0212] 27 is an explanatory diagram showing an example of the configuration of a compiler. In FIG. 27, a compiler 2700 includes a parser unit 2701, an intermediate code conversion unit 2702, an analysis unit 2703, an optimization unit 2704, and a code generation unit 2705.

[0213] The parser unit 2701 extracts reserved words (keywords) and performs lexical analysis on the source program 2710 to be compiled. The intermediate code conversion unit 2702 converts each statement of the source program 2710 passed from the parser unit 2701 into intermediate code based on certain rules.

[0214] The analysis unit 2703 detects a target loop (a loop location and an array that can be an SFI target) from the source program 2710. Specifically, for example, the analysis unit 2703 detects the target loop by referring to the DO loop management table stored in the loop data storage unit 2706 and the array definition information stored in the array data storage unit 2707.

[0215] Furthermore, the analysis unit 2703 may detect, as the target loop, a location specified by an ocl statement or the like in the source program 2710. Furthermore, the analysis unit 2703 may detect the target loop by referring to profile information or event information of the source program 2710. The detection unit 502 shown in FIG. 5 is realized by, for example, the analysis unit 2703.

[0216] The optimization unit 2704 performs optimization processing on the source program 2710. Specifically, for example, the optimization unit 2704 changes the detected target loop processing into three logically equivalent loop configurations (initial loop, kernel loop, and end loop). The loop configuration change processing by the optimization unit 2704 may be performed based on, for example, the intermediate code output by the intermediate code conversion unit 2702. Furthermore, the processing by the parser unit 2701 and the intermediate code conversion unit 2702 may be performed on the source program 2710 on which the loop configuration change processing has been performed by the optimization unit 2704.

[0217] Furthermore, the optimization unit 2704 may improve the execution speed and reduce the code size by performing processes such as instruction combination, redundancy removal, and instruction rearrangement on the intermediate code output from the intermediate code conversion unit 2702. The configuration change unit 503 shown in FIG. 5 is realized by, for example, the optimization unit 2704.

[0218] The code generation unit 2705 generates a machine language program 2720 corresponding to the optimized source program 2710. Specifically, for example, the code generation unit 2705 refers to a conversion table (not shown) or the like for the intermediate code output from the optimization unit 2704 and replaces all codes with machine language instructions, thereby generating the machine language program 2720. The translation unit 504 shown in FIG. 5 is realized by, for example, the code generation unit 2705.

[0219] Example 5 Next, a specific procedure for the compilation process of the information processing device 101 will be described as a fifth embodiment.

[0220] Fig. 28 is a flowchart showing an example of a specific processing procedure of the compilation processing of the information processing device 101. In the flowchart of Fig. 28, first, the information processing device 101 executes a target loop detection process (step S2801). The target loop detection process is a process for detecting a target loop process from the target program.

[0221] The specific processing procedure of the target loop detection processing will be described later with reference to FIGS.

[0222] Next, the information processing device 101 executes a loop configuration change process for the detected target loop process (step S2802). The loop configuration change process is a process for changing the target loop process into three logically equivalent loop configurations (initial loop, kernel loop, and end loop).

[0223] The specific processing procedure for the loop configuration change processing will be described later with reference to FIG.

[0224] The information processing apparatus 101 then generates a machine language program corresponding to the target program after the loop structure change (step S2803), and ends the series of processes according to this flowchart. Note that in step S2802, if no change has been made to any of the loop structures in the target program, a machine language program corresponding to the target program is generated. Also, if another instruction is scheduled in step S2906 shown in FIG. 29, which will be described later, a machine language program corresponding to the target program in which the other instruction has been scheduled is generated.

[0225] This allows the information processing device 101 to improve the performance of the target program.

[0226] Next, a specific processing procedure of the target loop detection processing of step S2801 shown in Fig. 28 will be described using Fig. 29 and Fig. 30. Here, the target loop detection processing will be described by taking the first and second target loop detection processing as an example. Only one of the first and second target loop detection processing may be executed, or both may be executed.

[0227] First, a specific processing procedure of the first target loop detection processing will be described with reference to FIG.

[0228] 29 is a flowchart showing an example of a specific processing procedure of the first target loop detection processing. In the flowchart of FIG. 29, first, the information processing device 101 selects an unselected loop number from among the loop numbers in the DO loop management table of the target program (step S2901). The loop number to be selected may be, for example, the loop number of the innermost loop.

[0229] Next, the information processing device 101 identifies array definition information corresponding to the selected loop number (step S2902). Then, the information processing device 101 searches for arrays that satisfy all of the conditions (i) to (iv) for consecutive table numbers "i" and "i+1" of the identified array definition information (step S2903).

[0230] (i) ARRAY_TBL(i).array = ARRAY_TBL(i+1).array

[0231] (ii) |ARRAY_TBL(i).1D index - ARRAY_TBL(i+1).1D index |*element size < cachelinesize

[0232] (iii) ARRAY_TBL(i).definition = 1 (setting), and ARRAY_TBL(i+1).definition = 0 (reference)

[0233] (iv)ARRAY_TBL(i).Sentence identification number≦ARRAY_TBL(i+1).Sentence identification number

[0234] Next, the information processing device 101 determines whether a sequence satisfying all of the conditions (i) to (iv) has been found (step S2904). If no sequence has been found (step S2904: No), the information processing device 101 proceeds to step S2908.

[0235] On the other hand, if an array is found (step S2904: Yes), the information processing device 101 determines whether or not another instruction can be moved between the preceding store instruction and the subsequent load instruction that access the found array (step S2905). The other instruction is, for example, an instruction that has no dependency relationship with the preceding store instruction and the subsequent load instruction in the same basic block, and is an operation instruction, transfer instruction, or the like that requires more cycles than the number of cycles delayed by the SFI (or more than a predetermined number of cycles).

[0236] If the other instruction can be moved (step S2905: Yes), the information processing apparatus 101 schedules the other instruction between the preceding store instruction and the subsequent load instruction (step S2906), and proceeds to step S2908.

[0237] On the other hand, if other instructions cannot be moved (step S2905: No), the information processing device 101 detects the loop processing (loop processing of the selected loop number) that includes a preceding store instruction and a subsequent load instruction that access the searched array as the target loop processing (step S2907).

[0238] Then, the information processing device 101 determines whether there are any unselected loop numbers among the loop numbers in the DO loop management table (step S2908). If there are any unselected loop numbers (step S2908: Yes), the information processing device 101 returns to step S2901.

[0239] On the other hand, if there is no unselected loop number (step S2908: No), the information processing apparatus 101 returns to the step that called the target loop detection process (first target loop detection process).

[0240] This allows the information processing device 101 to automatically detect, as a target loop, a loop that includes a store instruction and a load instruction that cause an SFI.

[0241] Next, a specific processing procedure of the second target loop detection processing will be described with reference to FIG.

[0242] 30 is a flowchart showing an example of a specific processing procedure of the second target loop detection processing. In the flowchart of FIG. 30, first, the information processing device 101 identifies, from the target program, a loop processing specified by an ocl statement and including an array to be SFI-avoided (step S3001).

[0243] Then, the information processing apparatus 101 detects the identified loop processing as a target loop processing (step S3002), and returns to the step that called the target loop detection processing (second target loop detection processing).

[0244] This allows the information processing apparatus 101 to detect, as a target loop process, a loop process that is likely to become a high-cost loop designated by the user.

[0245] In step S3002, the information processing device 101 may, for example, refer to the DO loop management table and the array definition information to determine whether the identified loop includes an array that satisfies all of the above conditions (i) to (iv). If the identified loop includes an array that satisfies all of the above conditions (i) to (iv), the information processing device 101 may detect the identified loop as a target loop.

[0246] This allows the information processing apparatus 101 to detect, as a target loop, a loop that is specified by the user and for which performance improvement due to SFI suppression is expected.

[0247] In step S3002, the information processing apparatus 101 may, for example, refer to profile information or event information at the time of execution for the identified loop processing and, if it determines that the identified loop processing is a high-cost loop, detect the identified loop processing as a target loop processing. In step S3001, the information processing apparatus 101 may, for example, identify the loop processing determined to be a high-cost loop based on profile information or event information at the time of execution.

[0248] Although the target loop is specified by an ocl statement here, this is not limiting. For example, a loop to be excluded from the target loop may be specified by an ocl statement. In this case, the information processing device 101 may detect the target loop from the target program by excluding the loop specified by the ocl statement.

[0249] Next, a specific processing procedure of the loop configuration change processing in step S2802 shown in Fig. 28 will be described with reference to Fig. 31. Note that if a target loop processing is not detected in the target loop detection processing in step S2801 shown in Fig. 28, the information processing device 101 skips the loop configuration change processing in step S2802.

[0250] 31 is a flowchart showing an example of a specific processing procedure of a loop configuration change process. In the flowchart of FIG. 31, first, the information processing device 101 divides the detected target loop process into a loop process (LS) including a preceding store process (PS) and a loop process (LL) including a succeeding load process (PL) (step S3101).

[0251] The number of rotations of the two divided loop processes (LS, LL) is the same as before the division. Also, the execution order of the loop process (LS) and the loop process (LL) is "LS → LL".

[0252] Next, the information processing device 101 changes the divided loop process (LS) and loop process (LL) into an initial loop, a kernel loop, and an end loop (step S3102). Then, the information processing device 101 calculates the number of rotations D of the initial loop (loop rotation number) (step S3103). The number of rotations D is calculated using, for example, the above formula (1).

[0253] Next, the information processing device 101 sets control variables (initial value: is, final value: ie, increment value: id) of the initial loop based on the calculated number of rotations D (step S3104). Then, the information processing device 101 calculates the number of rotations (nD) of the kernel loop based on the calculated number of rotations D (step S3105).

[0254] Next, the information processing device 101 sets the control variables (initial value: ks, final value: ke, increment value: kd) of the kernel loop based on the calculated number of rotations (nD) (step S3106). At this time, the information processing device 101 changes the subscript (i) of the array and the variable i in the store process (PS) so that the store process (PS) is not executed twice for the same array in the kernel loop.

[0255] Then, the information processing device 101 sets the number of rotations of the end loop to the same number of rotations D as the initial loop, sets the control variables of the end loop (initial value: es, final value: ee, increment value: ed) (step S3107), and returns to the step that called the loop configuration change process.

[0256] As a result, the information processing apparatus 101 can change the target loop process into three logically equivalent loop configurations (initial loop, kernel loop, and end loop).

[0257] As described above, the information processing device 101 according to the embodiment can detect a target loop including a preceding store instruction and a subsequent load instruction from a target program, and change the detected target loop into an initial loop (first loop), a kernel loop (second loop), and an end loop (third loop). Here, the initial loop is a loop in which the preceding store instruction is executed in advance for a number of rotations D (first number) of the number of loop rotations n (number of iterations) of the target loop, so that the access address of the preceding store instruction and the access address of the subsequent load instruction do not become the same cache line. The kernel loop is a loop in which the preceding store instruction and the subsequent load instruction are executed (nD) times, which is the number of loop rotations n of the target loop minus the number of rotations D, after the initial loop. The end loop is a loop in which the subsequent load instruction is executed for a number of rotations D after the kernel loop. A cache line is an example of a unit of access from a processor (e.g., the CPU 401) to a memory (e.g., the memory 402).

[0258] As a result, the information processing device 101 can avoid performance degradation due to SFI occurring between the preceding store instruction and the subsequent load instruction in the target loop processing of the target program, thereby improving the performance of the target program.

[0259] Furthermore, the information processing device 101 can calculate the rotation count D based on the access address difference between the preceding store instruction and the subsequent load instruction, the element size, and the cache line size. Here, the element size is an example of the data size of the processing unit of the preceding store instruction and the subsequent load instruction. The cache line size is an example of the data size of the access unit from the processor to the memory.

[0260] As a result, the information processing device 101 can set an access address difference between the preceding store instruction and the subsequent load instruction so that they do not access the same address or nearby addresses in the same cache line. Specifically, for example, the information processing device 101 can calculate the rotation count D by dividing a value obtained by subtracting a size corresponding to the access address difference between the preceding store instruction and the subsequent load instruction from the cache line size by the element size. As a result, the information processing device 101 can adjust the rotation count D so that the preceding store instruction is executed one cache line size ahead in the initial loop. Furthermore, in the kernel loop, the information processing device 101 can avoid performance degradation without causing an SFI. Furthermore, by setting the preceding store instruction executed ahead in the initial loop to be one cache line size, the information processing device 101 can prevent a large discrepancy in processing amount between loops (e.g., the initial loop and the end loop).

[0261] In addition, according to the information processing device 101, a loop process that includes an earlier store instruction and a subsequent load instruction for the same array, and in which the value obtained by multiplying the access address difference between the earlier store instruction and the subsequent load instruction by the element size is less than the cache line size, can be detected as a target loop process.

[0262] This allows the information processing device 101 to automatically detect a loop location (high-cost loop) that includes a preceding store instruction and a subsequent load instruction for an array that is the target of SFI.

[0263] Furthermore, the information processing device 101 can detect a loop specified by a directive in a target program as a target loop. For example, in FORTRAN, the directive is an ocl statement. In C, the directive is a character string beginning with "#pragma."

[0264] This allows the information processing apparatus 101 to detect, as a target loop process, a loop location that is likely to become a high-cost loop designated in advance by the user.

[0265] Furthermore, according to the information processing device 101, it is possible to set the control variables of the initial loop (initial value: is, final value: ie, increment value: id), the control variables of the kernel loop (initial value: ks, final value: ke, increment value: kd), and the control variables of the end loop (initial value: es, final value: ee, increment value: ed) based on the rotation speed D.

[0266] As a result, the information processing device 101 can adjust the control variables of each loop so that the number of executions of the preceding store instruction and the subsequent load instruction are the same before and after changing the loop configuration.

[0267] Furthermore, the information processing device 101 can detect a target loop process from a target program based on execution information (for example, profile information, event information) obtained by executing the target program.

[0268] As a result, the information processing apparatus 101 can detect, as a target loop process, a loop portion that is determined to be a high-cost loop and that should be SFI-avoided, based on profile information, event information, and the like obtained during execution.

[0269] Furthermore, the information processing device 101 can generate a machine language program corresponding to the changed target program.

[0270] This allows the information processing device 101 to translate the optimized target program into a machine language program.

[0271] These findings demonstrate that the present compilation program and compilation method can avoid SFI-induced interlocks and significantly improve program performance. For example, applying the present compilation method to a program containing a high-cost loop has resulted in an 8- to 9-fold increase in processing speed. Furthermore, the present compilation program and compilation method eliminate delays caused by internal cycles, improving processor operating efficiency and reducing power consumption. For example, applying the present compilation method to environmental simulations and disaster simulations can be expected to significantly reduce power consumption.

[0272] The compiling method described in this embodiment can be realized by executing a prepared program on a computer such as a personal computer or a workstation. The compiling program is recorded on a computer-readable recording medium such as a hard disk, flexible disk, CD-ROM, DVD, or USB memory, and is executed by being read from the recording medium by the computer. The compiling program may also be distributed via a network such as the Internet.

[0273] The following additional notes are provided regarding the above-described embodiment.

[0274] (Note 1) A target loop process including a store instruction and a load instruction following the store instruction is detected from a program to be optimized, the detected target loop process is changed to a first loop process in which the store instruction is executed first for a first number of iterations of the target loop process, a second loop process in which the store instruction and the load instruction are executed a second number of iterations obtained by subtracting the first number from the number of iterations, after the first loop process, and a third loop process in which the load instruction is executed the first number of iterations, so that the access address of the store instruction and the access address of the load instruction do not become the same unit of access from the processor to the memory; A compiled program that causes a computer to execute a process.

[0275] (Supplementary Note 2) The first number of times is calculated based on an access address difference between the store instruction and the load instruction, a data size of a processing unit of the store instruction and the load instruction, and a data size of the access unit. 2. The compilation program according to claim 1, wherein the compilation program causes the computer to execute a process.

[0276] (Appendix 3) The detecting process is a loop process including a store instruction for the same variable and a load instruction following the store instruction, wherein a value obtained by multiplying an access address difference between the store instruction and the load instruction by a data size of a processing unit of the store instruction and the load instruction is less than the data size of the access unit is detected as the target loop process; 3. The compilation program according to claim 1 or 2.

[0277] (Appendix 4) The detecting process is 4. The compile program according to claim 1, wherein a loop specified by a directive in the program is detected as the target loop.

[0278] (Supplementary Note 5) The compiled program according to any one of Supplementary Notes 1 to 4, wherein the access unit is a cache line.

[0279] (Appendix 6) The calculation process is The compilation program according to claim 2, wherein the first number of times is calculated by dividing a value obtained by subtracting a size corresponding to the access address difference from the data size of the access unit by the data size of the processing unit.

[0280] (Appendix 7) The change process is setting a control variable for the first loop process, a control variable for the second loop process, and a control variable for the third loop process based on the first number of times; 3. The compilation program according to claim 2,

[0281] (Appendix 8) The detecting process is 8. The compilation program according to claim 1, further comprising: detecting the target loop process from the program based on execution information obtained by executing the program.

[0282] (Supplementary Note 9) A machine language program corresponding to the program after the target loop process is changed to the first loop process, the second loop process, and the third loop process is generated. 9. The compile program according to any one of claims 1 to 8, which causes the computer to execute a process.

[0283] (Appendix 10) A target loop process including a store instruction and a load instruction following the store instruction is detected from a program to be optimized; the detected target loop process is changed to a first loop process in which the store instruction is executed first for a first number of iterations of the target loop process, a second loop process in which the store instruction and the load instruction are executed a second number of iterations obtained by subtracting the first number from the number of iterations, after the first loop process, and a third loop process in which the load instruction is executed the first number of iterations, so that the access address of the store instruction and the access address of the load instruction do not become the same unit of access from the processor to the memory; A compilation method characterized in that the processing is executed by a computer. [Explanation of symbols]

[0284] 101 Information processing equipment 110,200,300,2200 programs 111a First loop processing 111b Second loop processing 111c Third loop processing 111 Target Loop Processing 210,310,1210,1610,1620,2210 Loop processing 401 CPU 402 memory 403 disk drive 404 Disk 405 Communication I / F 406 Portable Recording Media I / F 407 Portable Recording Media 410 Bus 411 Cache Memory 500 control section 501 Reception 502 detection unit 503 Configuration Change Section 504 Translation Department 710,1700 Initial Loop 720,1800 kernel loops 730,2000 End Loop 1200 Target Programs 1300 DO Loop Management Table 1500, 1510, 1520 loop 2201 ocl statement 2310,2500 Profile Information 2320 Event Information 2700 Compiler 2701 Parser 2702 Intermediate Code Conversion Unit 2703 Analysis Department 2704 Optimization Department 2705 ​​Code Generation Unit 2706 Loop data storage unit 2707 Sequence Data Storage Unit 2710 Source Program 2720 ​​Machine Language Program

Claims

1. Detecting a target loop process including a store instruction and a load instruction following the store instruction from a program to be optimized; the detected target loop process is changed to a first loop process in which the store instruction is executed first for a first number of iterations of the target loop process, a second loop process in which the store instruction and the load instruction are executed a second number of iterations obtained by subtracting the first number from the number of iterations of the target loop process, after the first loop process, and a third loop process in which the load instruction is executed the first number of iterations after the second loop process, so that the access address of the store instruction and the access address of the load instruction do not become the same unit of access from the processor to the memory; A compiled program that causes a computer to execute a process.

2. calculating the first number of times based on an access address difference between the store instruction and the load instruction, a data size of a processing unit of the store instruction and the load instruction, and a data size of the access unit; 2. The compilation program according to claim 1, wherein the compilation program causes the computer to execute a process.

3. The detecting process includes: a loop process including a store instruction for the same variable and a load instruction following the store instruction, wherein a value obtained by multiplying an access address difference between the store instruction and the load instruction by a data size of a processing unit of the store instruction and the load instruction is less than the data size of the access unit is detected as the target loop process; 2. The compilation program according to claim 1.

4. The detecting process includes:

2. The compilation program according to claim 1, wherein a loop specified by a directive in the program is detected as the target loop.

5. 5. The compiled program according to claim 1, wherein the access unit is a cache line.

6. Detecting a target loop process including a store instruction and a load instruction following the store instruction from a program to be optimized; the detected target loop process is changed to a first loop process in which the store instruction is executed first for a first number of iterations of the target loop process, a second loop process in which the store instruction and the load instruction are executed a second number of iterations obtained by subtracting the first number from the number of iterations of the target loop process, after the first loop process, and a third loop process in which the load instruction is executed the first number of iterations after the second loop process, so that the access address of the store instruction and the access address of the load instruction do not become the same unit of access from the processor to the memory; A compilation method characterized in that the processing is executed by a computer.

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