Imaging apparatus

Abstract

To provide an imaging apparatus connected to a neural network.SOLUTION: An imaging apparatus having neurons of a neural network has a plurality of first pixels, a first circuit, a second circuit, and a third circuit. Each of the first pixel has a photoelectric conversion element. The first pixels are electrically connected to the first circuit. The first circuit is electrically connected to the second circuit. The second circuit is electrically to the third circuit. Each of the first pixel generates an input signal for neurons in the neural network. The first, second, and third circuits have neuronal functions. The third circuit has an interface connected to the neural network.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device, an imaging module, an electronic device, and an imaging system. .

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. , machine, manufacture, or composition of matter In particular, one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a method for driving these devices or a method for manufacturing these devices.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. It refers to a semiconductor element, circuit, or device, etc. Examples include a transistor, a diode, and other semiconductor elements. In another example, a circuit having a semiconductor element is a semiconductor device. As another example, a device including a circuit having a semiconductor element is a semiconductor device. do. [Background technology]

[0004] Oxide semiconductors have been attracting attention as semiconductor materials that can be used in transistors. Transistors are made using zinc oxide or In-Ga-Zn oxide semiconductors as oxide semiconductors. Patent Document 1 discloses a technique for manufacturing the capacitor.

[0005] Furthermore, an imaging device including a transistor including an oxide semiconductor in part of a pixel circuit is This is disclosed in Patent Document 2.

[0006] Further, a transistor including silicon, a transistor including an oxide semiconductor, and a crystal Patent Document 3 discloses an imaging device having a structure in which photodiodes each having a conductive silicon layer are stacked. It is being done.

[0007] In addition, neural networks have the ability to learn, nonlinearity, and pattern matching. It has excellent performance and is used in many fields such as control, prediction, and diagnosis. Many neural network structures have been proposed, but most of them have not been put into practical use. Most of the neural networks are three-layered, with two layers (hidden layer and output layer) of neuron elements with sigmoid functions. The reason why this three-layer type is often used is that it can handle any function. This is because it has been proven that it is possible to model with reasonable accuracy.

[0008] In addition, an information system that extracts and judges an object from an image acquired using an imaging device is This is proposed in Patent Document 4. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-119711 [Patent Document 3] Japanese Patent Application Laid-Open No. 2013-243355 [Patent Document 4] Japanese Patent Application Publication No. 2014-032542 Summary of the Invention [Problem to be solved by the invention]

[0010] In semiconductor integrated circuits, while there is a trend toward higher density and higher capacity, there is also a demand for miniaturization. The transition from simple integration to three-dimensional integration is underway. Although it can be complicated, it allows for greater freedom in the materials and design rules of each layer, making it ideal for The challenge is to fabricate highly functional semiconductor integrated circuits, which are difficult to fabricate through multi-dimensional integration.

[0011] The pixel of the imaging device includes a photoelectric conversion element and a transistor. The transistor is required to have a high photosensitivity, and the transistor is required to have a low off-state current and low noise characteristics. The photoelectric conversion element and the transistor are integrated three-dimensionally, and The challenge is to create more sophisticated imaging devices by using suitable materials in the manufacturing process. is.

[0012] In addition, peripheral circuits such as driver circuits are formed in the same manufacturing process as the pixels, simplifying the connection process. It is preferable to make it

[0013] In addition, artificial intelligence (AI) will be used to identify and judge the information captured by the imaging device. Artificial intelligence is expected to use neural networks to mimic some of the characteristics of human brain function. This is an attempt to achieve this through networking, which requires a huge amount of calculations. The challenge is to efficiently operate neural networks by implementing hardware computations. be.

[0014] In one aspect of the present invention, a plurality of pieces of pixel information are compressed and converted into information having one feature. One of the objectives is to increase the speed of calculations in an imaging device. It is an object of the present invention to provide an imaging device that is dimensionally integrated. It is an object of the present invention to provide an imaging device capable of reducing degradation of converted signals. One of the objects is to provide a novel imaging device.

[0015] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc.

[0016] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least the above-listed and / or other objects. It solves one problem. [Means for solving the problem]

[0017] One aspect of the present invention is an imaging device having neurons of a neural network, A first pixel includes a plurality of first pixels, a first circuit, a second circuit, and a third circuit. has a photoelectric conversion element, the photoelectric conversion element is electrically connected to the first circuit, and the first circuit is electrically connected to a second circuit, the second circuit is electrically connected to a third circuit, and the The pixel of 1 generates the input signal for a neuron in the neural network, and The first circuit, the second circuit, and the third circuit have the function of a neuron, and the third circuit An imaging device having an interface for connection to a global network. be.

[0018] In each of the above configurations, the first pixel has a function of converting received light into an analog signal. The first circuit has a function of amplifying an analog signal, and the second circuit outputs the amplified analog signal. The third circuit has a function of adding analog signals, and the added analog signals are used to generate an activation function. The third circuit has a function of converting the signal into feature data by Preferably, the imaging device is characterized by having:

[0019] In each of the above configurations, the first circuit includes an amplifier circuit, a first memory circuit, and a first adder circuit. a second circuit including a second summing circuit, and a third circuit including a first arithmetic circuit and The first pixel has a function of converting light into a first signal and outputting the first signal. The amplifier circuit has a function of amplifying the first signal at the amplification factor stored in the first memory circuit. the first adder circuit has a function of adding an offset voltage to the amplified first signal; The first adder circuit outputs the result of adding the offset voltage as a second signal, which is an analog signal. the second adder circuit has a function of adding a plurality of second signals; The second adder circuit adds the second signals together to produce a third signal, which is an analog signal. The first arithmetic circuit has a function of determining the third signal and binarizing it. The first arithmetic circuit supplies the binarized signal as feature data to the second memory circuit. The second memory circuit has a function of outputting the feature data to the neural network. Preferably, the imaging device is characterized by the above.

[0020] In each of the above configurations, the first pixel converts the received light into an analog signal and outputs the analog signal as a fourth signal. The first circuit has a function of converting an analog signal into a digital signal. The first circuit classifies the magnitude of the digital signal by a bit shift operation. and a second circuit for generating a fifth signal having a characteristic of The third circuit extracts and aggregates the aggregated results, and the third circuit extracts and aggregates the aggregated results using an activation function. The third circuit has a function of converting the characteristic data into the characteristic data. The featured imaging device is preferred.

[0021] In each of the above configurations, the first circuit includes a first input selection circuit and an analog-to-digital conversion circuit. a first decision circuit and a first memory circuit, and the second circuit has a second input selection a circuit and a feature extraction circuit, and a third circuit includes a second decision circuit and a second memory circuit. and the first input selection circuit has a function of selecting one of the plurality of fourth signals. , the analog-to-digital conversion circuit converts the selected fourth signal from an analog signal to a digital signal. The first decision circuit has a function of converting the digital signal into a selected bit shift amount. The first decision circuit has a function of amplifying the signal by a power of 2, and the first decision circuit determines the magnitude of the amplified signal. , the first decision circuit has a function of determining the result of the decision based on the bit shift amount, and outputs the result of the decision as a fifth signal. The second input selection circuit has a function of providing the first memory circuit with a The fifth signal held in the circuit is sequentially selected and output to the feature extraction circuit. The circuit has a function of counting a fifth signal having a characteristic, and the second decision circuit counts the fifth signal having a characteristic. The second decision circuit compares the result of the comparison with a given condition, and determines the result as feature data. The second memory circuit has a function of storing the feature data in a neural network. Preferably, the imaging device is characterized in that it outputs to a network.

[0022] In each of the above configurations, in an imaging device having neurons of a neural network, The imaging device further includes a signal line and a second analog-to-digital conversion circuit. has a function of converting received light into the analog signal, and the first pixel has a function of converting the signal line into the analog signal. the analog signal is provided to the second analog-to-digital conversion circuit via An imaging device in which

[0023] In each of the above configurations, the third circuit has a selection circuit and selects the feature data in a selected length. and outputting the resulting image to a neural network. stomach.

[0024] In each of the above structures, the pixel of the imaging device has a first transistor, The image pickup device preferably has a metal oxide in the semiconductor layer.

[0025] In each of the above structures, the first transistor included in the first pixel has a metal oxide layer in a semiconductor layer. and a second transistor included in another circuit has polycrystalline silicon in its semiconductor layer. An imaging device characterized by the above is preferred.

[0026] In each of the above structures, the first transistor having a metal oxide in the semiconductor layer is An imaging device characterized by having a port is preferred.

[0027] In each of the above structures, each of the first transistors has an area overlapping with the photoelectric conversion element. Preferably, the imaging device is characterized by having: [Effects of the Invention]

[0028] In one aspect of the present invention, a plurality of pieces of pixel information are compressed and converted into information having one feature. Alternatively, it is possible to provide a method for increasing the speed of calculations in an imaging device. Alternatively, it is possible to provide an imaging device that is three-dimensionally integrated. It is possible to provide an imaging device that can reduce the deterioration of the converted signal. We can provide facilities, etc.

[0029] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention has at least the above-listed effects and / or other effects. Therefore, one aspect of the present invention is to provide the above-mentioned series of In some cases, it may not have the effect described. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 2 is a block diagram illustrating an image sensor. [Figure 2] FIG. 2 is a block diagram illustrating an image sensor. [Figure 3] FIG. 2 is a circuit diagram illustrating an image sensor. [Figure 4] 1A is a timing chart illustrating the operation of an image sensor, and FIG. 1B is a timing chart illustrating the operation of a pixel. [Figure 5] FIG. 2 is a block diagram illustrating an image sensor. [Figure 6] FIG. 2 is a block diagram illustrating an image sensor. [Figure 7] FIG. 2 is a circuit diagram illustrating an image sensor. [Figure 8] 1A is a timing chart illustrating the operation of an image sensor, and FIG. 1B is a timing chart illustrating the operation of a pixel. [Figure 9] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 10] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 11] FIG. 3 is a cross-sectional view illustrating a connection configuration of photoelectric conversion elements. [Figure 12] FIG. 3 is a cross-sectional view illustrating a connection configuration of photoelectric conversion elements. [Figure 13] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 14] FIG. 3 is a cross-sectional view illustrating a connection configuration of photoelectric conversion elements. [Figure 15] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 16] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 17] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 18] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 19] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 20] 2A and 2B are block diagrams of an analog-to-digital conversion circuit and diagrams showing a connection between an imaging element and the analog-to-digital conversion circuit. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 22] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 23] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 24] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 25] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 26]1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 27] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 28] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 29] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Figure 30] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Figure 31] 1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the present invention in various ways without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details of the present invention. The present invention should not be construed as being limited to the description of the following embodiments.

[0032] Also, in the drawings, the size, thickness of layers, or areas are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0033] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the number of components. It should be noted that this is added to avoid confusion and is not intended to limit the number.

[0034] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The terms are not limited to those given above and can be rephrased appropriately depending on the situation.

[0035] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain A transistor is placed between the drain electrode and the source terminal. A current flows between the source and the drain through the channel forming region. In this specification and the like, the channel formation region is a region through which a current can flow. This refers to the region where the current mainly flows.

[0036] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0037] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0038] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0039] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to

[0040] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also known as a cut-off state). Unless otherwise specified, for an n-channel transistor, the voltage V between the gate and source When gs is lower than the threshold voltage Vth, the gate and This refers to the state in which the voltage Vgs between the n-channel and n-channel transistors is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage between the gate and source, Vgs, that is, the threshold voltage, Vt It may refer to the drain current when it is lower than h.

[0041] The off-state current of a transistor may depend on Vgs. The off-state current of the transistor is I or less when the Vgs value is I or less. The off-state current of a transistor is the off-state current at a given Vgs. state, an off state at Vgs within a given range, or a sufficiently reduced off current is obtained. It may refer to the off-state current at Vgs.

[0042] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The on-current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -1 3 A, and the drain current at Vgs = -0.5 V is 1 × 10 -19 A and Vg The drain current at s = -0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: , or 1×10 in the range of Vgs from −0.5V to −0.8V -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 It may be said that it is below A. The drain current of the transistor is 1×10 -22 Because there exists a Vgs below A , the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0043] In this specification and the like, the off-state current of a transistor having a channel width W is calculated based on the It is sometimes expressed as the current value that flows per watt. In the latter case, the unit of the off-state current is current / length. It may be expressed in units with an element (e.g., A / μm).

[0044] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the values ​​are measured at off-state current at room temperature, 60℃, 85℃, 95℃, or 125℃. Or, the reliability of the semiconductor device including the transistor may be insured. or the temperature at which a semiconductor device including the transistor is used (for example, The term "off-state current" may refer to the off-state current at any temperature between 5°C and 35°C. The off-state current of the transistor is I or less when the transistor is operated at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of a semiconductor device including a transistor is guaranteed, or The temperature at which the included semiconductor device, etc. is used (for example, any one of 5°C to 35°C) , there exists a value of Vgs at which the off-state current of the transistor is I or less. There is.

[0045] The off-state current of a transistor can depend on the voltage Vds between the drain and source In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or It may also represent the off-state current at 20 V. Vds that guarantees the reliability of devices, etc., or in semiconductor devices, etc. that include the transistor The off-state current of a transistor is sometimes expressed as the off-state current at the Vds used in the I or less means that Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, V, 3V, 3.3V, 10V, 12V, 16V, 20V, and the semiconductor Vds that guarantees the reliability of semiconductor devices, or semiconductor devices that include the transistor Vds used in, Vgs value at which the transistor off-current is I or less It may refer to the existence of

[0046] In the above description of the off-state current, the drain may be read as the source. Current may also refer to the current through the source when the transistor is in the off state.

[0047] In this specification and the like, the term "leak current" may be used to mean the same thing as "off-state current." In this specification, the off-state current is, for example, the current when a transistor is in an off state. , may refer to the current flowing between the source and drain.

[0048] Voltage refers to the potential difference between two points, and potential refers to the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) of a unit charge in a particle. However, in general, the potential difference between the potential at a certain point and a reference potential (for example, ground potential) This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, the term "potential" may be read as "voltage." , voltage may be read as potential.

[0049] (Embodiment 1) In this embodiment, an imaging device having an interface for connecting to a neural network is used. The device will be described with reference to FIGS.

[0050] One aspect of the present invention is an imaging device in which decision circuits for determining signals output from pixels are distributed within an imaging element. The imaging device is constructed and operated in accordance with the present invention.

[0051] FIG. 1 is a block diagram showing an example of the configuration of an image pickup device 100. The image pickup device 100 includes an image pickup element 10, an analog-to-digital conversion circuit (hereinafter referred to as an analog-to-digital conversion circuit 26), a decoder The control circuit 29 includes a circuit 27, a selector circuit 28, and a control unit 29.

[0052] The image sensor 10 includes a plurality of determination circuits 20a, a plurality of scanning lines G1, a plurality of scanning lines G2, It has a plurality of signal lines OUT and a plurality of signal lines OUT1.

[0053] The decision circuit 20a includes a plurality of pixels 20, a feature extraction circuit 30, and a decision output circuit 31. The pixel 20 has a light receiving circuit 21 including a photoelectric conversion element PD (FIG. 3(A)). reference).

[0054] The image sensor 10 has pixels 20 arranged in m rows and n columns. As an example, let us consider a part of pixel 20 Pix(i,j) to Pix(i+ 3, j+3) (i is a natural number between 1 and m, j is a natural number between 1 and n, m is a natural number between 2 and n, and k is a natural number between 1 and n. natural numbers below)

[0055] The decision circuit 20a includes four pixels 20, a feature extraction circuit 30, and a decision output circuit 31. The decision output circuit 31 includes an arithmetic circuit 31a and a memory circuit 31b (see FIG. 3(B)). It has the following characteristics:

[0056] Each pixel 20 is electrically connected to a feature extraction circuit 30. The line 30 is electrically connected to a decision output circuit 31 .

[0057] However, the number of pixels 20 included in the determination circuit 20a is appropriately selected depending on the area to be determined. In addition, the light receiving circuit 21 may be connected to a plurality of amplifier circuits 22. (See Figure 2(B)).

[0058] Pix(i,j) and Pix(i,j+1) are electrically connected to the signal line OUT1(i). Pix(i+1,j) and Pix(i+1,j+1) are connected to the signal line OUT1(i+ 1). Pix(i,j) and Pix(i+1,j) are the driving It is electrically connected to the scanning line G1(j), and Pix(i,j+1), Pix(i+1,j The scanning line G1(j+1) is electrically connected to the scanning line G1(j+1). It is electrically connected to the signal line OUT(i).

[0059] The pixel 20 and the decision circuit 20a can be configured with unipolar transistors, and the number of processes can be increased. The pixel 20 and the decision circuit 20a can be formed in parallel without any need for a separate process.

[0060] The photoelectric conversion element PD of the pixel 20 converts the received light into a current, which is then converted into a voltage. Furthermore, the pixel 20 amplifies the voltage of the analog signal and outputs the output signal b. It is possible.

[0061] The plurality of output signals b are calculated by the feature extraction circuit 30. The calculation function may be addition or subtraction. In this embodiment, the feature extraction circuit 30 is described as an adder circuit. The feature extraction circuit 30 can output the output signal c as an analog signal.

[0062] The decision output circuit 31 decides the output signal c given to the input terminal by the calculation circuit 31a, and The binarized signal is stored in the memory circuit 31b as a digital signal. (See FIG. 3(B)).

[0063] The memory circuit 31b outputs an output signal d. The output signal d is transmitted via a signal line OUT as follows: The selector circuit 28 (see FIG. 1) selects the signal from the decision circuit 20a. The measurement results can be rearranged to the required data length and transferred to the control unit 29. The data length depends on the signal communication method, whether it is parallel communication or serial communication such as I2C. Alternatively, you can select a communication method such as differential transmission such as MIPI.

[0064] The pixel 20 also outputs the output signal a to the analog-to-digital converter 2 via the signal line OUT1. 6 (see FIG. 2(A)). The analog-to-digital conversion circuit 26 outputs the output signal The signal a can be converted into a digital signal and output to the control unit 29. The method of transmission from 26 to the control unit 29 can be selected as the most suitable method.

[0065] The control unit 29 has two input interfaces. One is composed of a digital interface and supports parallel or serial input. The data length of the input data is fixed. The output signal a is an analog-digital The signal is sent to the digital interface of the control unit 29 via the conversion circuit 26 .

[0066] The other input interface corresponds to the input of the neural network. Since neural networks receive input data directly, the length of the input data is It is preferable to be able to switch to a data length that is easy for the neural network to handle. The data length of the signal d can be switched by the selector circuit 28. The output signal d is The data is processed to an appropriate data length and is given to the neural network interface of the control unit 29. can be obtained.

[0067] Furthermore, the imaging device 100 can freely select the type of photoelectric conversion element. For example, an oxide semiconductor is formed on a single crystal silicon substrate on which a photodiode is formed. The pixel 20 and the decision circuit 20a can be formed by the transistors having the above structure.

[0068] The transistor having the above oxide semiconductor in a semiconductor layer has a small off-state current and is suitable for the pixel 20 and The floating node, latch, and memory for holding the data of the decision circuit 20a are simply Therefore, the transistor can be configured in various ways depending on the desired function. The semiconductor layer of the GaN layer can be selected.

[0069] The imaging device can be constructed using only unipolar transistors, but the area becomes large. For this reason, a transistor having an oxide semiconductor in a semiconductor layer is used in a pixel or a memory circuit. It is preferable to select the amplifier circuit, the decision circuit 20a, the analog-to-digital conversion circuit, 26 and the decoder circuit 27, circuits that require current supply capacity are made of single crystal silicon. A transistor having a semiconductor layer made of single crystal silicon can be selected. A transistor having an oxide semiconductor as a semiconductor layer is stacked on the transistor having an oxide semiconductor as a semiconductor layer. An example of the oxide semiconductor will be described in detail in Embodiment 6.

[0070] FIG. 2A is a block diagram showing the details of the decision circuit 20a. The decision circuit 20a has four The pixel 20 includes a light receiving circuit 21, an amplifier circuit 22, and a memory cell. The amplifier circuit 22 includes an amplifier circuit 22a, a memory circuit 22b, and It has an adder circuit 22c.

[0071] The input terminal of the amplifier circuit 22a is connected to the output terminal of the light receiving circuit 21 and the output terminal of the memory circuit 22b. The output terminal of the amplifier circuit 22a is electrically connected to the adder circuit 22c. The light receiving circuit 21 is electrically connected to the memory circuit 23 via the amplifier circuit 22a. The memory circuit 23 is electrically connected to the signal line OUT1.

[0072] The light receiving circuit 21 converts the generated current into a voltage and receives the The optical circuit 21 outputs the voltage as the output signal a. The memory circuit 22b can set the amplification factor of the amplifier circuit 22a. The adder circuit 22c can add an offset voltage B to the output signal a1 of the amplifier circuit 22a. The adder circuit 22c outputs the output signal b to the output terminal, and the output signal b is input to the input terminal of the feature extraction circuit 30. However, the output signal a1 is sent to the feature extraction circuit 30 without passing through the addition circuit 22c. may be given to.

[0073] The block diagram in Figure 2(A) shows the functions of a neuron in a neural network. Neurons have synapses and activation functions. The synapse circuit multiplies a plurality of input signals by weighting coefficients, and outputs each of the multiplied input signals. In other words, a neuron can perform a multiply-and-sum operation on multiple input signals. The activation function circuit has the function of calculating the sum of products. It has a judgment function to extract features from

[0074] Figure 2(B) shows the block diagram of Figure 2(A) as a neuron schematic diagram. Synapse Circuit 3 0N includes a pixel 20 and a feature extraction circuit 30. The activation function circuit 31N is , and a decision output circuit 31.

[0075] FIG. 2B shows an example in which four light receiving circuits 21 are connected to a feature extraction circuit 30. However, the number of connected light receiving circuits 21 is not limited. Let us explain the circuit 21 as PD(i), PD(i+1), PD(i+2), and PD(i+3). i and j are natural numbers greater than or equal to 1.

[0076] The amplifier circuit 22 can multiply the output signal a by a weighting factor A. The weighting factor A is The weighting coefficient A can be replaced with the amplification factor. Therefore, the feature extraction circuit 30 multiplies the output signal a by a weighting coefficient A and then A corrected output signal b is given, such as set B.

[0077] The feature extraction circuit 30 can add up multiple output signals b. The output signal c of the circuit 30 can be expressed by the following equation: The weighting coefficient A of the amplifier circuit 22 is The same weighting coefficient may be set, or different weighting coefficients may be set.

[0078] Under the above conditions, the sum of the outputs of the feature extraction circuit 30 is expressed by the following equation 1.

[0079] c(j)=Σ(PD(i)·A(i)+B) (Equation 1)

[0080] The output signal c1(j) outputted by the calculation circuit 31a of the activation function circuit 31N is It is expressed by the following equation 2.

[0081] c1(j)=f(c(j)) (Equation 2)

[0082] The output function f(c(j)) of the activation function circuit 31N means a sigmoid function. The decision output circuit 31 of the activation function circuit 31N receives a threshold potential from the outside as a decision condition. The threshold voltage may be given as a condition or may be given as a fixed threshold voltage. The decision output circuit 31 generates a condition called firing in the neural network. A digitized digital signal can be output.

[0083] 3A to 3C show examples of the circuit of FIG. 2A. FIG. 3A shows the pixel 20. 3B shows an example of the determination circuit 20a, and FIG. 3C shows an example of the amplifier circuit 22. 1 shows an example of the circuit of the adder circuit 22c.

[0084] 3A, the pixel 20 will be described in detail. The pixel 20 includes a light receiving circuit 21 and an amplifier circuit The amplifier circuit 22 includes an amplifier circuit 22a and a memory circuit 22b. The light receiving circuit 21 includes a photoelectric conversion element PD, capacitance elements C1 and C2, and a transistor 4. One of the electrodes of the photoelectric conversion element PD is electrically connected to the terminal VPD (71). The other electrode of the photoelectric conversion element PD is connected to the source or drain of the transistor 41. One of the gates is electrically connected to one of the source and drain of the transistor 42. The other of the source or drain of the transistor 41 is electrically connected to one of the electrodes of the capacitance element C1. The gate of the transistor 41 is electrically connected to the terminal Tx(61). The other of the source or drain of the transistor 42 is connected to one of the source or drain of the transistor 43. The gate of the transistor 42 is electrically connected to the terminal VRS (72). The gate of the transistor 43 is electrically connected to the terminal RS (62), and the source of the transistor 43 is The other drain is electrically connected to one electrode of the capacitance element C2. The wiring may be connected in other ways. For other connection methods, see the wiring diagrams shown in Figures 18 and 19. FIG. 19B shows an example of a connection in which the transistor 43 is not provided. There are.

[0085] The capacitance element C1 holds the potential generated by the photoelectric conversion element PD as an output signal a. The capacitance element C2 is a reference voltage for comparing the magnitude of the output signal a. The transistors 41 to 43 are used to hold and reset signals. The timing for this can be controlled.

[0086] The amplifier circuit 22a can be a Gilbert cell circuit. Transistor 44a, transistor 45a, transistor 44b, transistor 45b, A transistor 46, a transistor 47, a transistor 48, a resistor element Ra, and a resistor element R One of the electrodes of the resistor element Ra is connected to one of the electrodes of the resistor element Rb and to the terminal VP The other electrode of the resistor element Ra is electrically connected to the source of the transistor 44a. The source or drain of the transistor 45b is electrically connected to the source or drain of the transistor 45c. The other of the source and drain of the transistor 44a is connected to the 5a and one of the source or drain of the transistor 46. The other of the source and drain of the transistor 45a is electrically connected to the resistor Rb. The other electrode is electrically connected to one of the source and drain of the transistor 44b. The other of the source and drain of the transistor 44b is connected to the source of the transistor 45b. The other of the drains is electrically connected to the source or drain of the transistor 47. The other of the source and drain of the transistor 46 is connected to the source of the transistor 47. The other of the source and drain of the transistor 48 is electrically connected to the other of the source and drain of the transistor 48. The gate of transistor 47 is electrically connected to terminal VCS, and the gate of transistor 4 The gate of transistor 8 is electrically connected to terminal Vbias1, and the source or drain of transistor 48 is The other drain of the transistor 44a is electrically connected to the terminal VSS (79). The gate of the transistor 44b is electrically connected to one of the electrodes of the capacitance element C1. The gate of the transistor 45a is connected to the gate of the transistor 45b and the gate of the capacitance element C2. One of the electrodes is electrically connected to the other.

[0087] The transistor 44a and the transistor 45a form a differential amplifier circuit. The same applies to the transistor 44b and the transistor 45b. is compared with the reference potential of the capacitance element C2 and amplified.

[0088] The memory circuit 22b includes a transistor 49 and a capacitance element C3. One of the source and drain of the transistor 49 is electrically connected to the terminal Wd1 (75). The other of the source and drain of the transistor 49 is connected to one of the electrodes of the capacitor C3. The gate of the transistor 49 is electrically connected to the terminal W1 ( 74) and is electrically connected.

[0089] The memory circuit 22b amplifies the signal from the signal line Wd1 through the transistor 49 to the capacitance element C3. The amplification factor is calculated externally and is provided to the memory circuit 22b. The amplifier circuit 22 amplifies the analog signal, which allows the circuit scale to be reduced. Furthermore, it has the ability to follow the output signal a and smooth out noise. Although not shown in FIG. 3, in order to provide an amplification factor to the capacitance element C3, a column driver, row A separate driver may be provided, or the decoder circuit 27 in FIG.

[0090] The memory circuit 22b can control the amplification factor of the amplifier circuit 22a. This corresponds to the weighting coefficient A in the NAPSC circuit. When the amplification coefficient A is set, the output signal a1 is uniformly amplified, improving the light receiving accuracy at low gradations. When a different weighting factor A is set, the output signal a1 is This emphasizes a pattern according to the pattern, making it easier to extract a specific pattern.

[0091] The transistor 48 controls the total current flowing through the amplifier circuit 22a. If you do not want to operate the image sensor 10, or if you want to disable it intentionally, The gate of the transistor 48 is controlled by the amplifier circuit 2. This allows the operation of transistor 2 to be stopped, thereby reducing power consumption. The off-state current can be reduced by using an oxide semiconductor for the semiconductor layer of a transistor. Therefore, the transistor 48 reduces the standby current when the amplifier circuit 22 is in the off state. This can be done.

[0092] The memory circuit 23 can store the output signal a2 of the amplifier circuit 22a. The output signal a2 held on the line 23 is converted into a signal line G1 by a scanning signal applied to the scanning line G1. OUT1 to the analog-to-digital conversion circuit 26. By applying w, the capacitance element C1 can hold the output signal a. The memory circuit 23 may not be included in the configuration 20 .

[0093] 3B shows an example of the circuit of the decision circuit 20a. However, the addition circuit 22c is an amplifier. The circuit 22 is included in the adder circuit 22. FIG. 3(C) shows an example of the adder circuit 22c configured with passive elements. The adder circuit 22c has a plurality of resistors.

[0094] The addition parameter can be given as a voltage from terminal Vbias2. The data may be uniformly provided to all pixels of the image sensor 10, or may be provided by adding a memory circuit. The summing parameter is the output of the amplifier circuit 22. Since the force can be corrected, it can be used as an offset adjustment function. The circuit 22c may be a circuit having a function of adding a signal, and may be a circuit having the configuration shown in FIG. Not limited to.

[0095] Next, the feature extraction circuit 30 and the decision output circuit 31 included in the decision circuit 20a will be explained. The feature extraction circuit 30 is an example in which an operational amplifier is used in the adder circuit. 30 includes an operational amplifier 30a and resistor elements R1, R2, R3, R4, Rc, and Rf. do.

[0096] One terminal of each of the resistor elements R1, R2, R3, and R4 is electrically connected to the amplifier circuit 22. The other terminals of the resistor elements R1, R2, R3, and R4 are connected to the negative input of the operational amplifier 30a. One terminal of the resistor element Rf is electrically connected to the output terminal of the operational amplifier 30a. The input terminal and the other terminal of the resistor element Rf are electrically connected to the output terminal. The resistance value of the element can be selected to be appropriately large as required.

[0097] The negative input terminal of the operational amplifier 30a is the reference point where a virtual short is established. Therefore, the resistor element Rf can perform current-voltage conversion. The result of adding the signal b is output as a voltage value to the output terminal of the operational amplifier 30a. An output terminal of the circuit 30 is supplied with an output signal c which is an analog signal.

[0098] Next, the decision output circuit 31 will be described. The decision output circuit 31 comprises an arithmetic circuit 31a and The arithmetic circuit 31a has a memory circuit 31b. The arithmetic circuit 31a stores the voltage of the determination condition. The device may have a memory for performing the above steps.

[0099] The input terminal of the arithmetic circuit 31a is electrically connected to the output terminal of the operational amplifier 30a. The output terminal of the arithmetic circuit 31a is connected to the input terminal of the memory circuit 31b. When the circuit 31a has a memory circuit, a column driver for writing the voltage of the determination condition Alternatively, the decoder circuit 27 in FIG. stomach.

[0100] The calculation circuit 31a uses the output function f to determine the output signal c of the feature extraction circuit 30. When processing with software, it is possible to use a sigmoid function, etc. However, when processing by hardware, the same function can be achieved by using the arithmetic circuit 31a. It can be prepared.

[0101] The arithmetic circuit 31a is supplied with a voltage representing a determination condition from a signal line Wd2. The output signal c of the feature extraction circuit 30 is compared with the voltage of the judgment condition, and the output signal c is If the voltage of signal c is high, the calculation circuit 31a outputs a high signal. If the voltage of output signal c is smaller than the The force signal a is processed by the neuron and converted into a binary digital signal by the output function f. can be converted to

[0102] The binarized signal is stored in the memory circuit 31b and can be read out as needed. To read out the signal, a scanning signal is applied to the scanning line G2, and a signal is output via the signal line OUT. and output to the selector circuit 28. To read data from the memory circuit 31b, Alternatively, a line driver and a row driver may be provided separately. Good too.

[0103] FIG. 4A shows a timing chart of the imaging device 100 of FIG. A scanning signal is applied to the scanning line G1(j) from the encoder circuit 27 and is stored in the memory circuit 23. The data is transferred to the analog-to-digital conversion circuit 26. A scanning signal is applied to the scanning line G2(k) from the data buffer circuit 27 and is stored in the memory circuit 31b. The data stored in the memory circuit 23 and the memory circuit 31b are transferred to the selector circuit 28. Therefore, the memory circuit 31b can switch between acquiring and transferring data. The signal controlling the transfer gate may be a decoder. A scanning signal provided by the circuit can be used.

[0104] FIG. 4B shows a timing chart of the light receiving circuit 21 included in the pixel 20 of FIG. The operation of the optical circuit 21 is controlled by the scanning line G1(j). The applied scanning signal is also applied to the terminal RS (62). The period corresponds to T11 to T13 in FIG. 4(B).

[0105] During the period from T11 to T12, the holding potential of the capacitance element C2 is applied to the terminal VRS (72). During the period from T11 to T12, the terminal Tx(61) is refreshed with the voltage When the transistor 41 is in the OFF state, the transistor 41 remains in the OFF state. The period of time required for data to be saved in the memory circuit 23 and the memory circuit 31b is The memory circuit 23 and the memory circuit 31b are configured with transfer gates. Therefore, the period from T11 to T12 can be shortened by using a transistor with high mobility. The transistor 41 is a CAC-OS transistor described in the sixth embodiment. It is preferable to use a resistor.

[0106] During the period from T12 to T13, the terminal Tx(61) becomes High, and the transistor 41 Therefore, the holding potential of the capacitance element C1 is applied to the terminal VRS (72). It is refreshed with a given voltage.

[0107] At the timing of T13, the scanning signal applied to the scanning line G1(j) becomes Low. Furthermore, the terminal RS(62) becomes low. Therefore, the transistors 42 and 43 are OFF. The photoelectric conversion element PD The data acquisition period begins when the scanning line G1(j) is selected in the next frame. However, the decoder circuit of the imaging device 100 has a configuration in which multiple The data acquisition period may be divided into regions and processed in parallel. When this happens, it can be done in less than one frame.

[0108] The image sensor 10 includes a decision circuit 20a, which allows the image sensor 10 to realize the functions executed by the neurons in the brain. Analog calculations can be performed using analog data in the same way as analog data processing. The imaging element 10 minimizes the frequency of converting analog data into digital data. It is possible to perform calculation processing while

[0109] Neural networks require a huge amount of calculations and hierarchical processing. By using this embodiment, the neural network is Therefore, the decision circuit 20a can perform the process corresponding to the input layer. The circuit 20a receives light from the pixel 20 and performs analog arithmetic processing to obtain a signal. Therefore, two types of output results of the signal of the received light data can be obtained. This reduces the amount of software-based calculation processing, and reduces the power consumption associated with calculations. Furthermore, the time required for calculation processing can be reduced.

[0110] In this embodiment, the imaging device 100 processes normal image data and neural network data. The imaging device 100 can output data corresponding to the different data. It is preferable that the image capturing timing is synchronized with the scanning line. Therefore, when the image capturing device 100 moves at high speed, a time difference occurs. To photograph a subject, it is preferable to use a global shutter system.

[0111] In the global shutter system, all the light receiving circuits 21 of the image sensor 10 are connected to the terminals It is preferable to control Tx (61) and terminal RS (62) simultaneously. The device 100 can simultaneously acquire the light reception data received by the light receiving circuit 21. The memory circuit 31b of the circuit 20a stores the data processed by the multilayer perceptron. The data is given at the same time.

[0112] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0113] (Embodiment 2) In this embodiment, an imaging device having an interface for connecting to a neural network is used. The device will be described with reference to FIGS.

[0114] One aspect of the present invention is a configuration and an operation method of an imaging device that is different from those in the first embodiment.

[0115] 5 is a block diagram showing an example of the configuration of the imaging device 100 different from that shown in FIG. The difference from FIG. 1 is that the decision circuit 20a The image forming apparatus includes a width circuit 300 and a decision output circuit 310.

[0116] In FIG. 5, four pixels 20 included in the determination circuit 20a will be described.

[0117] Each pixel 20 is electrically connected to an amplifier circuit 300. 0 is electrically connected to the decision output circuit 310.

[0118] However, the number of pixels 20 included in the determination circuit 20a is appropriately selected depending on the area to be determined. In addition, the light receiving circuit 21a included in the pixel 20 preferably includes a plurality of amplifier circuits 300. may be connected to

[0119] The photoelectric conversion element PD included in the light receiving circuit 21a included in the pixel 20 converts received light into a voltage. Therefore, the pixel 20 outputs the output signal a. is the output signal b, which is the result of converting an analog signal to a digital signal and then amplifying the digital signal. can be output.

[0120] The output signal b is calculated by the decision output circuit 310. The calculation function is addition or multiplication. In this embodiment, an adder circuit is used.

[0121] The decision output circuit 310 can extract information features from the output signal b. The obtained information is further judged, and the judged result can be output as an output signal d.

[0122] 6A is a block diagram showing the details of the decision circuit 20a. In FIG. 0a, an example in which four pixels 20 are connected will be described. Each pixel 20 includes a light receiving circuit 21a and a memory The determination circuit 20a includes an amplifier circuit 300 and a feature extraction circuit 310. 2 and an output circuit 33.

[0123] The amplifier circuit 300 includes an input selection circuit 301, an analog-to-digital conversion circuit 302, and a decision circuit. The determination circuit 303 includes a logic circuit 306 and a memory circuit 304. and a selection circuit 305.

[0124] The light receiving circuit 21a is electrically connected to the memory circuit 23. The memory circuit 23 stores a signal. The output terminal of the light receiving circuit 21a is electrically connected to the line OUT1. The input terminal of the input selection circuit 301 is electrically connected to the input terminal of the input selection circuit 301 in the input terminal 300 .

[0125] The light receiving circuit 21a converts the current generated by the photoelectric conversion element PD included in the light receiving circuit 21a into an electric current. The output signal a is converted into a voltage and output as an output signal a. 0 can be given to the input terminal.

[0126] The input selection circuit 301 is electrically connected to the analog-to-digital conversion circuit 302 . The analog-to-digital conversion circuit 302 is electrically connected to a determination circuit 303. The path 303 is electrically connected to the memory circuit 304 .

[0127] The input selection circuit 301 selects one of the four output signals a as the clock signal given to the terminal CLK. The analog-to-digital converter circuit 3 can select the signal generated from the clock signal. 02 converts the selected output signal a from a voltage to a digital signal and outputs it to the input of the decision circuit 303 The decision circuit 303 amplifies the digital signal by bit shifting. By bit shifting, the upper bits are extracted and the size of the upper bits is determined. The determination result of the upper bits can be stored in the memory circuit 304. The held signal can be given to the input terminal of the feature extraction circuit 32 as the output signal b. Cut.

[0128] The feature extraction circuit 32 is electrically connected to the output circuit 33. The feature extraction circuit 32 The information feature is extracted from the output signal b given to the input terminal. The extracted information is counted. The output signal c is then sent to the input terminal of the output circuit 33. is further judged by the output circuit 33, and the judged result is output as an output signal d. can.

[0129] The block diagram in Figure 6(A) shows the functions of a neuron in a neural network. Neurons have synapses and activation functions. The synapse circuit multiplies a plurality of input signals by weighting coefficients, and outputs each of the multiplied input signals. In other words, a neuron can multiply and add the results of multiple input signals. The activation function circuit has the function of converting the result of the product-sum operation into a It has a judgment function to extract features from the image.

[0130] Figure 6(B) shows the block diagram of Figure 6(A) as a neuron schematic diagram. Synapse Circuit 3 2N includes an amplifier circuit 300 and a feature extraction circuit 32. Also, an activation function circuit 3 3N has an output circuit 33.

[0131] FIG. 6B shows an example in which four light receiving circuits 21a are connected to an amplifier circuit 300. However, the number of connected light receiving circuits 21a is not limited. The optical circuits 21a are explained as PD(i), PD(i+1), PD(i+2), and PD(i+3). Let i and j be natural numbers greater than or equal to 1.

[0132] The amplifier circuit 300 can multiply the output signal a by a weighting coefficient A. The weighting coefficient A is expressed as follows: It is set by the decision circuit 303 in FIG. 6(A). The weighting coefficient A can be replaced with the amplification factor. Therefore, the information obtained by multiplying the output signal a by the weighting coefficient A is extracted as the output signal b. is provided to circuit 32.

[0133] However, the weighting coefficient A of the decision circuit 303 may be set to the same weighting coefficient or to different weighting coefficients. A weighting factor may be set.

[0134] Under the above conditions, the sum of the outputs of the feature extraction circuit 32 is expressed by the formula 1 shown in the first embodiment. In addition, the output signal d(i) outputted by the activation function circuit 33N can be expressed as follows: This can be expressed by Equation 2 shown in State 1.

[0135] The output function f(c(i)) of the activation function circuit 33N means a sigmoid function. The output circuit 33 of the activation function circuit 33N receives an output signal indicating whether the determination condition is updated or not. Therefore, the output circuit 33 can be used to generate a neural network. It generates a condition called firing in the network and outputs a binary digital signal. This can be done.

[0136] FIG. 7 shows an example of the circuit of FIG. 6(A). FIG. 7 shows the pixel 20, the amplifier circuit 300, the feature extraction circuit, 1 shows examples of the circuit 32 and the output circuit 33.

[0137] First, the pixel 20 will be described. The pixel 20 includes a light receiving circuit 21a and a memory circuit 23. The light receiving circuit 21a includes a photoelectric conversion element PD, a capacitance element C1, a transistor 41, and a It has a transistor 42 .

[0138] The capacitance element C1 holds the potential generated by the photoelectric conversion element PD as an output signal a. The transistors 41 and 42 are used to hold and reset the signals. The timing for this can be controlled.

[0139] The output signal a is stored in the memory circuit 23 and can be read out as needed. In order to read out the data, a scanning signal is applied to the scanning line G1, and the data is read out via the signal line OUT1. The signal is transferred to the analog-to-digital conversion circuit 26. The column driver for reading the memory circuit 23 Alternatively, a decoder circuit 27 may be used.

[0140] Next, the amplifier circuit 300 will be described. The amplifier circuit 300 includes an input selection circuit 301, Analog-to-digital conversion circuit 302, memory circuit 304, selection circuit 305, logic circuit 306 The amplifier circuit 300 includes four light receiving circuits 21a and a counter circuit CN1. The explanation will be given assuming that the clock signal is electrically connected to the amplifier circuit 300. The clock signal is given from the LK terminal. Since the clock signal is the reference for circuit operation, it is It is also given to 10.

[0141] The input selection circuit 301 can select one of the four output signals a. One method is to use a counter circuit CN1. can provide an output signal cnt1 to the input selection circuit 301. The counter circuit CN 1 is a counter circuit CN1 according to the number of light receiving circuits 21a connected to the amplifier circuit 300. The counter circuit CN1 is connected to the clock input terminal CLK. Since the counting operation is synchronized with the clock signal, the input selection circuit 301 Therefore, the output signal a can be selected sequentially.

[0142] The input selection circuit 301 selects the output signal a by the output signal cnt1 and outputs it as an analog The analog-to-digital conversion circuit 302 can provide the Here is an example of converting an output signal a given by voltage into an 8-bit digital signal D[7:0]. The analog-to-digital conversion circuit 302 can appropriately select the data width as needed. preferable.

[0143] As a method of amplifying digital signals, calculations are performed by overflowing digits through bit shifting. The decision circuit 303 performs a bit sequence on the digital signal D[7:0]. The software amplifies the signal and can classify the magnitude of the digital signal into multiple ranges.

[0144] Bit shifting is a power of 2 operation, where the value is shifted one bit to the left. Therefore, by shifting one bit to the left, the digital signal When the most significant bit D[7] of D[7:0] is high, the digital signal is 128 It means that it is larger than the LSB. Also, the most significant 2 bits D[7:6] are High means that the digital signal is greater than 192 LSB. The selection circuit 305 can amplify the digital signal and classify the magnitude range of the digital signal. can.

[0145] The selection circuit 305 receives a signal for selecting the range of the magnitude of the digital signal from the GAIN terminal. The selection circuit 305 outputs a High signal if the digital signal is within the specified selection range. If the signal is outside the specified range, a Low signal is sent to the memory circuit 304. The signal output to the memory circuit 304 is referred to as an output signal a1.

[0146] However, the bit shift amount, which is the amplification factor, is calculated externally and given from the GAIN terminal. Therefore, the amplifier circuits 300 may all be judged under the same conditions, or may be judged under different conditions. Therefore, the decision condition of the logic circuit 306 may be set by the programmable logic Rays may be used to reconstruct the criteria depending on the process.

[0147] The memory circuit 304 can be a latch circuit. By using a circuit, the circuit size can be reduced and the number of control signals can be reduced. The timing of writing to the memory circuit 304 is preferably set by the counter circuit CN1. As an example, the input selection circuit 301 can use the output signal cnt1. When the high level of cnt1 is selected, the timing of the falling edge of the output signal cnt1 In synchronization with this, the output signal a1 is held in the memory circuit 304. The held signal is b is given to the input terminal of the feature extraction circuit 32.

[0148] The feature extraction circuit 32 can extract information features from the output signal b. It indicates whether the output signal a extracted by the decision circuit 303 is within the specified range.

[0149] The feature extraction circuit 32 includes an input selection circuit 32a, a counter circuit 32c, and a counter circuit C. The output circuit 33 includes a decision circuit 33a, a switching circuit 33b, and an inverter 32b. The circuit 33b includes a memory circuit 33c.

[0150] The input selection circuit 32a can select one of the four output signals b. As an example of the method, the counter circuit CN2 can be used. Since the data is captured after the output signal b of the memory circuit 304 is determined, the amplifier circuit 30 The clock signal given to 0 is inverted by inverter 32b and sent to counter circuit CN2. The input selection circuit 32a outputs the output signal b to the output signal b1 in order. It is possible.

[0151] The counter circuit 32c receives an output signal b that satisfies a specified range from the GAIN terminal. The number of 1s can be counted. The output signal b1 is generated when the magnitude of the output signal a is within the specified range. If it is included, it outputs High, and if it is not included, it outputs Low.

[0152] Therefore, the counter circuit 32c can count the number of items having the information characteristic. The collected result is sent to the output circuit 33 of the decision output circuit 310 as an output signal c. This can be done.

[0153] The determination circuit 33a is given a determination value from the CMPD terminal. The memory circuit 33c determines whether the output signal c having the characteristic is greater than the determination value. The signal dout is given as the result of the decision. However, the output signal c is stored in the memory circuit 33c. The selection of the determination method can be switched by the switching circuit 33b.

[0154] The memory circuit 33c can be made of various memory circuits, but the output is preferably set to high impedance. For example, a circuit with silicon in the semiconductor layer of a transistor is preferable. Alternatively, a memory having an oxide semiconductor in a semiconductor layer of a transistor can be selected. Note that an oxide semiconductor will be described in detail in Embodiment 6. will be explained.

[0155] The output signal dout held in the memory circuit 33c can be read out as needed. It is preferable that the signal is read out by a scanning signal given to the scanning line G2. The data is transferred to the selector circuit 28 via the line OUT. To output the signal, a column driver and a row driver may be provided separately. A delay circuit 27 may also be used.

[0156] FIG. 8A shows a timing chart (T21 to T25) of the imaging device 100 of FIG. During the period from T21 to T22, the decoder circuit 27 supplies the pixel 20 with a signal of the scanning line G1(j). A scanning signal is given via the The decision circuit 20a receives the scan line G2 (k ) is given a scanning signal, and the data held in the memory circuit 33c is input to the selector circuit 28 Transfer to.

[0157] 8B shows a timing chart of the determination circuit 20a in FIG. The operation of is controlled by the scan line G1(j). The scanning signal is also applied to the terminal RS (62). , which corresponds to T31 to T43 in FIG. 8(B).

[0158] During the period from T31 to T41, a low voltage is applied to the terminal Tx(61), and the transistor 4 1 remains in the OFF state. Also, terminal RS (62) is given a high level, and the transistor Therefore, the potential held by the capacitance element C1 is equal to the output signal a. The output signal a is fed to the amplifier circuit 300. The amplifier circuit 300 and the decision output circuit 310 The calculation is performed as follows.

[0159] During the period from T41 to T43, the terminal Tx (61) and the terminal RS (62) are high. Therefore, the transistors 41 and 42 are turned on. Therefore, the potential held by the capacitance element C1 is It is refreshed by the voltage applied to terminal VRS (72).

[0160] At the timing of T43, the scanning signal applied to the scanning line G1(j) becomes Low. Furthermore, the terminal RS (62) becomes low. Therefore, the transistor 42 is in the OFF state. The transistor 41 is maintained in the ON state. The data acquisition period is until the scanning line G1(j) is selected in the next frame. However, the decoder circuit of the image pickup device 100 is divided into multiple areas. Therefore, when the data acquisition period is processed in parallel, It can be done in less than one frame.

[0161] In FIG. 8(B), a scanning signal is applied to the scanning line G1(j) and a scanning signal is applied to the scanning line G2(k-1). The example shows that the scanning signals are applied at the same timing. The read timing from 33c is controlled by a scanning signal given independently to the scanning line G2. This may also be done.

[0162] The image sensor 10 shown in FIG. 7 includes a determination circuit 20a, which determines whether neurons in the brain Analog data is converted to digital data and processed similarly to the processing performed by With the above configuration, the image sensor 10 can extract the characteristics of information from analog data. The image sensor can extract the image data and perform compression calculations using digital data. 10 is capable of performing multiple parallel processing operations.

[0163] Neural networks require a huge amount of calculations and hierarchical processing. By using this embodiment, the neural network is Therefore, the decision circuit 20a can perform the process corresponding to the input layer. The circuit 20a receives light from the pixel 20 and performs digital processing to obtain a signal. Therefore, two types of output results of the signal of the received light data can be obtained. This reduces the amount of software-based calculation processing, and reduces the power consumption associated with calculations. Furthermore, the time required for calculation processing can be reduced.

[0164] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0165] (Embodiment 3) In this embodiment, the structure of the imaging device of the first embodiment will be explained with reference to FIGS. 9 to 20. explain.

[0166] FIG. 9 is a diagram illustrating an example of a specific configuration of the pixel 20. The transistor 41, the transistor 42, and the transistors 46 and 47 of the amplifier circuit 22a 7 is a cross-sectional view showing the channel length direction of the semiconductor device 7.

[0167] In the cross-sectional views described in this embodiment, wiring, electrodes, metal layers, and contact plates are Although the lugs (conductors 82) are shown as separate elements, they are electrically connected. In some cases, they may be provided as the same element. The embodiment in which elements such as these are connected via the conductor 82 is an example, and each element is connected via the conductor 82. In some cases, the connection is made directly without any need for a

[0168] 9 to 15 and 17, the substrate and each element such as a transistor On the substrate, insulating layers 81a to 81g are formed, which function as a protective film, an interlayer insulating film, or a planarizing film. , insulating layer 81j, etc. are provided. For example, the insulating layers 81a to 81g are silicon oxide films, An inorganic insulating film such as a silicon oxynitride film can be used. Alternatively, an acrylic resin, a poly An organic insulating film such as an imide resin may be used. CMP (Chemical Mechanical Polishing) as needed A flattening process may be performed by a method such as a flattening method.

[0169] Note that there may be cases where some of the wirings, transistors, etc. shown in the drawings are not provided, or where the wirings, transistors, etc. shown in the drawings are not provided. In some cases, each layer may contain wiring, transistors, etc. that are not included.

[0170] The pixel 20 may have a layer 1100 and a layer 1200 as shown in FIG.

[0171] The layer 1100 can include a photoelectric conversion element PD. The photoelectric conversion element PD can include, for example, For example, a two-terminal photodiode can be used. pn-type photodiodes using single-crystal silicon substrates, amorphous silicon thin films, microcrystalline silicon pin-type photodiodes using silicon thin films or polycrystalline silicon thin films, selenium or selenium A photodiode using a compound such as the above or an organic compound can be used.

[0172] In FIG. 9, the photoelectric conversion element PD of the layer 1100 is made of a single crystal silicon substrate. The photoelectric conversion element PD is a pn-type photodiode. + territory Area 620, p. - region 630, n-type region 640, p + The structure may have a region 650. can.

[0173] The layer 1200 includes transistors that constitute the light receiving circuit 21, the amplifier circuit 22a, and the memory circuit 22b. The transistor may have an oxide semiconductor in the semiconductor layer. In FIG. 9, the light receiving circuit 21 has The transistor 41 and the transistor 42 included in the amplifier circuit 22a are 6 and 47 are shown as examples. In this way, the photoelectric conversion element PD, the light receiving circuit 21, and the amplifier circuit 22a can be configured to overlap with each other, and the light receiving area of ​​the photoelectric conversion element PD can be increased. An example of the oxide semiconductor will be described in detail in Embodiment 6.

[0174] The region where the OS transistor is formed and the region where the Si device (Si transistor or Si phototransistor) is formed are An insulating layer 80 is provided between the region where the diode or the like is to be formed.

[0175] The insulating layer provided near the Si device contains a conductor that terminates the dangling bonds of silicon. On the other hand, the semiconductor layers of the transistors 41 and 42 and the like contain hydrogen. Hydrogen in the insulating layer provided near the oxide semiconductor layer transports carriers into the oxide semiconductor layer. Therefore, the hydrogen is one of the factors that cause the reliability of the transistors 41, 42, etc. Therefore, one layer has a Si device and the other has an OS When stacking another layer having a transistor, it has the function of preventing hydrogen diffusion between them. It is preferable to provide an insulating layer 80 having the following properties. The insulating layer 80 prevents hydrogen from diffusing. This allows for improved reliability of both Si devices and OS transistors. do.

[0176] The insulating layer 80 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0177] One electrode (n-type region 640) of the photoelectric conversion element PD is made up of, for example, two conductors 82 and The transistor 41 and the transistor 42 can be electrically connected through the wiring 69. do.

[0178] Here, since the conductor 82 is provided to penetrate the insulating layer 80, the conductor 82 is also resistant to the diffusion of hydrogen. For example, as shown in FIG. In both cases, the outer side in contact with the side wall of the through hole is a conductor 82b having a barrier property against hydrogen, and the inner For example, the conductor 82a may be made of tungsten, Tantalum nitride or the like can be used for the conductive body 82b. Also, the layer containing impurities such as hydrogen and the conductor 82 may be in contact with each other. In this case, the conductor 82 may be composed of only the conductor 82b.

[0179] FIG. 9 shows a structure in which a top-gate OS transistor is provided in layer 1200. For example, The OS transistor is formed by stacking insulating layers (insulating layers 81a, 80, 81b), and an oxide semiconductor layer 130 and a layer functioning as a source electrode or a drain electrode. The conductive layers 140 and 150 function as a gate insulating layer, and the insulating layer 160 functions as a gate insulating layer. The insulating layer 81b functions as a gate insulating layer. It can also have the ability.

[0180] In FIG. 9, the OS transistor is provided with a conductive layer 173 functioning as a back gate electrode. In the configuration shown in Figure 9, light passing through layer 1100 causes the transistor to emit light. Therefore, a back gate electrode is provided to also function as a light blocking layer. Furthermore, by providing a back gate, the threshold voltage of the OS transistor can be reduced. It is possible to control pressure, etc.

[0181] The pixel 20 may also have a stacked structure as shown in FIG. The OS transistor has a structure in which a layer 1200 and a layer 1100 are provided on a substrate 115. Therefore, one of the OS transistor and the photoelectric conversion element PD is provided. This makes it easier to make electrical connection with the other electrode.

[0182] FIG. 10 illustrates an embodiment in which a selenium-based material is used for the photoelectric conversion layer 561. The photoelectric conversion element PD using this material has the characteristic of high external quantum efficiency for visible light. In addition, since selenium-based materials have a high light absorption coefficient, they have the advantage that the photoelectric conversion layer 561 can be easily made thin. In photoelectric conversion elements (PDs) that use selenium-based materials, the amplification is large due to avalanche multiplication. In other words, when a selenium-based material is used for the photoelectric conversion layer 561, a highly sensitive sensor can be obtained. This allows for sufficient photocurrent to be obtained even if the pixel area is reduced. The photoelectric conversion element PD using this material is also suitable for imaging in low-light environments.

[0183] As the selenium-based material, amorphous selenium or crystalline selenium can be used. Crystalline selenium can be obtained, for example, by forming amorphous selenium into a film and then heat treating it. By making the crystal grain size smaller than the pixel pitch, it is possible to reduce the characteristic variations between pixels. Crystalline selenium also has higher spectral sensitivity and light absorption for visible light than amorphous selenium. It has high coefficient characteristics.

[0184] In FIG. 10, the photoelectric conversion layer 561 is illustrated as a single layer, but as shown in FIG. On the light receiving surface side, a hole injection blocking layer 568 is formed of gallium oxide, cerium oxide or In-Ga- Alternatively, as shown in FIG. 11B, an electron ion implantation layer may be formed on the electrode 566 side. Nickel oxide or antimony sulfide may be provided as the injection blocking layer 569. 11(C), a hole injection blocking layer 568 and an electron injection blocking layer 569 are provided. It may also be possible to use the following.

[0185] The photoelectric conversion layer 561 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. In CIS and CIGS, avalanche multiplication is used as the light source, similar to the case of a single layer of selenium. An electric conversion element can be formed.

[0186] The photoelectric conversion element PD using a selenium-based material has an electrode 5 formed of, for example, a metal material. A photoelectric conversion layer 561 can be provided between the light-transmitting conductive layer 66 and the light-transmitting conductive layer 562 . In addition, CIS and CIGS are p-type semiconductors, and sulfur dioxide from n-type semiconductors is used to form junctions. Cadmium, zinc sulfide, or the like may be provided in contact therewith.

[0187] In FIG. 10, the transparent conductive layer 562 and the wiring 571 are in direct contact with each other. As shown in FIG. 10, the two may be connected via a wiring 588. The photoelectric conversion layer 561 and the light-transmitting conductive layer 562 are not separated between pixels. As shown in FIG. 1(E), the circuits may be separated. A partition wall 567 made of an insulator is provided in the region where the electrode 566 is not provided, and the photoelectric conversion layer 561 and the transparent conductive layer 566 are It is preferable to prevent cracks from occurring in the conductive layer 562. In this way, the partition wall 567 may not be provided.

[0188] The electrode 566, the wiring 571, and the like may have multiple layers. In this way, the electrode 566 is made of two layers, a conductive layer 566a and a conductive layer 566b, and the wiring 571 is made of a conductive material. The conductive layer 571a and the conductive layer 571b can be two layers. For example, the conductive layer 566a and the conductive layer 571a are formed by selecting a low-resistance metal or the like. The conductive layer 566b and the conductive layer 571b are formed by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 561. By adopting such a configuration, the electrical characteristics of the photoelectric conversion element PD can be improved. In addition, some metals can be electrically conductive by contacting with the transparent conductive layer 562. Even if such a metal is used for the conductive layer 571a, the conductive layer 571 By using b, electrolytic corrosion can be prevented.

[0189] The conductive layer 566b and the conductive layer 571b are made of, for example, molybdenum or tungsten. The conductive layer 566a and the conductive layer 571a may include, for example, aluminum. Aluminum, titanium, or stacks such as aluminum sandwiched between titanium can be used.

[0190] As shown in FIG. 12(D), the transparent conductive layer 562 and the wiring 571 are connected to the conductor 82 and the wiring 571. The connection may be via line 588.

[0191] The partition wall 567 can be formed using an inorganic insulator, an insulating organic resin, or the like. The partition wall 567 serves to shield the transistors and the like from light and / or to reduce the area of ​​the light receiving portion per pixel. It may be colored black or the like for clarity.

[0192] The pixel 20 may also have a stacked structure as shown in FIG. 10 differs from the pixel 20 shown in FIG. 10 only in the layer 1100, and the other configurations are the same.

[0193] In FIG. 13, the photoelectric conversion element PD included in the layer 1100 has an amorphous silicon layer. The photodiode shown is a pin-type photodiode that uses a silicon film or a microcrystalline silicon film. The conversion element PD is made up of an n-type semiconductor layer 565, an i-type semiconductor layer 564, and a p-type semiconductor layer 563. , an electrode 566 , a wiring 571 , and a wiring 588 .

[0194] The electrode 566 is in contact with the insulating layer 80. The p-type semiconductor layer 563 is connected to a wiring 588. The wiring 588 is electrically connected to the electrode 566 through the insulating layer 81e. can be.

[0195] It is preferable to use amorphous silicon for the i-type semiconductor layer 564. The n-type semiconductor layer 563 and the n-type semiconductor layer 565 contain dopants that impart their respective conductivity types. Amorphous silicon or microcrystalline silicon, which includes a photoelectric conversion layer, can be used. The photodiode used as the conversion layer has high sensitivity in the visible light wavelength range, and can detect weak visible light. Easy to detect.

[0196] In addition, the photoelectric conversion element PD has a configuration of a pin-type thin film photodiode. The photoelectric conversion element PD and the wiring connection are shown in the examples of FIGS. 14(A), (B), and (C). The configuration of the photoelectric conversion element PD and the connection between the photoelectric conversion element PD and the wiring may be the same as above. The present invention is not limited to these, and other forms may also be used.

[0197] FIG. 14(A) shows a transparent conductive layer 56 in contact with a p-type semiconductor layer 563 of a photoelectric conversion element PD. The transparent conductive layer 562 acts as an electrode and is connected to the output of the photoelectric conversion element PD. The power current can be increased.

[0198] The transparent conductive layer 562 may be made of, for example, indium tin oxide or silicon-containing indium tin. Oxides, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, aluminum zinc oxide containing fluorine, tin oxide, tin oxide containing antimony, graphene or The light-transmitting conductive layer 562 is not limited to a single layer. It may also be a laminate of different films.

[0199] In FIG. 14B, the light-transmitting conductive layer 562 and the wiring 571 are connected via the conductor 82 and the wiring 588. The p-type semiconductor layer 563 of the photoelectric conversion element PD and the wiring 571 are connected to each other. may be connected via the conductor 82 and the wiring 588. In (B), the light-transmitting conductive layer 562 may not be provided.

[0200] FIG. 14C shows a state in which the p-type semiconductor layer 563 is exposed in the insulating layer 81e covering the photoelectric conversion element PD. An opening is provided, and the light-transmitting conductive layer 562 covering the opening and the wiring 571 are electrically connected. It has a structure having a continuity.

[0201] The photoelectric conversion element PD formed using the above-mentioned selenium-based material or amorphous silicon is Manufactured using general semiconductor manufacturing processes such as film processes, lithography processes, and etching processes In addition, selenium-based materials have high resistance, and as shown in Figure 10, they can be used for photoelectric conversion. The layer 561 may be configured not to separate the circuits. It can be produced at low cost.

[0202] The pixel 20 may also have a stacked structure as shown in FIG. The layer 1300 has a structure in which the layer 1200 and the layer 1100 are provided on the layer 1300. For example, the multiply-and-accumulate circuit shown in FIG. 3, an adder circuit, a memory circuit such as a latch, an analog-to-digital converter, A data conversion circuit such as a data conversion circuit, a buffer circuit, and a control circuit for the entire imaging device are provided. It is possible.

[0203] The layer 1300 includes an amplifier circuit 22a, a memory circuit 22b, a feature extraction circuit 30, and a decision output. The Si transistor used in the circuit 31 (for example, the transistor 44 of the amplifier circuit 22a) In FIG. 15, transistors 44a, 44b, 45a , 45b exemplify a fin-type structure provided on a silicon substrate 600, and FIG. It may be a planar type as shown in Figure 16(A), or a serial type as shown in Figure 16(B). The semiconductor layer 660 may be a thin film transistor. Crystalline silicon and single-crystal silicon of SOI (Silicon on Insulator) It can be said that:

[0204] In addition, FIG. 15 shows a configuration in which a layer 1300 is added to the configuration shown in FIG. 10. Layer 1300 may be added to the configuration shown in FIG.

[0205] FIG. 17 is a cross-sectional view of a configuration in which a layer 1400 is added to the configuration shown in FIG. 9, and shows the structure for three pixels (pixels It represents elements 20A, 20B, and 20C).

[0206] The layer 1400 includes a light-shielding layer 1530, optical conversion layers 1550a, 1550b, and 1550c, A microlens array 1540 or the like may be provided.

[0207] An insulating layer 81h is formed in the region in contact with the layer 1100. The insulating layer 81h is resistant to visible light. A highly transparent silicon oxide film can be used as the passivation film. Alternatively, a silicon nitride film may be laminated as the anti-reflection film. Alternatively, a dielectric film such as aluminum may be laminated.

[0208] A light-shielding layer 1530 can be provided on the insulating layer 81h. This light-shielding layer 153 is placed at the boundary between pixels and has the function of blocking stray light entering from an oblique direction. The film includes a metal layer such as aluminum or tungsten, and a combination of the metal layer and the anti-reflection film. The dielectric film may be laminated with other dielectric films having the same function.

[0209] On the insulating layer 81h and the light-shielding layer 1530, optical conversion layers 1550a, 1550b, and 1550c are provided. For example, the optical conversion layers 1550a, 1550b, and 1550c can be provided with , R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta) By assigning a filter, a color image can be obtained.

[0210] In addition, if a filter that blocks light with wavelengths shorter than visible light is used in the optical conversion layer, the infrared imaging device In addition, a filter that blocks light having wavelengths shorter than near-infrared rays is used in the optical conversion layer. If the optical conversion layer is made of a material having a wavelength longer than that of visible light, it can be used as a far-infrared imaging device. By using a filter that blocks ultraviolet light, it can be used as an ultraviolet imaging device.

[0211] In addition, if a scintillator is used in the optical conversion layer, it can be used in X-ray imaging devices and other devices that can detect strong radiation. The imaging device can be used to obtain images that visualize weak radiation such as X-rays that have passed through the subject. When radiation is incident on the scintillator, it is converted into visible and ultraviolet light by the photoluminescence phenomenon. Then, the light is detected by the photoelectric conversion element PD. Image data may be acquired by using the imaging device having this configuration as a radiation detector. .

[0212] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy. These include materials that emit visible light and ultraviolet light as a result of the addition of ions. For example, Gd2O2S:Tb, Gd2O2S: Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, and ZnO dispersed in resin or ceramics can be used. can.

[0213] The microlens array 154 is disposed on the optical conversion layers 1550a, 1550b, and 1550c. 0 can be provided. Light passing through each lens of the microlens array 1540 passes through the optical conversion layers 1550a, 1550b, and 1550c directly below and is illuminated by the photoelectric conversion element PD. You will be shot.

[0214] As shown in FIG. 18(A), the light receiving circuit 21 has capacitance elements C1 and C2. The floating nodes Fn1 and Fn2 may be configured as floating nodes Fn1 and Fn2. Fn1 is the gate capacitance of the transistor 41 and the transistor 44a, and the parasitic capacitance between the wirings. is used to hold the charge.

[0215] The transistors 41 to 43 used in the light receiving circuit 21 are as shown in FIG. Alternatively, a back gate may be provided. A constant potential may be applied to the back gate. As an example, the threshold voltage of the transistors 41 to 45 can be controlled by the above-described method. The transistor having a back gate is shown in the transistor 43. This may be applied to all or some of the transistors.

[0216] As shown in FIG. 18B, the barriers of the transistors 41 to 43 The wiring connected to the gate of each transistor is electrically connected to the gate of the other transistor. It's fine.

[0217] In an n-channel transistor, a potential lower than the source potential is applied to the back gate. Conversely, if the back gate is applied with a potential higher than the source potential, the threshold voltage shifts in the positive direction. When a large potential is applied, the threshold voltage shifts in the negative direction. When controlling the on / off of each transistor with a gate voltage, the source is connected to the back gate. When a potential lower than the back gate potential is applied, the off-state current can be reduced. When a potential higher than the source potential is applied to the gate, the on-current can be increased.

[0218] In the light receiving circuit 21, the floating nodes Fn1 and Fn2 have a high potential holding capability. Therefore, as described above, the transistors 41 to 43 are OS transistors with low off-state current. It is preferable to use a source voltage applied to the back gates of the transistors 41 to 43. By applying a potential lower than the potential, the off-state current can be further reduced. This can improve the potential holding capability of the floating nodes Fn1 and Fn2.

[0219] As described above, as an example, the amplifier circuit 22a has, as shown in FIG. It is preferable to use transistors with high on-state current for the transistors 44a and 45a. Applying a potential higher than the source potential to the back gates of the transistors 44a and 45a In FIG. 18(C), a common bus for the light receiving circuit 21 is shown. The back gate of the amplifier circuit 22a is connected to the terminal VBG (73). Although an example of connecting BG (73a) is shown, the back gate of each transistor Therefore, the on-current can be increased. This improves the response of the amplifier circuit of the circuit 22a, allowing it to operate at a high frequency. can.

[0220] To increase the light sensitivity of an imaging device, the voltage applied between the photodiodes is changed. The amount of current flowing through the photodiode can be controlled, enabling the environmental sensor to detect and manage the operating environment. The appropriate light sensitivity can be set based on the information detected by sensors (illuminance sensor, temperature sensor, humidity sensor, etc.). It can be made possible.

[0221] Inside the imaging device, in addition to each power supply potential, a signal potential and a potential applied to the back gate are When multiple potentials are supplied from the outside of the imaging device, the number of terminals, etc. Therefore, it is preferable that the imaging device has a power supply circuit that generates a plurality of potentials inside. It's nice.

[0222] Also, as shown in FIG. 19(A), the transistors 41 and 42 of the light receiving circuit 21 are connected. The source or drain of the transistor 41 and the source of the transistor 42 may be connected to each other. The source or drain of the transistor 44a is electrically connected to the gate of the transistor 44b. The routing node Fn1.

[0223] In addition, in FIG. 19(B), the terminal VRS (72) shown in FIG. 19(A) is a transistor It may be configured to be directly connected to the gate of 45a.

[0224] FIG. 20A is a block diagram showing an example of the analog-to-digital conversion circuit 26. The log-to-digital conversion circuit 26 includes a comparator 26a, a counter circuit 26b, etc. This allows multi-bit digital data to be output to the wiring 93 (OUT3). .

[0225] The comparator 26a detects the signal potential input from the terminal 37 to the terminal 38 and the rising or falling The output voltage is compared with the reference potential (VREF) which is swept down. Counter circuit 26b operates in response to the output of 6a, and a digital signal is output to wiring 93 (OUT3). The number is output.

[0226] Here, the analog-to-digital conversion circuit 26 is a CMOS circuit for high-speed operation and power saving. It is preferable to form the transistor from a silicon transistor that can form a circuit.

[0227] The image sensor 10 and the analog-to-digital conversion circuit 26 are connected as shown in FIG. As shown in the figure, the terminals 37 and 38 can be connected with wires by wire bonding or the like. That's fine.

[0228] Note that one embodiment of the present invention has been described in this embodiment. However, the present invention is not limited to these. In other words, various aspects of the invention are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. Although an example in which the present invention is applied to an imaging device has been described, one embodiment of the present invention is not limited thereto. In some cases or depending on the situation, one aspect of the present invention may not be applied to an imaging device. For example, one embodiment of the present invention may be applied to a semiconductor device having another function. As one embodiment of the present invention, a channel formation region, a source / drain region, etc. of a transistor Although an example in which an oxide semiconductor is included is shown above, one embodiment of the present invention is not limited thereto. In some cases, or depending on the situation, various transistors, The channel forming region of a transistor or the source / drain region of a transistor may be formed by various In some cases, or depending on the circumstances, one aspect of the present invention may include Various transistors in the semiconductor device, a channel forming region of a transistor, or a semiconductor device The source and drain regions are made of, for example, silicon, germanium, silicon germanium, carbon, etc. Silicon nitride, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride or an organic semiconductor. Depending on the situation, various transistors, transistors A channel formation region of the transistor, a source / drain region of the transistor, or the like is formed using an oxide semiconductor. For example, in one embodiment of the present invention, in the case of a global shutter system, However, one aspect of the present invention is not limited to this. In accordance with this, one embodiment of the present invention may use another method, for example, a rolling shutter method. Or, in some cases or depending on the situation, it may be necessary to use the global shutter method. Good too.

[0229] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0230] (Fourth embodiment) In this embodiment, an OS transistor that can be used in one embodiment of the present invention will be described. In the drawings of the present embodiment, some elements are shown in a simplified form for clarity. are illustrated enlarged, reduced, or omitted.

[0231] 21A, 21B, and 21C are top views of a transistor 101 of one embodiment of the present invention. 21(A) is a top view, and is a cross-sectional view taken along the dashed line X1-X2 shown in FIG. 21(B). The cross section in the direction of the dashed line Y1-Y2 shown in FIG. 21(A) corresponds to FIG. The cross section corresponds to FIG. 21(C).

[0232] In the drawings described in this embodiment, the direction of the dashed dotted line X1-X2 is the channel length. The direction of the dashed dotted line Y1-Y2 is called the channel width direction.

[0233] The transistor 101 includes an insulating layer 120 in contact with the substrate 115 and a conductive layer 122 in contact with the insulating layer 120. the oxide semiconductor layer 130 in contact with the insulating layer 120; The conductive layer 140 and the conductive layer 150 are electrically connected to each other, and the oxide semiconductor layer 130 and the conductive layer 14 0 and the conductive layer 150, and an insulating layer 160 in contact with the insulating layer 160, and a conductive layer 170 in contact with the insulating layer 160. do.

[0234] The oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 15 are formed over the transistor 101. 0, an insulating layer 180 in contact with the insulating layer 160 and the conductive layer 170 may be provided as needed.

[0235] The oxide semiconductor layer 130 includes, for example, oxide semiconductor layers 130a, 130b, and 130c. The above three-layer structure can be used.

[0236] The conductive layer 140 and the conductive layer 150 are source and drain electrode layers, and the insulating layer 160 is a gate electrode. The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0237] In addition, by using the conductive layer 173 as a second gate electrode layer (back gate), The conductive layer 173 can increase the current and control the threshold voltage. It can also function as a

[0238] To increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and In order to control the threshold voltage, A constant potential different from that of the conductive layer 170 may be supplied to the conductive layer 173 .

[0239] In the oxide semiconductor layer 130, the regions in contact with the conductive layer 140 and the conductive layer 150 are It can function as a source region or a drain region.

[0240] The oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies remain in the oxide semiconductor layer 130 or are absorbed from the outside. Due to the interaction with hydrogen diffusing from the surface, the region becomes a low-resistance region of n-type conductivity.

[0241] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. When using a current source, or when the direction of the current changes during circuit operation, For this reason, in this specification, the terms "source" and "drain" are interchangeable. In addition, the term "electrode layer" can be replaced with "wiring." It is also possible.

[0242] The conductive layer 140 and the conductive layer 150 are in contact with the top surface of the oxide semiconductor layer 130 and the side surface thereof. By adopting such a structure, the oxygen contained in the insulating layer 120 is This makes it easier to compensate for oxygen vacancies in the oxide semiconductor layer 130.

[0243] A transistor of one embodiment of the present invention has a structure shown in FIGS. 22A is a top view of the transistor 102. The cross section along the line X1-X2 corresponds to Fig. 22(B). The cross section in the Y1-Y2 direction corresponds to FIG. 22(C).

[0244] The transistor 102 is formed by connecting the conductive layer 140 and the conductive layer 150 to the insulating layer 120. and the conductive layer 140 and the conductive layer 150 are in contact with the side surfaces of the oxide semiconductor layer 130. The transistor 101 has a similar structure to that of the transistor 101.

[0245] Further, the transistor of one embodiment of the present invention has the structure shown in FIGS. FIG. 23A is a top view of the transistor 103. The cross section along the dashed line X1-X2 corresponds to FIG. 23(B). The cross section taken along the dashed dotted line Y1-Y2 corresponds to FIG. 23(C).

[0246] The transistor 103 includes oxide semiconductor layers 130a and 130b, a conductive layer 140, and a conductive layer 150 is covered with an oxide semiconductor layer 130c and an insulating layer 160. It has the same configuration as the controller 101.

[0247] By covering the oxide semiconductor layers 130a and 130b with the oxide semiconductor layer 130c, the oxide semiconductor The effect of supplementing oxygen to the conductor layers 130a and 130b and the insulating layer 120 can be improved. Furthermore, the presence of the oxide semiconductor layer 130c prevents the conductive layer 110 from being formed by the insulating layer 180. Oxidation of the conductive layer 40 and the conductive layer 150 can be suppressed.

[0248] Further, the transistor of one embodiment of the present invention has the structure shown in FIGS. FIG. 24A is a top view of the transistor 104. The cross section along the dashed line X1-X2 corresponds to FIG. 24(B). The cross section taken along the dashed dotted line Y1-Y2 corresponds to FIG. 24(C).

[0249] The transistor 104 includes oxide semiconductor layers 130a and 130b, a conductive layer 140, and a conductive layer The conductive layer 170 is covered with the insulating layer 210. The transistor 101 has a similar structure to the transistor 101 except for the above.

[0250] The insulating layer 210 can be made of a material that has a blocking property against oxygen. The insulating layer 210 may be made of a metal oxide such as aluminum oxide. The presence of the insulating layer 210 suppresses oxidation of the conductive layer 170 due to the insulating layer 180. It is possible.

[0251] The transistors 101 to 104 are formed by overlapping the conductive layer 170, the conductive layer 140, and the conductive layer 150. The width of the region in the channel length direction is In order to reduce the thickness, it is preferable that the thickness is 3 nm or more and less than 300 nm. Since no offset region is formed in the compound semiconductor layer 130, a transistor with a high on-state current It is easy to form.

[0252] A transistor of one embodiment of the present invention has a structure shown in FIGS. FIG. 25A is a top view of the transistor 105. The cross section along the line X1-X2 corresponds to Fig. 25(B). The cross section in the Y1-Y2 direction corresponds to FIG. 25(C).

[0253] The transistor 105 includes an insulating layer 120 in contact with the substrate 115 and a conductive layer 122 in contact with the insulating layer 120. the oxide semiconductor layer 130 in contact with the insulating layer 120; It has an insulating layer 160 in contact with the insulating layer 160 and a conductive layer 170 in contact with the insulating layer 160 .

[0254] The insulating layer 180, which functions as an interlayer insulating film, includes the region 23 of the oxide semiconductor layer 130. 1 and a conductor 201 in contact with a region 232 of the oxide semiconductor layer 130. The conductor 200 and the conductor 201 are a part of the source electrode layer or a part of the drain electrode layer. It can function as part of

[0255] In the region 231 and the region 232 of the transistor 105, oxygen vacancies are formed, and the conductivity It is preferable to add an impurity to the oxide semiconductor layer in order to increase the oxygen vacancy. Impurities include, for example, phosphorus, arsenic, antimony, boron, aluminum, silicon, Nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine One or more selected from the group consisting of titanium, zinc, and carbon can be used. The impurity addition method may be a plasma treatment method, an ion implantation method, an ion doping method, a plasma treatment ... Plasma implantation ion implantation and the like can be used.

[0256] When the above-described elements are added to the oxide semiconductor layer as impurity elements, the gold in the oxide semiconductor layer is The bond between the metal element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes the oxide semiconductor The conductivity of the conductor layer can be increased.

[0257] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by adding an impurity element, oxygen Hydrogen enters the vacancy site and a donor level is formed near the conduction band. As a result, the oxide conductor Here, an oxide semiconductor that has been made into a conductor is called an oxide conductor. .

[0258] The transistor 105 has a region where the conductive layer 170 overlaps with the conductive layer 140 and the conductive layer 150. The self-aligned structure does not have a gate electrode layer. The parasitic capacitance between the source electrode layer and the drain electrode layer is extremely small, making it suitable for high-speed operation. is doing.

[0259] A transistor of one embodiment of the present invention has a structure shown in FIGS. 26A is a top view of the transistor 106. The cross section along the line X1-X2 corresponds to Fig. 26(B). The cross section in the Y1-Y2 direction corresponds to FIG. 26(C).

[0260] The transistor 106 comprises a substrate 115, an insulating layer 120 on the substrate 115, and a gate insulating layer 120. The conductive layer 173 in contact with the insulating layer 120 and the oxide semiconductor layer 130 (oxide semiconductor layer 13 0a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) and oxide semiconductor layer 130 The conductive layer 140 and the conductive layer 150 are in contact with each other and spaced apart from each other, and the oxide semiconductor layer 130 c) and a conductive layer 170 that contacts the insulating layer 160.

[0261] The oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 are The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the insulating layer 180 on the substrate 6 are It is provided in an opening that reaches the insulating layer 120 .

[0262] A transistor of one embodiment of the present invention has a structure shown in FIGS. 27A is a top view of the transistor 107. The cross section along the line X1-X2 corresponds to Fig. 27(B). The cross section in the Y1-Y2 direction corresponds to FIG. 27(C).

[0263] The transistor 107 includes oxide semiconductor layers 130a and 130b, a conductive layer 140, and a conductive layer 150 is covered with the oxide semiconductor layer 130c and the oxide semiconductor layer 130d. The oxide semiconductor layer 130d has a structure similar to that of the transistor 106. It can be made of the same material as 30c.

[0264] By covering the oxide semiconductor layers 130a and 130b with the oxide semiconductor layers 130c and 130d, , and enhances the effect of oxygen supplementation to the oxide semiconductor layers 130a and 130b and the insulating layer 120. Furthermore, the presence of the oxide semiconductor layer 130d can prevent the insulating layer 180 from Therefore, oxidation of the conductive layers 140 and 150 can be suppressed.

[0265] The transistors 106 and 107 are configured by a conductor serving as a source or drain and a gate electrode. Since the overlapping area of ​​the conductors is small, the parasitic capacitance can be reduced. Therefore, the transistors 106 and 107 are suitable as elements of a circuit that requires high-speed operation. .

[0266] In addition, as shown in FIG. 28A, the transistor of one embodiment of the present invention includes an oxide semiconductor layer 28(B), the oxide semiconductor layer 130 may be formed as a single layer. 0 may be formed in two layers.

[0267] In addition, as shown in FIG. 28C, the transistor of one embodiment of the present invention includes a conductive layer 173. It may be configured not to have this.

[0268] In the transistor of one embodiment of the present invention, the conductive layer 170 and the conductive layer 173 are electrically 28(D), for example, an insulating layer 120, an oxide semiconductor layer 1 An opening is provided in the insulating layer 160 and the conductive layer 173, and a The conductive layer 170 may be formed.

[0269] In addition, the transistor of one embodiment of the present invention includes the conductive layer 140 and the Insulating layers 145 and 155 may be provided in contact with the conductive layers 150, respectively. The insulating layer 145 and the insulating layer 155 can suppress oxidation of the conductive layer 140 and the conductive layer 150. Cut.

[0270] The insulating layer 145 and the insulating layer 155 are made of a material having a blocking property against oxygen. For example, aluminum oxide can be used as the insulating layer 145 and the insulating layer 155. Metal oxides such as the above can be used.

[0271] In addition, as shown in FIG. 28F, the transistor of one embodiment of the present invention includes a conductive layer 170. The conductive layer 171 and the conductive layer 172 may be stacked.

[0272] In addition, in the case of one embodiment of the present invention in which the conductive layers 140 and 150 are provided over the oxide semiconductor layer 130, In the transistor, the oxide semiconductor layer 130 and the oxide semiconductor layer 140 are formed as shown in the top views of FIGS. The width (W) of the oxide semiconductor layer 130 is OS ) of the conductive layer 140 and the conductive layer 150. SD ) may be formed short. OS ≧W SD (W SD is W OS (below) so that the gate electric field is distributed over the entire channel formation region. This makes it easier for the transistor to be exposed to the radiation, thereby improving the electrical characteristics of the transistor.

[0273] Although the transistor 101 is illustrated as a modified example in FIGS. This modification can also be applied to the other transistors described in this embodiment.

[0274] In any of the structures of the transistors according to one embodiment of the present invention, the conductive layer is a gate electrode layer. The conductive layer 170 (and the conductive layer 173) has a channel width of the oxide semiconductor layer 130 through an insulating layer. This structure electrically surrounds the gate electrode in the direction of the gate. This is called a surrounded channel (s-channel) structure.

[0275] A transistor including an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, and The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In the transistor, the materials of the two or three layers constituting the oxide semiconductor layer 130 are appropriately selected. By selecting the oxide semiconductor layer 130b, a current can be passed through the oxide semiconductor layer 130b. By allowing the current to flow through 0b, it is less susceptible to the effects of interface scattering and a high on-current can be obtained. Cut.

[0276] By using a transistor having the above structure, it is possible to provide a semiconductor device with good electrical characteristics. It is possible.

[0277] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0278] (Embodiment 5) In this embodiment, components of the transistor described in Embodiment 3 will be described in detail. do.

[0279] The substrate 115 may be a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or a substrate with an insulating surface. A processed metal substrate can be used. Alternatively, a transistor or a photodiode can be used. and a silicon substrate on which an insulating layer, wiring, contact plugs, and the like are formed. It is possible to use a silicon-based conductive material having a function as a conductive material. When forming a p-channel transistor on the plate, n -Silicon substrate having a conductivity type It is preferable to use n - The SOI substrate had a silicon layer of either type or i-type. In addition, when the transistor provided on the silicon substrate is a p-ch type, It is preferable to use a silicon substrate having a (110) surface orientation on which a transistor is formed. By forming a p-ch transistor on the (110) plane, it is possible to increase the mobility. can.

[0280] The insulating layer 120 serves to prevent the diffusion of impurities from elements contained in the substrate 115. In addition, it can also play a role in supplying oxygen to the oxide semiconductor layer 130. The insulating layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. For example, the surface temperature of the film is 100°C or more and 700°C or more. In the TDS method, which is preferably performed by heat treatment at 100°C or higher and 500°C or lower, oxygen atoms are removed. The amount of oxygen released converted to 1.0 x 10 19 atoms / cm 3 The membrane is as above. In addition, if the substrate 115 is a substrate on which other devices are formed, the insulating layer 120 may be an interlayer insulating layer. It also functions as a film. In that case, the surface is flattened using a CMP method or similar. It is preferable to carry out the following.

[0281] The conductive layer 173 acting as a back gate electrode layer is made of, for example, Al, Ti, Cr, C Conductors such as O, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W Alternatively, alloys of the above materials or conductive nitrides of the above materials may be used. In addition, it is preferable to use a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials. It may be a laminate of materials.

[0282] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or oxide. Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide oxide insulating film such as tantalum oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and , silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. The insulating film may be a laminate of the above materials. That's fine.

[0283] The oxide semiconductor layer 130 includes an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. The compound semiconductor layer 130c can be stacked in order from the insulating layer 120 side to form a three-layer structure.

[0284] When the oxide semiconductor layer 130 is a single layer, the oxide semiconductor layer 1 A layer corresponding to 30b may be used.

[0285] When the oxide semiconductor layer 130 has two layers, the layer corresponding to the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are A lamination structure in which layers corresponding to the compound semiconductor layer 130b are stacked in order from the insulating layer 120 side may be used. In this configuration, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b can be interchanged. It is also possible.

[0286] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band) than the oxide layer 130c. A compound semiconductor is used.

[0287] In such a structure, when a voltage is applied to the conductive layer 170, the oxide semiconductor layer 130 A channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. Therefore, it can be said that the oxide semiconductor layer 130b has a region that functions as a semiconductor. However, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are insulators or semi-insulators. It can also be said that it has a functional area.

[0288] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are The oxide semiconductor that can be used preferably contains at least In or Zn. Alternatively, it is preferable that both In and Zn are contained. In order to reduce the variation in the electrical properties of the transistors, Al, Ga, Y, or Sn It is preferable to include a stabilizer such as

[0289] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are made of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1:9 :6 (atomic ratio) and In-Ga-Zn oxides with atomic ratios close to that. The oxide semiconductor layer 130b can be formed by In:Ga:Zn=1:1:1, 2 :1:3, 5:5:6, 3:1:2, 3:1:4, 5:1:6, or 4:2:3 (atom number In-Ga-Zn oxides having atomic ratios of 1000 to 10000 and the like can be used. .

[0290] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include: For example, by using crystals oriented along the c-axis, It is possible to give stable electrical properties. In addition, the crystals oriented along the c-axis are resistant to distortion and The reliability of a semiconductor device using a flexible substrate can be improved.

[0291] Conductive layer 140 acts as a source electrode layer and conductive layer 1 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and a single layer or laminate of a material selected from the group consisting of alloys of the metallic materials and conductive nitrides. In addition, by using tantalum nitride, which is a conductive nitride, oxidation can be prevented. In addition, it is possible to use a laminate of low-resistance Cu or Cu-Mn alloys and the above materials. That's fine.

[0292] The above-mentioned material has a property of extracting oxygen from the oxide semiconductor film. In a part of the oxide semiconductor film, oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed. The oxygen vacancies are bonded to hydrogen contained in a small amount in the oxide semiconductor layer. The region becomes significantly n-type. Therefore, the n-type region becomes the source or can act as a drain.

[0293] The insulating layer 160 acting as a gate insulating film is made of aluminum oxide, magnesium oxide, or the like. , silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide An insulating film containing one or more of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a stack of the above materials.

[0294] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When a conductor comes into contact with the material, the density of levels caused by nitrogen oxides may increase.

[0295] By using the insulating film as the insulating layer 120 and the insulating layer 160, the transistor It is possible to reduce the shift in threshold voltage, thereby reducing the fluctuation in the electrical characteristics of the transistor. It is possible.

[0296] The conductive layer 170 acting as a gate electrode layer may be made of, for example, Al, Ti, Cr, Co, or N. Conductive films such as I, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W Furthermore, alloys of the above materials and conductive nitrides of the above materials may also be used. Also, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials. Typically, tungsten, a stack of tungsten and titanium nitride, A laminate of tungsten and tantalum nitride can be used. Also, low-resistance Cu or An alloy such as Cu-Mn or a laminate of the above material with Cu or an alloy such as Cu-Mn may also be used. For example, titanium nitride is used for the conductive layer 171 and tungsten is used for the conductive layer 172. 70 can be formed.

[0297] The conductive layer 170 may be made of In-Ga-Zn oxide, zinc oxide, indium oxide, or silicon oxide. A conductive oxide layer such as indium tin oxide or indium tin oxide may be used. By providing the oxide conductive layer in the oxide semiconductor layer 130, oxygen can be supplied from the oxide conductive layer to the oxide semiconductor layer 130. can be provided.

[0298] The insulating layer 180 may be made of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, or the like. Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, silicon dioxide Contains one or more of: lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide The insulating layer may be a stack of the above materials.

[0299] Here, the insulating layer 180 has more oxygen than the stoichiometric composition, similar to the insulating layer 120. It is preferable that oxygen released from the insulating layer 180 passes through the insulating layer 160 and enters the oxide semiconductor. Since the ions can be diffused into the channel forming region of the organic layer 130, The oxygen vacancies can be filled with oxygen, resulting in a stable transistor. The electrical characteristics can be obtained.

[0300] In addition, on the transistor or the insulating layer 180, a layer having an effect of blocking impurities is formed. The blocking film may be a silicon nitride film, an aluminum nitride film, or the like. For example, a film made of aluminum or an aluminum oxide film can be used.

[0301] The nitride insulating film has the function of blocking moisture and other substances, improving the reliability of transistors. In addition, the aluminum oxide film can remove impurities such as hydrogen and moisture, and oxygen. Therefore, the aluminum oxide film has a high blocking effect, preventing both from penetrating the film. During and after the manufacturing process of the transistor, impurities such as hydrogen and moisture are removed from the oxide semiconductor layer. 130, preventing oxygen from being released from the oxide semiconductor layer, and preventing oxygen from being released from the insulating layer 120. It is suitable for use as a protective film having the effect of preventing unwanted emission.

[0302] To increase the integration density of semiconductor devices, miniaturization of transistors is essential. As transistors become smaller, their electrical characteristics tend to deteriorate. If it is made smaller, the on-state current will decrease.

[0303] In the transistor of one embodiment of the present invention, the oxide semiconductor layer 130b in which a channel is formed is The channel formation layer may be covered with the oxide semiconductor layer 130c. Since the gate insulating film does not come into contact with the channel forming layer, the carriers generated at the interface between the channel forming layer and the gate insulating film This can suppress scattering of electrons and increase the on-current of the transistor.

[0304] In the transistor of one embodiment of the present invention, as described above, the channel Since the gate electrode layer (conductive layer 170) is formed so as to electrically surround the gate electrode in the width direction, In addition to the gate electric field from the direction perpendicular to the top surface of the oxide semiconductor layer 130, a vertical electric field is applied to the side surface. The gate electric field is applied perpendicularly to the channel forming layer. Since a ground electric field is applied, the effective channel width is enlarged, and the on-current is further increased. can be done.

[0305] The various films such as the metal film, the semiconductor film, and the inorganic insulating film described in this embodiment are typically It can be formed by sputtering or plasma CVD, but other methods, such as thermal CV The thermal CVD method may be MOCVD (Metal Organic Chemical Vapor Deposition). Chemical Vapor Deposition (ALD) and Ato Micro-Layer Deposition (MIC Layer Deposition) method.

[0306] The thermal CVD method is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no further processing is required.

[0307] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time. The reaction is carried out in the vicinity of or on the substrate under atmospheric or reduced pressure, and the material is deposited on the substrate. Membrane may also be performed.

[0308] In the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is introduced into the chamber. The film is formed by repeating this process. For example, two or more kinds of carrier gases (e.g., argon, nitrogen, etc.) may be introduced. The source gases may be supplied to the chamber in order. In this case, multiple source gases are not mixed. In this way, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be introduced into the surface of the substrate to form a first layer by adsorbing and reacting with the surface of the substrate. The second source gas introduced later is adsorbed and reacted with the first layer, and the second layer is formed on the first layer. The order of gas introduction is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is introduced. This is suitable for fabricating miniaturized FETs.

[0309] A facing target sputtering device can also be used to form the oxide semiconductor layer. The film formation method using this facing target sputtering device is called VDSP (vapor deposition sputtering). It can also be called position SP).

[0310] By forming an oxide semiconductor layer using a facing target sputtering device, This reduces plasma damage during film formation of the compound semiconductor layer. In addition, by using a facing target sputtering device, Since the film can be formed at high pressure, the impurity concentration (for example, hydrogen, It is possible to reduce the amount of rare gases (such as argon), water, etc.

[0311] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0312] (Embodiment 6) In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductors (also called oxide semiconductors or simply OS), For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal Oxides are sometimes called oxide semiconductors. In other words, metal oxides have amplifying and rectifying properties. and a switching action, the metal oxide is A semiconductor (metal oxide semiconductor), abbreviated as OS. In addition, when referring to an OS transistor, it is possible to use a metal oxide or an oxide In other words, it is a transistor having a semiconductor.

[0313] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0314] In the present specification and the like, CAAC (c-axis aligned crystal) l), and CAC (Cloud-Aligned composite) CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration. Represents.

[0315] In addition, in this specification and the like, CAC-OS or CAC-metal oxide means A part of the material has a conductive function, and a part of the material has an insulating function, and the whole material It functions as a semiconductor. CAC-OS or CAC-metal oxide When used in the semiconductor layer of a transistor, the conductive function is to The insulating function is the function of not allowing the flow of electrons, which are carriers. By making the conductive function and insulating function work in a complementary manner, The function to turn the camera on / off is CAC-OS or CAC-metal. xide can be attached to CAC-OS or CAC-metal oxide. By separating the functions, it is possible to maximize the functionality of both. .

[0316] In addition, CAC-OS and CAC-metal oxide have different band gaps. For example, CAC-OS or CAC-metal oxide e is a component with a wide gap due to the insulating region and a narrow gap due to the conductive region. - A component having a gap, and is composed of. In the case of this configuration, when a carrier flows, In the component having a narrow gap, carriers mainly flow. Also, the narrow gap The component having acts complementarily on the component having a wide gap, and carriers also flow through the component having a wide gap in conjunction with the component having a narrow gap. Therefore, in the case where the above CA C-OS or CAC-metal oxide is used in the channel region of a transistor, a high current driving force, that is, a large on-current, and a high field effect mobility can be obtained in the on state of the transistor. That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite

[0317] (matrix composite), or a metal matrix composite (metal m atrix composite).

[0318] <Configuration of CAC-OS> Hereinafter, the configuration of CAC-OS that can be used for the transistor disclosed in one aspect of the present invention will be described.

[0319] CAC-OS is, for example, a material composition in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following, in the oxide semiconductor, one or more metal elements are unevenly distributed, and the region having the metal element is mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof, and this state is also referred to as a mosaic state or a patch state.

[0320] ​​​​Note that the oxide semiconductor preferably contains at least indium. and zinc. In addition to these, aluminum, gallium, yttrium, Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more selected from tantalum, tungsten, magnesium, etc. It may be possible.

[0321] For example, CAC-OS in In-Ga-Zn oxide (In- Ga-Zn oxide may be specifically referred to as CAC-IGZO. (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0). ), or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are ) is a real number greater than 0. ) and the material is separated into mosaics. Zyclic InO X1 , or In X2 Zn Y2 O Z2 However, the structure is uniformly distributed in the film (hereafter (Also called cloud-like.)

[0322] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 OZ2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0323] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In (1 +x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0324] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0325] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some of the nanoparticles are mainly composed of Ga. The region where the In nanoparticles are observed is shown in part. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0326] Note that CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, Not at all.

[0327] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0328] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. Aluminum, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will The region observed is a nanoparticle with the metal element as the main component, and a nanoparticle with In as the main component in part. The structure is such that the areas observed as particles and the areas observed as particles are randomly dispersed in a mosaic pattern. cormorant.

[0329] CAC-OS is formed by sputtering under conditions where the substrate is not intentionally heated. When the CAC-OS is formed by a sputtering method, the deposition gas The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the oxygen gas, the better. For example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%. It is preferable that the content is 0% or more and 10% or less.

[0330] CAC-OS is an X-ray diffraction (XRD) measurement method. When measured using one of the out-of-plane θ / 2θ scans In other words, from the X-ray diffraction, no clear peaks are observed in the measurement area. It can be seen that the orientation of the regions in the ab plane direction and the c axis direction is not observed.

[0331] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the sample, a ring-shaped region with high brightness and the corresponding Several bright spots are observed in the ring region. Therefore, the electron diffraction pattern indicates that the CAC- The crystal structure of OS is nc (nano) which has no orientation in the plane direction and cross-sectional direction. It can be seen that it has a (-crystal) structure.

[0332] For example, in the CAC-OS of In-Ga-Zn oxide, energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using scopy revealed that GaO X3 The region where is the principal component And, In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed. It can be confirmed that it has the structure shown in the figure.

[0333] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from GZO compounds. X3 The main components are and the region where In X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0334] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 When carriers flow through the region where the oxide is the main component, Conductivity as a semiconductor is exhibited. X2 Zn Y2 O Z2 , or InO X The cloud-like distribution of the region where 1 is the main component in the oxide semiconductor results in a high field effect. Mobility (μ) can be achieved.

[0335] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO is the main component. X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching. Switching operation can be realized.

[0336] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation due to Sex and In X2 Zn Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on) and high field-effect mobility (μ) can be done.

[0337] Furthermore, semiconductor devices using CAC-OS have high reliability. is ideal for various semiconductor devices including displays.

[0338] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0339] (Embodiment 7) In this embodiment, a package containing an image sensor chip and a camera module An example will be described. The image sensor chip has a structure of an imaging device according to one embodiment of the present invention. The composition can be used.

[0340] FIG. 29(A) is a perspective view showing the appearance of the upper surface of a package containing an image sensor chip. The package includes a package substrate 810 to which an image sensor chip 850 is fixed, It includes a cover glass 820 and an adhesive 830 that bonds the two together.

[0341] FIG. 29(B) is a perspective view of the bottom surface of the package. The structure of BGA (Ball grid array) with solder balls as bumps 840 In addition to BGA, LGA (Land grid array) and PGA ( Pin Grid Array) may also be used.

[0342] FIG. 29(C) shows the package with the cover glass 820 and part of the adhesive 830 omitted. 29(A) is a perspective view of the package, and FIG. 29(B) is a cross-sectional view of the package. An electrode pad 860 is formed on the substrate 810, and the electrode pad 860 and the bump 840 are formed through the substrate 810. The electrode pad 860 is electrically connected via a hole 880 and a land 885. The image sensor chip 850 is electrically connected to electrodes by wires 870. do.

[0343] Also, Figure 30(A) shows a camera in which an image sensor chip is housed in a lens-integrated package. 1 is a perspective view of the top surface of a camera module. A package substrate 811 for fixing a chip 851, a lens cover 821, and a lens 835 In addition, an imaging device is provided between the package substrate 811 and the image sensor chip 851. An IC chip 890 having functions such as a drive circuit and a signal conversion circuit for the device is also provided. It has a SiP (System in package) configuration.

[0344] 30(B) is a perspective view of the appearance of the lower surface side of the camera module. The bottom surface and four side surfaces of 811 are provided with lands 841 for mounting. This structure is an example only. It may be a QFP (Quad flat package) or the BGA mentioned above. stomach.

[0345] FIG. 30(C) shows the module with the lens cover 821 and part of the lens 835 omitted. FIG. 30(D) is a cross-sectional view of the camera module. A part of the electrode pad 861 is used as the image sensor chip. The electrodes of the chip 851 and the IC chip 890 are electrically connected by wires 871. There are.

[0346] By placing the image sensor chip in a package like the one described above, it becomes easier to mount. The semiconductor device can be incorporated into various semiconductor devices and electronic devices.

[0347] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0348] (Embodiment 8) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, and the like. personal computers, image storage devices or image playback devices with recording media, mobile phones, Game consoles, including those with a camcorder, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copying machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of these electronic devices are shown in Figure 31.

[0349] FIG. 31(A) shows a surveillance camera having a housing 951, a lens 952, a support portion 953, etc. The image capturing device of one aspect of the present invention is used as one of the components for capturing images in the surveillance camera. The term "surveillance camera" is a common name and does not limit its use. For example, equipment that functions as a surveillance camera is not a camera or video camera. Also called La.

[0350] FIG. 31B shows a video camera, which includes a first housing 971, a second housing 972, and a display unit 973. , an operation key 974, a lens 975, a connection part 976, etc. 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. As one of the components for acquiring images in the video camera, one aspect of the present invention is The imaging device may include:

[0351] FIG. 31C shows a digital camera, which includes a housing 961, a shutter button 962, a microphone, and the like. 963, a light emitting unit 967, a lens 965, etc. The imaging device according to one embodiment of the present invention can be provided as one of the components for obtaining the above object.

[0352] FIG. 31(D) shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, a wristband, and 933, operation buttons 935, a crown 936, a camera 939, etc. It may be a touch panel. As one example, the imaging device according to one embodiment of the present invention can be provided.

[0353] FIG. 31(E) shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 31(E) has two display units 90 3 and a display unit 904, but the number of display units that a portable game machine has is not limited to this. The present invention is not applicable to the portable game machine as one of the components for acquiring images. The imaging device may include an imaging device according to an embodiment.

[0354] FIG. 31(F) shows a portable data terminal, which includes a housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input and output of information. As one of the components for acquiring images in the portable data terminal, An imaging device may be provided. [Explanation of symbols]

[0355] a1 output signal a2 output signal b1 output signal c1 output signal C1 Capacitor element C2 Capacitor element C3 Capacitor element CN1 counter circuit CN2 counter circuit cnt1 output signal Fn1 Floating Node G1 scan line G2 scan line OUT1 signal line R1 Resistor element Vbias2 terminal Wd1 signal line Wd2 signal line 10. Image sensor 20 pixels 20a Judgment circuit 20A pixels 20B pixels 20C pixels 21 Photodetector circuit 21a Photodetector circuit 22 Amplification circuit 22a Amplifier circuit 22b Memory Circuit 22c Adding circuit 23 Memory Circuit 26 Analog-to-digital conversion circuit 26a Comparator 26b Counter circuit 27 Decoder circuit 28 Selector Circuit 29 Control Unit 30 Feature Extraction Circuit 30a op amp 30N synapse circuit 31 Judgment output circuit 31a Arithmetic circuit 31b Memory circuit 31N activation function circuit 32 Feature Extraction Circuit 32a Input selection circuit 32b inverter 32c counter circuit 32N synapse circuit 33 Output circuit 33a Judgment circuit 33b circuit 33c Memory Circuit 33N Activation Function Circuit 37 terminals 38 terminals 41 Transistor 42 transistors 43 Transistor 44 transistors 44a transistor 44b transistor 45a transistor 45b transistor 46 transistors 47 Transistor 48 transistors 49 Transistors 69 Wiring 80 insulating layer 81a Insulating layer 81b Insulating layer 81e Insulating layer 81g insulating layer 81h insulating layer 82 Conductors 82a Conductor 82b Conductor 93 Wiring 100 Imaging device 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 106 transistors 107 Transistor 115 PCB 120 insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide semiconductor layer 130c Oxide semiconductor layer 130d Oxide semiconductor layer 140 Conductive layer 145 Insulating Layer 150 conductive layer 155 Insulating Layer 160 Insulating Layer 170 Conductive Layer 171 Conductive layer 172 Conductive layer 173 Conductive Layer 180 insulating layer 200 Conductors 201 Conductors 210 Insulating layer 231 areas 232 areas 300 Amplification Circuit 301 Input selection circuit 302 Analog-to-Digital Conversion Circuit 303 Judgment circuit 304 Memory Circuit 305 Selection Circuit 306 Logic Circuits 310 Judgment output circuit 561 Photoelectric conversion layer 562 Transparent conductive layer 563 Semiconductor Layer 564 Semiconductor layer 565 Semiconductor Layer 566 Electrode 566a conductive layer 566b Conductive layer 567 Bulkhead 568 Hole injection blocking layer 569 Electron injection blocking layer 571 Wiring 571a Conductive layer 571b Conductive layer 588 Wiring 600 silicon substrate 620 p+ area 630 p-region 640 n-type region 650 p+ area 660 Semiconductor layer 810 package substrate 811 Package Substrate 820 Cover Glass 821 Lens cover 830 Adhesive 835 Lens 840 Bump 841 rand 850 image sensor chip 851 image sensor chip 860 electrode pads 861 Electrode Pads 870 Wire 871 Wire 880 through hole 885 rand 890 IC chips 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 chassis 912 Display section 919 Camera 931 Case 932 Display section 933 Wristband 935 Button 936 Crown 939 Camera 951 Case 952 Lens 953 Support part 961 Case 962 Shutter button 963 Mike 965 Lens 967 Light-emitting part 971 Case 972 case 973 Display section 974 Operation Key 975 Lens 976 Connection 1530 Light blocking layer 1540 Microlens Array 1550a Optical conversion layer 1550b Optical conversion layer 1550c optical conversion layer

Claims

[Claim 1] In an imaging device having neurons of a neural network, a plurality of first pixels, a first circuit, a second circuit, and a third circuit; the first pixel has a photoelectric conversion element, the photoelectric conversion element is electrically connected to the first circuit, the first circuit is electrically connected to the second circuit; the second circuit is electrically connected to the third circuit; the first pixel generates an input signal for the neuron in the neural network; the first circuit, the second circuit, and the third circuit have the function of the neuron; The imaging device, wherein the third circuit has an interface connected to the neural network.

Images