Image sensor, and manufacturing method for image sensor

Abstract

To provide an image sensor capable of preventing noise generation and miniaturization of a SPAD pixel while suppressing reduction of PDE (Photon Detection Efficiency).SOLUTION: An image sensor has a plurality of SPAD elements formed on a substrate. The SPAD elements include: trenches for separating the SPAD elements from other SPAD elements; first conductivity type semiconductor layers formed on side walls of the trenches; insulator films formed inside the trenches and covering a part of the first conductivity type semiconductor layers; and first electrodes which are formed inside the trenches and have parts that do not contact the first conductivity type semiconductor layers by being surrounded by the insulator films and first electrode ends that contact the first conductivity type semiconductor layers and form first contacts of the SPAD elements.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an image sensor and a method for manufacturing an image sensor. [Background technology]

[0002] In recent years, attention has been drawn to SPADs (Single Photon Avalanche Diodes), which amplify the charge generated by the photoelectric conversion of incident light using avalanche amplification and output it as an electrical signal. SPADs enable the detection of individual light particles and have extremely high time resolution.

[0003] To generate avalanche amplification, a high reverse bias voltage must be applied to the PN junction. However, if the PN junction is close to the power contact, a strong electric field may form between them, generating a tunneling current. This current may be amplified in the strong electric field even in the dark, when no light is shining, and may be detected as a false signal, resulting in noise.

[0004] Patent Document 1 below discloses the following solid-state imaging device. The device includes a first surface of a semiconductor substrate having a plurality of photoelectric conversion elements, a lattice-shaped first trench, and a second trench provided along the bottom of the first trench. Each photoelectric conversion element includes a photoelectric conversion region that photoelectrically converts incident light and generates electric charges within an element region defined by the first and second trenches. Each photoelectric conversion element includes a first semiconductor region that surrounds the photoelectric conversion region within the element region, a first contact that contacts the first semiconductor region at the bottom of the first trench, and a first electrode that contacts the first contact within the first trench. Each photoelectric conversion element includes a second semiconductor region that is provided in a region that contacts the first semiconductor region within the element region and has the same first conductivity type as the first semiconductor region. Each photoelectric conversion element also includes a third semiconductor region that is provided in a region that contacts the second semiconductor region within the element region, between the second semiconductor region and the first surface, and has a second conductivity type opposite to the first conductivity type. Each photoelectric conversion element includes a second contact provided on the first surface so as to contact the third semiconductor region, and a second electrode in contact with the second contact, The height of the first contact from the first surface is different from the height of the third semiconductor region from the first surface. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2020 / 203222 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the above prior art, because a power contact is formed at the bottom of the first trench of two trenches connected in series, the width of the first trench must be larger than the width of the second trench. Furthermore, to prevent tunneling current, a distance must be maintained between the PN junction and the power contact, so the height of the first trench from the first surface must be increased during miniaturization. This results in a reduction in the photoelectric conversion region by the width of the first trench, resulting in a problem of reduced photon detection efficiency (PDE).

[0007] The present invention has been made to solve the above problems, and aims to provide an image sensor and a method for manufacturing the image sensor that can reduce the size of SPAD pixels while preventing noise generation and suppressing a decrease in PDE. [Means for solving the problem]

[0008] an insulating film formed inside the trench and covering a portion of the first conductivity type semiconductor layer; a first electrode formed inside the trench and having a portion that is not in contact with the first conductivity type semiconductor layer as it is surrounded by the insulating film; and a first electrode end that contacts the first conductivity type semiconductor layer to form a first contact of the SPAD element. [Effects of the Invention]

[0009] This makes it possible to prevent noise generation and suppress a decrease in PDE while miniaturizing SPAD pixels. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of an image sensor. [Figure 2] FIG. 1 is a circuit diagram showing an example of a schematic configuration of a SPAD pixel. [Figure 3] FIG. 2 is a diagram showing a stacked structure of a pixel array. [Figure 4] FIG. 2 is a cross-sectional view showing the structure of a SPAD pixel. [Figure 5A] 5 is an example of a plan view of the AA plane in FIG. 4. [Figure 5B] 5 is another example of a plan view of the AA plane in FIG. 4. [Figure 6] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 7] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 8] 1A to 1C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 9] 1A to 1C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 10] 1A to 1C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 11] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 12] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 13] 1A to 1C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 14] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 15] 1A to 1C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 16] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 17] 12 is a flowchart showing main steps in a method of manufacturing the image sensor corresponding to FIGS. 6 to 11. [Figure 18A] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 18B] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 19A] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 19B] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 20A] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 20B] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 21A] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 21B] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 22A] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 22B] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 23] 22B. FIG. 23 is a flowchart showing main steps in a method of manufacturing the image sensor corresponding to FIGS. 18A to 22B. [Figure 24] FIG. 10 is a cross-sectional view showing the structure of a SPAD pixel according to a modified example. [Figure 25] FIG. 2 is a cross-sectional view showing the structure of a SPAD pixel. [Figure 26] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 27] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 28] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 29] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 30] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 31] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 32]32 is a flowchart showing main steps in a method of manufacturing the image sensor corresponding to FIGS. 26 to 31. [Figure 33] FIG. 2 is a cross-sectional view showing the structure of a SPAD pixel. [Figure 34] FIG. 34 is a plan view of the AA plane in FIG. 33. [Figure 35] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 36] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 37] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 38] 10A to 10C are explanatory diagrams for explaining a method of manufacturing an image sensor. [Figure 39] 39 is a flowchart showing main steps in a manufacturing method of an image sensor, corresponding to FIGS. 35 to 38. [Figure 40] FIG. 2 is a cross-sectional view showing the structure of a SPAD pixel. [Figure 41] FIG. 2 is a cross-sectional view showing the structure of a SPAD pixel. [Figure 42] FIG. 42 is a plan view of the AA plane in FIG. [Figure 43] 1 is a flowchart showing the main steps in a method for manufacturing an image sensor. [Figure 44] FIG. 2 is a cross-sectional view showing the structure of a SPAD pixel. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an image sensor and a method for manufacturing an image sensor according to an embodiment will be described in detail with reference to the accompanying drawings. The described embodiments are merely exemplary, and various modifications may be made to the embodiments. Hereinafter, the same reference numerals in the drawings refer to the same components, and the dimensions of the components in the drawings are not proportional to the actual size for the sake of clarity and convenience of the description.

[0012] Hereinafter, the expressions "upper" or "above" include not only what is directly above / below / left / right in contact, but also what is above / below / left / right without contact.

[0013] Terms such as "first" and "second" are used to describe various components, but are used only to distinguish one component from another, and are not intended to limit the materials or structures of the components.

[0014] An element expressed in the singular includes a plurality of elements unless the context clearly dictates otherwise. Furthermore, when a part "comprises" a certain element, this does not mean that other elements are excluded, but that other elements may also be included, unless otherwise specified to the contrary.

[0015] Furthermore, terms such as "module" used in the specification refer to a unit that processes one or more functions or operations, and may be realized by hardware or software, or a combination of hardware and software.

[0016] The term "end" means an end portion in a certain direction.

[0017] For ease of explanation, the following description will be given taking an example where the first conductivity type is P-type and the second conductivity type is N-type. However, this is for ease of explanation only, and the first conductivity type may be N-type and the second conductivity type may be P-type. The following description will be given taking an example where the first conductivity type semiconductor layer is a P-type semiconductor layer. The following description will be given taking an example where the second conductivity type semiconductor layer is an N-type semiconductor layer. The first conductivity type semiconductor layer may be an N-type semiconductor layer. The second conductivity type semiconductor layer may be a P-type semiconductor layer.

[0018] (First embodiment) <Image sensor 1> FIG. 1 is a block diagram showing a schematic configuration of an image sensor 1. The image sensor 1 is, for example, a back-illuminated image sensor 1. The image sensor 1 may also be a front-illuminated image sensor 1. In a back-illuminated image sensor 1, the surface opposite to the element formation surface of a semiconductor substrate 510 (see FIG. 4, etc.) is the light incident surface. In a front-illuminated image sensor 1, the element formation surface is the light incident surface. For ease of explanation, the following description will be given taking the case where the image sensor 1 is a back-illuminated image sensor 1 as an example.

[0019] The image sensor 1 includes a pixel array 10, a control circuit 20, a drive circuit 30, and an output circuit 40.

[0020] The pixel array 10 includes a plurality of SPAD pixels 11 arranged in a matrix. Each SPAD pixel 11 is connected to a pixel drive line 50 for each column and to an output signal line 60 for each row. The pixel drive lines 50 are connected to output terminals of a drive circuit 30 corresponding to each column. The output signal lines 60 are connected to input terminals of an output circuit 40 corresponding to each row.

[0021] The drive circuit 30 includes a shift register, an address decoder, etc., and drives all of the SPAD pixels 11 in the pixel array 10 simultaneously or column by column. The drive circuit 30 also includes a circuit that applies a quench voltage VQ, which will be described later, to each SPAD pixel 11. When driving each SPAD pixel 11 column by column, the drive circuit 30 may also include a circuit that applies a selection signal voltage VSEL to each SPAD pixel 11 in a selected column. In this case, each SPAD pixel 11 is selected by the selection signal voltage VSEL, a power supply voltage is applied only to the selected SPAD pixel 11, and a detection signal VOUT is output from that SPAD pixel 11.

[0022] The detection signals VOUT output from the respective SPAD pixels 11 are input to the output circuit 40 through the respective output signal lines 60. The output circuit 40 outputs the detection signals VOUT input from the respective SPAD pixels 11 as image signals.

[0023] The control circuit 20 includes a timing generator or the like that generates various timing signals, and controls the drive circuit 30 and the output circuit 40 based on the various timing signals generated by the timing generator.

[0024] <SPAD pixel 11> FIG. 2 is a circuit diagram showing a schematic configuration example of the SPAD pixel 11.

[0025] The SPAD pixel 11 includes a SPAD element 100, a quench resistor 200, and an inverter 300. As will be described later, the SPAD element 100 is formed on a pixel chip 500 (see FIG. 3), and the quench resistor 200 and the inverter 300 can be formed on a logic chip 600. The pixel chip 500 and the logic chip 600 are aligned and joined for each SPAD pixel 11, thereby forming each SPAD pixel 11. In FIG. 2, a connection point where the SPAD element 100 and the quench resistor 200 are connected by the joining of the pixel chip 500 and the logic chip 600 is shown as a node N1. Also, the boundary between the pixel chip 500 and the logic chip 600 is shown by a dashed line.

[0026] The SPAD element 100 is a light-receiving element, and when photons are incident in a state where a reverse bias voltage equal to or higher than the breakdown voltage is applied between the anode and the cathode, an avalanche current is generated. An anode voltage VA is applied to the anode of the SPAD element 100, and a cathode voltage VC is applied to the cathode via the quench resistor 200. The anode voltage VA is set, for example, to -15V to -30V The cathode voltage VC is set, for example, to 3V. The SPAD element 100 operates in Geiger mode when a reverse bias voltage VSPAD equal to or higher than the breakdown voltage is applied, and can detect one photon. The reverse bias voltage VSPAD is the sum of the absolute value of the anode voltage VA and the absolute value of the cathode voltage VC.

[0027] The quench resistor 200 is configured by, for example, a PMOS (Metal Oxide Semiconductor) transistor. The quench resistor 200 operates as a quench resistor when a quench voltage VQ supplied from the drive circuit 30 is applied to the gate of the quench resistor 200. The quench resistor 200 also has a recharge function that returns the voltage supplied to the SPAD element 100 to VC by passing a current equivalent to the voltage drop caused by the quench operation.

[0028] The current flowing through the SPAD element 100 is converted into a voltage by the quench resistor 200 and output to the inverter 300 .

[0029] The inverter 300 is configured by connecting a PMOS transistor 300P and an NMOS transistor 300N in series. The source of the PMOS transistor 300P is connected to the power supply VHV for driving the digital circuit, and the drain is connected to the drain of the NMOS transistor 300N. The drain of the NMOS transistor 300N is connected to the drain of the PMOS transistor 300P, and the source of the NMOS transistor 300N is grounded. The gates of the PMOS transistor 300P and the NMOS transistor 300N are connected to each other, and their connection point serves as the input of the inverter 300. The connection point of the drain of the PMOS transistor 300P and the drain of the NMOS transistor 300N serves as the output of the inverter 300. The input of the inverter 300 is connected to a node N1, which is the connection point between the SPAD element 100 and the quench resistor 200.

[0030] The inverter 300 converts the input voltage into a digital signal and outputs it as a detection signal VOUT. Note that a buffer for impedance conversion may be provided at the output of the inverter 300, so that an impedance-converted detection signal VOUT may be output from each SPAD pixel 11.

[0031] The detection signal VOUT is input to the output circuit 40. The output circuit 40 outputs the detection signal VOUT to a processor (not shown) via, for example, a TDC (Time to Digital Converter) (not shown). Various processes are performed on the detection signal VOUT by the processor.

[0032] <Operation of SPAD Pixel 11> When photons are incident on the SPAD element 100 in a state where a reverse bias voltage VSPAD greater than or equal to the breakdown voltage is applied to the SPAD element 100 via the quench resistor 200, an avalanche current is generated in the SPAD element 100. When the avalanche current flows through the quench resistor 200, the voltage of the node N1 drops. When the voltage of the node N1 becomes lower than the threshold voltage of the PMOS transistor 300P of the inverter 300, the PMOS transistor 300P conducts, and the power supply VHV is output from the inverter 300 as a detection signal at a high level.

[0033] Thereafter, when the voltage of the node N1 continues to drop, the voltage applied to the SPAD element 100 becomes smaller than the breakdown voltage. As a result, the avalanche current stops flowing, and the voltage of the node N1 rises. When the voltage of the node N1 becomes higher than the threshold voltage of the NMOS transistor 300N of the inverter 300, the NMOS transistor 300N conducts, and the ground voltage is output from the inverter 300 as a detection signal at a low level.

[0034] <Stacked Structure of Pixel Array 10> FIG. 3 is a diagram showing the stacked structure of the pixel array 10.

[0035] The SPAD pixels 11 are arranged in an array to form the pixel array 10. The SPAD elements 100 are arranged in an array to form the element array 70. The pixel array 10 has a structure in which the pixel chip 500 and the logic chip 600 are stacked. The pixel chip 500 is a semiconductor chip in which the SPAD elements 100 are formed in an array. The logic chip 600 is a semiconductor chip in which a quench resistor 200 and an inverter 300 are formed at positions corresponding to each SPAD element 100. A control circuit 20, a drive circuit 30, and an output circuit 40 may be further formed in the logic chip 600. A buffer, as described above, for impedance-converting the detection signal VOUT may be formed in the logic chip 600.

[0036] The pixel chip 500 and the logic chip 600 can be joined by an electronic force, for example, by flattening and contacting their respective bonding surfaces. Specifically, the pixel chip 500 and the logic chip 600 can be joined by metal bonding of metal pads (connection pads 521c, connection pads 621a (see FIG. 4)) formed on their respective surfaces (bonding surfaces).

[0037] <Structure of SPAD Element 100> FIG. 4 is a cross-sectional view of a cross-section including the SPAD pixel 11 and the node N1. FIG. 5A is a plan view of the A-A plane in FIG. 4.

[0038] The surface on which the light indicated by the thick arrow in FIG. 4 is incident is also referred to as the light incident surface of the semiconductor substrate 510. The light incident surface constitutes the first surface 150. The surface of the semiconductor substrate 510 opposite to the light incident surface constitutes the second surface 160.

[0039] A plurality of SPAD elements 100 are formed in the semiconductor substrate 510 that constitutes the pixel chip 500. The semiconductor substrate 510 constitutes the substrate. The semiconductor substrate 510 is, for example, a silicon substrate.

[0040] Each SPAD element 100 includes a trench 109 for isolating it from other SPAD elements 100. The trenches 109 of the multiple SPAD elements 100 formed in the semiconductor substrate 510 are connected to each other, forming a lattice shape when viewed in plan from the light incident surface.

[0041] The photoelectric conversion region 104 converts incident light into electricity to generate electron-hole pairs (hereinafter also referred to as "charges"). The photoelectric conversion region 104 is configured as a region doped with impurities at a relatively low concentration. The photoelectric conversion region 104 may also be configured to include an intrinsic semiconductor that is not doped with impurities.

[0042] The P-type semiconductor layer 101 is a layer containing an acceptor and is formed on the sidewall of the trench 109. For example, boron (B) is used as the acceptor. When a reverse bias voltage VSPAD is applied between the anode electrode 102 and the cathode electrode 107 of the SPAD element 100, the P-type semiconductor layer 101 forms an electric field for guiding charges generated in the photoelectric conversion region 104 to the P+ type semiconductor region 105, which forms a PN junction with the N+ type semiconductor region 106. The N+ type semiconductor region 106 constitutes the N-type semiconductor layer of the SPAD element 100. The anode electrode 102 constitutes a first electrode, and the cathode electrode 107 constitutes a second electrode.

[0043] The P+ type semiconductor region 105 is a region containing a relatively high concentration of acceptors. For example, boron (B) is used as the acceptor. The N+ type semiconductor region 106 is a region containing a relatively high concentration of donors. For example, phosphorus (P) or arsenic (As) is used as the donor. The P+ type semiconductor region 105 and the N+ type semiconductor region 106 contact each other to form a PN junction, which functions as an amplification region that accelerates charges that have flowed into the P+ type semiconductor region 105 and generates an avalanche current.

[0044] The cathode electrode 107 is a region containing donors at a higher concentration than the N+ type semiconductor region 106, and is in contact with the N+ type semiconductor region 106. The cathode electrode 107 forms an ohmic junction with a cathode wiring 521b, which is a wiring pattern of a metal layer formed in the wiring layer 520. The portion where the cathode electrode 107 and the cathode wiring 521b contact each other is called a cathode contact 108. The cathode contact 108 constitutes a second contact.

[0045] Inside the trench 109, a first insulating film 103 is formed to cover a part of the P-type semiconductor layer 101.

[0046] An anode electrode 102 is formed inside the trench 109. The anode electrode 102 includes a non-contact portion 102a that is surrounded by the first insulating film 103 and does not contact the P-type semiconductor layer 101, and an anode electrode end portion 102b that contacts the P-type semiconductor layer 101 and forms an anode contact 110. The anode electrode end portion 102b constitutes the end portion of the anode electrode 102. The portion where the anode electrode 102 and the P-type semiconductor layer 101 contact each other is called the anode contact 110. The non-contact portion 102a of the anode electrode 102 may be made of polysilicon. The anode electrode end portion 102b may be made of P-type polysilicon. The anode contact 110 constitutes a first contact.

[0047] The anode contact 110 can be formed closer to the light incident surface than the cathode contact 108. This increases the distance between the anode contact 110 and the cathode contact 108, thereby preventing noise generation.

[0048] Fig. 5A is an example of a plan view of the AA plane in Fig. 4. In the example shown in Fig. 5A, the anode electrode end 102b is formed in the entire region of the trench 109, including the region where the trenches 109 intersect with each other. As a result, the anode contact 110 is formed in the entire region of the trench 109, including the region where the trenches 109 intersect with each other.

[0049] The anode contacts 110 may be formed only in regions of the pixel array 10 where the trenches 109 intersect with each other. FIG. 5B is another example of a plan view of the AA plane in FIG. 4. In the example shown in FIG. 5B, the anode electrode end portions 102b are formed only in regions where the trenches 109 intersect with each other. As a result, the anode contacts 110 are formed only in regions where the trenches 109 intersect with each other. This configuration further increases the distance between the anode contacts 110 and the cathode contacts 108, preventing noise generation; however, the anode contacts 110 may also be formed in regions of the pixel array 10 other than regions where the trenches 109 intersect with each other.

[0050] An anti-reflection film 111 is formed on the light incident surface of the semiconductor substrate 510 to prevent reflection of incident light.

[0051] Color filters (not shown) and on-chip lenses (not shown) corresponding to each SPAD element 100 may be formed on the anti-reflection film 111. The color filters may be any of a color filter that selectively transmits light of a red (R) wavelength component, a color filter that selectively transmits light of a green (G) wavelength component, and a color filter that selectively transmits light of a blue (B) wavelength component, corresponding to each SPAD element 100. Each color filter may be formed to form a Bayer array.

[0052] A wiring layer 520 is formed on the surface of the semiconductor substrate 510 opposite the light incident surface. The wiring layer 520 is configured by laminating a second insulating film 522 and wiring 521. A plurality of layers of wiring 521 may be laminated with the second insulating film 522 interposed therebetween. In this case, adjacent wiring 521 of the same node across the second insulating film 522 are connected to each other by vias formed in the second insulating film 522. The wiring 521 may include an anode wiring 521a for supplying an anode voltage VA to the SPAD element 100 and a cathode wiring 521b for supplying a cathode voltage VC to the SPAD element 100. The anode wiring 521a is connected to the anode electrode 102. The cathode wiring 521b is connected to the cathode electrode 107. The wiring 521 includes a connection pad 521c. The connection pad 521c is exposed on the surface of the wiring layer 520 (the lower surface in FIG. 4).

[0053] The connection pads 521c can be joined by metal bonding to the connection pads 621a exposed on the surface (upper surface in FIG. 4) of the logic chip 600. In this way, the pixel chip 500 and the logic chip 600 can be joined.

[0054] Logic chip 600 may be composed of a substrate and a wiring layer. In this case, elements constituting a logic circuit, including transistors constituting quench resistor 200 and inverter 300, are formed on the substrate. Furthermore, wiring for constituting the logic circuit, including wiring connecting quench resistor 200 and inverter 300, and wiring 621 including connection pads 621a are formed on the wiring layer.

[0055] <Manufacturing method of image sensor 1> A method for manufacturing the image sensor 1 will now be described.

[0056] 6 to 16 are explanatory diagrams for explaining a method for manufacturing the image sensor 1. Figures 6 to 16 correspond to a method for manufacturing the image sensor 1 including the SPAD pixel 11 shown in Figure 5A.

[0057] 6, layers of hard mask materials 700 and 701 are formed on the surface of the semiconductor substrate 510 opposite the light incident surface, and the hard mask materials 700 and 701 are etched by reactive ion etching using a mask in which openings corresponding to the positions of the trenches 109 are formed. Then, the semiconductor substrate 510 is etched by reactive ion etching using the hard mask materials 700 and 701 in which openings corresponding to the positions of the trenches 109 are formed by etching as a mask, thereby forming the trenches 109.

[0058] 7, for example, an acceptor impurity is implanted by plasma doping and activated by heat treatment to form a P-type semiconductor layer 101 on the sidewall of the trench 109. As the acceptor, for example, boron (B) is used. Alternatively, the P-type semiconductor layer 101 may be formed by depositing a material containing boron (for example, a glass material) inside the trench and diffusing the boron in the material into the semiconductor substrate 510 through solid-phase diffusion by heat treatment.

[0059] 8, a first insulating film 103 covering the P-type semiconductor layer 101 is formed inside the trench 109. The first insulating film 103 is formed by depositing SiO2 on the P-type semiconductor layer 101 by, for example, CVD (Chemical Vapor Deposition).

[0060] 9, a non-contact portion 102a of the anode electrode 102 that contacts the first insulating film 103 is formed in a part of the trench 109 with the first insulating film 103 formed therein. The non-contact portion 102a of the anode electrode 102 is formed, for example, by depositing polysilicon in the trench 109 by CVD and then removing a part of the polysilicon by etch-back.

[0061] Next, as shown in FIG. 10, a part of the first insulating film 103 is removed by isotropic etching such as wet etching.

[0062] 11, an anode electrode end 102b is formed by isotropic etching to contact the exposed P-type semiconductor layer 101 and the non-contact portion 102a of the remaining anode electrode 102. The anode electrode end 102b is formed, for example, by depositing polysilicon doped with boron (B), which is an acceptor, inside the trench 109 by CVD, and then removing a portion of the polysilicon by etch-back.

[0063] 12, a first insulating film 103 that covers the P-type semiconductor layer 101 and the anode electrode end portion 102b is formed inside the trench 109. The first insulating film 103 is formed, for example, by depositing SiO2 on the P-type semiconductor layer 101 and the anode electrode end portion 102b by CVD.

[0064] Next, as shown in FIG. 13, the bottom of the first insulating film 103 is removed by etching back, thereby exposing the anode electrode end 102b.

[0065] 14, a non-contact portion 102a of the anode electrode 102 that contacts the first insulating film 103 and the anode electrode end portion 102b is formed in the trench 109. The non-contact portion 102a of the anode electrode 102 is formed, for example, by depositing polysilicon in the trench 109 by CVD and then removing part of the polysilicon by etch-back.

[0066] 15, donor and acceptor ions are appropriately implanted into a predetermined region surrounded by the trench 109 to form a P+ type semiconductor region 105, an N+ type semiconductor region 106, and a cathode electrode 107. Thereafter, a second insulating film 522 and wiring 521 are formed on the surface of the semiconductor substrate 510 opposite the light incident surface, thereby forming a wiring layer 520.

[0067] 16, the pixel chip 500 is bonded to the logic chip 600. Thereafter, the semiconductor substrate 510 is thinned by grinding from the light incident surface side until the first insulating film 103 is exposed. In addition, an anti-reflection film 111 (not shown in FIG. 16) is formed on the light incident surface of the semiconductor substrate 510.

[0068] FIG. 17 is a flowchart showing the main steps in a method for manufacturing the image sensor 1 corresponding to FIGS.

[0069] A lattice-shaped trench 109 is formed to separate a plurality of SPAD elements 100 formed on a silicon substrate, which is a semiconductor substrate 510, from each other (S101).

[0070] Next, a P-type semiconductor layer 101 is formed on the sidewall of the trench 109 (S102).

[0071] Next, the first insulating film 103 that covers the P-type semiconductor layer 101 is formed inside the trench 109 (S103).

[0072] Next, a non-contact portion 102a of the anode electrode 102 that contacts the first insulating film 103 is formed in a part of the trench 109 in which the first insulating film 103 is formed (S104).

[0073] Next, a portion of the first insulating film 103 is removed by isotropic etching (S105).

[0074] Next, a portion of the first insulating film 103 is removed by isotropic etching to form an anode electrode end 102b that contacts the exposed P-type semiconductor layer 101 and the remaining non-contact portion 102a of the anode electrode 102 (S106).

[0075] 18A to 22B are explanatory diagrams for describing a manufacturing method of an image sensor 1 including the SPAD pixel 11 shown in Fig. 5B. The figures ending with A are cross-sectional views of the aa plane in Fig. 5B, and the figures ending with B are cross-sectional views of the bb plane in Fig. 5B. The figures ending with B show trenches 109 in the intersection regions of trenches 109.

[0076] 18A and 18B, a non-contact portion 102a of the anode electrode 102 that contacts the first insulating film 103 is formed in a part of the trench 109 having the first insulating film 103 formed therein. Note that the steps shown in FIGS. 6 to 8 may be performed before the step shown in FIG. 18A. The non-contact portion 102a of the anode electrode 102 is formed, for example, by depositing polysilicon in the trench 109 by CVD and then removing part of the polysilicon by etch-back.

[0077] 19A and 19B, a resist film 702 is formed to cover regions other than the intersection regions of the trenches 109. As a result, as shown in Fig. 19A, the resist film 702 fills the trenches 109 other than the intersection regions of the trenches 109. On the other hand, as shown in Fig. 19B, the resist film 702 does not fill the trenches 109 in the intersection regions of the trenches 109.

[0078] 20B, a portion of the first insulating film 103 is removed by isotropic etching such as wet etching. At this time, as shown in FIG. 20A, the resist film 702 serves as a mask and the first insulating film 103 in the trenches 109 other than the intersection regions of the trenches 109 is not removed by the isotropic etching.

[0079] 21B, anode electrode end 102b is formed by isotropic etching to contact P-type semiconductor layer 101 exposed and non-contact portion 102a of remaining anode electrode 102. Anode electrode end 102b is formed, for example, by depositing polysilicon doped with boron (B), an acceptor, inside trench 109 by CVD, and then removing part of the polysilicon by etch-back. At this time, as shown in FIG. 21A, a layer made of the same material as anode electrode end 102b is formed in trench 109 except for the intersection region of trench 109, in contact with anode electrode 102 and first insulating film 103.

[0080] Next, as shown in FIG. 22B, a first insulating film 103 covering the P-type semiconductor layer 101 and the anode electrode end portion 102b is formed inside the trench 109. The first insulating film 103 is formed, for example, by depositing SiO2 on the P-type semiconductor layer 101 and the anode electrode end portion 102b by CVD. At this time, as shown in FIG. 22A, the first insulating film 103 is also formed inside the trench 109 in areas other than the intersection region of the trench 109. A layer made of the same material as the anode electrode end portion 102b that is in contact with the anode electrode 102 and the first insulating film 103 is not in contact with the P-type semiconductor layer 101 because it is surrounded by the first insulating film 103.

[0081] Next, the steps shown in FIGS. 13 to 16 can be carried out.

[0082] FIG. 23 is a flowchart showing the main steps in a method for manufacturing the image sensor 1 corresponding to FIGS. 18A to 22B.

[0083] A lattice-shaped trench 109 is formed to separate and separate a plurality of SPAD elements 100 formed on a silicon substrate, which is a semiconductor substrate 510 (S101A).

[0084] Next, the P-type semiconductor layer 101 is formed on the sidewall of the trench 109 (S102A).

[0085] Next, the first insulating film 103 that covers the P-type semiconductor layer 101 is formed inside the trench 109 (S103A).

[0086] Next, a non-contact portion 102a of the anode electrode 102 that contacts the first insulating film 103 is formed in a part of the trench 109 in which the first insulating film 103 is formed (S104A).

[0087] Next, a resist film 702 is formed to cover the areas other than the intersection areas of the trenches 109 (S105A).

[0088] Next, a part of the first insulating film 103 inside the trench 109 that is not covered with the resist film 702 is removed by isotropic etching (S106A).

[0089] Next, a portion of the first insulating film 103 is removed by isotropic etching to form an anode electrode end 102b that contacts the exposed P-type semiconductor layer 101 and the remaining non-contact portion 102a of the anode electrode 102 (S107A). As a result, the anode electrode end 102b is formed only in the intersection region of the trenches 109.

[0090] (Variation) FIG. 24 is a cross-sectional view showing the structure of a SPAD pixel 11 according to a modified example.

[0091] As in this modification, the non-contact portion 102a of the anode electrode 102 does not have to be formed on the light incident surface side of the semiconductor substrate 510, closer to the anode electrode end portion 102b.

[0092] (Second embodiment) The second embodiment will be described. The present embodiment differs from the first embodiment in the following respects. In the first embodiment, the anode electrode end 102b is formed at a position that does not contact the light incident surface of the semiconductor substrate 510. On the other hand, in the present embodiment, the anode electrode end 102b is formed at a position that contacts the light incident surface of the semiconductor substrate 510. In other respects, the present embodiment is similar to the first embodiment, and therefore, redundant explanations will be omitted or simplified.

[0093] FIG. 25 is a cross-sectional view showing the structure of the SPAD pixel 11. FIGS. 26 to 31 are explanatory diagrams for explaining the manufacturing method of the image sensor 1.

[0094] <Structure of the SPAD element 100 etc.> As shown in FIG. 25, the anode electrode end 102b is formed at a position in contact with the light incident surface of the semiconductor substrate 510. Thereby, the anode contact 110 is formed at the position of the anode electrode 102 closest to the light incident surface of the semiconductor substrate 510.

[0095] Referring to FIG. 5A, by arranging the SPAD elements 100 in an array, the anode electrodes 102 of the respective SPAD elements 100 forming the element array 70 are formed in a lattice pattern along the lattice-shaped trenches 109 in the element array 70. In the present embodiment, outside the element array 70, it can be connected to the power supply wiring 51 (the power supply wiring for supplying the anode voltage VA) formed outside the pixel array (see FIG. 1). Thereby, the anode voltage VA can be supplied to the anode electrode 102 of the SPAD element 100 without passing through the anode wiring 521a of the wiring layer 520. Therefore, in the wiring layer 520, there is no need to form the anode wiring 521a.

[0096] As shown in FIG. 25, the anode wiring 521a is not formed in the wiring layer 520, and the cathode wiring 521b is expanded to the region where the trenches 109 are formed. That is, when the semiconductor substrate 510 is viewed in plan from the light incident surface of the semiconductor substrate 510, the space between the lattices of the lattice-shaped trenches 109 is covered by the cathode wiring 521b. Thereby, by the cathode wiring 521b functioning as a reflection plate for incident light, the PDE (Photon Detection Efficiency) can be improved.

[0097] <Manufacturing method of the image sensor 1> 26, layers of hard mask materials 700 and 701 are formed on the surface of the semiconductor substrate 510 opposite the light incident surface, and the hard mask materials 700 and 701 are etched by reactive ion etching using a mask in which openings corresponding to the positions of the trenches 109 are formed. Then, the semiconductor substrate 510 is etched by reactive ion etching using the hard mask materials 700 and 701 in which openings corresponding to the positions of the trenches 109 are formed by etching as a mask, thereby forming the trenches 109.

[0098] 27, for example, an acceptor impurity is implanted by plasma doping and activated by heat treatment to form a P-type semiconductor layer 101 on the sidewall of the trench 109. As the acceptor, for example, boron (B) is used. Alternatively, the P-type semiconductor layer 101 may be formed by depositing a material containing boron (for example, a glass material) inside the trench and diffusing the boron in the material into the semiconductor substrate 510 in a solid phase by heat treatment.

[0099] 28, an anode electrode end 102b that contacts the P-type semiconductor layer 101 is formed in a part of the trench 109. The anode electrode end 102b is formed, for example, by depositing polysilicon doped with boron (B), which is an acceptor, inside the trench 109 by CVD, and then removing a part of the polysilicon by etch-back.

[0100] 29, a first insulating film 103 that covers the P-type semiconductor layer 101 and the anode electrode end portion 102b is formed inside the trench 109. The first insulating film 103 is formed, for example, by depositing SiO2 on the P-type semiconductor layer 101 by CVD.

[0101] Next, as shown in FIG. 30, a part of the first insulating film 103 is removed by etching back to expose the anode electrode end 102b.

[0102] 31, a non-contact portion 102a of the anode electrode 102 that contacts the anode electrode end portion 102b exposed by etching back is formed inside the trench 109. The non-contact portion 102a of the anode electrode 102 is formed, for example, by depositing polysilicon in the trench 109 by CVD and then removing part of the polysilicon by etching back.

[0103] The subsequent steps are the same as those in the first embodiment described with reference to FIGS. 15 and 16, and therefore will not be described again.

[0104] FIG. 32 is a flowchart showing the main steps in a method for manufacturing the image sensor 1 corresponding to FIGS.

[0105] A plurality of SPAD elements 100 formed on a silicon substrate, which is a semiconductor substrate 510, are partitioned to form lattice-shaped trenches 109 that separate the elements from one another (S201).

[0106] Next, the P-type semiconductor layer 101 is formed on the sidewall of the trench 109 (S202).

[0107] Next, an anode electrode end portion 102b that contacts the P-type semiconductor layer 101 is formed in a part of the trench 109 (S203). As a result, an anode contact of the SPAD element 100 is formed.

[0108] Next, the first insulating film 103 is formed inside the trench 109 to cover the P-type semiconductor layer 101 and the anode electrode end portion 102b (S204).

[0109] Next, a portion of the first insulating film 103 is removed by etching back (S205).

[0110] Next, the non-contact portion 102a of the anode electrode 102 is formed in contact with the end portion 102b of the anode electrode 102 exposed by etching back the first insulating film 103 (S206).

[0111] (Third embodiment) The third embodiment will be described. The differences between this embodiment and the second embodiment are as follows. In the second embodiment, the non-contact portion 102a of the anode electrode 102 is polysilicon. On the other hand, in this embodiment, at least the non-contact portion 102a of the anode electrode 102 is a metal whose light transmittance detected by the SPAD element 100 is lower than that of polysilicon. In other respects, this embodiment is the same as the second embodiment, so overlapping explanations will be omitted or simplified.

[0112] FIG. 33 is a cross-sectional view showing the structure of the SPAD pixel 11. FIG. 34 is a plan view of the A-A plane in FIG. 33. FIGS. 35 to 38 are explanatory diagrams for explaining the manufacturing method of the image sensor 1.

[0113] <Structure of the SPAD element 100 etc.> As shown in FIGS. 33 and 34, the non-contact portion 102a of the anode electrode 102 is a metal (hereinafter also referred to as "low light transmittance metal") whose light transmittance detected by the SPAD element 100 is lower than that of polysilicon. The low light transmittance metal includes, for example, tungsten (W) and aluminum (Al). The anode electrode end portion 102b is formed at a position in contact with the light incident surface of the semiconductor substrate 510. Thereby, the anode contact 110 is formed at the position of the anode electrode 102 closest to the light incident surface of the semiconductor substrate 510.

[0114] By arranging the SPAD elements 100 in an array, the anode electrodes 102 of the respective SPAD elements 100 forming the element array 70 are formed in a lattice pattern along the lattice-shaped trenches 109 in the element array 70. In this embodiment, outside the element array 70, it can be connected to a power supply wiring (power supply wiring for supplying the anode voltage VA) formed outside the element array 70. Thereby, the anode voltage VA can be supplied to the anode electrode 102 of the SPAD element 100 without passing through the anode wiring 521a of the wiring layer 520. Therefore, there is no need to form the anode wiring 521a in the wiring layer 520.

[0115] 33, the anode wiring 521a is not formed in the wiring layer 520, and the cathode wiring 521b extends to the region where the trench 109 is formed. That is, when the semiconductor substrate 510 is viewed from the light incident surface of the semiconductor substrate 510, the spaces between the lattice of the lattice-shaped trenches 109 are covered with the cathode wiring 521b. This allows the cathode wiring 521b to function as a reflector of incident light, thereby further improving the PDE.

[0116] <Manufacturing method of image sensor 1> In this embodiment, the non-contact portion 102a of the anode electrode 102 is formed of polysilicon by the method described with reference to FIGS. 26 to 31 , and then the P+ type semiconductor region 105, the N+ type semiconductor region 106, and the cathode electrode 107 are formed in the same manner as with the method described with reference to FIGS. 15 and 16 . A second insulating film 522 and wiring 521 are formed on the surface of the semiconductor substrate 510 opposite the light incident surface to form a wiring layer 520. Then, the pixel chip 500 is bonded to the logic chip 600. Thereafter, as described below, the non-contact portion 102a of the anode electrode 102 made of polysilicon, which is formed at least in the trench 109, is replaced with a low light transmittance metal. This forms the non-contact portion 102a of the anode electrode 102 made of a low light transmittance metal.

[0117] 35, a portion of the antireflection film 111 formed on the light incident surface of the semiconductor substrate 510, which corresponds to the trench 109, is removed by etching using a resist mask, thereby opening a portion of the light incident surface side of the trench 109. Reactive ion etching, for example, is used to etch the antireflection film 111.

[0118] 36, the anode electrode 102 (non-contact portion 102a and anode electrode end 102b) is removed by etching while leaving a portion of the anode electrode end 102b that is in contact with the P-type semiconductor layer 101. Reactive ion etching, for example, is used to etch the non-contact portion 102a and anode electrode end 102b of the anode electrode 102. By appropriately adjusting the selectivity in the reactive ion etching, the anode electrode 102 can be removed by etching while leaving a portion of the anode electrode end 102b that is in contact with the P-type semiconductor layer 101.

[0119] 37, the areas in the trench 109 where the non-contact portion 102a of the anode electrode 102 and the anode electrode end portion 102b have been removed by etching are filled with a low light transmittance metal. The low light transmittance metal is filled by, for example, CVD or sputtering. Thereafter, the filled low light transmittance metal is planarized by CMP (Chemical Mechanical Polishing) or the like.

[0120] Next, as shown in FIG. 38, an anti-reflection film 111a is formed to cover the anti-reflection film 111 and the planarized low light transmittance metal.

[0121] FIG. 39 is a flowchart showing the main steps in the method for manufacturing the image sensor 1, corresponding to FIGS.

[0122] A part of the antireflection film 111 formed on the light incident surface of the semiconductor substrate 510, which corresponds to the trench 109, is removed to open a part of the trench 109 on the light incident surface side (S301).

[0123] Next, the anode electrode 102 is removed by etching while leaving a portion of the anode electrode end 102b in contact with the P-type semiconductor layer 101 (S302).

[0124] Next, the portion of the anode electrode 102 in the trench 109 that has been removed by etching is filled with a low light transmittance metal (S303).

[0125] Next, an antireflection film 111 is formed on the substrate 510 and in contact with the low light transmittance metal filled in the trench 109 (S304).

[0126] (Fourth Embodiment) The fourth embodiment will be described. The difference between this embodiment and the third embodiment is as follows. In the third embodiment, the width of the trench 109 is substantially constant in the direction from the light incident surface of the semiconductor substrate 510 toward the opposite surface of the light incident surface, and the thickness of the first insulating film 103 surrounding the anode electrode 102 is also substantially constant in the direction from the light incident surface toward the opposite surface of the light incident surface. On the other hand, in this embodiment, the width of the trench 109 increases in the direction from the light incident surface of the semiconductor substrate 510 toward the opposite surface of the light incident surface, and the thickness of the first insulating film 103 surrounding the anode electrode 102 also becomes thicker in the direction from the light incident surface toward the opposite surface of the light incident surface. In other respects, this embodiment is the same as the second embodiment, so overlapping explanations will be omitted or simplified.

[0127] FIG. 40 is a cross-sectional view showing the structure of the SPAD pixel 11.

[0128] <Structure of the SPAD element 100, etc.> As shown in FIG. 40, the non-contact portion 102a of the anode electrode 102 is a low light transmittance metal. The anode electrode end portion 102b is formed at a position in contact with the light incident surface of the semiconductor substrate 510. Thereby, the anode contact 110 is formed at the position of the anode electrode 102 closest to the light incident surface of the semiconductor substrate 510.

[0129] The SPAD elements 100 are arranged in an array to form an element array 70, and the anode electrodes 102 of the SPAD elements 100 are formed in a lattice pattern along lattice-shaped trenches 109 in the element array 70. In this embodiment, the anode electrodes 102 can be connected to power supply wiring 51 (power supply wiring that supplies anode voltage VA) formed outside the element array 70 (see FIG. 1 ) outside the element array 70. This allows the anode voltage VA to be supplied to the anode electrodes 102 of the SPAD elements 100 without passing through the anode wiring 521a of the wiring layer 520. Therefore, there is no need to form the anode wiring 521a in the wiring layer 520.

[0130] No anode wiring 521a is formed in the wiring layer 520, and the cathode wiring 521b extends to the region where the trench 109 is formed. That is, when the semiconductor substrate 510 is viewed from the light incident surface of the semiconductor substrate 510, the spaces between the lattice of the lattice-shaped trenches 109 are covered with the cathode wiring 521b. This allows the cathode wiring 521b to function as a reflector of incident light, thereby further improving the PDE.

[0131] 40, the width of the surface of trench 109 that contacts the surface opposite the light incident surface is greater than the width of the surface that contacts the light incident surface of semiconductor substrate 510, and the sidewalls are inclined in the direction from the light incident surface to the surface opposite the light incident surface. An angle θ1 of the sidewall of trench 109 with respect to the direction from the light incident surface to the surface opposite the light incident surface constitutes a first angle. An angle θ2 (not shown in FIG. 40 because it is 0 degrees) of the side surface of non-contact portion 102a of anode electrode 102 with respect to the direction from the light incident surface to the surface opposite the light incident surface is smaller than the angle θ1 of the sidewall of trench 109 with respect to the direction from the light incident surface to the surface opposite the light incident surface. An angle θ2 of the sidewall of non-contact portion 102a of anode electrode 102 with respect to the direction from the light incident surface to the surface opposite the light incident surface constitutes a second angle. That is, the width of trench 109 increases in the direction from the light incident surface of semiconductor substrate 510 toward the surface opposite the light incident surface, and the thickness of first insulating film 103 surrounding anode electrode 102 also increases in the direction from the light incident surface toward the surface opposite the light incident surface. This increases the potential gradient from photoelectric conversion region 104 to the multiplication region, that is, strengthens the transfer electric field, improving the transfer speed of charges generated in photoelectric conversion region 104, and alleviating the electric field between the cathode electrode 107 and the portion of anode electrode 102 closest to the cathode electrode 107, thereby more effectively preventing noise.

[0132] (Fifth embodiment) The fifth embodiment will be described. The present embodiment differs from the fourth embodiment in the following respects. In the fourth embodiment, trenches 109 are formed whose width increases in the direction from the light incident surface of the semiconductor substrate 510 toward the surface opposite the light incident surface. On the other hand, in the present embodiment, the trenches 109 are formed by connecting a first trench provided on the light incident surface side of the semiconductor substrate 510 with a second trench provided on the surface opposite the light incident surface. At least a portion of the second trench contacts the N+ type semiconductor region 106 (the N type semiconductor layer of the cathode) of the SPAD element 100. In other respects, this embodiment is similar to the fourth embodiment, and therefore, redundant explanations will be omitted or simplified.

[0133] FIG. 41 is a cross-sectional view showing the structure of the SPAD pixel 11. FIG. 42 is a plan view of the A-A plane in FIG. 41.

[0134] <Structure of SPAD element 100 etc.> As shown in FIG. 41, the non-contact portion 102a of the anode electrode 102 is a metal with low light transmittance. The anode electrode end portion 102b is formed at a position in contact with the light incident surface of the semiconductor substrate 510. Thereby, the anode contact 110 is formed at the position of the anode electrode 102 closest to the light incident surface of the semiconductor substrate 510.

[0135] By arranging the SPAD elements 100 in an array, the anode electrodes 102 of the respective SPAD elements 100 forming the element array 70 are formed in a lattice pattern along the lattice-like trenches 109 in the element array 70. In the present embodiment, outside the element array 70, it can be connected to the power supply wiring 51 (the power supply wiring for supplying the anode voltage VA) formed outside the pixel array (FIG. 1). Thereby, the anode voltage VA can be supplied to the anode electrode 102 of the SPAD element 100 without passing through the anode wiring 521a of the wiring layer 520. Therefore, there is no need to form the anode wiring 521a in the wiring layer 520.

[0136] The anode wiring 521a is not formed in the wiring layer 520, and the cathode wiring 521b is extended to the region where the trenches 109 are formed. That is, when the semiconductor substrate 510 is viewed in plan from the light incident surface of the semiconductor substrate 510, the space between the lattices of the lattice-like trenches 109 is covered by the cathode wiring 521b. Thereby, by the cathode wiring 521b functioning as a reflector for incident light, the PDE can be further improved.

[0137] 41, the trench 109 is formed by connecting a first trench 109a provided on the light incident surface side of the semiconductor substrate 510 to a second trench 109b provided on the surface opposite to the light incident surface. At least a portion of the second trench 109b contacts the N+ type semiconductor region 106 of the SPAD element 100. This reduces the junction capacitance between the N+ type semiconductor region 106 and the P type semiconductor layer including the P+ type semiconductor region 105, thereby suppressing power consumption.

[0138] The width of the surface of the first trench 109a connected to the second trench 109b is greater than the width of the surface in contact with the light incident surface of the semiconductor substrate 510, and the sidewalls are inclined in the direction from the light incident surface toward the surface opposite the light incident surface. An angle θ3 of the sidewall of the first trench 109a with respect to the direction from the light incident surface toward the surface opposite the light incident surface constitutes a first angle. An angle θ4 (not shown in FIG. 41 because it is 0 degrees) of the side surface of the non-contact portion 102a of the anode electrode 102 with respect to the direction from the light incident surface toward the surface opposite the light incident surface is smaller than the angle θ3 of the sidewall of the first trench 109a with respect to the direction from the light incident surface toward the surface opposite the light incident surface. An angle θ4 of the sidewall of the non-contact portion 102a of the anode electrode 102 with respect to the direction from the light incident surface toward the surface opposite the light incident surface constitutes a second angle. That is, the width of first trench 109a increases in the direction from the light incident surface of semiconductor substrate 510 toward the surface opposite the light incident surface, and the thickness of first insulating film 103 surrounding anode electrode 102 also increases in the direction from the light incident surface toward the surface opposite the light incident surface. The width of second trench 109b is greater than the width of first trench 109a.

[0139] The distance from the bottom of the second trench 109b to the surface of the semiconductor substrate 510 opposite to the light incident surface is greater than the distance from the surface of the semiconductor substrate 510 opposite to the light incident surface to the PN junction that forms the multiplication region of the SPAD element 100. This further improves the effect of reducing the capacitance (parasitic capacitance) around the PN junction that forms the multiplication region of the SPAD element 100.

[0140] 42, the area of ​​the N+ type semiconductor region 106 (N type semiconductor layer) when viewed from the light incident surface of the semiconductor substrate 510 to the surface opposite the light incident surface is smaller than the area of ​​the second trench 109b. This further improves the effect of reducing the junction capacitance between the N+ type semiconductor region 106 and the P type semiconductor layer including the P+ type semiconductor region 105.

[0141] FIG. 43 is a flowchart showing the main steps in the method for manufacturing the image sensor 1.

[0142] A plurality of SPAD elements 100 formed on a silicon substrate, which is a semiconductor substrate 510, are partitioned and separated from one another by forming second trenches 109b in a lattice pattern (S401).

[0143] Next, the second trench 109b is filled with the first insulating film 103 (S402).

[0144] Next, a first trench 109a is formed at the bottom of the second trench 109b (S403). Specifically, in step S402, the first insulating film 103 filling the second trench 109b and the first trench 109a penetrating the bottom of the second trench 109b are formed, thereby forming the first trench 109a at the bottom of the second trench 109b.

[0145] Next, the P-type semiconductor layer 101 is formed on the sidewall of the first trench 109a (S404).

[0146] Next, the anode electrode end 102b is formed in part of the first trench 109a so as to contact the P-type semiconductor layer 101 (S405). As a result, the anode contact of the SPAD element 100 is formed.

[0147] Next, the first insulating film 103 is formed inside the first trench 109a to cover the P-type semiconductor layer 101 and the anode electrode end portion 102b (S406).

[0148] Next, a portion of the first insulating film 103 is removed by etching back (S407).

[0149] Next, a non-contact portion 102a of the anode electrode 102 that contacts the exposed anode electrode end portion 102b due to the etch-back of the first insulating film 103 is formed (S408).

[0150] (Sixth Embodiment) The sixth embodiment will be described. The difference between this embodiment and the fifth embodiment is as follows. In the fifth embodiment, the distance from the surface of the semiconductor substrate 510 opposite to the light incident surface at the bottom of the second trench 109b is greater than the distance from the surface of the semiconductor substrate 510 opposite to the light incident surface of the PN junction forming the multiplication region of the SPAD element 100. On the other hand, in this embodiment, the distance from the surface of the semiconductor substrate 510 opposite to the light incident surface at the bottom of the second trench 109b is smaller than the distance from the surface of the semiconductor substrate 510 opposite to the light incident surface of the PN junction forming the multiplication region of the SPAD element 100. In other respects, this embodiment is the same as the fifth embodiment, so overlapping explanations will be omitted or simplified.

[0151] FIG. 44 is a cross-sectional view showing the structure of the SPAD pixel 11.

[0152] <Structure of the SPAD element 100, etc.> As shown in FIG. 44, the trench 109 is formed by connecting a first trench 109a provided on the light incident surface side of the semiconductor substrate 510 and a second trench 109b provided on the side opposite to the light incident surface. And at least a part of the second trench 109b contacts the N+-type semiconductor region 106 of the SPAD element 100. Thereby, the junction capacitance between the N+-type semiconductor region 106 and the P-type semiconductor layer including the P+-type semiconductor region 105 can be reduced, and the power consumption can be suppressed.

[0153] The distance from the surface of the semiconductor substrate 510 opposite to the light incident surface at the bottom of the second trench 109b is smaller than the distance from the surface of the semiconductor substrate 510 opposite to the light incident surface of the PN junction forming the multiplication region of the SPAD element 100. Thereby, by suppressing the electric field concentration at the corner of the second trench 109b due to the formation of the second trench 109b, noise can be effectively suppressed.

[0154] The embodiment has the following advantages.

[0155] An image sensor having a plurality of SPAD elements formed on a substrate, each SPAD element comprising: a trench for isolating it from other SPAD elements; a P-type semiconductor layer formed on the sidewall of the trench; an insulating film formed inside the trench and covering a portion of the P-type semiconductor layer; an anode electrode formed inside the trench and surrounded by the insulating film so as not to contact the P-type semiconductor layer; and an anode electrode end portion that contacts the P-type semiconductor layer and forms an anode contact of the SPAD element. This prevents noise generation and suppresses a decrease in PDE, enabling miniaturization of SPAD pixels.

[0156] In addition, the anode contact is formed closer to the first surface of the substrate, where light detected by the SPAD pixel is incident, than the cathode contact of the SPAD element, thereby increasing the distance between the anode contact and the cathode contact and mitigating the electric field strength, thereby effectively preventing noise generation.

[0157] In addition, the anode electrode end is formed from P-type polysilicon, which allows for easy formation of the anode contact.

[0158] In addition, SPAD elements are arranged in an array to form an element array, and the anode electrode is formed in a lattice pattern along the lattice-shaped trenches within the element array and connected to power supply wiring formed outside the element array. This eliminates the need to form wiring to supply the anode voltage in the wiring layer on the substrate, and the area of ​​the wiring to supply the cathode voltage to the cathode contact can be increased and used as a light reflector, improving the PDE.

[0159] In addition, the end of the anode electrode is in contact with the first surface of the substrate, where the light detected by the SPAD element is incident. This further increases the distance between the anode contact and the cathode contact, further mitigating the electric field strength and more effectively preventing noise generation.

[0160] Furthermore, the anode contact is formed only in the region where the trenches intersect with each other, which further reduces the electric field strength and more effectively prevents noise generation.

[0161] Furthermore, at least the portion of the anode electrode that does not contact the P-type semiconductor layer is made of a metal that has a lower transmittance than polysilicon for light detected by the SPAD element, and is in contact with the first surface 150 of the substrate onto which the light is incident. This reduces crosstalk between the SPAD elements.

[0162] Furthermore, at least the portion of the anode electrode that does not come into contact with the P-type semiconductor layer is made of tungsten, which effectively reduces crosstalk between SPAD elements.

[0163] Furthermore, at least the portion of the anode electrode that does not come into contact with the P-type semiconductor layer is made of aluminum, which reduces crosstalk between SPAD elements.

[0164] Furthermore, the width of the trench's surface in contact with the first surface 150 is greater than the width of the surface in contact with the first surface 150, and the sidewall is inclined at a first angle relative to the direction from the first surface 150 to the second surface 160. The second angle, which is the angle of the side surface of the anode electrode relative to the direction from the first surface 150 to the second surface 160, is made smaller than the first angle. This causes the thickness of the insulating film in the trench to gradually increase from the first surface 150 to the second surface 160. This increases the potential gradient from the photoelectric conversion region 104 to the multiplication region, i.e., strengthens the transfer electric field, thereby improving the transfer speed of charges generated in the photoelectric conversion region 104. Furthermore, the electric field between the cathode electrode 107 and the portion of the anode electrode 102 closest to the cathode electrode 107 is alleviated, thereby more effectively preventing noise.

[0165] The trenches are configured such that a first trench provided on the first surface 150 side of the substrate, on which light detected by the SPAD element is incident, is connected to a second trench provided on the second surface 160 side of the substrate opposite the first surface 150. At least a portion of the second trench is in contact with the N-type semiconductor layer of the cathode of the SPAD element. This can improve the noise reduction effect by alleviating the electric field.

[0166] In addition, the distance from the second surface 160 to the bottom of the second trench is set to be greater than the distance from the second surface 160 to the PN junction that forms the multiplication region of the SPAD element. This further improves the effect of reducing the junction capacitance between the N+ type semiconductor region 106 and the P type semiconductor layer including the P+ type semiconductor region 105, thereby reducing power consumption.

[0167] In addition, the distance from the bottom of the second trench to the second surface 160 is set to be shorter than the distance from the second surface 160 to the PN junction that forms the multiplication region of the SPAD element. This prevents electric field concentration at the corners of the second trench due to the formation of the second trench, thereby effectively suppressing noise.

[0168] In addition, the area of ​​the N-type semiconductor layer when the second surface 160 is viewed in plan is made smaller than the area of ​​the second trench, thereby further improving the effect of reducing the junction capacitance between the N+ type semiconductor region 106 and the P-type semiconductor layer including the P+ type semiconductor region 105, and reducing power consumption.

[0169] The bottom of the trench, which contains the insulating layer and cathode electrode, is then partially opened, and the anode electrode is removed by etching, leaving a portion of the anode electrode edge that contacts the P-type semiconductor layer. The portion of the trench from which the anode electrode was removed is then filled with a metal material that has a lower transmittance than polysilicon for light detected by the SPAD pixel. This minimizes the impact of mask misalignment during the anode electrode replacement process, enabling stable formation of the insulating film.

[0170] The above-described embodiments are merely examples, and those skilled in the art will recognize that various modifications and equivalent embodiments are possible. Therefore, the disclosed embodiments should be considered from an illustrative perspective, not a restrictive one. The scope of the invention is defined in the claims, and all structures within the scope of the claims should be construed as being within the scope of the invention. [Explanation of symbols]

[0171] 1 image sensor, 10 pixel array, 11 SPAD pixels, 20 control circuit, 30 drive circuit, 40 output circuit, 50 pixel drive lines, 60 output signal line, 70 element array, 100 SPAD elements, 101 P-type semiconductor layer, 102 anode electrode, 102a anode electrode (portion not in contact with the P-type semiconductor layer), 102b anode electrode end portion; 103 first insulating film, 104 Photoelectric conversion region, 105 P+ type semiconductor region, 106 N+ type semiconductor region, 107 cathode electrode, 108 cathode contact, 109 Trench, 109a First Trench, 109b Second trench, 110 anode contact, 111 Anti-reflective coating, 150 Page 1, 160 2nd page, 200 quench resistance, 300 inverter, 500 pixel chip, 510 semiconductor substrate, 521 wiring, 521a anode wiring, 521b cathode wiring, 521c connection pad, 522 second insulating film, 600 logic chips, 621 wiring, 621a connection pad, 700 hard mask material, 701 hard mask material, 702 resist film.

Claims

1. a plurality of SPAD elements formed on a substrate; The SPAD element is a trench for isolating the SPAD element from other SPAD elements; a first conductivity type semiconductor layer formed on a sidewall of the trench; an insulating film formed inside the trench and covering a portion of the first conductivity type semiconductor layer; a first electrode formed inside the trench and surrounded by the insulating film so as not to contact the first conductive type semiconductor layer, and a first electrode end portion that contacts the first conductive type semiconductor layer to form a first contact of the SPAD element.

2. 2. The image sensor according to claim 1, wherein the first contact is formed at a position closer to the first surface of the substrate, on which light to be detected by the SPAD element is incident, than the second contact of the SPAD element.

3. The image sensor of claim 1 , wherein the first electrode end is polysilicon of a first conductivity type.

4. The SPAD elements are arranged in an array to form an element array, 2. The image sensor according to claim 1, wherein the first electrode is formed in a lattice pattern along the lattice-shaped trenches in the element array, and is connected outside the element array to a power supply wiring formed outside the element array.

5. The image sensor of claim 1 , wherein the first electrode end is in contact with a first surface of the substrate on which light to be detected by the SPAD element is incident.

6. The image sensor of claim 1 , wherein the first contacts are formed only in areas where the trenches intersect with each other.

7. 2. The image sensor of claim 1, wherein at least a portion of the first electrode that does not contact the first conductivity type semiconductor layer is formed of a metal having a lower transmittance than polysilicon for light detected by the SPAD element, and is in contact with the first surface of the substrate onto which the light is incident.

8. 8. The image sensor according to claim 7, wherein at least a portion of said first electrode that is not in contact with said first conductivity type semiconductor layer is formed of a material mainly containing tungsten.

9. 8. The image sensor according to claim 7, wherein at least a portion of said first electrode that is not in contact with said first conductivity type semiconductor layer is formed of a material mainly containing aluminum.

10. the trench has a surface in contact with the first surface, the surface being larger in width at a surface in contact with a second surface of the substrate opposite to the first surface, and the sidewall is inclined at a first angle with respect to a direction from the first surface toward the second surface; The image sensor of claim 7 , wherein a second angle, which is an angle of the side surface of the first electrode with respect to a direction from the first surface toward the second surface, is smaller than the first angle.

11. 2. The image sensor of claim 1, wherein the trench is formed by connecting a first trench provided on a first surface side of the substrate, on which light to be detected by the SPAD element is incident, and a second trench provided on a second surface side of the substrate opposite the first surface, and at least a portion of the second trench is in contact with a second conductivity type semiconductor layer forming a second electrode of the SPAD element.

12. 12. The image sensor of claim 11, wherein a distance from the second surface to a bottom of the second trench is greater than a distance from the second surface to a junction of the first conductive type semiconductor layer and the second conductive type semiconductor layer that form the multiplication region of the SPAD element.

13. 12. The image sensor of claim 11, wherein a distance from the second surface to a bottom of the second trench is smaller than a distance from the second surface to a junction between the first conductive type semiconductor layer and the second conductive type semiconductor layer that form a multiplication region of the SPAD element.

14. The image sensor according to claim 11 , wherein an area of ​​the second conductive type semiconductor layer in a plan view of the second surface is smaller than an area of ​​the second trench.

15. a step (a1) of forming a lattice-shaped trench for separating and isolating a plurality of SPAD elements formed on a substrate; (b1) forming a first conductive type semiconductor layer on a sidewall of the formed trench; (c1) forming an insulating film covering the formed first conductive type semiconductor layer inside the trench; (d1) forming a first electrode in contact with the insulating film in at least a portion of the trench in which the insulating film is formed; and (e1) forming a first contact of the SPAD element by removing a portion of the insulating film by isotropic etching and forming a first electrode end portion in contact with the exposed first conductive type semiconductor layer and the remaining first electrode.

16. forming a lattice-shaped trench to separate a plurality of SPAD elements formed on the substrate; (b2) forming a first conductive type semiconductor layer on a sidewall of the formed trench; (c2) forming a first contact of the SPAD device by forming a first electrode end portion in contact with the first conductive type semiconductor layer formed in a portion of the trench; forming an insulating film covering the formed first conductive type semiconductor layer and the end of the first electrode inside the trench (d2); (e2) etching back a portion of the insulating film to expose an end of the first electrode; (f2) forming a first electrode in contact with the exposed end of the anode electrode; The method for manufacturing an image sensor comprising the steps of:

17. After the step (f2), a step (g) of opening a portion of the bottom of the trench and removing the first electrode by etching while leaving a portion of an end of the first electrode that is in contact with the first conductive type semiconductor layer; 17. The method of claim 16, further comprising: (h) filling the portion of the trench from which the first electrode is removed with a metal material having a lower transmittance than polysilicon for light detected by the SPAD element.

18. the trenches include a first trench and a second trench; The step (a2) (a21) forming the second trench; (a22) filling the second trench with an insulating film; and (a23) forming the first trench at the bottom of the second trench, The step (b2) forming a first conductive type semiconductor layer on a sidewall of the formed first trench; The step (c2) a first electrode end portion contacting the formed P-type semiconductor layer is formed in a part of the first trench, thereby forming a first contact of the SPAD element; The method for manufacturing the image sensor according to claim 16.

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