Imaging device

Abstract

To reduce the noise of an imaging device.SOLUTION: An imaging device includes a substrate, a photodiode semiconductor layer on the substrate, an upper electrode and a lower electrode having the photodiode semiconductor layer held therebetween, and a light-blocking wire upper than the upper electrode when the substrate is regarded as a lowermost layer. The photodiode semiconductor layer includes a first semiconductor layer, and a second semiconductor between the first semiconductor layer and the lower electrode. The photodiode semiconductor layer includes a concave part excluding the first semiconductor layer in a region covered with the light-blocking wire in a plan view. In a region overlapping with the concave part in the plan view, the upper electrode is excluded. In the region overlapping with the concave part in the plan view, a part of the second semiconductor layer and a part of the lower electrode exist.SELECTED DRAWING: Figure 3B

Description

Technical Field

[0001] This disclosure relates to an imaging device.

Background Art

[0002] For example, in an image sensor equipped with a photodiode having a P-N junction or a P-I-N junction, by holding it in a reverse bias state where a negative voltage is applied to the P side and a positive voltage is applied to the N side, the charges generated from the incident light are effectively drifted. The drifted charges are read out as an electrical signal by a detection circuit. By arranging this image sensor in one dimension or two dimensions, it can be utilized as an imaging device that outputs an image from an optical signal.

[0003] Such an imaging device is used, for example, as a Flat Panel Detector (FPD) of an X-ray sensor. The FPD used in an X-ray sensor is generally classified into a direct conversion type and an indirect conversion type. The direct conversion type FPD uses a photoelectric conversion element that directly converts X-rays into an electrical signal, such as amorphous selenium or CdTe. The indirect conversion type FPD uses a phosphor (scintillator) that converts X-rays into light, for example, visible light or ultraviolet light, on an X-ray detection panel, and a photodiode array that converts the light into an electrical signal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The SNR is used as an index for the sensitivity characteristics of an image sensor or an imaging device using an image sensor. In order to achieve a high SNR, an increase in sensitivity and a reduction in noise are required.

Means for Solving the Problems

[0006] An imaging apparatus according to one aspect of the present disclosure includes a substrate, a photodiode semiconductor layer on the substrate, an upper electrode and a lower electrode sandwiching the photodiode semiconductor layer, and light-shielding wiring above the upper electrode, with the substrate as the lowest layer. The photodiode semiconductor layer includes a first semiconductor layer and a second semiconductor layer between the first semiconductor layer and the lower electrode. The photodiode semiconductor layer includes a recess in a plan view where the first semiconductor layer is removed in a region covered by the light-shielding wiring. The upper electrode is excluded from the region overlapping the recess in the plan view. A portion of the second semiconductor layer and a portion of the lower electrode are present in the region overlapping the recess in the plan view. [Effects of the Invention]

[0007] According to one aspect of this disclosure, noise in the imaging device can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram showing the configuration of the image sensor in the embodiment. [Figure 2] This is a circuit diagram showing the equivalent circuit of the pixels of the image sensor in this embodiment. [Figure 3A] This is a schematic plan view showing the structure including pixels, gate lines, data lines, and bias lines. [Figure 3B] Figure 3A shows a cross-sectional view along the IIIB-IIIB' section. [Figure 3C] This is another plan view schematically showing an example structure including pixels, gate lines, data lines, and bias lines. [Figure 3D] Figure 3C shows a cross-sectional view along the IIID-IIID' cutting line. [Figure 4A] This diagram schematically shows the laminated structure on the insulating substrate during the manufacturing process. [Figure 4B] This diagram schematically shows the laminated structure on the insulating substrate during the manufacturing process. [Figure 4C] This diagram schematically shows the laminated structure on the insulating substrate during the manufacturing process. [Figure 4D] Schematically shows the laminated structure on the insulating substrate in the process of the manufacturing method. [Figure 4E] Schematically shows the laminated structure on the insulating substrate in the process of the manufacturing method. [Figure 4F] Schematically shows the laminated structure on the insulating substrate in the process of the manufacturing method. [Figure 4G] Schematically shows the laminated structure on the insulating substrate in the process of the manufacturing method. [Figure 5A] It is a plan view schematically showing another structural example including pixels, gate lines, data lines, and bias lines. [Figure 5B] Shows a cross-sectional view taken along the cutting line VB-VB' in FIG. 5A. [Figure 6] It is a plan view schematically showing another structural example including pixels, gate lines, data lines, and bias lines. [Figure 7] It is a cross-sectional view of a region including pixels. [Figure 8] It is a cross-sectional view of a region including pixels. [Figure 9A] It is a plan view schematically showing another structural example including pixels, gate lines, data lines, and bias lines. [Figure 9B] Shows a cross-sectional view taken along the cutting line IXB-IXB' in FIG. 9A. [Figure 10A] It is a plan view schematically showing another structural example including pixels, gate lines, data lines, and bias lines. [Figure 10B] Shows a cross-sectional view taken along the cutting line XB-XB' in FIG. 10A. [Figure 11A] It is a plan view schematically showing another structural example including pixels, gate lines, data lines, and bias lines. [Figure 11B] Shows a cross-sectional view taken along the cutting line XIB-XIB' in FIG. 11A. [Figure 12] It is a plan view schematically showing another structural example including pixels, gate lines, data lines, and bias lines.

MODE FOR CARRYING OUT THE INVENTION

[0009] Embodiments of this disclosure will be described in detail below with reference to the drawings. The size and scale of each component in each drawing have been appropriately modified to ensure the visibility of the figures. In addition, the hatching in each drawing is for distinguishing each component and does not necessarily represent a cross-section. Furthermore, the term "transistor" is used for nonlinear elements used as switching elements or amplifying elements, and this includes Thin Film Transistors (TFTs).

[0010] One embodiment of this specification is an image sensor. The image sensor of this disclosure can be used, for example, in imaging devices and is applicable to radiography equipment in the fields of medical and industrial non-destructive testing. The light detected by the image sensor is an electromagnetic wave having any frequency and may include infrared light, visible light, and X-rays.

[0011] For example, in an image sensor equipped with a photodiode having a PN junction or PIN junction, the charge generated from the incident light is generally effectively drifted by maintaining a reverse bias state, where a negative voltage is applied to the P side and a positive voltage to the N side. Since separate potentials must be applied to the P side and N side to maintain a reverse bias, electrodes or wiring are required for each.

[0012] Either the P-side or N-side of the photodiode acts as the window layer into which light is incident. However, during the reverse bias holding period, if it is covered by a wiring layer or other material, the photodiode portion is in shadow and does not contribute to photoelectric conversion.

[0013] The signal-to-noise ratio (SNR) is used as an indicator of the sensitivity characteristics of an image sensor. Achieving a high SNR requires increased sensitivity and reduced noise. A junction capacitance exists between the P-layer and N-layer, proportional to their area. However, maintaining this under reverse bias conditions generates kTC noise proportional to the capacitance, degrading image quality. This junction capacitance and kTC noise are independent of whether or not the area is covered by the wiring layer. Therefore, areas covered by the wiring layer are considered to be more negatively affected by noise than the benefits obtained from the image sensor, compared to other areas.

[0014] One embodiment of this specification partially etches and removes the upper impurity-doped semiconductor layer (e.g., p-aSi layer) in the region where wiring spans a semiconductor layer of a photodiode, for example, consisting of a PN layer or a PIN layer, thereby releasing the junction. The kTC noise is reduced in proportion to the area where the junction is removed, and the image quality is improved. Furthermore, it prevents breaks in the wiring layer that spans the photodiode semiconductor layer, improving the yield.

[0015] kTC noise is proportional to the pixel capacitance, but most of it is due to the junction capacitance of the photodiode. Since junction capacitance is proportional to the area of ​​the opposing P and N layers, removing the upper layer by etching reduces the junction capacitance and thus the kTC noise.

[0016] The electric field generated by the opposing P and N layers causes the charge generated by light to drift; therefore, etching in the light-receiving region impairs the image sensor's original function. To achieve this, the reduction in photoelectric conversion efficiency is suppressed by releasing the junction in the region covered and shaded by the wiring.

[0017] Furthermore, because photodiodes effectively absorb light, they are generally deposited in thick films. However, this creates a significant step difference between the upper and lower layers, which can easily cause discontinuities in the wiring. By partially removing only the upper layer of the photodiode semiconductor layer, steps are formed for the wiring, reducing the drop at the step. This improves the coverage of the step and reduces the frequency of discontinuities.

[0018] A typical material used for the photodiode semiconductor layer is amorphous silicon. The features of this embodiment can also be applied to photodiodes using semiconductor materials other than amorphous silicon.

[0019] In this specification, a photodiode semiconductor layer consisting of a PN layer or a PIN layer is described as one embodiment. However, the photodiode semiconductor layer can also be a Schottky photodiode semiconductor layer that can be expressed as, for example, a PI layer or an IN layer, or an avalanche photodiode semiconductor layer formed by stacking four or more P, I, or N layers.

[0020] <Embodiment 1> [Image sensor configuration] Figure 1 is a block diagram showing an example configuration of an image sensor, which is an imaging device according to one embodiment of this specification. The image sensor 10 includes a sensor substrate 11 and a control circuit. The control circuit includes a drive circuit 14, a signal detection circuit 16, and a main control circuit 18.

[0021] The sensor substrate 11 includes an insulating substrate (for example, a glass substrate) and a detection region 12 on the insulating substrate in which pixels 13 are arranged in a vertical and horizontal matrix. Each pixel 13 is a substrate element that includes a photodiode, which is a photodetector. Note that the layout of the pixels 13 is not limited to the matrix layout shown in Figure 1; for example, a line layout consisting of a row of pixels 13 may also be used. In the example of an X-ray image sensor, a scintillator that emits fluorescence when it receives radiation, which is the detection light, is placed in the detection region 12.

[0022] Pixel 13 is located at each intersection of multiple data lines 106 extending vertically and arranged horizontally in Figure 1, and multiple gate lines (scan lines) 105 extending horizontally and arranged vertically. Each pixel 13 is connected to a bias line 107 extending vertically and arranged horizontally in Figure 1. In Figure 1, only one pixel, one data line, one gate line, and one bias line are indicated by the reference numerals 13, 106, 105, and 107, respectively.

[0023] Each data line 106 is connected to a different pixel row. Each gate line 105 is connected to a different pixel row. The data lines 106 are connected to the signal detection circuit 16, and the gate lines are connected to the drive circuit 14. The bias line 107 is connected to the common bias line 108. A bias potential is applied to the pad 109 of the common bias line 108. The drive circuit 14 drives the gate lines 105 of the pixels 13 for light detection by the pixels 13. The signal detection circuit 16 detects the signals from each data line. The main control circuit 18 controls the drive circuit 14 and the signal detection circuit 16.

[0024] [Pixel circuit configuration] Figure 2 is a circuit diagram showing the equivalent circuit of a single pixel 13. Pixel 13 includes a photodiode 121, which is a photoelectric conversion element, and a thin-film transistor (TFT) 122, which is a switching element. The gate terminal of the thin-film transistor 122 is connected to the gate line 105, the drain terminal is connected to the data line 106, and the source terminal is connected to the cathode terminal of the photodiode 121. In the example in Figure 2, the anode terminal of the photodiode 121 is connected to the bias line 107.

[0025] The thin-film transistor 122 is, for example, an oxide semiconductor thin-film transistor. Examples of oxide semiconductors are IGZO (InGaZnO) and ZnO. In one embodiment of this specification, the conductivity type of the thin-film transistor 122 is N-type.

[0026] Pixel 13 further includes a junction capacitance (not shown) of the photodiode 121. Circuit-wise, the junction capacitance is connected in parallel with the photodiode 121 to the thin-film transistor 122 and the bias line 107. The image sensor 10, used as an X-ray imaging device, stores a signal charge corresponding to the amount of light irradiated onto the photodiode 121 in the capacitance component of pixel 13.

[0027] The main control circuit 18 reads out the signal by making the thin-film transistor 122 located in the pixel 13 conduct, thereby extracting the charge accumulated in the capacitive component of the pixel 13 to the outside. Specifically, the drive circuit 14 sequentially selects the gate line 105 and applies pulses that make the thin-film transistor 122 conduct. The anode terminal of the photodiode 121 is connected to the bias line 107, and a reference potential is applied to the data line 106 by the signal detection circuit 16. Therefore, the photodiode 121 is charged with the difference voltage between the bias potential of the bias line 107 and the reference potential. Generally, this difference voltage is set to a reverse bias voltage in which the cathode potential is higher than the anode potential.

[0028] The charge required to recharge the photodiode 121 to this reverse bias voltage depends on the amount of light irradiated onto the photodiode 121. The signal detection circuit 16 reads out the signal charge by integrating the current that flows when the photodiode 121 is recharged to the reverse bias.

[0029] In reading the signal charge, the voltage at the terminal connected to the data line 106 of the thin-film transistor 122 is greater than or equal to the voltage at the terminal connected to the photodiode 121. In detecting the signal charge, the terminal connected to the data line 106 of the thin-film transistor 122 is the drain, and the terminal connected to the photodiode 121 is the source. Note that the pixel 13 may include additional components not shown in Figure 2, such as additional thin-film transistors.

[0030] [Example of pixel structure] Below, several examples of the device structure of pixel 13 are described. Figure 3A is a schematic plan view showing an example structure including pixel 13, gate line 105, data line 106, and bias line 107. In Figure 3A, the data line 106 extends in the vertical direction (Y direction), and the gate line 105 extends in the horizontal direction (X direction), with a thin-film transistor 122 positioned at their intersection.

[0031] Pixel 13 includes a lower electrode 301 and an upper electrode 305. In the configuration example shown in Figure 3A, the entire area of ​​the upper electrode 305 overlaps with the lower electrode 301 in a plan view (viewed in the stacking direction). In other words, in a plan view, the entire area of ​​the upper electrode 305 is included within the area of ​​the lower electrode 301.

[0032] The photodiode 121 includes a photodiode semiconductor layer, for example, a PN layer or a PIN layer, and an upper electrode and a lower electrode sandwiching it. In the example configuration shown in Figure 3A, the outer diameter of the upper electrode 305 and the amorphous silicon layer of the photodiode 121 may be the same in a plan view, or the outer shapes of the upper electrode 305 and the semiconductor layer may not be the same in a plan view; for example, the area of ​​the upper electrode 305 may be small. The portion of the lower electrode 301 that contacts the photodiode semiconductor layer constitutes the lower electrode of the photodiode 121.

[0033] Pixel 13 includes a thin-film transistor 122 and a bias line 107. The thin-film transistor 122 includes a gate electrode 251, an island-shaped semiconductor portion 252, a source electrode 253, and a drain electrode 254.

[0034] The bias line 107 extends in the vertical direction (Y direction) in Figure 3A. The bias line 107 is above the upper electrode 305 and is connected to each of the upper electrodes 305 of multiple pixels 13 via the contact portion 323. The bias line 107 passes over the upper electrode 305 from one end to the other. The bias line 107 transmits a bias potential and applies a bias potential to the upper electrode 305 of the photodiode 121.

[0035] In the example configuration shown in Figure 3A, the lower electrode 301 and the upper electrode 305 are spaced apart from the gate line 105 and the data line 106 in a plan view, without overlapping them. The lower electrode 301 and the upper electrode 305 are also spaced apart from the semiconductor portion 252 in a plan view, without overlapping them. Note that Figure 3A shows an example of a pixel structure, and the pixel 13 may have other structures.

[0036] Figure 3B shows a cross-sectional view along the IIIB-IIIB' line in Figure 3A. Note that in the following drawings, the reference numerals of some elements may be omitted. Referring to Figure 3B, the thin-film transistor 122 includes a gate electrode 251 formed on an insulating substrate 271, a gate insulating layer 272 on the gate electrode 251, and a semiconductor portion 252 on the gate insulating layer 272. The relationship between the two layers is such that the layer closer to the substrate 271 is called the lower layer, and the layer further from the substrate 271 is called the upper layer.

[0037] As shown in Figure 3A, the gate electrode 251 protrudes upward from the gate wire 105 which extends laterally (in the X direction). The gate electrode 251 and the gate wire 105 are formed on an insulating substrate (insulating layer) 271 and are contained within the same conductor layer. A silicon insulating layer may be present between the insulating substrate 271 and the gate electrode 251 and gate wire 105.

[0038] Continuous or separated conductive portions within the same conductive layer are made of the same material, on the same insulating layer, and in direct contact with the insulating layer. In manufacturing, conductive portions within the same conductive layer are formed in the same process. The conductive layer may have a single-layer structure or a laminated structure.

[0039] In this configuration example, the thin-film transistor 122 has a bottom gate structure, and the gate electrode 251 is located below the semiconductor portion 252. The thin-film transistor 122 further includes a source electrode 253 and a drain electrode 254 on the gate insulating layer 272. The source electrode 253 and the drain electrode 254 are contained within the same conductive layer. Note that the thin-film transistor may also have a top gate structure.

[0040] Depending on the carrier flow in the detection of charge in the photodiode 121, electrode 253 becomes the source electrode and electrode 254 becomes the drain electrode. The source electrode 253 and drain electrode 254 each overlap with the semiconductor portion 252 of the conductive film in a plan view. The source electrode 253 and drain electrode 254 each directly contact the semiconductor portion 252. The source electrode 253 and drain electrode 254 are formed so as to be in contact with the side surface and part of the top surface of the island-shaped semiconductor portion 252.

[0041] The gate insulating layer 272 is formed to cover the entire surface of the gate electrode 251. The gate insulating layer 272 is formed between the gate electrode 251 and the semiconductor portion 252. The first interlayer insulating layer 273 covers the entire thin-film transistor 122. Specifically, the first interlayer insulating layer 273 covers the upper surface of the semiconductor portion 252, and the upper surfaces of the source electrode 253 and the drain electrode 254.

[0042] The substrate 271 is formed of, for example, glass or resin. The gate electrode 251 is a conductor and can be formed of a metal such as Al, Mo, Cr, Ti, Cu, an alloy thereof, or a laminate thereof. The gate insulating layer 272 may be formed of an insulating material described as SiNxOy (where x and y are 0), or an insulating material such as Al2O3, or a laminate thereof.

[0043] The semiconductor constituting the semiconductor section 252 is, for example, an oxide semiconductor. The oxide semiconductor includes, for example, at least one of In, Ga, and Zn, and examples include amorphous InGaZnO (α-InGaZnO) and microcrystalline InGaZnO. The semiconductor may also be, for example, amorphous silicon or polysilicon.

[0044] The source electrode 253 and the drain electrode 254 are conductors and can be formed from metals such as Al, Mo, Cr, Ti, Cu, alloys thereof, or laminates thereof. The first interlayer insulating layer 273 is an inorganic or organic insulator. The first interlayer insulating layer 273 may be composed of an insulating material represented by SiNxOy (where x and y are 0), or an insulating material such as Al2O3, or a laminate thereof.

[0045] The lower electrode 301 is connected to a conductive film including the source electrode 253 of the thin-film transistor 122 via a contact portion 227 in a via hole in the first interlayer insulating layer 273. The lower electrode 301 is a conductor and can be formed from, for example, a metal such as Al, Mo, Cr, Ti, Cu, an alloy thereof, or a laminate thereof.

[0046] The photodiode 121 consists of a photoelectric conversion section between the lower electrode 301 and the upper electrode 305, and the portions of the lower electrode 301 and upper electrode 305 that are in contact with the photoelectric conversion section. The example of the photodiode 121 shown in Figure 3B is a PIN diode. The PIN diode can efficiently detect light by forming a wide depletion layer in the film thickness direction. The upper electrode 305 is an electrode that is transparent to light from the scintillator, and is, for example, ITO.

[0047] The photoelectric conversion section of the photodiode 121 includes an N-type amorphous silicon layer (film) 202 (second semiconductor layer) on the lower electrode 301, an intrinsic amorphous silicon layer (film) 203 (second or third semiconductor layer) on the N-type amorphous silicon layer 202, and a P-type amorphous silicon layer (film) 204 (first semiconductor layer) on the intrinsic amorphous silicon layer 203. In this example, the photodiode semiconductor layer is composed of three stacked semiconductor layers 202, 203, and 204. The N-type amorphous silicon layer and the P-type amorphous silicon layer are examples of impurity-doped semiconductor layers. Note that the positions of the N-type amorphous silicon layer 202 and the P-type amorphous silicon layer 204 may be reversed.

[0048] The N-type amorphous silicon layer 202 is composed of, for example, phosphorus-doped hydrogenated amorphous silicon. The P-type amorphous silicon layer 204 is composed of, for example, boron-doped hydrogenated amorphous silicon. The N-type amorphous silicon layer and the P-type amorphous silicon layer are sometimes simply referred to as the N layer and the P layer.

[0049] In this configuration example, the N-type amorphous silicon layer 202 is in direct contact with the lower electrode 301. The upper electrode 305 is formed on the P-type amorphous silicon layer 204. In this configuration example, the upper electrode 3 05 is in direct contact with the P-type amorphous silicon layer 204. The light to be detected is incident on the photodiode 121 from the upper electrode 305 side. Note that the positions of the N-type amorphous silicon layer 202 and the P-type amorphous silicon layer 204 may be reversed, and the intrinsic amorphous silicon layer 203 may be omitted.

[0050] The second interlayer insulating layer 275 is formed to cover the lower electrode 301, the silicon layers 202-204, and the upper electrode 305. The second interlayer insulating layer 275 is an inorganic or organic insulator. The second interlayer insulating layer 275 can be formed from, for example, SiNxOy (where x and y are 0), or from an acrylic resin, phenolic resin, or epoxy resin, or from a laminate thereof.

[0051] A bias line 107 and a data line 106 are formed on the second interlayer insulating layer 275. In this example, the bias line 107 and the data line 106 are in direct contact with the second interlayer insulating layer 275. The data line 106 is connected to a conductive film including the drain electrode 254 of the thin-film transistor 122 via contact portions 228 in via holes of the second interlayer insulating layer 275 and the first interlayer insulating layer 273.

[0052] The bias wire 107 is connected to the upper electrode 305 by a contact portion 323 formed in a via hole in the second interlayer insulating layer 275. The bias wire 107 and data wire 106 are conductors and can be formed from metals such as Al, Mo, Cr, Ti, Cu, alloys thereof, or laminates thereof. The bias wire 107 is light-shielding (opaque) to the light that the photodiode 121 performs photoelectric conversion on. The data wire 106 may be formed from a transparent material such as ITO. The light-shielding metallic material includes a variety of materials with desirable properties, broadening the range of designs.

[0053] A passivation layer 276 is formed to cover the data line 106, the bias line 107, and the second interlayer insulating layer 275. The passivation layer 276 covers the entire detection region 12. The passivation layer 276 is an inorganic or organic insulator. The passivation layer 276 can be formed from, for example, SiNxOy (where x and y are 0), or from an acrylic resin, phenolic resin, or epoxy resin, or from a laminate thereof. A scintillator (not shown) is placed on the passivation layer 276.

[0054] A scintillator (not shown) covers the entire detection area 12. The scintillator emits light when excited by radiation. Specifically, the scintillator converts incident X-rays into light of a wavelength that the photodiode 121 can detect. The photodiode 121 generates a signal charge in response to the light from the scintillator and accumulates it in the capacitive component of the pixel 13.

[0055] In one embodiment of this specification, a recess 210A is formed in the upper portion of the photodiode semiconductor layer. In the recess 210A, a portion of the P-type amorphous silicon layer 204 is removed in a plan view. In the example of Figure 3B, a portion of the intrinsic amorphous silicon layer 203 is also removed in the stacking direction. The intrinsic amorphous silicon layer 203 does not necessarily have to be removed. In a plan view, the upper electrode 305 is excluded from the region overlapping with the recess 210A and does not exist. In other words, the recess 210A is formed outside the area covered by the upper electrode 305.

[0056] In the recess 210A, in the stacking direction, the entire upper electrode 305 and the entire P-type amorphous silicon layer 204 are removed, and a portion of the intrinsic amorphous silicon layer 203 is removed. The recess 210A extends along the longitudinal direction (Y direction) of the bias line 107 and has two inner surfaces that face each other in the short direction.

[0057] The inner surface is composed of a lamination of the side surface of the upper electrode 305, the side surface of the P-type amorphous silicon layer 204, and the inner surface of the recess of the intrinsic amorphous silicon layer 203. The bottom surface of the recess 210A is composed of a part of the top surface of the intrinsic amorphous silicon layer 203. By forming a recess in the intrinsic amorphous silicon layer 203, the P-type amorphous silicon layer 204 can be reliably removed.

[0058] In other words, within the recess 210A, the side surface of the upper electrode 305 and the side surface of the P-type amorphous silicon layer 204 are exposed. Also, the inner surface of the recess of the intrinsic amorphous silicon layer 203 and a portion of the upper surface of the intrinsic amorphous silicon layer 203 (the bottom surface of the recess) are exposed. The recess 210A is filled with the second interlayer insulating layer 275.

[0059] At least a portion of the recess 210A is covered by the bias line 107 in a plan view. In the example shown in Figure 3B, the left and right ends of the bias line 107 coincide with the left and right ends (left and right inner walls) of the recess 210A. The width of the recess 210A, i.e., its lateral size in Figure 3B, may be smaller or larger than the width of the bias line 107. Also, in a plan view, only one of the left and right ends of the recess 210A and the bias line 107 may coincide, while the other is offset. In a plan view, both left and right ends of the bias line 107 may be located inside the recess 210A, or both or only one may be located outside the recess 210A.

[0060] In the example shown in Figure 3B, the upper doped silicon layer (P-type amorphous silicon layer 204 in Figure 3B) is partially removed in the region covered by the bias line 107 of the thick amorphous silicon layer (photodiode semiconductor layer) consisting of PIN layers. Most of the kTC noise is due to the junction capacitance of the photodiode 121. Since the junction capacitance is proportional to the area of ​​the opposing P-layer and N-layer, removing the layer located on the upper side reduces the junction capacitance and thus reduces the kTC noise.

[0061] At least part or all of the recess 210A is formed in the layer below the opaque bias line 107 and is covered by the bias line 107. Therefore, the decrease in photoelectric conversion efficiency due to the formation of the recess 210A can be suppressed. In the example shown in Figure 3B, a part of the intrinsic amorphous silicon layer 203 is left in the stacking direction, and its upper surface forms the bottom surface of the recess 210A. This makes the recess 210A shallower compared to a configuration in which all of the intrinsic amorphous silicon layer 203, and even the underlying N-type amorphous silicon layer 202, are removed. A shallow recess 210A reduces the possibility of undesirable effects on the shape of the bias line 107, such as breakage, which can occur due to a large drop in the bias line caused by a deep recess.

[0062] Figure 3C is another plan view schematically showing an example structure including pixel 13, gate line 105, data line 106, and bias line 107. In Figure 3C, only the outline of the bias line 107 is shown with a dashed line, and the recesses 210A and 210B below the bias line 107 and the intrinsic amorphous silicon layer 203 are depicted as being transparent to the bias line 107. The other parts are the same as in Figure 3A.

[0063] In Figure 3C, there are two recesses 210A and 210B flanking the contact portion 323. One of the recesses 210 may be omitted. As explained with reference to Figure 3B, the P-type amorphous silicon layer 204 is removed in the recesses 210A and 210B, exposing the intrinsic amorphous silicon layer 203.

[0064] Each of the recesses 210A and 210B extends in the Y direction in Figure 3C so as to overlap with the bias line 107. In this example, the width (size in the X direction) of recesses 210A and 210B coincides with the width of the bias line 107, and their ends coincide in a plan view. The Y-direction end of recess 210B (upper end in Figure 3C) coincides with the edge 215B of the photodiode semiconductor layer. The Y-direction end of recess 210A (lower end in Figure 3C) coincides with the upper electrode 305 and the edge 215A of the photodiode semiconductor layer of photodiode 121.

[0065] Thus, in a plan view, the bias line 107 crosses one end of the N-type amorphous silicon layer 202 (the upper side in Figure 3C) and the recess 210 B A portion of it overlaps with its edge in a plan view. Also, the bias line 107 crosses the other edge of the N-type amorphous silicon layer 202 (the lower side in Figure 3C) in a plan view, and the recess 210 A A portion of it overlaps with its edge in a plan view.

[0066] Figure 3D shows a cross-sectional view along the IIID-IIID' cutting line in Figure 3C. The bias line 107 is connected to the upper electrode 305 via the contact portion 323. The two recesses 210A and 210B reach the edges of the photodiode semiconductor layer, i.e., the edges 215A and 215B of the remaining N-type amorphous silicon layer 202 and intrinsic amorphous silicon layer 203, respectively. In Figure 3D, the upper parts of the left and right edges 215A and 215B of the photodiode semiconductor layer are partially removed, and the left and right edges 215A and 215B are located within the recesses 210A and 210B.

[0067] In Figure 3D, the thickness of the photodiode 121 in the area where recesses 210A and 210B are formed, that is, the thickness D2 at the edge of the photodiode semiconductor layer, is smaller than the thickness D1 near the contact area 323 where recesses 210A and 210B are not formed and the P-type amorphous silicon layer 204 remains.

[0068] The photodiode semiconductor layer is deposited thickly to effectively absorb light. As a result, at the edge of the photodiode semiconductor layer, the step height on the underside of the bias line 107 spanning the photodiode semiconductor layer becomes high. This makes the bias line 107 prone to step breaks. By partially removing only the upper side of the photodiode semiconductor layer to form recesses 210A and 210B, a step is formed for the bias line 107, reducing the step height at the edge of the photodiode semiconductor layer. This improves step coverage and reduces the frequency of step breaks in the bias line 107.

[0069] Depending on the design, the intrinsic amorphous silicon layer may be completely removed in the stacking direction within the recesses of the photodiode semiconductor layer.

[0070] [Manufacturing method example] An example of a manufacturing method for the sensor substrate 11 (pixel 13) is described below. Figures 4A to 4G schematically show the laminated structure on the insulating substrate 271 in different steps of the manufacturing method. Referring to Figure 4A, the manufacturing method involves forming a gate electrode 251 (including a gate line not shown in Figure 4A) on the insulating substrate 271 by, for example, sputtering and etching, and then forming a gate insulating layer 272 so as to cover the gate electrode 251 of the insulating substrate 271 by, for example, CVD (Chemical Vapor Deposition). Next, the semiconductor portion 252 is formed by, for example, sputtering or CVD and etching, and then the source electrode 253 and drain electrode 254 are formed by, for example, sputtering and etching.

[0071] Referring to Figure 4B, the manufacturing method involves forming a first interlayer insulating layer 273 over the TFT, for example by CVD, and then forming contact holes by etching. Next, a metal layer 401 including the lower electrode 301 is formed, for example by sputtering. The contact portion 227 fills the holes in the first interlayer insulating layer 273 and makes direct contact with the source electrode 253.

[0072] Referring to Figure 4C, the manufacturing method involves stacking an N-type amorphous silicon layer 402, an intrinsic amorphous silicon layer 403, and a P-type amorphous silicon layer 404. The N-type amorphous silicon layer 402 is formed, for example, by forming an amorphous silicon layer by CVD and then doping it with phosphorus. The P-type amorphous silicon layer 404 is formed, for example, by forming an amorphous silicon layer by CVD and then doping it with boron. Parts of these amorphous silicon layers 402, 403, and 404 are included in the photodiode 121.

[0073] Next, the manufacturing method involves forming the upper electrode 305 on the P-type amorphous silicon layer 404, for example, by sputtering and etching. In order to form the recesses 210A and 210B of the photodiode 121, the upper electrode 305 has openings in the etched-off portions.

[0074] Referring to Figure 4D, the manufacturing method involves using the upper electrode 305 as a mask to remove a portion of the P-type amorphous silicon layer 404 and a portion of the intrinsic amorphous silicon layer 403 by etching. Alternatively, a photoresist (not shown) patterned on the upper layer of the upper electrode 305 may be used as a mask. The removed portion of the P-type amorphous silicon layer 404 is completely removed in the stacking direction. The removed portion of the intrinsic amorphous silicon layer 403 is only a portion in the stacking direction. In the example shown in Figure 4D, the width of the upper electrode 305 matches the width of the remaining inner surface of the P-type amorphous silicon layer 404 and the intrinsic amorphous silicon layer 403, but the widths do not have to match.

[0075] Referring to Figure 4E, the manufacturing method involves removing unnecessary portions of the intrinsic amorphous silicon layer 403, the N-type amorphous silicon layer 402, and the metal layer 401 by etching using photolithography to form the amorphous silicon layers 202, 203, and 204 of the lower electrode 301 and the photodiode 121.

[0076] Referring to Figure 4F, the manufacturing method involves forming a second interlayer insulating layer 275 by CVD, for example, to cover the photodiode 121 and the first interlayer insulating layer 273. Referring to Figure 4G, the manufacturing method involves forming contact holes in the second interlayer insulating layer 275 by etching, and then forming a bias line 107 and a data line 106 by sputtering and etching, for example. The data line 106 is connected to the drain electrode 254 via a contact portion 228. The bias line 107 is connected to the upper electrode 305 via a contact portion 323 (not shown in Figure 4G). Next, the manufacturing method involves forming a passivation layer 276 by CVD, for example, to cover the entire detection region 12.

[0077] <Embodiment 2> Other structural examples of the detection region 12 will be described. Figure 5A is a schematic plan view showing another structural example including the pixel 13, gate line 105, data line 106, and bias line 107. In Figure 5A, only the outline of the bias line 107 is shown with a dashed line, and the recesses 210C and 210D below the bias line 107, and the intrinsic amorphous silicon layer 203 are depicted as being transparent to the bias line 107. The differences from the configuration described below with reference to Figures 3A to 3D will be mainly explained.

[0078] The position of the bias line 107 in the structural example shown in Figure 5A is different from the position shown in Figure 3A. In the structural example shown in Figure 5A, the bias line 107 extends in the Y direction along the right end 216 of the photodiode (semiconductor layer) 121, covering the right end 216. Two recesses 210C and 210D, which sandwich the contact portion 323 in the Y direction, are formed on the lower side of the bias line 107. Note that one of the recesses 210C and 210D may be omitted. In a plan view, the upper electrode 305 is excluded from the region overlapping with the recesses 210C and 210D and does not exist. The recesses 210C and 210D are formed outside the area covered by the upper electrode 305.

[0079] One end of the recess 210C in the longitudinal direction (Y direction) coincides with the edge 215A of the photodiode semiconductor layer, and one end in the short direction (X direction) coincides with the edge 216 of the photodiode semiconductor layer. Thus, in a plan view, a portion of the recess 210C overlaps with the edge 215A of the photodiode semiconductor layer, and the other portion overlaps with the edge 216.

[0080] One end of the recess 210D in the longitudinal direction (Y direction) coincides with the edge 215B of the photodiode semiconductor layer, and one end in the short direction (X direction) coincides with the edge 216 of the photodiode semiconductor layer. In a plan view, a portion of the recess 210D overlaps with the edge 215B of the photodiode semiconductor layer, and another portion overlaps with the edge 216.

[0081] As described above, the edge of the photodiode semiconductor layer is composed of a stack of the remaining N-type amorphous silicon layer 202 and the intrinsic amorphous silicon layer 203. The recesses 210C and 210D have, for example, the same width and depth.

[0082] Figure 5B shows a cross-sectional view along the VB-VB' cutting line in Figure 5A. The recess 210C reaches the edge of the photodiode semiconductor layer in the photodiode 121. In Figure 5B, the upper right end of the photodiode 121 is partially removed to form the recess 210C.

[0083] The recess 210C extends along the longitudinal direction of the bias line 107 and has an inner surface on only one side in the short direction. The inner surface is composed of a stack of the side surface of the upper electrode 305, the side surface of the P-type amorphous silicon layer 204, and the inner surface of the recess of the intrinsic amorphous silicon layer 203. The side opposite the inner surface of the recess 210C is open.

[0084] The recesses 210C are formed by removing the right end of the photodiode 121 and its vicinity. As a result, the height of the right end of the photodiode 121 is lower than that of other parts. The recesses 210C are filled with the second interlayer insulating layer 275. The explanation of recess 210C with reference to Figure 5B can also be applied to recess 210D.

[0085] At least part or all of the recesses 210C and 210D are formed on the lower side of the opaque bias line 107 and are covered by the bias line 107. Therefore, the decrease in photoelectric conversion efficiency caused by forming the recesses 210C and 210D can be suppressed.

[0086] As shown in Figure 5B, one inner wall of recesses 210C and 210D is absent, and one end in the shorter direction is open. Furthermore, the height of the edge (side wall) 216 of the photodiode semiconductor layer in which recesses 210C and 210D are formed is lower due to recesses 210C and 210D.

[0087] In this way, by forming recesses along the edges of the photodiode semiconductor layer, the area of ​​the photodiode sidewall that is damaged by etching is reduced. This suppresses the generation of photodiode defect levels due to etching damage, thus reducing the increase in dark current.

[0088] Other structural examples of the detection region 12 will be described. Figure 6 is a schematic plan view showing another structural example including the pixel 13, gate line 105, data line 106, and bias line 107. In Figure 6, only the outline of the bias line 107 is shown with a dashed line, and the recess 210 below the bias line 107 and the intrinsic amorphous silicon layer 203 are depicted as being transparent to the bias line 107. The differences from the configuration described with reference to Figures 5A and 5B will be mainly explained below.

[0089] The photodiode semiconductor layer includes a protrusion 213. The protrusion of the upper electrode 305 overlaps with a portion of the protrusion 213, and a contact portion 323 is formed in that portion. The bias line 107 covers at least a portion of the protrusion 213, but does not cover the portion of the photodiode semiconductor layer other than the protrusion 213. A portion of the upper layer side in the plane of the protrusion is removed to form recesses 210E and 210F that sandwich the contact portion 323. One of the recesses 210E and 210F may be omitted. In a plan view, the upper electrode 305 is excluded from the region overlapping with the recesses 210E and 210F and does not exist. The recesses 210E and 210F are formed outside the area covered by the upper electrode 305. The length of the recesses 210E and 210F in the longitudinal direction (Y direction) is shorter than the length of the recesses 210C and 210D shown in Figure 5A.

[0090] <Embodiment 3> Other structural examples of the detection region 12 will be described. Figure 7 is a cross-sectional view of the region including the pixel 13, corresponding to Figure 3B. The differences from the structural example shown in Figure 3B will be mainly described below. This embodiment includes an etching protective layer 307 on the upper electrode 305. The etching protective layer 307 has, for example, the same pattern shape as the upper electrode 305 and covers its entire area. In the example shown in Figure 7, the shape and dimensions of the etching protective layer 307 and the upper electrode 305 are identical, i.e., congruent, but they may be similar shapes with the same pattern shape but one being larger in dimensions. The etching protective layer 307 can be formed from, for example, silicon nitride or silicon oxide.

[0091] In this embodiment, in order to form a recess, at least the upper electrode 305 and the upper layer of the amorphous silicon layer are removed by etching. Dry etching is one possible method for etching the amorphous silicon. To form a pattern on the amorphous silicon layer, the amorphous silicon is etched using either a resist or the upper electrode 305 as a mask.

[0092] Etching of amorphous silicon damages the upper electrode 305, which alters the film quality and adhesion, potentially leading to delamination between the upper electrode and the second interlayer insulating layer 275. In this embodiment, an etching protection layer 307 is provided above the upper electrode 305, for example, in direct contact with the upper electrode 305, and these are used as a mask to etch the amorphous silicon layer. This reduces etching damage to the upper electrode 305.

[0093] Other structural examples of the detection region 12 are described below. Figure 8 is a cross-sectional view of the region including the pixel 13, corresponding to Figure 3B. The differences from the structural example shown in Figure 3B will be mainly explained below. In the structural example shown in Figure 8, the width W1 of the recess 210G, that is, the size in the shorter direction, is greater than the width W2 of the bias line 107. Furthermore, in a plan view, the shorter end of the bias line 107 is located inside the end of the recess 210G of the photodiode semiconductor layer. In a surface view, the bias line 107 covers a portion of the recess 210G such that both ends defining the width of the bias line 107 are located within the recess 210G.

[0094] If the recess 210G is narrower than the bias wire width and the second interlayer insulating layer 275 covers the recess in accordance with its shape, the cross-sectional shape of the bias wire will follow the shape of the second interlayer insulating layer 275, becoming V-shaped, which may cause voids over a wide area. These voids can progress through migration, potentially leading to wire breakage. By making the area of ​​the recess 210G larger than the bias wire width and arranging the bias wire 107 and the recess 210G such that the recess 210G includes the upper bias wire 107 in a plan view, the shape of the bias wire 107 can be made flatter, thereby suppressing voids.

[0095] <Embodiment 4> Other structural examples of the detection region 12 will be described. Figure 9A is a schematic plan view showing another structural example including the pixel 13, gate line 105, data line 106, and bias line 107. In Figure 9A, only the outline of the data line 106 is shown with a dashed line, and the structure below the data line 106 is drawn by passing through the data line 106. Also, the upper electrode 305 covers the entire area of ​​the lower electrode 301, and the outline of the lower electrode 301 is shown with a dashed line. Note that the lower electrode 301 may not be partially covered by the upper electrode 305, for example. Figure 9B shows a cross-sectional view at the IXB-IXB' cutting line in Figure 9A. Below, the differences from the configuration described with reference to Figures 3A to 3D will be mainly explained.

[0096] The data line 106 is light-shielding to the light that the photodiode 121 performs photoelectric conversion on. The bias line 107 may be light-shielding or light-transmitting. In the structural example shown in Figures 9A and 9B, a recess 210H is formed in the region that overlaps with the data line 106 in a plan view. H The bottom surface of the electrode is exposed, with an intrinsic amorphous silicon layer 203 exposed. The recess 210H is formed outside the lower electrode 301 in a plan view. The lower electrode 301 may partially or completely overlap the recess 210H in a plan view. The recess 210H is also formed outside the area covered by the upper electrode 305.

[0097] In this embodiment, the upper portion of the photodiode semiconductor layer is removed in the region that overlaps with the data line 106 in a plan view. This structure reduces kTC noise. Furthermore, the parasitic capacitance formed between the data line 106 and the upper electrode 305 or the impurity-doped amorphous silicon layer on the upper side can be reduced, thereby reducing data line noise.

[0098] The recess 210H reaches the edge of the photodiode semiconductor layer through which the data line 106 crosses. In other words, the edge of the recess 210H in the Y direction coincides with the edge (sidewall) of the photodiode semiconductor layer. Therefore, the risk of disconnection of the data line 106 can be reduced. In addition, in the structural example shown in Figures 9A and 9B, the inner surface of the recess 210H in the short direction (X direction) is composed of a stack of the side surface of the upper electrode 305, the side surface of the P-type amorphous silicon layer 204, and the inner surface of the recess of the intrinsic amorphous silicon layer 203. However, as described in Embodiment 2, one end of the recess 210H may be open.

[0099] As explained with reference to Figures 9A and 9B, the region where the recess of the photodiode semiconductor layer is formed may overlap with the bias line and other wiring in a plan view. Furthermore, as explained in the other embodiments described above, a recess of the photodiode semiconductor layer may also be formed beneath the bias line 107.

[0100] <Embodiment 5> Other structural examples of the detection region 12 will be described. Figure 10A is a schematic plan view showing another structural example including pixels 13, gate lines 105, data lines 106, and bias lines 107. In Figure 10A, only the outline of the bias line 107 is shown with a dashed line, and the structure below the bias line 107 is drawn by passing through the bias line 107. Figure 10B shows a cross-sectional view along the XB-XB' cutting line in Figure 10A. Below, the differences from the configuration described with reference to Figures 3A to 3D will be mainly explained.

[0101] In a plan view, recesses 210I and 210J of the photodiode semiconductor layer are formed in the region covered by the bias line 107. The intrinsic amorphous silicon layer 203 is exposed in recesses 210I and 210J, and recesses 210I and 210J are formed outside the region covered by the upper electrode 305.

[0102] In a plan view, the recess 210I covers at least a portion of the contact portion 227 between the source electrode 253 and the lower electrode 301. In a plan view, only a portion of the contact portion 227, including its center in the plan view, may overlap with the recess 210I.

[0103] If a high step exists on the lower side of the amorphous silicon layer region, the film quality of the amorphous silicon layer spanning the step deteriorates, making it more prone to generating defect levels than flat areas. A step can exist when the contact portion 227 between the source electrode 253 and the lower electrode 301 of the thin-film transistor 122 is located on the lower side of the region that overlaps with the amorphous silicon layer in a plan view. This step deteriorates the dark current characteristics of the photodiode 121 located above it. By removing the impurity-doped amorphous silicon layer above the step, which is prone to deterioration, and eliminating the vertical electric field between the upper and lower impurity-doped amorphous silicon layers, the increase in dark current can be suppressed.

[0104] <Embodiment 6> Other structural examples of the detection region 12 will be described. Figure 11A is a schematic plan view showing another structural example including pixels 13, gate lines 105, data lines 106, and bias lines 107. In Figure 11A, only the outline of the bias line 107 is shown with a dashed line, and the structure below the bias line 107 is drawn by passing through the bias line 107. Figure 11B shows a cross-sectional view at the XIB-XIB' cutting line in Figure 11A. Below, the differences from the configuration described with reference to Figures 3A to 3D will be mainly explained.

[0105] Instead of the recesses 210A and 210B shown in Figures 3A to 3D, recesses 210K and 210L are formed. The bottom surface of recess 210K gradually slopes downward toward the edge 215A of the photodiode semiconductor layer. The bottom surface of recess 210L gradually slopes downward toward the edge 215B of the photodiode semiconductor layer.

[0106] In the example shown in Figure 11B, the bottom surface of the recess 210K is composed of two step surfaces 217A and 217B of different heights. The height of step surface 217B from the lower electrode 301 is lower than the height of step surface 217A from the lower electrode 301. Step surface 217A is located between the contact portion 323 and step surface 217B. Step surface 217B reaches the edge 215A of the photodiode semiconductor layer (N-type amorphous silicon layer 202 and intrinsic amorphous silicon layer 203).

[0107] The bottom surface of the recess 210L is composed of two step surfaces 217C and 217D of different heights. The height of step surface 217D from the lower electrode 301 is lower than the height of step surface 217C from the lower electrode 301. Step surface 217C is located between the contact portion 323 and step surface 217D. Step surface 217D reaches the edge 215B of the photodiode semiconductor layer (N-type amorphous silicon layer 202 and intrinsic amorphous silicon layer 203).

[0108] Thus, the bottom surface of the recess is composed of multiple stepped surfaces, and the height decreases towards the edge, thereby reducing the possibility of the upper bias line 107 being interrupted by steps. The number of stepped surfaces on the bottom surface may be three or more. In the configuration example shown in Figures 5A, 5B, or 6, the recess 210 C, 210D, 210E, 210F The bottom surface may gradually decrease in height towards the edge 215B of the photodiode semiconductor layer.

[0109] <Embodiment 7> Other structural examples of the detection region 12 are described below. Figure 12 is a schematic plan view showing another structural example including pixels 13, gate lines 105, data lines 106, and bias lines 107. The differences from the configuration described with reference to Figure 5A will be explained below.

[0110] In the configuration example described with reference to Figure 5A, the data line 106 is formed in the same layer as the bias line 107. In this embodiment, the data line 106 is located in a lower layer than the bias line 107. In one example, the data line 106 is formed in the same layer as the source electrode 253 and drain electrode 254 of the thin-film transistor 122.

[0111] For example, if the bias line 107 is placed at the edge of the photodiode semiconductor layer, it will be close to the data line 106 of the adjacent pixel, making it prone to noise between the data line 106 and the bias line 107. By placing the data line 106 in the same layer as the source electrode 253 and the drain electrode 254, the distance between the data line 106 and the bias line 107 can be increased, thereby reducing noise on the data line.

[0112] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. Those skilled in the art can easily modify, add to, and transform each element of the above embodiments within the scope of the present disclosure. It is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of Symbols]

[0113] 10 Image Sensors 11 Sensor board 13 pixels 14. Drive Circuit 16 Signal detection circuit 18 Main control circuit 105 Gate Line 106, 161 data lines 107 Bias line 121 Photodiode 122 Thin-film transistors 202 N-type amorphous silicon layer 203 Intrinsic amorphous silicon layer 204 P-type amorphous silicon layer 210 recess 251 Grid Control Terminal 252 Semiconductor Section 253 Source electrode 254 Drain electrode 271 Insulating substrate 272-276 Insulating layer 301 Lower electrode 305 Upper electrode

Claims

1. An imaging device, circuit board and A photodiode semiconductor layer on the aforementioned substrate, The upper electrode and lower electrode sandwich the aforementioned photodiode semiconductor layer, With the aforementioned substrate as the lowest layer, and light-shielding wiring above the aforementioned upper electrode, Includes, The aforementioned photodiode semiconductor layer is The first semiconductor layer, A second semiconductor layer between the first semiconductor layer and the lower electrode, Includes, The photodiode semiconductor layer includes a recess in a region covered by the light-shielding wiring in a plan view, where the first semiconductor layer has been removed. In the aforementioned plan view, the upper electrode is excluded from the region overlapping with the recess. In the plan view, a portion of the second semiconductor layer and a portion of the lower electrode are located in the region overlapping with the recess. Imaging device.

2. The imaging apparatus according to claim 1, The photodiode semiconductor layer includes a third semiconductor layer between the first semiconductor layer and the second semiconductor layer. The bottom surface of the recess is composed of a part of the third semiconductor layer. Imaging device.

3. The imaging apparatus according to claim 2, The third semiconductor layer has a recess that constitutes part of the recess, Imaging device.

4. The imaging apparatus according to claim 1, The light-shielding wiring is a bias line that applies a bias potential to the photodiode semiconductor layer via the upper electrode. Imaging device.

5. The imaging apparatus according to claim 1, The light-shielding wiring crosses the edge of the second semiconductor layer in the plan view, The end of the recess coincides with the end of the second semiconductor layer in a plan view. Imaging device.

6. The imaging apparatus according to claim 1, The light-shielding wiring extends along the edge of the second semiconductor layer and covers the edge. The recess extends along the end, The end of the recess coincides with the end of the second semiconductor layer in a plan view. Imaging device.

7. The imaging apparatus according to claim 1, The upper electrode further includes an insulating layer covering the upper electrode, having a pattern shape similar to or congruent to the upper electrode. Imaging device.

8. The imaging apparatus according to claim 1, The width of the light-shielding wiring is smaller than the width of the recess. In the plan view, the light-shielding wiring covers a portion of the recess such that both ends defining the width of the light-shielding wiring are located within the recess. Imaging device.

9. The imaging apparatus according to claim 1, The light-shielding wiring is a data line that transmits signals from the photodiode semiconductor layer. Imaging device.

10. The imaging apparatus according to claim 1, The system further includes a transistor connected to the lower electrode, In the plan view, the recess covers at least a portion of the contact area between the transistor and the lower electrode. Imaging device.

11. The imaging apparatus according to claim 5, The bottom surface of the recess is progressively lower towards the edge of the second semiconductor layer. Imaging device.

12. The imaging apparatus according to claim 1, The system further includes data lines for transmitting signals from the photodiode semiconductor layer, The light-shielding wiring is a bias line that applies a bias potential to the photodiode semiconductor layer via the upper electrode. The data line and the bias line extend along a common direction. The data line is located below the bias line. Imaging device.

Images