CXPI low EMI transceiver

Abstract

To provide a system and method for a Clock Enhanced Peripheral Interface (CXPI) low electromagnetic interference (EMI) transceiver that reduces EMI caused by significant level differences between master and slave signals.SOLUTION: A method includes receiving a bus signal generated on the basis of a first signal associated with a master device and a second signal associated with a slave device, identifying a specific portion of a falling edge of the bus signal on the basis of a predetermined threshold, and enabling slew rate control on the specific portion of the falling edge of the bus signal to reduce electromagnetic interference (EMI) on the bus signal caused by a difference in dominant levels of the first signal and the second signal.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates generally to the field of electronic components, and more particularly to a Clock Enhanced Peripheral Interface (CXPI) low electromagnetic interference (EMI) transceiver that detects low voltage levels of bus signals derived from master and slave signals, adjusts the slew rate of falling edges of the bus signals during the low voltage levels, and reduces EMI caused by significant level differences between the master and slave signals. [Background technology]

[0002] CXPI is a communications protocol based on an automotive communications protocol known as Local Interconnect Network (LIN). LIN is a relatively inexpensive serial network protocol that supports remote communications and applications within automotive networks. It is intended specifically for mechatronic nodes in distributed automotive applications, but is equally suitable for industrial applications. It is intended to complement existing CAN networks that lead to hierarchical networks within the vehicle.

[0003] The present disclosure is illustrated by way of example only, and not by way of limitation, in the accompanying drawings in which like reference numerals refer to similar elements and in which: [Brief explanation of the drawings]

[0004] [Figure 1] 1 shows a block diagram of an example environment for using a conventional CXPI transceiver to communicate with master and slave devices using a serial network protocol. [Figure 2] 2 shows a block diagram of a conventional CXPI system 200 according to some embodiments. [Figure 3] 3 is a block diagram depicting example waveforms of the conventional CXPI system of FIG. 2 according to some embodiments. [Figure 4]4 shows a block diagram of an extended CXPI system 400 according to some embodiments. [Figure 5A] 5 is a block diagram depicting an example waveform of a bus signal conditioned by the extended CXPI system of FIG. 4 in the absence of a master signal, according to some embodiments. [Figure 5B] 5 is a block diagram depicting an example waveform of a bus signal conditioned by the extended CXPI system of FIG. 4 in the presence of a master signal, according to some embodiments. [Figure 6] 1 illustrates a block diagram of an example CXPI transmitter including drivers in a cascaded configuration, according to some embodiments. [Figure 7] 1 illustrates a block diagram of an example CXPI transmitter including drivers in a cascaded configuration, according to some embodiments. [Figure 8] 1 illustrates a block diagram of an example CXPI transmitter including drivers in a non-cascaded configuration, according to some embodiments. [Figure 9] FIG. 1 is a flow diagram of a procedure for reducing EMI caused by significant level differences between master and slave signals using an extended CXPI system, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0005] The following description sets forth numerous specific details, such as examples of particular systems, components, methods, etc., to better understand various embodiments of the techniques described herein, e.g., for reducing (or eliminating) EMI on a bus signal caused by significant level differences between a master signal and a slave signal associated with the bus signal by using an extended CXPI system (e.g., circuitry). However, it will be apparent to those skilled in the art that at least some embodiments may be practiced without these specific details. In other instances, well-known components, elements, or methods are not described in detail or are presented in simple block diagram form to avoid unnecessarily obscuring the techniques described herein. Accordingly, the specific details described below are merely exemplary. Particular implementations may vary from these example details and still be considered within the scope of the present disclosure.

[0006] In a conventional CXPI system, a conventional CXPI transceiver enables a master device and one or more slave devices to communicate using a serial network protocol across a shared bus. That is, the master device generates a master signal on the bus, and the slave device generates a slave signal on the bus, resulting in a combined bus signal on the bus. The conventional CXPI transceiver receives the bus signal and adjusts the slew rate of the bus signal. If the master device increases the frequency of its master signal (e.g., by reducing the low width of its master signal to 5.5 μs or less), the conventional CXPI system must also reduce the response time of the slave side (e.g., by reducing the low width of the slave signal to less than 5.5 μs) so that the slave signal is faster than the master signal. Otherwise, the conventional CXPI system may fail compliance testing.

[0007] However, performance differences between the master and slave devices may exist due to various differences (e.g., different voltage thresholds between the diodes of the master and slave devices) that cause the master signal to have a higher dominant level than the dominant level of the slave signal. In such cases, increasing the speed of response of the slave device may cause EMI problems when transitioning the dominant level from master to slave. Thus, additional EMI on the shared bus reduces the ability of the master and / or slave devices to share important information about the vehicle 150 with each other (e.g., battery level, telemetry information, braking information, etc.). Without the ability to accurately monitor the performance of the vehicle 150, the CXPI system would not know whether corrective action needs to be taken to resolve vehicle faults and / or avoid potential accidents.

[0008] Aspects of the present disclosure address these and other shortcomings by detecting low voltage levels in bus signals derived from master and slave signals, adjusting the slew rate of falling edges of the bus signals during the low voltage levels, and reducing EMI caused at least in part by significant level differences between the master and slave signals.

[0009] In an exemplary embodiment, a CXPI system receives a bus signal generated based on a first signal associated with a master device and a second signal associated with a slave device. The CXPI system identifies a specific portion of a falling edge of the bus signal (e.g., a range of voltage during a specific time period of the bus signal) based on a predetermined threshold. The CXPI system activates (e.g., enables) slew rate control on the specific portion of the falling edge of the bus signal to reduce electromagnetic interference (EMI) on the bus signal caused by a difference in the dominant levels of the first and second signals.

[0010] 1 shows a block diagram of an example environment for using a conventional CXPI transceiver to communicate with master and slave devices using a serial network protocol. Environment 100 includes an automobile 105, which includes CXPI slave devices 102 (e.g., CXPI slave device 102a, CXPI slave device 102b, CXPI slave device 102c), a CXPI master device 103, and a conventional CXPI transceiver 101, each communicatively coupled together via a bus 110 located onboard vehicle 150. Each of the coupled devices may transmit / receive any type of communication (e.g., battery level signals) via bus 110. Because CXPI is based on LIN, the transmitter portion of CXPI transceiver 101 includes a slew rate controller to address electromagnetic interference (EMI) generated by the master and slave devices across communication bus 110.

[0011] Although FIG. 1 illustrates the components (e.g., CXPI slave device 102, CXPI master device 103, conventional CXPI transceiver 101, bus 110) each being positioned in a vehicle 150, in some embodiments of the present disclosure, the components may be positioned in any type of vehicle, including, for example, a land vehicle (e.g., motorcycle, long-haul truck, etc.), a watercraft (e.g., boat), or an aircraft.

[0012] 2 shows a block diagram of a conventional CXPI system 200 according to some embodiments. The conventional CXPI system 200 includes the conventional CXPI transceiver 101 of FIG. 1, a battery 231, a bus 110, diodes 216, 218, 220, a resistor 230 (Rbus), a CXPI master device 103, and one or more CXPI slave devices 102. The CXPI transceiver 101 is communicatively coupled to the CXPI master device 103 and one or more CXPI slave devices 102 via the bus 110.

[0013] Conventional CXPI transceiver 101 includes a logic device 202 (e.g., one or more processors, central processing units (CPUs), etc.), a CXPI receiver 204, and a CXPI transmitter 206. CXPI transmitter 206 includes a slew rate controller 208, a driver 212, and a diode 214.

[0014] 3 is a block diagram depicting example waveforms of the conventional CXPI system of FIG. 2, according to some embodiments. Still referring to FIG. 2, CXPI master device 103 generates a master signal on bus 110, which is synchronized with a master clock of conventional CXPI system 200. CXPI slave device 102 generates a slave signal on bus 110. The master and slave signals combine to form a bus signal on bus 110, which is received by CXPI receiver 204. CXPI receiver 204 generates an Rxd signal based on the bus signal and sends the Rxd signal to logic device 202, which then generates a Txd signal based on the Rxd signal and sends the Txd signal to CXPI transmitter 206.

[0015] CXPI transmitter 206 adjusts the slew rate of the bus signal by using its slew rate controller 208, where slew rate refers to the change in voltage or current per unit time. Specifically, when Txd is high, CXPI system 200 enables slew rate controller 208 to control the rising slew rate of the bus signal. Conversely, when Txd is low, CXPI system 200 disables the slew rate control and enables driver 212 fast. The time difference between the falling edge of the bus signal and the falling edge of the Txd signal is Rxd_delay. The time difference between the falling edge of the bus signal and the point in time when CXPI system 200 transitions the dominant level of the bus signal from the master signal to the slave signal (Txd) is Txd_delay.

[0016] In conventional CXPI systems 200, the falling slew rate of the bus signal is controlled by the master side (e.g., the master device) and the rising slew rate is controlled by the slave side (e.g., the CXPI transmitter), so EMI is not considered an issue. However, a challenge with conventional CXPI systems 200 is that the slave side requires a fast response to pass compliance testing. That is, if the dominant level of the master signal is higher than the dominant level of the slave signal, increasing the speed of the slave device's response may cause EMI issues when transitioning the dominant level from master to slave. Therefore, the additional EMI reduces the ability of the master and / or slave devices to share important information about the vehicle 150 with each other (e.g., battery level, telemetry information, braking information, etc.).

[0017] For example, as shown in FIG. 3, a conformance test may be performed with a master low width of 5.5 μs. Under this condition, the slave device must respond faster than 5.5 μs or fail the conformance test for CXPI. CXPI system 200 may use its slew rate controller 208 to control the slew rate of the bus signal to address electromagnetic interference (EMI) caused by communication of the master and slave devices across bus 110. However, if slew rate controller 208 sets the ramp time to 10 μs, Txd_delay is also approximately 10 μs, failing the conformance test for CXPI. Therefore, CXPI system 200 has no countermeasure for EMI associated with the significant level difference between the master and slave signals.

[0018] 4 shows a block diagram of an extended CXPI system 400 according to some embodiments. The extended CXPI system 400 includes an extended CXPI transceiver 401, a battery 231, a bus 110, diodes 216 and 218, a resistor 230 (Rbus), a CXPI master device 103, and one or more CXPI slave devices 102. The extended CXPI transceiver 401 is communicatively coupled to the CXPI master device 103 and one or more CXPI slave devices 102 via the bus 110.

[0019] The extended CXPI transceiver 401 includes a logic device 202 (e.g., one or more processors, central processing units (CPUs), etc.), a CXPI receiver 204, and an extended CXPI transmitter 406. The extended CXPI transmitter 406 includes an extended slew rate controller 408, a driver 212, a diode 214, and a low-level detector 410.

[0020] 2, but replaces CXPI transmitter 206 with an extended CXPI transmitter 406 that includes a low-level detector 410 that detects low levels on the bus signal and an extended slew rate controller 408 that, when enabled, can increase or decrease the slew rate of the rising and / or falling edges of the bus signal. By using low-level detector 410 and extended slew rate controller 408, extended CXPI system 400 can reduce any EMI on the bus signal caused, at least in part, by significant level differences between the master and slave signals.

[0021] Specifically, low level detector 410 is configured to continuously monitor and measure the bus signal and determine whether the bus signal is below a predetermined threshold corresponding to a low bus level. In some embodiments, the low bus level may be any voltage that is below 30% of the battery voltage (e.g., vbat) provided by battery 231. However, in other embodiments, different predetermined thresholds (e.g., 10%, 20%, 50%) may be used to detect when the bus signal is at a low bus level. For each measured voltage, low level detector 410 sends a low level (LL) signal to extended slew rate controller 408, which indicates whether the bus signal is at a low bus level defined by the predetermined threshold.

[0022] The enhanced slew rate controller 408 is configured to reduce (e.g., mitigate or eliminate) EMI caused, at least in part, by any significant level difference between the master and slave signals on the bus signals by enabling slew rate control on the falling edges of the bus signals whenever the LL signal indicates that the falling edge is at the low bus level, and by disabling slew rate control on the falling edges of the bus signals whenever the LL signal indicates that the falling edge is no longer at the low bus level.

[0023] Conversely, the extended slew rate controller 408 may be configured to apply slew rate control to some or all of the rising edges of the bus signal. For example, the extended slew rate controller 408 may apply slew rate control to the rising edges of the bus signal only when the bus signal is less than (including equal to) and / or greater than a predetermined threshold.

[0024] In some embodiments, the enhanced CXPI transceiver 401 receives a bus signal generated based on a first signal associated with a master device and a second signal associated with a slave device. In some embodiments, the enhanced CXPI transceiver 401 identifies a specific portion of a falling edge of the bus signal based on a predetermined threshold. In some embodiments, the enhanced CXPI transceiver 401 enables slew rate control on the specific portion of the falling edge of the bus signal to reduce EMI on the bus signal caused by a difference in the dominant levels of the first and second signals.

[0025] In some embodiments, the dominant level of the first signal is higher than the dominant level of the second signal, the first signal being synchronous to the master clock, and the second signal being asynchronous to the master clock.

[0026] In some embodiments, the enhanced CXPI transceiver 401 identifies different portions of the falling edge of the bus signal based on a predetermined threshold, and in some embodiments, the enhanced CXPI transceiver 401 prevents activation of the slew rate control on different portions of the falling edge of the bus signal (e.g., by disabling the slew rate control).

[0027] In some embodiments, enhanced CXPI transceiver 401 determines to enable slew rate control on a rising edge of the bus signal that follows the falling edge. In some embodiments, enhanced CXPI transceiver 401 enables slew rate control on the rising edge of the bus signal in response to determining to enable slew rate control on the rising edge of the bus signal.

[0028] In some embodiments, the enhanced CXPI transceiver 401 determines to enable slew rate control on the rising edge of the bus signal that follows the falling edge, regardless of a predetermined threshold.

[0029] In some embodiments, the enhanced CXPI transceiver 401 identifies a particular portion of the falling edge of the bus signal based on a low-level detector 410 (eg, a voltage detector) coupled to the drivers in a cascade configuration.

[0030] In some embodiments, the enhanced CXPI transceiver 401 identifies a particular portion of the falling edge of the bus signal based on the slew rate controller. In some embodiments, the enhanced CXPI transceiver 401 routes a feedback voltage from the output of the low level detector 410 to the input of the slew rate controller 208.

[0031] In some embodiments, the enhanced CXPI transceiver 401 identifies a particular portion of the falling edge of the bus signal based on a low level detector 410 coupled to the driver in a non-cascaded configuration.

[0032] In some embodiments, the enhanced CXPI transceiver 401 enables slew rate control on specific portions of the falling edge of the bus signal by reducing the slew rate on specific portions of the falling edge of the bus signal.

[0033] In some embodiments, the enhanced CXPI transceiver 401 receives a first signal associated with a first device (e.g., CXPI master device 103) and a second signal associated with a second device (e.g., CXPI slave device 102) over the bus 110 (e.g., a signal path). In some embodiments, the enhanced CXPI transceiver 401 detects a voltage difference between a dominant level of the first signal and a dominant level of the second signal. In some embodiments, the enhanced CXPI transceiver 401 generates a bus signal on the signal path based on the first signal and the second signal. In some embodiments, the enhanced CXPI transceiver 401 adjusts the slew rate of the bus signal based on the voltage difference.

[0034] 5A is a block diagram illustrating an example waveform of a bus signal conditioned by the extended CXPI system of FIG. 4 in the absence of a master signal, according to some embodiments. That is, the extended CXPI transceiver 401 detects that there is a voltage difference between the dominant levels of the master and slave signals when transitioning from master to slave, causing EMI on the bus signal. To reduce EMI, the extended CXPI transceiver 101 uses its extended slew rate controller 408 to reduce the slew rate on the falling edge of the bus signal for voltage levels below a predetermined threshold (e.g., 30% of vbat) so that the bus signal no longer exhibits the voltage difference between the dominant levels of the master and slave signals. Conversely, the extended slew rate controller 408 applies slew rate control to some or all of the rising edge of the bus signal.

[0035] FIG. 5B is a block diagram depicting an example waveform of a bus signal conditioned by the extended CXPI system of FIG. 4 in the presence of a master signal, according to some embodiments. Similar to FIG. 5A, the extended CXPI transceiver 401 detects that a voltage difference exists between the dominant levels of the master and slave signals when transitioning the dominant level from master to slave, causing EMI on the bus signal. To reduce EMI, the extended CXPI transceiver 101 uses its extended slew rate controller 408 to reduce the slew rate on the falling edge of the bus signal for voltage levels below a predetermined threshold (e.g., 30% of vbat) so that the bus signal no longer exhibits the voltage difference between the dominant levels of the master and slave signals. Conversely, the extended slew rate controller 408 applies slew rate control to some or all of the rising edge of the bus signal.

[0036] 6 shows a block diagram of an example CXPI transmitter including drivers in a cascade configuration, according to some embodiments. The CXPI transmitter 600 includes a slew rate controller 608, a low-level detector 610, a selector (SWfb) 690, a resistor 632, and diodes 622, 624. The CXPI transmitter 600 is coupled to the bus 110, which is coupled to a resistor 630 (Rbus), a diode 616, a capacitor 640 (Cbus), and a battery 231.

[0037] The slew rate controller 608 includes sw1, sw2, an operational amplifier 670, and a capacitor 642 (Cwave). The low level detector 610 includes a transistor 685 (Ncas).

[0038] When TXD is low, sw1 is closed, sw2 is open, and the selector 690 selects path s2 as feedback. Conversely, when TXD is high, sw1 is open, sw2 is closed, and the selector 690 selects path s1 as feedback.

[0039] 6, the driver 210 is configured in a cascade connection type, whereby the vclamp node of the low level detector 610 can be used as the output of the low level detector 610. For example, if vddd=3V and vth_cas=1V, the slew rate control can start from a bus signal of about 2V.

[0040] In some embodiments, the slew rate of the falling edge is defined by equation (1) below: (1) Slew Rate fe =I wave / C wave

[0041] In some embodiments, the slew rate for a rising edge is defined by equations (2) and (3) below: (2) ΔV tin / Δt≒I wave / (C wave ×Rfb2 / (R fb1 +R fb2 )) (3) I wave ≪Vlin·(R fb1 +R fb2 )

[0042] The slew rate controller 608 controls the slew rate of the bus signal based on the Miller effect. The slew rate controller 608 adjusts the slew rate of the falling edge of the bus signal only at low dominant levels by changing the feedback to come from the output of the low level detector 610 (e.g., vclamp). Conversely, the slew rate controller 608 adjusts the slew rate of the rising edge of the bus signal by returning the feedback to come from a common node.

[0043] 7 shows a block diagram of an example CXPI transmitter including drivers in a cascade configuration, according to some embodiments. The CXPI transmitter 700 includes a slew rate controller 708, a low-level detector 710, a selector (SWfb) 790, a resistor 732, and diodes 722, 724. The CXPI transmitter 700 is coupled to the bus 110, which is coupled to a resistor 730 (Rbus), a diode 716, a capacitor 740 (Cbus), and a battery 231.

[0044] The slew rate controller 708 includes sw1, sw2, an operational amplifier 770, and a capacitor 742 (Cwave). The low level detector 710 includes a transistor 785 (Ncas) and a resistor 791 (Rbais).

[0045] When TXD is low, sw1 is closed, sw2 is open, and the selector 790 selects path s2 as feedback. Conversely, when TXD is high, sw1 is open, sw2 is closed, and the selector 790 selects path s1 as feedback.

[0046] In some embodiments, the slew rate for a falling edge is defined by equation (1): In some embodiments, the slew rate for a rising edge is defined by equations (2) and (3).

[0047] The CXPI transmitter 700 can adjust the slew rate to any starting point for slew rate control by applying vbias as shown in FIG.

[0048] 8 shows a block diagram of an example CXPI transmitter including drivers in a non-cascaded configuration, according to some embodiments. The CXPI transmitter 800 includes a slew rate controller 808, a low-level detector 810, a selector (SWfb) 890, a resistor 832, and diodes 822, 824. The CXPI transmitter 800 is coupled to a bus 110, which is coupled to a resistor 830 (Rbus), a diode 816, a capacitor 840 (Cbus), and a battery 231.

[0049] The slew rate controller 808 includes sw1, sw2, an operational amplifier 870, and a capacitor 842 (Cwave). The low level detector 810 includes a transistor 885 (Ncas) and a resistor 891 (Rbais).

[0050] When TXD is low, sw1 is closed, sw2 is open, and the selector 890 selects path s2 as feedback. Conversely, when TXD is high, sw1 is open, sw2 is closed, and the selector 890 selects path s1 as feedback.

[0051] In some embodiments, the slew rate for a falling edge is defined by equation (1): In some embodiments, the slew rate for a rising edge is defined by equations (2) and (3).

[0052] FIG. 9 is a flow diagram of a procedure for reducing EMI caused by significant level differences between master and slave signals using an extended CXPI system, according to some embodiments. While FIG. 9 depicts the operations as integrated operations in a particular order for illustrative purposes, in other implementations, one or more operations or portions thereof may be performed in a different order, may be performed serially or in parallel, may overlap in time, may be omitted, may include one or more additional operations, or may vary the method in some combination of manners. In some embodiments, procedure 900 may be performed by processing logic including hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), firmware, or a combination thereof. In some embodiments, some or all of the operations of procedure 900 may be performed by one or more components of the extended CXPI system (e.g., low-level detector 610, slew rate controller 608, driver 210, selector 690, etc.).

[0053] Procedure 900 is described with respect to extended CXPI system 400 of FIG. 4, but may also be implemented using extended CXPI system 600 of FIG. 6, extended CXPI transmitter 700 of FIG. 7, and / or extended CXPI system 800 of FIG. 8. At operation 902, in some embodiments, extended CXPI system 400 receives a bus signal generated based on a first signal associated with a master device and a second signal associated with a slave device. At operation 904, in some embodiments, extended CXPI system 400 identifies a portion of the falling edge of the bus signal. At operation 906, in some embodiments, extended CXPI system 400 compares the identified portion of the falling edge of the bus signal with a predetermined threshold. If the identified portion is greater than the predetermined threshold, extended CXPI system 400 proceeds to operation 909, identifies a next portion of the falling edge of the bus signal, and then proceeds to operation 906.

[0054] Alternatively, if the particular portion is below the predetermined threshold, the enhanced CXPI system 400 proceeds to operation 910 and enables slew rate control on the identified portion of the falling edge of the bus signal to reduce electromagnetic interference (EMI) on the bus signal caused by the difference in the dominant levels of the first signal and the second signal.

[0055] In operation 912, in some embodiments, extended CXPI system 400 determines whether there are other portions of the bus signal that have not yet been checked, and if there are unchecked portions, extended CXPI system 400 proceeds to operation 909 and repeats operation 909 using the unchecked portions. Alternatively, if there are no unchecked portions of the bus signal, extended CXPI system 400 proceeds to operation 914, selects the next falling edge of the bus signal, and proceeds to operation 904 and repeats operation 904 using the next falling edge.

[0056] In the foregoing description, some portions of the detailed descriptions are presented in terms of algorithms and symbolic representations of operations on analog and / or digital signals or data bits within non-transitory storage media. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. These quantities usually, though not necessarily, take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0057] References in the description to "an embodiment," "one embodiment," "exemplary embodiment," "some embodiments," and "various embodiments" mean that the particular feature, structure, step, act, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Moreover, the appearances of the phrases "an embodiment," "one embodiment," "exemplary embodiment," "some embodiments," and "various embodiments" in various places in the description do not necessarily all refer to the same embodiments.

[0058] The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show illustrative examples in accordance with exemplary embodiments. These embodiments, which may also be referred to herein as "examples," are described in sufficient detail to enable one of ordinary skill in the art to practice embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the spirit and scope of the claimed subject matter. It is understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable one of ordinary skill in the art to practice, make, and / or use the subject matter.

[0059] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated as is apparent from the above description, throughout the description, discussions using terms such as "receive," "identify," "validate," "prevent," "determine," "reduce," and the like should be recognized to refer to the actions and processes of an integrated circuit (IC) controller or similar electronic device that manipulates and converts data represented as physical (e.g., electronic) quantities in the controller's registers and memory into other data also represented as physical quantities in the controller memory or registers, or other such information in a non-transitory storage medium.

[0060] As used herein, the term "example" or "exemplary" is used to mean serving as an example, illustration, or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the term "example" or "exemplary" is intended to present the concept in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless expressly stated otherwise or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, in any of the above examples, "X includes A or B" is satisfied if X includes A, if X includes B, or if X includes both A and B. Additionally, as used in this application and the appended claims, the singular indefinite article "a," "an," or "an" should generally be construed to mean "one or more" unless expressly stated otherwise or clear from context. Furthermore, use of the terms "in one embodiment" or "embodiment" throughout is not intended to refer to the same embodiment unless expressly stated.

[0061] The embodiments described herein may also relate to an apparatus (e.g., an AC-DC converter and / or an ESD protection system / circuit) that performs the operations herein. The apparatus may be specially configured for the required purposes, or may include firmware or hardware logic that is selectively enabled or reconfigured by the apparatus. Such firmware may be stored on a non-transitory computer-readable storage medium, such as, but not limited to, read-only memory (ROM), random-access memory (RAM), EPROM, EEPROM, flash memory, or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "computer-readable medium" should also be considered to include any medium that can store, encode, or transmit a set of instructions for execution by a machine, causing the machine to perform any one or more of the methodologies of the present embodiments. Thus, the term "computer-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, magnetic media, and any medium that can store a set of instructions for execution by a machine, causing the machine to perform any one or more of the methodologies of the present embodiments.

[0062] The foregoing description sets forth numerous specific details, such as examples of particular systems, components, methods, etc., to provide a thorough understanding of some embodiments of the present disclosure. It is to be understood that the foregoing description is intended to be illustrative and not limiting. Many other embodiments will be apparent to those skilled in the art upon reading and understanding the foregoing description. The scope of the present disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. receiving a bus signal generated based on a first signal associated with a master device and a second signal associated with a slave device; identifying a particular portion of the falling edge of the bus signal based on a predetermined threshold; enabling slew rate control on the particular portion of the falling edge of the bus signal to reduce electromagnetic interference (EMI) on the bus signal caused by a difference in dominant levels of the first signal and the second signal; A method comprising:

2. a dominant level of the first signal is higher than a dominant level of the second signal, the first signal being synchronous with a master clock and the second signal being asynchronous with the master clock; The method of claim 1.

3. The method comprises: identifying different portions of the falling edge of the bus signal based on the predetermined threshold; preventing activation of the slew rate control on the different portions of the falling edge of the bus signal; further comprising: The method of claim 1.

4. The method comprises: determining to enable the slew rate control on a rising edge of the bus signal that follows the falling edge; enabling the slew rate control on the rising edge of the bus signal in response to determining to enable the slew rate control on the rising edge of the bus signal; further comprising: The method of claim 1.

5. determining to enable the slew rate control on the rising edge of the bus signal subsequent to the falling edge, regardless of the predetermined threshold; The method of claim 4.

6. and identifying the particular portion of the falling edge of the bus signal is further based on a voltage detector coupled to a driver in a cascade configuration. The method of claim 1.

7. and identifying the particular portion of the falling edge of the bus signal further based on a slew rate controller. The method further includes routing a feedback voltage from an output of the voltage detector to an input of the slew rate controller. The method of claim 6.

8. and identifying the particular portion of the falling edge of the bus signal is further based on a voltage detector coupled to a driver in a non-cascaded configuration. The method of claim 1.

9. and identifying the particular portion of the falling edge of the bus signal further based on a slew rate controller. The method further includes routing a feedback voltage from an output of the voltage detector to an input of the slew rate controller. The method of claim 8.

10. enabling the slew rate control on the particular portion of the falling edge of the bus signal comprises decreasing the slew rate on the particular portion of the falling edge of the bus signal. The method of claim 1.

11. 1. An integrated circuit comprising a voltage detector and a slew rate controller, The voltage detector receiving a bus signal generated based on a first signal associated with the master device and a second signal associated with the slave device; identifying a particular portion of the falling edge of the bus signal based on a predetermined threshold; It is configured as follows: the slew rate controller is configured to enable slew rate control on the particular portion of the falling edge of the bus signal to reduce electromagnetic interference (EMI) on the bus signal caused by a difference in dominant levels of the first signal and the second signal. Integrated circuit.

12. a dominant level of the first signal is higher than a dominant level of the second signal, the first signal being synchronous with a master clock and the second signal being asynchronous with the master clock; 12. The integrated circuit of claim 11.

13. the voltage detector is further configured to identify different portions of the falling edge of the bus signal based on the predetermined threshold; the slew rate controller is further configured to prevent activation of the slew rate control on the different portions of the falling edge of the bus signal.

12. The integrated circuit of claim 11.

14. The slew rate controller determining to enable the slew rate control on a rising edge of the bus signal that follows the falling edge; in response to determining to enable the slew rate control on the rising edge of the bus signal, enabling the slew rate control on the rising edge of the bus signal. further configured as follows:

12. The integrated circuit of claim 11.

15. determining to enable the slew rate control on the rising edge of the bus signal is independent of the predetermined threshold; 15. The integrated circuit of claim 14.

16. the voltage detector is further coupled to a driver in a cascade configuration; 12. The integrated circuit of claim 11.

17. The voltage detector further routes a feedback voltage to an input of the slew rate controller.

17. The integrated circuit of claim 16.

18. the voltage detector is further coupled to a driver in a non-cascaded configuration; 12. The integrated circuit of claim 11.

19. The slew rate controller further reduces the slew rate on the particular portion of the falling edge of the bus signal.

12. The integrated circuit of claim 11.

20. receiving, via a signal path, a first signal associated with a first device and a second signal associated with a second device; detecting a voltage difference between a dominant level of the first signal and a dominant level of the second signal; generating a bus signal on the signal path based on the first signal and the second signal; adjusting a slew rate of the bus signal based on the voltage difference; A method comprising:

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