Voltage detection sensor, measuring device, and measurement method

Abstract

To provide an easily controlled voltage detection sensor, and a measuring device and a measurement method utilizing the voltage detection sensor.SOLUTION: Problems are solved by a voltage detection sensor (42) or the like having an integral circuit (51) that is disposed opposite to a measurement object (43), and generates integral signals (V2, V3, V4) by integrating current (I1) flowing to a measurement signal detection section (50) according to a potential difference between the measurement object (43), and the measurement signal detection section (50) to which a reference voltage (V7) is applied, a PWM signal generation circuit (54) for generating a PWM signal (V6) having a duty ratio corresponding to the voltages of the integral signals (V2, V3, V4), a booster circuit (57) that has a winding type transformer (70) and generates a reference voltage (V7) corresponding to the duty ratio of the PWM signal (V6), and an output processing circuit (58) for generating a voltage measurement signal (VS) on the basis of the reference voltage (V7).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a voltage detection sensor, a measuring device, and a measuring method, and more particularly to a voltage detection sensor, a measuring device, and a measuring method, which include a boost circuit having a wire-wound transformer. [Background technology]

[0002] Non-contact voltage detection sensors are widely used for measuring high-voltage AC power voltages, etc., because they can safely measure voltage without directly contacting the object being measured, and demand for them has been increasing in recent years. Figure 8 shows a schematic diagram of a measurement device 41 equipped with a voltage detection sensor 45 that has been used in the past.

[0003] When the measurement signal detector 50 of the voltage detection sensor 45 is brought close to the object to be measured 43 for capacitive coupling, a current I1 corresponding to the potential difference between the voltage V1 of the object to be measured 43 and the reference voltage V7 applied to the measurement signal detector 50 is generated in the measurement signal detector 50. This current I1 is converted into a voltage and integrated in the integrating circuit 51 to generate an integrated signal V2. The integrated signal V2 is input to the arithmetic circuit 47 via the insulating circuit 53 and the A / D conversion circuit 46, which generates a PWM signal V6 having a duty ratio corresponding to the voltage of the integrated signal V2. This PWM signal V6 is input to the boost circuit 48, which generates a reference voltage V7 corresponding to the duty ratio of the PWM signal V6.

[0004] The reference voltage V7 is fed back to the integrating circuit 51 and applied to the measurement signal detecting unit 50 via the integrating circuit 51. The reference voltage V7 is also input to the output processing circuit 58, where it is subjected to output signal processing, and is output as a voltage measurement signal VS for the voltage detection sensor 45. The voltage measurement signal VS is further subjected to signal processing and information processing in the measurement main unit 44, whereby the voltage V1 of the measurement object 43 is determined. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-3997 Summary of the Invention [Problem to be solved by the invention]

[0006] From the viewpoint of miniaturization, a piezoelectric transformer such as that disclosed in Patent Document 1 has generally been used in the boost circuit 48 of the voltage detection sensor 45. However, because a piezoelectric transformer utilizes the piezoelectric effect and electrostrictive effect of a dielectric, if the operating frequency (the frequency of the PWM signal V6) deviates from the resonant frequency of the piezoelectric transformer, no output voltage is generated. This necessitates frequency control, which poses a problem of difficult design.

[0007] An object of the present invention is to provide a voltage detection sensor that is easy to control, and a measurement device and a measurement method that utilizes the voltage detection sensor. [Means for solving the problem]

[0008] The above problem can be solved by a voltage detection sensor or the like that includes: an integration circuit that is arranged opposite the object to be measured and that generates an integrated signal by integrating a current flowing in the measurement signal detection unit in accordance with the potential difference between the object to be measured and a measurement signal detection unit to which a reference voltage is applied, a PWM signal generation circuit that generates a PWM signal having a duty ratio in accordance with the voltage of the integration signal, a boost circuit that includes a wire-wound transformer and generates a reference voltage in accordance with the duty ratio of the PWM signal, and an output processing circuit that generates a voltage measurement signal based on the reference voltage.By using a wire-wound transformer in the boost circuit, which has small changes in output voltage even when the operating frequency fluctuates, it is possible to provide a voltage detection sensor that is easy to control.

[0009] Here, the PWM signal generation circuit preferably includes a carrier signal generation circuit that generates a carrier signal having a periodic triangular waveform, and a comparison circuit that compares the voltage of the integrated signal with the voltage of the carrier signal to generate a PWM signal. Controlling a conventional boost circuit with a piezoelectric transformer requires digital signal processing to generate a PWM signal with minimal fluctuations in operating frequency. This requires A / D conversion of the integrated signal and generation of the PWM signal using an arithmetic circuit such as a microcomputer. This results in a complex circuit configuration, large phase delay, small phase margin, and an unstable feedback system. In contrast, a boost circuit with a wound transformer minimizes fluctuations in output voltage even with fluctuations in operating frequency. This allows the boost circuit to be controlled using a PWM signal generated by analog signal processing with a simple circuit configuration that compares a triangular wave and an integrated signal. Note that, in this application, "triangular waveform" or "triangular wave" refers to a triangular waveform or wave, including a sawtooth waveform.

[0010] The carrier signal preferably has a sawtooth waveform. In this case, the carrier signal has a sawtooth waveform with a steep fall and a gradual rise relative to the fall. The comparison circuit is a comparator having an inverting input and a non-inverting input, with the carrier signal input to the inverting input and the integral signal input to the non-inverting input. Alternatively, the carrier signal has a sawtooth waveform with a steep rise and a gradual fall relative to the rise. The comparison circuit is a comparator having an inverting input and a non-inverting input, with the carrier signal input to the non-inverting input and the integral signal input to the inverting input. Because the PWM signal transitions to a high level at the timing when the waveform changes sharply, the timing at which the PWM signal transitions to a high level can be constant regardless of the voltage of the integral signal. As a result, the voltage of the integral signal can be reflected in the reference voltage only when the PWM signal transitions to a low level, thereby reducing the phase delay of the feedback system and expanding the phase margin of the feedback system.

[0011] Furthermore, it is desirable for the voltage detection sensor to further include an amplitude limiting circuit that limits the amplitude of the integrated signal. Non-contact voltage detection sensors, due to the principle of capacitive coupling, cannot prevent excessive inputs that would destabilize the feedback system. When an excessively large voltage amplitude is input to the voltage detection sensor, the boost circuit cannot keep up, increasing the potential difference between the voltage being measured and the reference voltage, and increasing the amplitude of the signal transmitted through the feedback system. If this amplitude exceeds the allowable input / output range of the components constituting the feedback system, the feedback system becomes unstable. For example, the phase of the output relative to the input may be inverted, disrupting the feedback operation, or the delay until a component that exceeds the allowable input / output range returns to normal operation may become a phase delay in the feedback system, causing oscillation of the feedback system.

[0012] In the case of PWM signal generation using conventional digital signal processing, it was possible to limit the excessive amplitude in the calculation circuit in response to such excessive input. However, such limitation is difficult when PWM signal generation is performed using analog signal processing. For this reason, it is necessary to provide an amplitude limiting circuit to limit the amplitude of the integrated signal within a predetermined voltage range. By providing such an amplitude limiting circuit, it is possible to suppress excessive input and maintain the stability of the feedback system.

[0013] It is also desirable to further include an isolation circuit that electrically isolates the integrator circuit and the PWM signal generator circuit, and to provide an amplitude limiting circuit on the transmission path of the integrated signal between the integrator circuit and the isolation circuit. Since it is desirable to electrically isolate the integrator circuit and the PWM signal generator circuit, it is desirable to provide an isolation circuit on the transmission path of the integrated signal, but since isolation circuits formed by isolation amplifiers and the like are vulnerable to excessive input, it is possible to improve the stability of the feedback system by locating the amplitude limiting circuit on the transmission path closer to the input of the feedback system than the isolation circuit.

[0014] Furthermore, it is desirable for the amplitude limiting circuit to have voltage characteristics that transition continuously from the non-amplitude-limited region to the amplitude-limited region. This makes it possible to prevent the feedback system from becoming unstable due to discontinuous transitions. Here, "continuously transitioning voltage characteristics" means voltage characteristics that transition smoothly from the non-amplitude-limited region to the amplitude-limited region so that the voltage waveform of the integrated signal after amplitude limiting does not have any non-differentiable points.

[0015] The amplitude limiting circuit preferably includes an operational amplifier and two diodes arranged in series or parallel with opposite polarities between the inverting input and output of the operational amplifier, two diodes arranged in parallel with opposite polarities between the transmission path of the integrated signal and a constant voltage source, or an upper limit amplitude limiting circuit including a first operational amplifier and a first diode connected between the inverting input and output of the first operational amplifier, and a lower limit amplitude limiting circuit including a second operational amplifier and a second diode connected between the inverting input and output of the second operational amplifier. This configuration enables amplitude limiting with a simple circuit. The term "constant voltage source" refers to a voltage source with a constant voltage, and includes DC power supplies as well as ground.

[0016] The above problem can also be solved by a measurement device including the above-mentioned voltage detection sensor and a measurement main body that determines the voltage of the object to be measured based on the voltage measurement signal output from the voltage detection sensor.

[0017] Furthermore, the above-mentioned problems can also be solved by a method for measuring the voltage of an object to be measured using the above-mentioned measuring device, the method including the steps of capacitively coupling a measurement signal detection unit of the measuring device with the object to be measured, integrating a current flowing through the measurement signal detection unit in accordance with a potential difference between the object to be measured and the measurement signal detection unit to which a reference voltage is applied, generating an integrated signal, generating a PWM signal having a duty ratio in accordance with the voltage of the integrated signal, generating a reference voltage in accordance with the duty ratio of the PWM signal using a boost circuit including a wire-wound transformer, and determining the voltage of the object to be measured based on the reference voltage. In this case, the object to be measured is a conductor of a covered electric wire, and the capacitive coupling step preferably includes bringing the measurement signal detection unit close to the conductor of the covered electric wire via the insulating coating of the covered electric wire, and capacitively coupling the measurement signal detection unit with the conductor. [Effects of the Invention]

[0018] According to the present invention, it is possible to provide a voltage detection sensor that is easy to control, and a measurement device and a measurement method that utilizes the voltage detection sensor. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a schematic diagram illustrating the configuration of a voltage detection sensor and a measurement device according to the present invention. [Figure 2] FIG. 1 is a schematic diagram illustrating a boost circuit including a wire-wound transformer. [Figure 3] 1 is a configuration example of a PWM signal generating circuit. [Figure 4-1] 10 is a configuration example of an amplitude limiting circuit. [Figure 4-2] 10 is a configuration example of an amplitude limiting circuit. [Figure 5] FIG. 10 is an explanatory diagram of a phase delay. [Figure 6] FIG. 10 is an explanatory diagram of a phase margin. [Figure 7] 1 is a flowchart of a measurement method according to the present invention. [Figure 8] FIG. 1 is a schematic diagram illustrating the configuration of a conventional measuring device. DETAILED DESCRIPTION OF THE INVENTION

[0020] A voltage detection sensor 42 and a measurement device 40 according to an embodiment of the present invention will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing a state in which a measurement device 40 equipped with a voltage detection sensor 42 is capacitively coupled to a measurement target 43. The measurement target 43 is, for example, a coated electric wire having a conductor 43b that transmits AC power of 400 Vrms, 60 Hz, and an insulating coating 43a that coats the conductor 43b.

[0021] Measurement device 40 includes voltage detection sensor 42 and measurement main unit 44 connected to voltage detection sensor 42. When measurement signal detection unit 50 of voltage detection sensor 42 is placed facing and close to object of measurement 43, measurement signal detection unit 50 and object of measurement 43 are capacitively coupled. Voltage detection sensor 42 generates voltage measurement signal VS from current I1 that flows through measurement signal detection unit 50 due to capacitive coupling. Measurement main unit 44 receives voltage measurement signal VS and performs signal processing and information processing to determine voltage V1 of object of measurement 43.

[0022] The voltage detection sensor 42 includes a measurement signal detection unit 50, an integration circuit 51 connected to the measurement signal detection unit 50 and a boost circuit 57, an amplitude limiting circuit 52 connected to the integration circuit 51, an insulation circuit 53 connected to the amplitude limiting circuit 52, a PWM signal generation circuit 54 connected to the insulation circuit 53, a boost circuit 57 connected to the PWM signal generation circuit 54, and an output processing circuit 58 connected to the boost circuit 57. A feedback system including the integration circuit 51, the amplitude limiting circuit 52, the insulation circuit 53, the PWM signal generation circuit 54, and the boost circuit 57 is formed within the voltage detection sensor 42.

[0023] A reference voltage V7 is applied to the measurement signal detection unit 50 via an integration circuit 51, and a current I1 is generated whose magnitude corresponds to the potential difference between the voltage V1 of the capacitively coupled measurement object 43 and the reference voltage V7 (more precisely, whose magnitude corresponds to the potential difference and the coupling capacitance C0 between the measurement signal detection unit 50 and the measurement object 43).

[0024] The integration circuit 51 receives a reference voltage V7 from the boost circuit 57 and applies it to the measurement signal detection unit 50. It also converts the current I1 flowing through the measurement signal detection unit 50 into a current-voltage signal and integrates it to generate an integrated signal V2. The amplitude limiting circuit 52 is a voltage limiter circuit that limits the amplitude of the input signal. It receives the integrated signal V2 from the integration circuit 51 and generates an amplitude-limited integrated signal V3 if the voltage of the integrated signal V2 exceeds a predetermined amplitude. The isolation circuit 53 is a circuit that electrically isolates signals between input and output and transmits signals. It receives the amplitude-limited integrated signal V3 from the amplitude limiting circuit 52 and generates an integrated signal V4 electrically isolated from the integrated signal V3. The isolation circuit 53 can be configured, for example, with an isolation amplifier or a photocoupler.

[0025] Since amplitude limiting circuit 52 is a circuit for maintaining the stability of the feedback system, it is sufficient if it is provided on the transmission path of integrated signals V2, V3, and V4 between integrating circuit 51 and PWM signal generating circuit 54. However, from the viewpoint of suppressing the effects of excessive input, it is desirable to provide it on the transmission path as close as possible to the input of the feedback system, i.e., to integrating circuit 51. In particular, because the components that make up isolation circuit 53 are often vulnerable to excessive input, it is desirable to provide amplitude limiting circuit 52 on the transmission path of the integrated signal between integrating circuit 51 and isolation circuit 53. For this reason, measuring device 40 provides amplitude limiting circuit 52 between integrating circuit 51 and isolation circuit 53.

[0026] The PWM signal generation circuit 54 receives the integrated signal V4 and generates a PWM signal V6 having a duty cycle corresponding to the voltage of the integrated signal V4. The PWM signal V6 is a binary signal that takes on a high or low voltage level. The PWM signal generation circuit 54 includes a carrier signal generation circuit 55 and a comparison circuit 56 connected to the isolation circuit 53, the carrier signal generation circuit 55, and the boost circuit 57. The carrier signal generation circuit 55 generates a carrier signal V5 having a periodic triangular waveform. The comparison circuit 56 compares the voltage of the integrated signal V4 with the voltage of the carrier signal V5 to generate the PWM signal V6. Because the voltage comparison can be performed using a comparator, the PWM signal can be generated using analog signal processing with a simple circuit configuration. Furthermore, the simple circuit configuration results in little phase delay, enabling an expanded phase margin in the feedback system.

[0027] The boost circuit 57 is a flyback converter that receives the PWM signal V6 and generates a reference voltage V7 according to the duty ratio of the PWM signal V6. Fig. 2 shows a schematic configuration example of the boost circuit 57. The boost circuit 57 includes a wound transformer 70, and a constant voltage V0 is applied to the primary winding of the wound transformer 70 via a switch 71. The switch 71 is controlled to open or close by the PWM signal V6 generated by the PWM signal generating circuit 54, and controls the conduction between the input of the constant voltage V0 and the primary winding of the transformer 70. The switch 71 can be configured using a bipolar transistor, a MOSFET, or the like.

[0028] A rectifier circuit 72 is connected to the secondary winding of the wound transformer 70, and a reference voltage V7 is output from the rectifier circuit 72. The rectifier circuit 72 includes a diode 73 and a capacitor 74. The anode of the diode 73 is connected to one end of the secondary winding of the wound transformer 70, and the cathode is connected to one end of the capacitor 74. The other end of the capacitor 74 is connected to the other end of the secondary winding of the wound transformer 70, and the voltage generated across the terminals of the capacitor 74 becomes the reference voltage V7.

[0029] The operating principle of boost circuit 57 is as follows. First, when switch 71 is turned on, current flows through the primary winding, and the magnetic flux generated magnetizes the core, storing energy. At this time, because diode 73 is facing in the opposite direction, no induced current flows through the secondary winding. Next, when switch 71 is turned off, the energy stored in the core is released, and current flows through diode 73. This current is rectified and smoothed by diode 73 and capacitor 74 to generate reference voltage V7. By using wire-wound transformer 70 in boost circuit 57, which exhibits little change in output voltage even when the operating frequency fluctuates, it is possible to provide a voltage detection sensor 42 that is easy to control.

[0030] The output processing circuit 58 includes a voltage dividing circuit, a buffer circuit, etc., receives the reference voltage V7, performs output signal processing such as voltage division and buffering, and generates a voltage measurement signal VS based on the reference voltage V7.

[0031] Next, a configuration example of the PWM signal generation circuit 54 is shown in Fig. 3. As described above, the PWM signal generation circuit 54 includes a carrier signal generation circuit 55 that generates a carrier signal V5 having a periodic triangular waveform, and a comparison circuit 56 that compares the voltage of the integrated signal V4 with the voltage of the carrier signal V5 to generate a PWM signal V6. In the configuration example shown in Fig. 3, a triangular wave having a periodic sawtooth waveform is used as the carrier signal V5, and comparators 56a and 56b are used as the comparison circuit 56.

[0032] 3(a), a carrier signal generation circuit 55a generates a carrier signal V5 having a sawtooth waveform with a steep drop and a gradual rise. A comparator 56a receives the carrier signal V5 as an inverting input and the integrated signal V4 as an input to a non-inverting input. The comparator 56a compares the voltage of the integrated signal V4 with the voltage of the carrier signal V5. If the voltage of the carrier signal V5 is smaller than the voltage of the integrated signal V4, the comparator 56a generates a high-level PWM signal V6 (a voltage that turns on the switch 71 of the voltage boost circuit 57). If the voltage of the carrier signal V5 is equal to or greater than the voltage of the integrated signal V4, the comparator 56a generates a low-level PWM signal V6 (a voltage that turns off the switch 71 of the voltage boost circuit 57).

[0033] 3(b), a carrier signal generation circuit 55b generates a carrier signal V5 with a sawtooth waveform that rises sharply and then falls gently. A comparator 56b receives the carrier signal V5 at its non-inverting input and the integrated signal V4 at its inverting input. The comparator 56b compares the voltage of the integrated signal V4 with the voltage of the carrier signal V5. If the voltage of the carrier signal V5 is greater than the voltage of the integrated signal V4, the comparator 56b generates a high-level PWM signal V6 (a voltage that turns on the switch 71 of the voltage boost circuit 48). If the voltage of the carrier signal V5 is equal to or less than the voltage of the integrated signal V4, the comparator 56b generates a low-level PWM signal V6 (a voltage that turns off the switch 71 of the voltage boost circuit 48).

[0034] In either configuration example, the PWM signal V6 transitions to high level at the timing when the waveform changes sharply, so the timing when the PWM signal V6 transitions to high level can be kept constant regardless of the voltage of the integral signal V4. As a result, the voltage of the integral signal V4 can be reflected in the reference voltage V7 only at the time when the PWM signal V6 transitions to low level, making it possible to reduce the phase delay of the feedback system and expand the phase margin of the feedback system.

[0035] Next, configuration examples of the amplitude limiting circuit 52 will be described with reference to FIGS. 4-1 and 4-2. FIGS. 4(a) and 4(b) show configuration examples of an amplitude limiting circuit including two diodes arranged in parallel with opposite polarities between the transmission path 90 of the integrated signal V2 and a constant voltage source (Vdd or GND). The amplitude limiting circuit 52a in FIG. 4(a) includes a resistor 91a and two diodes 91b and 91c. One end of the resistor 91a is connected to the input of the amplitude limiting circuit 52a, and the other end is connected to one end of the two diodes 91b and 91c and the output of the amplitude limiting circuit 52a. The anode of the diode 91b is connected to ground GND, and the cathode is connected to the other end of the resistor 91a on the transmission path 90 of the integrated signal. This diode 91b limits negative voltages whose absolute value exceeds the forward voltage (lower limit of amplitude). The diode 91c has a cathode connected to the ground GND and an anode connected to the other end of the resistor 91a on the integrated signal transmission line 90, and limits the positive voltage that exceeds the forward voltage (upper limit of amplitude).

[0036] 4(b) includes a resistor 92a and two diodes 92b and 92c. One end of the resistor 92a is connected to the input of the amplitude limiting circuit 52b, and the other end is connected to one end of the two diodes 92b and 92c and the output of the amplitude limiting circuit 52b. The cathode of the diode 92b is connected to the constant voltage source Vdd, and the anode is connected to the other end of the resistor 92a on the integrated signal transmission path 90. This limits a positive voltage that exceeds the forward voltage of the constant voltage source Vdd (the upper limit of the amplitude). The anode of the diode 92c is connected to ground GND, and the cathode is connected to the other end of the resistor 91a on the integrated signal transmission path 90. This limits a negative voltage whose absolute value exceeds the forward voltage (the lower limit of the amplitude).

[0037] The amplitude limiting circuits 52c and 52d in Figures 4(c) and 4(d) each include an operational amplifier and two diodes arranged in series or parallel with opposite polarities between the inverting input and output of the operational amplifier. The amplitude limiting circuit 52c in Figure 4(c) includes an operational amplifier 93e, a resistor 93a connected between the inverting input of the operational amplifier 93e and the input of the amplitude limiting circuit 52c, a resistor 93b connected between the inverting input and output of the operational amplifier 93e, and two diodes 93c and 93d connected in series between the inverting input and output of the operational amplifier 93e. The non-inverting input of the operational amplifier 93e is connected to ground GND, and the output of the operational amplifier 93e is connected to the output of the amplitude limiting circuit 52c. The anode of the diode 93c is connected to the inverting input of the operational amplifier 93e and the cathode is connected to the cathode of the diode 93d. Diode 93d is a Zener diode, with its anode connected to the output of operational amplifier 93e and its cathode connected to the cathode of diode 93c. The forward voltage of diode 93c and the breakdown voltage of diode 93d set the upper and lower limits of the amplitude of integrated signal V2.

[0038] The amplitude limiting circuit 52d shown in FIG. 4(d) includes an operational amplifier 94e, a resistor 94a connected between the inverting input of the operational amplifier 94e and the input of the amplitude limiting circuit 52, a resistor 94b connected between the inverting input and output of the operational amplifier 94e, and two diodes 94c and 94d connected in parallel between the inverting input and output of the operational amplifier 94e. The non-inverting input of the operational amplifier 94e is connected to ground GND, and the output of the operational amplifier 94e is connected to the output of the amplitude limiting circuit 52d. The anode of the diode 94c is connected to the inverting input of the operational amplifier 93e and the cathode is connected to the output of the operational amplifier 94e. The anode of the diode 94d is connected to the output of the operational amplifier 94e and the cathode is connected to the inverting input of the operational amplifier 94e. The forward voltages of the diodes 94c and 94d set the upper and lower limits of the amplitude of the integrated signal V2.

[0039] 4(e) shows an amplitude limiting circuit 52e that includes a resistor 97 arranged in series with a transmission path 90 for the integrated signal between the input and output, and a lower-limit amplitude limiting circuit 95 and an upper-limit amplitude limiting circuit 96 connected to the transmission path 90. The lower-limit amplitude limiting circuit 95 includes an operational amplifier 95a, a constant voltage source 95c connected to the non-inverting input of the operational amplifier 95a, and a diode 95b connected between the output of the operational amplifier 95a and the transmission path 90. The anode of the diode 95b is connected to the output of the operational amplifier 95a, and the cathode is connected to the transmission path 90. The inverting input of the operational amplifier 95a is connected to the transmission path 90. The lower-limit amplitude limiting circuit 95 sets the lower limit of the amplitude of the integrated signal V2 by setting the voltage of the constant voltage source 95c.

[0040] The upper limit amplitude limiting circuit 96 includes an operational amplifier 96a, a constant voltage source 96c connected to the non-inverting input of the operational amplifier 96a, and a diode 96b connected between the output of the operational amplifier 96a and the transmission line 90. The diode 96b has a cathode connected to the output of the operational amplifier 96a and an anode connected to the transmission line 90. The inverting input of the operational amplifier 96a is connected to the transmission line 90. The upper limit amplitude limiting circuit 96 sets the upper limit of the amplitude of the integrated signal V2 by setting the voltage of the constant voltage source 96c.

[0041] The circuit configuration of the amplitude limiting circuit 52 shown in Figures 4(a) to 4(e) enables amplitude limiting with a simple circuit. Note that discontinuous amplitude limiting characteristics, i.e., a discontinuous transition from the non-amplitude-limiting region to the amplitude-limiting region, can cause the feedback system to become unstable. Therefore, it is desirable for the amplitude limiting circuit to have voltage characteristics that transition continuously from the non-amplitude-limiting region to the amplitude-limiting region. For example, the circuits of Figures 4(a) to 4(d) have voltage characteristics that transition continuously from the non-amplitude-limiting region to the amplitude-limiting region, while the circuit of Figure 4(e) has discontinuous voltage characteristics that are close to the characteristics of an ideal diode. For this reason, among the circuit configuration examples described above, the circuits of Figures 4(a) to 4(d), especially the circuit of Figure 4(d), which allows for easy setting of the upper and lower voltage limits, are desirable.

[0042] Next, a measurement method according to an embodiment of the present invention will be described with reference to Fig. 7. First, the measurement signal detection unit 50 of the measurement device 40 is capacitively coupled to the object to be measured 43 (step 80). In the embodiment shown in Fig. 1, to measure the voltage V1 of the conductor 43b of the insulated electric wire 43, the measurement signal detection unit 50 is clamped to the insulating coating 43a of the insulated electric wire 43, and the measurement signal detection unit 50 is brought close to the conductor 43b of the insulated electric wire 43 via the insulating coating 43a of the insulated electric wire 43, thereby capacitively coupling the measurement signal detection unit 50 to the conductor 43b.

[0043] Next, the integration circuit 51 integrates the current I1 flowing through the measurement signal detection unit 50 in accordance with the potential difference between the conductor 43b being measured and the measurement signal detection unit 50 to which the reference voltage V7 is applied, to generate an integrated signal V2 (step 81).Then, the amplitude limiting circuit 52 limits the amplitude of the integrated signal V2 to within a predetermined voltage range to generate an amplitude-limited integrated signal V3 (step 82).The amplitude-limited integrated signal V3 is then used by the isolation circuit 53 to generate an integrated signal V4 electrically isolated from the integrated signal V3 (step 83).

[0044] Next, the PWM signal generation circuit 54 generates a PWM signal V6 having a duty ratio corresponding to the voltage of the electrically separated integrated signal V4 (step 84). In step 84, the carrier signal generation circuit 55 generates a carrier signal V5 having a periodic triangular waveform, and the comparison circuit 56 compares the voltage of the integrated signal V4 with the voltage of the carrier signal V5 to generate the PWM signal V6.

[0045] Next, the boost circuit 57, which includes the wound transformer 70, generates a reference voltage V7 corresponding to the duty ratio of the PWM signal V6 (step 85).Then, the output processing circuit 58 generates a voltage measurement signal VS based on the reference voltage V7 (step 86).Finally, the measurement main unit 44 determines the voltage V1 of the object to be measured 43 based on the voltage measurement signal VS (step 87).

[0046] Figure 5 shows the phase delay of the feedback system for PWM signal generation using conventional digital signal processing and PWM signal generation using analog signal processing according to the present invention. In the figure, the horizontal axis represents time and the vertical axis represents the voltages of the signals used to generate the PWM signal and the input / output signals of the boost circuit. Figure 5(a) shows the timing of PWM signal generation using conventional digital signal processing in the conventional measuring device 41 shown in Figure 8, and Figure 5(b) shows the timing of PWM signal generation using analog signal processing in the PWM signal generating circuit 54 of the measuring device 40 according to the present invention shown in Figure 3(b).

[0047] First, in the case of the conventional measuring device 41 (PWM signal generation by digital signal processing) shown in FIG. 5(a), when an integrated signal V4 is input to an A / D conversion circuit 46 at time t0, an arithmetic circuit 47 generates a PWM signal V6 by digital signal processing based on the converted digital signal D. The PWM signal V6 goes high at time t1 and then goes low at time t2. When the generated PWM signal V6 controls the opening and closing of a switch 71 in a voltage boost circuit 48, the energy stored in the core is released after the switch 71 turns off, causing the reference voltage V7 to rise at time t3. Therefore, the phase delay between the integrated signal V4 and the reference voltage V7 is the sum of the conversion and arithmetic time A (= t1 - t0) required from A / D conversion to the generation of the PWM signal, the time B (= t2 - t1) required to store energy in the core of the voltage boost circuit 48, and the time C (= t3 - t2) required to release the energy.

[0048] In contrast, in the case of the measuring device 40 (PWM signal generation by analog signal processing) according to the present invention shown in FIG. 5(b), when the carrier signal V5 drops sharply at time t1, the voltage of the carrier signal V5 becomes lower than the voltage of the integrated signal V4, causing the PWM signal V6 to go high. Thereafter, the carrier signal V5 rises gradually. At time t2, when the voltage of the carrier signal V5 exceeds the voltage of the integrated signal V4, the PWM signal V6 inverts and goes low. When the switch 71 of the boost circuit 57 is controlled by the PWM signal V6 having such a waveform, the energy stored in the core is released after the switch 71 is turned off, causing the reference voltage V7 to rise at time t3. The phase delay between the integrated signal V4 and the reference voltage V7 is only the time C (= t3 - t2) required for the energy release. Thus, PWM signal generation by analog signal processing can significantly reduce the phase delay compared to PWM signal generation by digital signal processing.

[0049] Figure 6 shows the frequency characteristics of the phase margin of the feedback system of the measuring device and voltage detection sensor for PWM signal generation using conventional digital signal processing and PWM signal generation using analog signal processing. Figure 6(a) shows the frequency characteristics of the gain and phase of the feedback system of the measuring device 41 and voltage detection sensor 45 using conventional digital signal processing as shown in Figure 8, while Figure 6(b) shows the frequency characteristics of the gain and phase of the feedback system of the measuring device 40 and voltage detection sensor 42 using analog signal processing as shown in Figure 1 according to the present invention. In both figures, the horizontal axis represents frequency and the vertical axis represents gain and phase, with gain indicated by a solid line and phase indicated by a dashed line. As indicated by the dot-dash circle in the figure, it can be seen that the measuring device 40 and voltage detection sensor 42 using analog signal processing has a larger phase margin and a wider bandwidth.

[0050] As is clear from the above, by configuring a voltage detection sensor and a measurement device using a boost circuit with a wire-wound transformer, it is possible to provide a voltage detection sensor and a measurement device that exhibits minimal change in output voltage even when the operating frequency fluctuates, and that is easy to control. Furthermore, by utilizing the characteristic of minimal change in output voltage even when the operating frequency fluctuates, it is possible to generate a PWM signal using analog signal processing, thereby reducing the phase delay of the feedback system in the voltage detection sensor and the measurement device and expanding the phase margin. In particular, when a PWM signal is generated using a sawtooth waveform as the carrier signal, the PWM signal goes high when the waveform changes sharply, making the timing at which the PWM signal goes high constant regardless of the voltage magnitude of the integral signal. As a result, the voltage magnitude of the integral signal can be reflected in the reference voltage only when the PWM signal transitions to low, thereby reducing the phase delay of the feedback system and expanding the phase margin of the feedback system.

[0051] The above describes the voltage detection sensor, measurement device, and measurement method according to the present invention, but the present invention is not limited to the above-described embodiments and includes all aspects included in the concept of the present invention and the scope of the claims. [Explanation of symbols]

[0052] 40, 41 Measuring equipment 42, 45 Voltage detection sensor 43 Measurement target (coated wire) 43a Insulation coating 43b Conductor 44 Measurement main body 46 A / D conversion circuit 47 Arithmetic circuit 48, 57 Boost circuit 50 Measurement signal detection unit 51 Integrating circuit 52, 52a, 52b, 52c, 52d, 52e Amplitude limiting circuits 53 Insulation Circuit 54 PWM signal generation circuit 55, 55a, 55b Carrier signal generation circuit 56 Comparison circuit 56a, 56b Comparators 58 Output processing circuit 70 Wire-wound transformer 71 Switch 72 Rectifier circuit 73, 91b, 91c, 92b, 92c, 93c, 93d, 94c, 94d, 95b, 96b diodes 74 Capacitor 90 Transmission Line 91a, 92a, 93a, 93b, 94a, 94b, 97 resistance 93e, 94e, 95a, 96a Op-amps 95 Lower limit amplitude limiting circuit 95c, 96c constant voltage source 96 Upper limit amplitude limiting circuit

Claims

1. an integration circuit disposed opposite to the object to be measured, which integrates a current flowing in the measurement signal detection unit in accordance with a potential difference between the object to be measured and a measurement signal detection unit to which a reference voltage is applied, to generate an integrated signal; a PWM signal generating circuit that generates a PWM signal having a duty ratio corresponding to the voltage of the integrated signal; a boost circuit including a wound transformer and generating the reference voltage according to the duty ratio of the PWM signal; an output processing circuit that generates a voltage measurement signal based on the reference voltage; A voltage detection sensor comprising:

2. The PWM signal generating circuit a carrier signal generating circuit that generates a carrier signal having a periodic triangular waveform; a comparison circuit that compares the voltage of the integrated signal with the voltage of the carrier signal to generate the PWM signal; The voltage detection sensor according to claim 1 , comprising:

3. The voltage detection sensor according to claim 2 , wherein the carrier signal has a sawtooth waveform.

4. the carrier signal has a sawtooth waveform with a steep fall and a gradual rise relative to the fall, the comparison circuit is a comparator having an inverting input and a non-inverting input, the carrier signal is input to the inverting input, and the integrated signal is input to the non-inverting input; The voltage detection sensor according to claim 3 .

5. the carrier signal has a sawtooth waveform that rises sharply and falls gently relative to the rise, the comparison circuit is a comparator having an inverting input and a non-inverting input, the carrier signal is input to the non-inverting input, and the integrated signal is input to the inverting input; The voltage detection sensor according to claim 3 .

6. The voltage detection sensor according to claim 1 , further comprising an amplitude limiting circuit that limits the amplitude of the integrated signal.

7. further comprising an isolation circuit that electrically isolates the integrating circuit from the PWM signal generating circuit; the amplitude limiting circuit is provided on a transmission path of the integrated signal between the integrating circuit and the insulating circuit.

7. The voltage detection sensor according to claim 6.

8. 7. The voltage detection sensor according to claim 6, wherein the amplitude limiting circuit has a voltage characteristic that transitions continuously from a non-amplitude-limited region to an amplitude-limited region.

9. 7. The voltage detection sensor according to claim 6, wherein the amplitude limiting circuit comprises two diodes arranged in parallel with each other and having opposite polarities between a transmission line of the integral signal and a constant voltage source.

10. 7. The voltage detection sensor according to claim 6, wherein the amplitude limiting circuit comprises an operational amplifier and two diodes arranged in series or in parallel with each other so that their polarities are opposite to each other between the inverting input and the output of the operational amplifier.

11. The amplitude limiting circuit an upper limit amplitude limiting circuit including a first operational amplifier and a first diode connected between the inverting input and the output of the first operational amplifier; a lower limit amplitude limiting circuit including a second operational amplifier and a second diode connected between the inverting input and the output of the second operational amplifier; The voltage detection sensor according to claim 6 , comprising:

12. The voltage detection sensor according to any one of claims 1 to 11, a measurement main body that determines the voltage of the measurement object based on the voltage measurement signal output from the voltage detection sensor; A measuring device comprising:

13. A method for measuring a voltage of an object to be measured by the measurement device according to claim 12, comprising: capacitively coupling a measurement signal detection unit of the measurement device with the object to be measured; a step of integrating a current flowing through the measurement signal detection unit, which is disposed opposite the object to be measured, in accordance with a potential difference between the object to be measured and the measurement signal detection unit to which a reference voltage is applied, to generate an integrated signal; generating a PWM signal having a duty ratio corresponding to the voltage of the integrated signal; generating the reference voltage according to the duty ratio of the PWM signal by a boost circuit including a wire-wound transformer; determining a voltage of the object to be measured based on the reference voltage; , including, a measurement method.

14. The measurement object is a conductor of a coated electric wire, the capacitive coupling step includes a step of bringing the measurement signal detection unit close to the conductor of the insulated electric wire via the insulating coating of the insulated electric wire, and capacitively coupling the measurement signal detection unit and the conductor. The measurement method according to claim 13.

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