Photoelectric conversion device, equipment, and mobile unit

Abstract

To provide a photoelectric conversion device capable of improving image quality, in the photoelectric conversion device obtained by laminating a plurality of boards.SOLUTION: The photoelectric conversion device according to an embodiment comprises two or more boards of a first board having a pixel unit in which a plurality of pixels each including a photoelectric conversion unit and an amplification transistor is arranged in an array state and a second board having a memory for holding an analog signal output by the pixel unit. On a board different from the first board out of the two or more boards, there are arranged a current source and a transistor for clipping the electric potential of a node connected to the node through which signals output from the current source and the amplification transistor pass.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, a device, and a mobile object. [Background technology]

[0002] Patent Document 1 describes a photoelectric conversion device in which multiple substrates are stacked. The photoelectric conversion device in Patent Document 1 discloses a configuration in which a first substrate on which a photodiode (PD) and an amplification transistor are arranged has a clipping transistor that clips the signal output from a pixel readout circuit so that it does not fall below a predetermined voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 062935 Summary of the Invention [Problem to be solved by the invention]

[0004] In order to improve the image quality of a photoelectric conversion device, it is necessary to efficiently arrange the transistors while ensuring the area for arranging the PD and amplifying transistor that make up one pixel. However, in the photoelectric conversion device of Patent Document 1, the clipping transistor is arranged on the first substrate where the PD and amplifying transistor are arranged, which reduces the area available for arranging the PD and amplifying transistor, and it may not be possible to improve the image quality.

[0005] An object of the present invention is to provide a photoelectric conversion device in which a plurality of substrates are stacked, which can improve image quality. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device comprising at least two substrates: a first substrate having a pixel section in which a plurality of pixels, each of which includes a photoelectric conversion element and an amplification transistor, are arranged in an array; and a second substrate having a memory section that stores an analog signal output by the pixel section, wherein a current source and a transistor that clips the potential of a node connected to a node through which a signal output from the current source and the amplification transistor passes are arranged on a substrate different from the first substrate out of the at least two substrates. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a photoelectric conversion device capable of improving image quality. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 2] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 3] FIG. 2 is a circuit diagram showing a pixel section, a pixel memory section, and a part of a signal processing section in the block diagram illustrating the photoelectric conversion device according to the first embodiment. [Figure 4] FIG. 2 is a voltage switching circuit diagram for a voltage input to a gate of a clip transistor according to the first embodiment. [Figure 5] FIG. 3 is a diagram illustrating an image of scanning in the row direction with respect to time in the photoelectric conversion device according to the first embodiment. [Figure 6] FIG. 2 is an image diagram showing divided regions of the photoelectric conversion device according to the first embodiment. [Figure 7] FIG. 3 is a timing chart showing region selection in the photoelectric conversion device according to the first embodiment. [Figure 8] FIG. 3 is a timing chart of a pixel memory writing period of the photoelectric conversion device according to the first embodiment. [Figure 9] FIG. 3 is a timing chart of a pixel memory readout period of the photoelectric conversion device according to the first embodiment. [Figure 10]FIG. 10 is a circuit diagram showing a pixel section, a pixel memory section, and a part of a signal processing section in a block diagram illustrating a photoelectric conversion device according to a second embodiment. [Figure 11] 10 shows a voltage switching circuit for switching a voltage input to a gate of a transistor of a photoelectric conversion device according to a second embodiment. [Figure 12] FIG. 10 is a timing chart of a pixel memory writing period of the photoelectric conversion device according to the second embodiment. [Figure 13] FIG. 10 is a timing chart of a pixel memory readout period of the photoelectric conversion device according to the second embodiment. [Figure 14] FIG. 11 is a circuit diagram of a part of a signal processing unit of a photoelectric conversion device according to a third embodiment. [Figure 15] FIG. 10 is a schematic diagram illustrating a device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment will be described below with reference to the drawings. Note that the following embodiments do not limit the scope of the claimed invention. Although multiple features are described in the embodiments, not all of these features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar components are given the same reference numerals, and redundant description will be omitted. Also, in the following embodiments, an imaging sensor will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to an imaging sensor and can be applied to other examples of photoelectric conversion devices. Examples include an imaging device, a range finder (a device for measuring distance using focus detection or TOF (Time Of Flight)), and a photometric device (a device for measuring the amount of incident light).

[0010] In this specification, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) are used as necessary. The use of these terms is for the purpose of facilitating understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0011] In this specification, the phrase "electrically connecting component A and component B" does not necessarily mean that component A and component B are directly connected. For example, even if another component C is connected between component A and component B, it is acceptable as long as they are electrically connected.

[0012] In this specification, "plane" refers to a surface parallel to the main surface of a substrate. The main surface of a substrate may be the light incident surface of a substrate including a photoelectric conversion element, a surface on which multiple ADCs are repeatedly arranged, or a bonding surface between substrates in a stacked photoelectric conversion device. Furthermore, "planar view" refers to a view from a direction perpendicular to the main surface of the substrate. Furthermore, "cross section" refers to a surface perpendicular to the light incident surface of a semiconductor layer. Furthermore, "cross section" refers to a view from a direction parallel to the main surface of the substrate.

[0013] Metallic components such as wiring and pads described herein may be composed of a single metal element or a mixture (alloy). For example, wiring described as copper wiring may be composed of copper alone or may be composed primarily of copper with other components. Furthermore, for example, pads connected to external terminals may be composed of aluminum alone or may be composed primarily of aluminum with other components. The copper wiring and aluminum pads shown here are merely examples and can be replaced with various metals. Furthermore, the wiring and pads shown here are merely examples of metallic components used in photoelectric conversion devices and may also be applied to other metallic components.

[0014] (First embodiment) A photoelectric conversion device according to a first embodiment of the present invention, which is a photoelectric conversion device 10, will be specifically described with reference to FIGS. 1 to 9. FIG.

[0015] Fig. 1 is a schematic diagram of an example of a photoelectric conversion device 10 according to this embodiment. As shown in Fig. 1, the photoelectric conversion device 10 has a three-dimensional structure formed by stacking and bonding multiple substrates. The photoelectric conversion device 10 includes three substrates: a first substrate 100, a second substrate 200, and a third substrate 300. The third substrate 300, the second substrate 200, and the first substrate 100 are stacked in this order.

[0016] The first substrate 100, the second substrate 200, and the third substrate 300 may each include a semiconductor substrate such as a silicon substrate and a wiring structure. The first substrate 100, the second substrate 200, and the third substrate 300 may be approximately equal in size. The relationship of "approximately equal" here will be explained. Although they are designed to be equal, slight differences may occur due to manufacturing errors. This slight difference caused by manufacturing errors is included in the term "approximately equal."

[0017] The first substrate 100 has a pixel section 110, the second substrate 200 has a pixel memory section 210, and the third substrate 300 has a signal processing section 310. Each substrate may include a semiconductor layer such as silicon and a wiring layer. Each substrate may be in a wafer state or a chip state, but is preferably in a chip state.

[0018] FIG. 2 is an example of a block diagram of a photoelectric conversion device according to this embodiment. As shown in FIG. 2, the first substrate 100 has pixels 30, each including a photodiode (PD) and a pixel circuit, arranged two-dimensionally to form a pixel section 110. The pixel section 110 has a plurality of pixels 30 arranged in an array across multiple rows and multiple columns. The PD is a photoelectric conversion element that generates and accumulates signal charges corresponding to the amount of received light, and outputs an analog signal, which is a pixel signal corresponding to the amount of incident light. An externally input signal is input to the pixel control circuit 20, which outputs a control signal that controls the pixel vertical scanning circuit 120. The pixel vertical scanning circuit 120 then controls the pixel section 110. The output pixel signal is input from the first substrate 100 to the pixel memory 40 of the second substrate 200.

[0019] In this specification, the horizontal direction in the drawings is referred to as the row direction, and the vertical direction is referred to as the column direction. The number of rows and the number of columns of the multiple pixels 30 arranged in the pixel unit 110 are not particularly limited. The multiple pixels 30 may include effective pixels that output pixel signals according to the amount of incident light, as well as optical black pixels whose photoelectric conversion elements are shielded from light, dummy pixels that do not output signals, etc.

[0020] Furthermore, a plurality of control lines 103 are arranged in each row of the pixel section 110, extending in the row direction. Each of the plurality of control lines 103 is connected to a plurality of pixels 30 arranged in the row direction. One control line 103 commonly controls a plurality of pixels 30 arranged in each row. The pixel control circuit 20 is connected to a pixel vertical scanning circuit 120, and an externally input signal is input to the pixel control circuit 20. The pixel vertical scanning circuit 120 supplies a control signal to each pixel 30 via the control line 103. The pixel section 110, the pixel vertical scanning circuit 120, and the pixel control circuit 20 are supplied with a power supply voltage SVDD and a reference voltage SGND.

[0021] The second substrate 200 has a pixel memory unit 210. The pixel memories 40 are arranged in an array in a matrix corresponding to the pixels 30 of the first substrate, constituting the pixel memory unit 210. The pixel memory unit 210 includes a driving circuit such as a current source that writes pixel signals to the pixel memory 40, which will be described later. An externally input signal is input to a memory control circuit 21, which outputs a control signal that controls a memory vertical scanning circuit. The memory vertical scanning circuit then controls the pixel memory 40 of the pixel memory unit 210. The memory control circuit 21 is further input to a bias generation circuit 230, which controls the current value of a current source, which will be described later. The pixel memory 40 of the pixel memory unit 210 writes pixel signals output from the pixels 30 of the first substrate and reads pixel signals from the pixel memory 40. The read pixel signals are input to a signal processing circuit 50 on the third substrate 300.

[0022] The third substrate 300 has a signal processing unit 310. One signal processing circuit 50 is provided for each column of pixel memories 40 arranged two-dimensionally. In other words, the signal processing circuits 50 are arranged one-dimensionally in the column direction. Multiple signal processing circuits 50 are arranged side by side in the row direction to form the signal processing unit 310. The signal processing circuit 50 includes a comparator circuit that compares a reference voltage with pixel signals read from the pixel memories 40 of the second substrate, a drive circuit such as a current source, and an arithmetic processing circuit for data arithmetic processing, etc. The reference voltage may be a sloping voltage that changes over time, a voltage corresponding to successive approximation AD conversion, or a voltage corresponding to ΔΣ AD conversion.

[0023] A separate arithmetic processing circuit need not be provided for each column. For example, a configuration in which signals for each column are sequentially input to a single common arithmetic processing circuit may be used. Externally input signals are input to the signal processing control circuit 22, which controls the column control circuit 320, the ramp generator 340 that generates a reference voltage, and the bias generation circuit 330. The column control circuit 320, the ramp generator 340, and the bias generation circuit 330 then control the signal processing circuit 50. The controlled signal processing circuit 50 performs arithmetic processing based on pixel signals read from the pixel memory 40 on the second substrate and outputs the resulting signal to the outside via the output circuit. The output circuit includes a buffer amplifier, a differential amplifier, etc., and performs predetermined signal processing on the pixel signals output from the pixels 30 and outputs the processed image data. Examples of signal processing performed by the output circuit include correction processing using correlated double sampling (CDS) and amplification processing. The output circuit also includes a serial output circuit using a low-voltage differential signal (LVDS) system, which outputs the processed digital signal to the outside of the photoelectric conversion device at high speed and with low power consumption. The output method is not limited to LVDS, but may be other methods.

[0024] In this embodiment, a photoelectric conversion device having three stacked substrates has been described, but this is not limiting. A configuration having four or more stacked substrates, or a configuration having two stacked substrates, may also be used. Using multiple substrates allows for the arrangement of many circuit elements, such as transistors, per pixel, which has the advantage of enabling higher functionality, so it is preferable to have three or more stacked substrates. With reference to FIG. 3 , the circuit configuration will be described, including pixels 30 arranged on a semiconductor substrate serving as a first substrate, pixel memory 40 arranged on a semiconductor substrate serving as a second substrate, and a portion of the comparator circuit of signal processing circuit 50 arranged on a semiconductor substrate serving as a third substrate.

[0025] The pixel 30 includes at least PDs 115 and 116, a floating diffusion (FD), an amplifier transistor 111, and a reset transistor 112. The pixel 30 may further include transfer transistors 113 and 114, and a selection transistor 117.

[0026] One terminal of PD115 is connected to the SGND power supply line, and the other terminal is connected to the source or drain of the transfer transistor 113. Furthermore, one terminal of PD116 is connected to the SGND power supply line, and the other terminal is connected to one of the source or drain terminals of the transfer transistor 114. The transfer transistor 113 is controlled by supplying a control signal TXA to its gate, and the transfer transistor 114 is controlled by supplying a control signal TXB to its gate. The other of the source or drain terminals of the transfer transistors 113 and 114 is connected to FD.

[0027] The FD is connected to one of the source or drain terminals of the reset transistor 112. The reset transistor 112 is controlled by supplying a control signal RES to its gate. The other of the source or drain terminals of the reset transistor 112 is connected to the SVDD power supply line of the pixel power supply. The FD is also connected to the gate of the amplification transistor 111. One of the source or drain terminals of the amplification transistor 111 is connected to the SVDD power supply line, and the other of the source or drain terminals is connected to one of the source or drain terminals of the selection transistor 117. The selection transistor 117 is controlled by supplying a control signal SEL to its gate. In this embodiment, the amplification transistor 111 is a source follower transistor. The SGND voltage is, for example, 0 V, and the SVDD voltage is, for example, 3.5 V.

[0028] The other terminal of the source or drain of the selection transistor 117 is connected to a VREADP node (node) of the pixel memory unit 210 of the second substrate 200 from the pixel unit 110 of the first substrate 100 via a first connection unit 1-1. The first connection unit 1-1 is formed of wiring or the like that connects the pixel unit 110 and the pixel memory unit 210. For example, the first connection unit 1-1 is formed of a metal junction that contacts and bonds a metal portion (first metal portion) containing copper included in the wiring layer of the first substrate with a metal portion (second metal portion) containing copper included in the wiring layer of the second substrate. The first substrate 100 has a first insulating film arranged in the same layer as the wiring layer, and the second substrate 200 has a second insulating film arranged in the same layer as the wiring layer. In the photoelectric conversion device 10, a metal junction and a junction where the first insulating film and the second insulating film are joined are arranged at the bonding surfaces of the first substrate 100 and the second substrate 200. In this way, the first substrate 100 and the second substrate 200 are bonded together by hybrid bonding.

[0029] Note that the transfer transistors 113 and 114, the reset transistor 112, the amplification transistor 111, and the selection transistor 117 may each be an N-type MOS transistor or a P-type MOS transistor. In this embodiment, a case will be described in which electrons, of electron-hole pairs generated in the PD by incident light, are used as signal charges. When electrons are used as signal charges, each transistor included in the pixel 30 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, each transistor included in the pixel 30 may be configured as a P-type MOS transistor different from that described in this embodiment.

[0030] The VREADP node is connected to one of the source or drain terminals of a current source switch transistor 218. A control signal BLK is supplied to the gate of the current source switch transistor 218 to control it. The other of the source or drain terminal of the current source switch transistor 218 is connected to one of the source or drain terminals of a cascode transistor 216. Furthermore, the other of the source or drain terminal of the cascode transistor 216 is connected to one of the source or drain terminals of a pixel current source transistor 217. The cascode transistor 216 and the pixel current source transistor 217 are cascade-connected. A voltage VGATE1 controlled by a bias generation circuit 230 is input to the gate of the cascode transistor 216, and a voltage VBIAS1 controlled by the bias generation circuit 230 is input to the gate of the pixel current source transistor 217. Furthermore, the other of the source or drain terminal of the current source transistor 217 is connected to the AGND power supply line.

[0031] The VREADP node is connected to one of the sources or drains of sampling transistors 213, 214, and 215. The sampling transistor 213 is controlled by a control signal SWN supplied to its gate. The sampling transistor 214 is controlled by a control signal SWA supplied to its gate. The sampling transistor 215 is controlled by a control signal SWAB supplied to its gate. The other of the source or drain terminal of the sampling transistor 213 is connected to a hold capacitor CN, one terminal of which is connected to the MGND power line. The other of the source or drain terminal of the sampling transistor 214 is connected to a hold capacitor CA, one terminal of which is connected to the MGND power line. The other of the source or drain terminal of the sampling transistor 215 is connected to a hold capacitor CAB, one terminal of which is connected to the MGND power line. The MGND voltage is, for example, 0V.

[0032] The VREADP node is connected to one of the source and drain terminals of a reset transistor 212. The reset transistor 212 resets the read potential of the VREADP node. The reset transistor 212 is controlled by a control signal RESC supplied to its gate. The other of the source and drain terminals of the reset transistor 212 is connected to the MVDD power supply line. The MVDD voltage is, for example, 3.5 V.

[0033] The VREADP node is connected to one of the source and drain terminals of a clip transistor 220 (transistor). The clip transistor 220 is controlled by a control signal VCLIP supplied to its gate. The other of the source and drain terminals of the clip transistor 220 is connected to the MVDD power supply line.

[0034] Here, the control signal VCLIP input to the gate of the clip transistor 220 will be described with reference to FIG. 4. The gate of the clip transistor 220 is connected to a voltage switching circuit as shown in FIG. 4. The control signal VCLIP output from the voltage switching circuit is input to the gate of the clip transistor 220. In this embodiment, the voltage switching circuit has three switch transistors 401, 402, and 403. The switch transistor 401 is controlled by a control signal CLIPR supplied to its gate, and one terminal is connected to the GND power supply line (AGND). The switch transistor 402 is controlled by a control signal CLIPN supplied to its gate, and one terminal is connected to the VCLIPN voltage line. The switch transistor 403 is controlled by a control signal CLIIPS supplied to its gate, and one terminal is connected to the VCLIPS voltage line. The GND power supply voltage is, for example, 0 V, the VCLIPN voltage is, for example, 3.0 V, and the VCLIPS voltage is, for example, 1.0 V. As will be described later, it is preferable that the VCLIPN voltage and the VCLIPS voltage are different voltages, but they may be the same voltage. When the VCLIPN voltage and the VCLIPS voltage are connected, the VCLIP voltage is a different voltage, and the method for setting the voltages will be described later.

[0035] The VREADP node is connected to the gate of the amplifier transistor 211 (second amplifier transistor). One of the source and drain terminals of the amplifier transistor 211 is connected to the MVDD power supply line, and the other terminal is connected to one of the source and drain terminals of the selection transistor 219.

[0036] The other terminal of the source or drain of the selection transistor 219 is connected via a second connection portion 2-1 from the pixel memory unit 210 of the second substrate 200 to the VLOUT node of the signal processing unit 310 of the third substrate 300. The second connection portion 2-1 is formed of wiring connecting the pixel memory unit 210 and the signal processing unit 310. For example, the second connection portion 2-1 is formed of a metal junction portion that contacts and bonds a copper-containing metal portion included in the wiring layer of the second substrate with a copper-containing metal portion included in the wiring layer of the third substrate. The second substrate 200 also has a second insulating film disposed in the same layer as the wiring layer, and the third substrate 300 also has a third insulating film disposed in the same layer as the wiring layer. In the photoelectric conversion device 10, a junction portion is disposed at the bonding surface between the second substrate 200 and the third substrate 300, where the metal junction portion, the second insulating film, and the third insulating film are bonded. In this manner, the second substrate 200 and the third substrate 300 are bonded by hybrid bonding.

[0037] The VLOUT node (second node) is formed by readout lines 316 arranged in the row direction, and is selectively connected to a plurality of pixel memories 40 arranged in the row direction. The VLOUT node is also connected to one of the source or drain terminals of a current source switch transistor 315 (second transistor). The current source switch transistor 315 is controlled by a control signal BLKM supplied to its gate. The other of the source or drain terminal of the current source switch transistor 315 is connected to one of the source or drain terminals of the cascode transistor 313. The other of the source or drain terminal of the cascode transistor 313 is connected to one of the source or drain terminals of the current source transistor 314. The cascode transistor 313 and the current source transistor 314 are cascade-connected.

[0038] A signal VGATE2 controlled by the bias generation circuit 330 is input to the gate of the cascode transistor 313, and a signal VBIAS2 controlled by the bias generation circuit 330 is input to the gate of the current source transistor 314. The other terminal of the source or drain of the current source transistor 314 is connected to the AGND power supply line. The voltage of the AGND power supply line is common to the voltage of the AGND power supply line connected to the pixel current source transistor 217 configured on the second substrate 200 via the second connection part 2-2. The AGND voltage of the second substrate and the AGND voltage of the third substrate may be shared from a common pad.

[0039] The VLOUT node is connected to one differential input of a comparator circuit 311 that is connected to the AVDD power line and the AGND power line, and the other differential input receives a slope-shaped reference voltage RAMP generated by a ramp generator 340. Based on the comparison result of the comparator circuit 311, the image signal is converted from an analog signal to a digital signal and output to the outside.

[0040] As in this embodiment, by separating the SVDD power supply, MVDD power supply, AVDD power supply, SGND power supply, MGND power supply, AGND power supply, and GND power supply, the influence of power supply fluctuations on other circuits is less likely to extend. However, without being limited to this embodiment, each power supply may be connected to the same power supply.

[0041] Furthermore, in this embodiment, two PDs are connected to a common FD, but this is not limiting. For example, three or more PDs may be connected to a common FD, or one PD may be connected to one FD. The configuration of pixel 30 is merely an example, and pixel 30 may further include transistors. For example, a transistor that changes the capacitance value of the FD or a transistor that discharges charge from the PD may be further provided. Furthermore, pixel 30 may be configured without the selection transistor 117, and the selected / unselected state of pixel 30 may be changed depending on the voltage input from the reset transistor 112 to the FD.

[0042] The cascode transistors 216 and 313 are transistors that facilitate suppressing current changes due to fluctuations in the drain voltage of the current source transistor 217 and the current source transistor 314. Therefore, they may not be necessary if the influence of current changes due to drain voltage fluctuations is not a concern.

[0043] Next, specific circuit operations of the photoelectric conversion device will be described with reference to FIGS.

[0044] Figure 5(a) shows an example of scanning in the row direction over time. First, let us explain the periods. Period A is the accumulation period in which charge is accumulated in the PD after the shutter operation. Period B is the pixel memory write period in which the charge accumulated in the PD is converted into a voltage and the signal is written to the pixel memory. Period C is the pixel memory read period in which the signal is read from the pixel memory to the signal processing circuit. Next, we will explain scanning in the row direction.

[0045] In Figure 5(a), for multiple pixels arranged in multiple rows and multiple columns, periods A and B are the same period. A so-called global shutter operation is performed during periods A and B. Period C indicates that readout is performed sequentially for each column, in units of one or more rows.

[0046] As shown in Figures 5(b) and 5(c), periods A, B, and C may be shifted block by block. In this case, it is preferable to prevent period B, the pixel memory write period, from operating simultaneously in multiple blocks. In the circuit operation of Figure 5(b), there is a time when a block of a pixel memory write period and a block of a pixel memory read period operate simultaneously. Furthermore, in the circuit operation of Figure 5(c), after period B, the pixel memory write period, has ended for all blocks, period B, the pixel memory read period, is performed row-sequentially. The circuit operation of Figure 5(b) can shorten the time from the start of period A to the end of period C for all pixels compared to the circuit operation of Figure 5(c). On the other hand, in Figure 5(c), the time from the start of period A to the end of period C is longer than in the operation methods of Figures 5(a) and 5(b). However, in Figure 5(c), the pixel memory write period and the pixel memory read period do not overlap, which reduces degradation of image quality due to crosstalk caused by power supply fluctuations and other factors.

[0047] In the global shutter operation of this embodiment, a plurality of pixels 30 arranged in all rows may be driven simultaneously, or a block may be divided into a plurality of blocks each consisting of a plurality of pixels 30 arranged in a plurality of rows, and each block may be driven simultaneously. For example, as shown in FIG. 6, pixels in a plurality of rows and a plurality of columns may be grouped together and divided into N blocks (blk1, blk2, blk3, ..., blkN) and driven. For example, as shown in FIG. 7, the control signal SEL for the selection transistor 117 and the control signal BLK for the current source switch transistor 218 in FIG. 3 may be divided into BLK1 / SEL1, BLK2 / SEL2, ..., BLKN / SELN. Corresponding transistors may then be controlled using the control signals for each block. As shown in FIG. 7, signals from pixels included in each block may be processed on a block-by-block basis.

[0048] Next, referring to FIG. 8, a timing diagram of the pixel memory writing period B will be shown.

[0049] The accumulation period is up to just before time t1, and the pixel memory write period (period B) is from time t1 to time t10. First, just before time t1, the RES signal is at a High (H) level, so the reset transistor 112 is ON, and FD is set (reset) to the SVDD voltage. Also, the RESC signal input to the reset transistor 212 is at an H level, so the reset transistor 212 is ON, and the VREADP node is set to the MVDD voltage. Furthermore, the SWN signal input to the sampling transistor 213, the SWA signal input to the sampling transistor 214, and the SWAB signal input to the sampling transistor 215 are also at an H level. Therefore, the sampling transistors 213, 214, and 215 are ON, so one end of the hold capacitors CN, CA, and CAB is set to the MVDD voltage.

[0050] Next, at time t1, the RESC signal input to the reset transistor 212 changes from H level to Low (L) level, and the reset transistor 212 changes from ON to OFF. Also, the SWN signal input to the sampling transistor 213, the SWA signal input to the sampling transistor 214, and the SWAB signal input to the sampling transistor 215 change from H level to L level. Therefore, the sampling transistors 213, 214, and 215 change from ON to OFF. That is, the voltage of the VREADP node immediately before time t1 is held in the hold capacitors CN, CA, and CAB. Also, at time t1, the SEL signal of the selection transistor 117 and the BLK signal of the current source switch transistor 218 change from L level to H level. Therefore, the selection transistor 117 and the current source switch transistor 218 change from OFF to ON. This causes a current to flow through the amplification transistor 111 included in the pixel, and a signal is written from the pixel to the pixel memory based on the potential of FD. Furthermore, at time t1, the CLIPR signal input to the gate of switch transistor 401 included in the voltage switching circuit changes from H level to L level, and the CLIPN signal input to the gate of switch transistor 402 changes from L level to H level. Therefore, switch transistor 401 changes from ON to OFF, switch transistor 402 changes from OFF to ON, and the VCLIP signal input to the gate of clip transistor 220 changes from the GND voltage to the VCLIPN signal. That is, clip transistor 220 changes from the OFF state to a clip circuit operating state controlled by the VCLIPN signal.

[0051] Here, the operation state of the clipping circuit in which a desired voltage is set to the gate of the clipping transistor 220 will be described in detail. For example, when the gate voltage of the amplifier transistor 111 drops, the voltage of the VREADP node drops. This causes the gate-source voltage of the clipping transistor 220 to increase, and current begins to be supplied from the MVDD power supply to the VREADP node. In other words, the VREADP node is clipped to a voltage that is a certain amount lower than the VCLIPN voltage, which is the gate voltage of the clipping transistor 220. Here, being clipped means that when the gate voltage of the amplifier transistor 111 drops, the VREADP node no longer drops below a certain voltage and remains fixed.

[0052] Subsequently, at time t2, the RES signal input to the reset transistor 112 changes from H level to L level, and the FD is maintained in the state where it has been reset at the SVDD voltage up until that point.

[0053] Subsequently, at time t2, the SWN signal input to the gate of the sampling transistor 213 changes from L level to H level, and the sampling transistor 213 changes from OFF to ON. As a result, after time t2, the pixel noise signal voltage (hereinafter referred to as N signal) becomes available for writing to the hold capacitor CN. Then, at time t3, the SWN signal input to the gate of the sampling transistor 213 changes from H level to L level, and the sampling transistor 213 changes from ON to OFF. As a result, the N signal is held in the hold capacitor CN.

[0054] Next, at time t4, the TXA signal input to the transfer transistor 113 changes from L level to H level, the transfer transistor 113 changes from OFF to ON, and the charge of the PD 115 is transferred to the FD.

[0055] Also, at time t4, the CLIPN signal input to the gate of the switch transistor 402 changes from H level to L level, and the CLIIPS signal input to the gate of the switch transistor 403 changes from L level to H level. That is, the VCLIP signal input to the gate of the clip transistor 220 changes from the VCLIPN voltage to the VCLIPS voltage.

[0056] Here, we will explain in detail how to set the VCLIPN voltage and the VCLIPS voltage. First, we will explain how to set the VCLIPS voltage. When a pixel signal is output from the pixel 30 to which light is incident and the voltage of the pixel signal is read out to the VREADP node, the voltage of the VREADP node approaches the AGND voltage compared to when the N signal is output. In other words, the voltage of the VREADP node decreases. When the voltage of the VREADP node decreases, the drain-source voltage of the current source transistor 217 decreases. When the drain-source voltage of the current source transistor 217 decreases, the transistor's operating state changes and the current source transistor 217 can no longer pass a constant current. Therefore, it is necessary to ensure a sufficient drain-source voltage so that the current source transistor 217 can stably pass a constant current. Therefore, it is necessary to set the gate voltage of the clipping transistor 220 to the VCLIPS voltage so that the voltage of the VREADP node is clipped to a voltage that can sufficiently ensure the drain-source voltage of the current source transistor 217.

[0057] Furthermore, excessive changes in the voltage of the VREADP node during the period when the pixel signal voltage is read out when light is incident can result in degradation of image quality, such as crosstalk. When a large gain is applied using a RAMP signal or the like, the required gradation can be expressed even with smaller voltage changes at the VREADP node, compared to when a small gain is applied. Therefore, the voltage of the VCLIPS signal input to the gate voltage of the clipping transistor 220 must be set so that the voltage at the VREADP node is clipped at a voltage higher than the voltage that is sufficient to ensure the drain-source voltage of the current source transistor 217.

[0058] Next, we will explain how to set the VCLIPN voltage. For example, when high-intensity light, such as from an illuminator, is incident, the charge from the PD overflows, causing the N signal to change and the voltage at the VREADP node to drop. To read out an image, a voltage difference between the pixel signal and the N signal is required. If the difference between the pixel signal voltage and the N signal voltage becomes small, it becomes difficult to read out the image. Therefore, when reading out the pixel signal voltage described above, the VCLIPS voltage is input to the gate of the clip transistor 220. The pixel signal voltage and the N signal voltage must have the required voltage difference relative to the voltage at the VREADP node clipped by the clip transistor 220. Therefore, the voltage input to the gate of the clip transistor 220 when reading out the N signal is set to the VCLIPN voltage.

[0059] Subsequently, at time t5, the SWA signal input to the sampling transistor 214 changes from L level to H level, causing the sampling transistor 214 to change from OFF to ON. This causes a state in which a first pixel signal voltage (hereinafter referred to as the SA signal) corresponding to the charge of the PD 115 is written to the hold capacitor CA. Then, at time t6, the SWA signal input to the sampling transistor 214 changes from H level to L level, causing the sampling transistor 214 to change from ON to OFF. This causes the SA signal to be held in the hold capacitor CA.

[0060] At time t7, the TXA signal input to the transfer transistor 113 and the TXB signal input to the transfer transistor 114 change from L level to H level. As a result, the transfer transistors 113 and 114 change from OFF to ON, and the charges of PD115 and PD116 are transferred to FD. That is, the charges of PD115 and PD116 are added together in FD. Then, at time t8, the transfer transistors 113 and 114 change from ON to OFF.

[0061] At time t9, the SWAB signal input to the sampling transistor 215 changes from L level to H level, causing the sampling transistor 215 to change from OFF to ON. This causes a state in which a second pixel signal voltage (hereinafter referred to as the SAB signal) corresponding to the charges of PD115 and PD116 is written to the hold capacitor CAB. Then, at time t10, the SWAB signal input to the sampling transistor 215 changes from H level to L level, causing the sampling transistor 215 to change from ON to OFF. This causes the SAB signal to be held in the hold capacitor CAB.

[0062] Furthermore, at time t10, the CLIPS signal input to the switch transistor 403 changes from H level to L level, and the CLIPR signal input to the switch transistor 401 changes from L level to H level. Therefore, the voltage input to the gate of the clip transistor 220 changes from the VCLIPS voltage to the GND voltage, and the clip transistor 220 enters the OFF state. Also, the RESC signal input to the reset transistor 212 changes from L level to H level, and the reset transistor 212 enters the ON state. Therefore, the VREADP node becomes the MVDD voltage.

[0063] In this way, the N signal, SA signal, and SAB signal of each pixel can be held in the hold capacitance of the pixel memory.

[0064] Next, with reference to FIG. 9, the timing of the pixel memory readout period of period C, which follows the pixel memory write period of period B, will be described.

[0065] The pixel memory write period is up to time t21, and the pixel memory read period (period C) for one row is from time t21 to time t30. Figure 9 shows a pixel memory read period for two rows.

[0066] At time t21, the SELM signal (hereinafter referred to as the SELM(1) signal, with the row number shown in parentheses) input to the selection transistor 219 corresponding to the pixels in the first row changes from L level to H level, causing the selection transistor 219 to change from OFF to ON. Also, the BLKM signal input to the current source switch transistor 315 changes from L level to H level, causing the current source switch transistor 315 to change from OFF to ON. This allows current to flow through the amplification transistor 211, enabling a signal to be read out.

[0067] Then, at time t21, the RETC signal input to the reset transistor 212 changes from L level to H level, and the VREADP node is set to the SVDD voltage. In this embodiment, the reset voltage of the VREADP node is the SVDD voltage, but other reference voltages may be set. Then, at time t22, the RETC signal input to the reset transistor 212 changes from H level to L level, and the reset transistor 212 changes from ON to OFF.

[0068] After that, at time t23, the SWN signal input to the sampling transistor 213 changes from L level to H level, and the sampling transistor 213 changes from OFF to ON. As a result, the N signal held in the hold capacitor CN is input to the gate of the amplifying transistor 211. Then, the N signal output via the amplifying transistor 211 is input to the comparator circuit 311 that constitutes the signal processing circuit 50 and compared with the RAMP signal.

[0069] Subsequently, at time t24, the RETC signal input to the reset transistor 212 changes again from L level to H level, and the VREADP node is set to the MVDD voltage again. In this way, it is preferable to always set the VREADP node to the MVDD voltage before reading out a different signal from the hold capacitor. This reduces the influence of the state before the signal is read out from the selected hold capacitor on the selected read signal. Next, at time t25, the RETC signal input to the reset transistor 212 changes from H level to L level.

[0070] At time t26, the SWA signal input to the sampling transistor 214 changes from L level to H level, and the sampling transistor 214 changes from OFF to ON. As a result, the SA signal held in the hold capacitor CA is input to the gate of the amplifying transistor 211. The SA signal output via the amplifying transistor 211 is then input to the comparator circuit 311 that constitutes the signal processing circuit 50 and compared with the RAMP signal. Next, at time t27, the SWA signal input to the sampling transistor 214 changes from H level to L level, and the sampling transistor 214 changes from ON to OFF.

[0071] Furthermore, at time t27, the RETC signal input to the reset transistor 212 changes again from L level to H level, and the reset transistor 212 changes from OFF to ON. The VREADP node is set to the MVDD voltage. Then, at time t28, the RETC signal input to the reset transistor 212 changes from H level to L level, and the reset transistor 212 changes from ON to OFF.

[0072] At time t29, the SWAB signal input to the sampling transistor 215 changes from L level to H level, and the sampling transistor 215 changes from OFF to ON. As a result, the SAB signal held in the hold capacitor CAB is input to the gate of the amplifying transistor 211. The SAB signal output via the amplifying transistor 211 is then input to the comparator circuit 311 that constitutes the signal processing circuit 50 and compared with the RAMP signal. Then, at time t30, the SWAB signal input to the sampling transistor 215 changes from H level to L level, and the sampling transistor 215 changes from ON to OFF.

[0073] Also, at time t30, the SELM(1) signal changes from H level to L level, and the selection transistor 219 changes from ON to OFF. Meanwhile, the SELM(2) signal changes from H level to L level, and the selection transistor 219 of the pixel memory unit on a different row changes from OFF to ON.

[0074] The readout operation from time t21 to time t30 is performed row by row, selecting the pixel memory unit of the row sequentially. Note that the BLKM signal input to the current source switch transistor 315 changes from H level to L level at the end of the pixel memory readout period, changing the current source switch transistor 315 from ON to OFF. In this way, pixel signals of all pixels are read out to the signal processing circuit 50.

[0075] In this embodiment, a driving method has been described in which two PDs connected to an FD transfer charges to the FD by controlling their respective transfer transistors at different times, and two different pixel signals are written to and read from the pixel memory. However, this is not limiting. For example, two PDs connected to an FD may simultaneously turn on their respective transfer transistors to transfer charges to the FD. Furthermore, when there is only one PD, the sampling transistor 215 is not essential, and therefore there is no need to hold the signal in the hold capacitor CAB or read out the SAB signal.

[0076] Next, the problems and advantages of this embodiment will be described in detail.

[0077] The first is that the voltage at the VREADP node is clipped during the pixel memory write period. Furthermore, the clip voltage at the VREADP node is switched depending on the readout period of the N signal, SA signal, and SAB signal. As mentioned above, this makes it possible to express the required gradation even when high-intensity light, such as from an illuminator, is incident. It also helps reduce image quality degradation, such as crosstalk.

[0078] The second feature is that the clip transistor 220 is disposed not on the first substrate 100 but on a substrate different from the first substrate 100 on which the PD and amplification transistor 111 are disposed. In this embodiment, the clip transistor 220 is disposed on the second substrate 200 rather than on the first substrate 100. Because the clip transistor 220 is required for each pixel circuit, it is also possible to dispose it on the first substrate 100 on which the pixels are disposed. However, disposing the clip transistor 220 on the first substrate 100 requires securing an area on the first substrate 100 for disposing the clip transistor 220, which limits the area on the first substrate 100 on which the PD can be disposed. This also limits the number of pixels that can be disposed on the first substrate 100. However, to configure a high-resolution, high-sensitivity imaging device, it is necessary to secure as large an area as possible for disposing the PD and amplification transistor within the limited area determined by the resolution. According to this embodiment, the clip transistor 220 is disposed not on the first substrate 100 but on a substrate different from the first substrate 100, making it possible to provide a high-resolution, high-image-quality photoelectric conversion device.

[0079] The present embodiment has been described as an example of the present invention, but the present invention is not limited to the circuit configuration and driving method of the present embodiment, and may be realized by other forms of circuit configuration and driving method.

[0080] (Second embodiment) The photoelectric conversion device according to the second embodiment will be described with reference to FIGS.

[0081] 10, the circuit configuration of the pixels 30 arranged on the first substrate, the pixel memory 40 arranged on the second substrate, and part of the comparator circuit of the signal processing circuit 50 arranged on the third substrate will be described. The same components as those in the first embodiment are given the same reference numerals, and descriptions of these components may be omitted or simplified.

[0082] In the first embodiment, the clipping transistor 220 and the reset transistor 212 are provided separately to perform the clipping operation and the readout reset operation. In this embodiment, a single transistor 221 is used to perform the clipping operation and the readout reset operation. This embodiment differs from the first embodiment in that the voltage of the control signal VRESC input to the gate of the transistor 221 can be switched. Other than these points and the points described below, this embodiment can be substantially the same as the first embodiment.

[0083] The voltage switching circuit connected to the gate of the transistor 221 of this embodiment will be described with reference to Fig. 11. The voltage switching circuit shown in Fig. 11 is a circuit that switches the VRESC voltage input to the gate of the transistor 221 and supplies it.

[0084] 11, the control signal CLIPR input to the gate of the switch transistor 501, the GND power supply connected to one of the source or drain terminals, etc. are the same as those of the switch transistor 401 shown in Fig. 4. Furthermore, the control signal CLIPN input to the gate of the switch transistor 503, the VCLIPN power supply connected to one of the source or drain terminals, etc. are the same as those of the switch transistor 402 shown in Fig. 4. Furthermore, the control signal CLIIPS input to the gate of the switch transistor 504, the VCLIPS voltage connected to one of the source or drain terminals, etc. are the same as those of the switch transistor 403 shown in Fig. 4.

[0085] In this embodiment, a switch transistor 502 is added to the voltage switching circuit of the first embodiment shown in Fig. 4. The switch transistor 502 is controlled by a control signal CLIPC input to its gate, and when the switch transistor 502 is turned on, the MVDD power supply voltage can be switched to be output as the VRESC voltage.

[0086] The timing of the circuit operation during the pixel memory writing period will be described with reference to FIG.

[0087] Before time t101 and after time t110, the CLIPC signal input to the gate of the switch transistor 502 is at H level, and the switch transistor 502 is ON. During this period, the MVDD power supply voltage is supplied as the VRESC voltage to the gate of the transistor 221 via the switch transistor 502. That is, the transistor 221 functions as a switch and supplies the MVDD power supply voltage to the VREADP node. At time t101, the CLIPC signal input to the gate of the switch transistor 502 changes from H level to L level, and the switch transistor 502 changes from ON to OFF.

[0088] From time t101 to time t104, the CLIPN signal input to the gate of the switch transistor 503 is at H level, and the switch transistor 503 is turned ON. During this period, the VCLIPN voltage is supplied to the gate of the transistor 221 via the switch transistor 503 as the VRESC voltage. During this period, when the voltage of the VREADP node drops to a predetermined threshold, the transistor 221 performs a clipping operation on the gate voltage in response to the VCLIPN voltage. At time t104, the CLIPN signal input to the gate of the switch transistor 503 changes from H level to L level, and the switch transistor 503 changes from ON to OFF.

[0089] From time t104 to time t110, the CLIPS signal input to the gate of the switch transistor 504 is at H level, and the switch transistor 504 is turned ON. During this period, the VCLIPS voltage is supplied as the VRESC voltage to the gate of the transistor 221 via the switch transistor 504. During this period, when the voltage at the VREADP node drops to a predetermined threshold, the transistor 221 clips the gate voltage in response to the VCLIPS voltage.

[0090] Next, the timing of circuit operation during the pixel memory readout period will be described with reference to FIG. 13. The transistor 221 only switches between the ON and OFF states. When the CLIPC signal is at an H level, the MVDD power supply voltage is supplied to the transistor 221 as the VRESC voltage via the switch transistor 502. Furthermore, when the CLIPR signal is at an H level, the GND power supply voltage is supplied to the transistor 221 as the VRESC voltage via the switch transistor 501. When the VRESC voltage is the MVDD power supply voltage, the transistor 221 is in the ON state, and when the VRESC voltage is the GND power supply voltage, the transistor 221 is in the OFF state. When the transistor 221 is in the ON state, the potential of the VREADP node is reset, and when the transistor 221 is in the OFF state, the signal is read out to the third substrate 300. In this way, the signal is read out by switching the transistor 221 between ON and OFF.

[0091] In this embodiment, as in the first embodiment, the required gradation can be expressed by clipping the VREADP node. Furthermore, degradation of image quality due to crosstalk and the like can be suppressed. Furthermore, by arranging the transistor that clips the VREADP node on a substrate other than the first substrate 100, it is no longer necessary to reduce the area of ​​the PD or the area of ​​the amplification transistor, making it possible to provide an imaging device with high resolution and high image quality. Furthermore, by sharing the transistor 221 between the clipping operation and the reset operation, it is possible to reduce the number of transistors arranged on the second substrate 200.

[0092] In this embodiment, the transistor 221 is disposed on the second substrate 200, but the transistor 221 may be disposed on the third substrate 300.

[0093] (Third embodiment) A photoelectric conversion device according to the third embodiment will be described with reference to FIG.

[0094] 14 shows the circuit configuration of part of the comparator circuit of the signal processing circuit 50 arranged on the third substrate. Note that the same components as those in the first or second embodiment are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0095] This embodiment differs from the first and second embodiments in that a clip transistor 317 is connected to a VLOUT node to which a signal is output from the second substrate 200. Other than this point and points described below, this embodiment can be substantially the same as the first or second embodiment.

[0096] A VLCLIP signal is supplied to the gate of the clip transistor 317. One of the source and drain terminals of the clip transistor 317 is connected to the AVDD power supply, and the other terminal is connected to the VLOUT node.

[0097] The VLOUT node is connected to many loads, such as the readout lines 316 arranged in the row direction, and therefore has a large amount of charge to be charged and discharged. Therefore, it is preferable that the clipping transistor 317 has a larger driving capability than the clipping transistor 220 of the first embodiment and the transistor 221 of the second embodiment. For example, the ratio of the channel width to the channel length of the clipping transistor 317 can be made larger than that of the clipping transistor 220 or the transistor 221. Note that the voltage of the VLCLIP node is set as described in the first and second embodiments.

[0098] Even if there is no transistor that performs clipping operation on the VREADP node shown in the first and second embodiments, clipping operation on the VLOUT node can be performed by using the clip transistor 317 of this embodiment. In other words, in this embodiment, the clip transistor 220 and the transistor 221 are not essential components.

[0099] On the other hand, it is preferable to provide a transistor that performs clipping operation on each of the second substrate 200 and the third substrate 300. As a result, when performing a test to determine whether each substrate is good or bad, the second substrate 200 can be tested by controlling the VREADP node with a transistor that performs clipping operation. Also, the third substrate 300 can be tested by controlling the voltage of the VLOUT node with a transistor that performs clipping operation.

[0100] According to this embodiment, it is possible to express the necessary gradation and to suppress degradation of image quality due to crosstalk, etc. Furthermore, by arranging the transistor that performs clipping operation on the third substrate 300, it is not necessary to reduce the area of ​​the PD or the area of ​​the amplifying transistor on the first substrate 100, so it is possible to provide an imaging device with high definition and high image quality.

[0101] (Fourth embodiment) The fourth embodiment can be applied to any of the first to third embodiments. FIG. 15(a) is a schematic diagram illustrating an apparatus 9191 including a semiconductor device 930 according to this embodiment. The photoelectric conversion device according to any of the above-described embodiments can be used as the semiconductor device 930. The apparatus 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 can include a semiconductor device 910. The semiconductor device 930 can include, in addition to the semiconductor device 910, a package 920 that houses the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0102] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0103] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0104] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0105] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0106] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft (drone, aircraft). The mechanical device 990 in the transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0107] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0108] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0109] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 15(b) and 15(c).

[0110] FIG. 15(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 1. The photoelectric conversion device 1 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 1, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 8. Here, the photoelectric conversion system 8 may include an optical system (not shown) that guides light to the photoelectric conversion device 80, such as a lens, shutter, or mirror. Furthermore, multiple photoelectric conversion units that are approximately conjugate with the pupil of the optical system may be arranged in pixels of the photoelectric conversion device 80. For example, the multiple photoelectric conversion units that are approximately conjugate with the pupil are arranged corresponding to one microlens. The multiple photoelectric conversion units receive light beams that have passed through different positions on the pupil of the optical system, and the photoelectric conversion device 80 outputs image data corresponding to the light beams that have passed through the different positions. The parallax acquisition unit 802 may then calculate the parallax using the output image data. The system may also include a control unit that controls the movement of the moving object using a signal output by the photoelectric conversion device. For example, the photoelectric conversion system 8 includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information may be acquired using ToF (Time of Flight). The distance information acquisition means may be realized by dedicated hardware or a software module. It may also be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0111] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0112] In this embodiment, the photoelectric conversion system 8 captures an image of the surroundings of the vehicle, for example, the front or rear. Fig. 15(c) shows the photoelectric conversion system 8 when capturing an image of the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 1. This configuration can further improve the accuracy of distance measurement.

[0113] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as autonomous driving control to follow other vehicles and autonomous driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system 8 can be applied not only to automobiles and other vehicles, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generator that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generator can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, an aircraft's propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0114] As used herein, expressions such as "A or B," "at least one of A and B," "at least one of A or / and B," "one or more of A or / and B," and the like, include all possible combinations of the listed items unless expressly defined otherwise. That is, the above expressions are understood to disclose all cases, including cases containing at least one A, cases containing at least one B, and cases containing both at least one A and at least one B. This applies equally to combinations of three or more elements.

[0115] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0116] The disclosure of this embodiment includes the following configurations.

[0117] (Configuration 1) A photoelectric conversion device comprising at least two substrates: a first substrate having a pixel section in which a plurality of pixels, each including a photoelectric conversion element and an amplification transistor, are arranged in an array; and a second substrate having a memory section that holds analog signals output by the pixel section, wherein a current source and a transistor that clips the potential of a node connected to a node through which signals output from the current source and the amplification transistor pass are arranged on one of the at least two substrates, different from the first substrate.

[0118] (Configuration 2) A photoelectric conversion device comprising at least two substrates: a first substrate having a pixel section in which a plurality of pixels, each including a photoelectric conversion element and an amplification transistor, are arranged in an array; and a second substrate having a memory section that holds analog signals output by the pixel section, wherein a current source and a transistor connected to a node through which signals output from the current source and the amplification transistor pass are arranged on one of the at least two substrates, different from the first substrate, and the transistor is switchable between an operation of resetting the potential of the node and an operation of clipping the potential of the node.

[0119] (Configuration 3) The photoelectric conversion device described in configuration 1 or 2, characterized in that the at least two substrates further include a third substrate including a signal processing circuit that processes analog signals from the memory unit, the second substrate is arranged between the first substrate and the third substrate, and the current source and the transistor are arranged on the third substrate.

[0120] (Configuration 4) The photoelectric conversion device described in configuration 1 or 2, characterized in that the at least two substrates further include a third substrate including a signal processing circuit that processes an analog signal from the memory unit, the second substrate is arranged between the first substrate and the third substrate, the second substrate includes a second amplification transistor, and the third substrate has arranged thereon a second current source and a second transistor that clips the potential of the second node connected to a second node through which a signal output from the second current source and the second amplification transistor passes.

[0121] (Configuration 5) 5. The photoelectric conversion device according to configuration 4, wherein the second transistor has a driving capability greater than that of the first transistor.

[0122] (Configuration 6) 6. The photoelectric conversion device according to Structure 4 or 5, wherein the ratio of the channel width to the channel length of the second transistor is larger than the ratio of the channel width to the channel length of the first transistor.

[0123] (Configuration 7) The photoelectric conversion device according to any one of configurations 1 to 6, wherein the pixel included in the pixel unit has a floating diffusion that converts the charge generated in the photoelectric conversion element into a signal, the amplification transistor has an amplification transistor that amplifies the signal, and the analog signal output by the pixel unit is the signal output by the amplification transistor.

[0124] (Configuration 8) 8. The photoelectric conversion device according to configuration 7, wherein the amplifying transistor is a source follower transistor.

[0125] (Configuration 9) The photoelectric conversion device according to configuration 7 or 8, wherein the memory unit has a plurality of pixel memories arranged in an array, and each of the plurality of pixel memories holds the analog signal output from each of the plurality of pixels.

[0126] (Configuration 10) The photoelectric conversion device described in any one of structures 1 to 9, characterized in that the first substrate has a first metal portion and a first insulating film, the second substrate has a second metal portion and a second insulating film, and at the bonding surfaces of the first substrate and the second substrate, a bonding portion between the first metal portion and the second metal portion and a bonding portion between the first insulating film and the second insulating film are arranged.

[0127] (Configuration 11) An apparatus comprising the photoelectric conversion device according to any one of configurations 1 to 10, further comprising at least one of an optical device that guides light to the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes signals output from the photoelectric conversion device, a display device that displays information obtained by the photoelectric conversion device, a memory device that stores information obtained by the photoelectric conversion device, and a mechanical device that operates based on the information obtained by the photoelectric conversion device.

[0128] (Configuration 12) 11. A moving body including the photoelectric conversion device according to any one of configurations 1 to 10, characterized in that the moving body further includes a control unit that controls the movement of the moving body using a signal output by the photoelectric conversion device. [Explanation of symbols]

[0129] 10 Photoelectric conversion device 30 pixels 100 First substrate 110 Pixel section 200 Second board

Claims

1. a first substrate having a pixel section in which a plurality of pixels, each including a photoelectric conversion element and an amplification transistor, are arranged in an array; a second substrate having a memory unit for storing an analog signal output from the pixel unit, A photoelectric conversion device characterized in that a current source and a transistor that clips the potential of a node connected to a node through which a signal output from the current source and the amplification transistor passes are arranged on a substrate different from the first substrate of the at least two substrates.

2. a first substrate having a pixel section in which a plurality of pixels, each including a photoelectric conversion element and an amplification transistor, are arranged in an array; a second substrate having a memory unit for storing an analog signal output from the pixel unit, a current source and a transistor connected to a node through which a signal output from the current source and the amplifying transistor passes are disposed on a substrate different from the first substrate of the at least two substrates; The photoelectric conversion device, wherein the transistor is capable of switching between an operation of resetting the potential of the node and an operation of clipping the potential of the node.

3. the at least two substrates further include a third substrate including a signal processing circuit; the second substrate is disposed between the first substrate and the third substrate; 2. The photoelectric conversion device according to claim 1, wherein the current source and the transistor are disposed on the third substrate.

4. the at least two substrates further include a third substrate including a signal processing circuit that processes an analog signal from the memory unit; the second substrate is disposed between the first substrate and the third substrate; 3. The photoelectric conversion device according to claim 2, wherein the current source and the transistor are disposed on the third substrate.

5. the at least two substrates further include a third substrate including a signal processing circuit that processes an analog signal from the memory unit; the second substrate is disposed between the first substrate and the third substrate; the second substrate includes a second amplification transistor; The photoelectric conversion device according to claim 1, characterized in that the third substrate is provided with a second current source and a second transistor connected to a second node through which a signal output from the second current source and the second amplification transistor passes, the second transistor clipping the potential of the second node.

6. the at least two substrates further include a third substrate including a signal processing circuit that processes an analog signal from the memory unit; the second substrate is disposed between the first substrate and the third substrate; the second substrate includes a second amplification transistor; The photoelectric conversion device according to claim 2, characterized in that the third substrate is provided with a second current source and a second transistor connected to a second node through which a signal output from the second current source and the second amplification transistor passes, the second transistor clipping the potential of the second node.

7. 6. The photoelectric conversion device according to claim 5, wherein the second transistor has a driving capability greater than that of the first transistor.

8. 7. The photoelectric conversion device according to claim 6, wherein the second transistor has a driving capability greater than that of the first transistor.

9. 6. The photoelectric conversion device according to claim 5, wherein the ratio of the channel width to the channel length of the second transistor is larger than the ratio of the channel width to the channel length of the first transistor.

10. 7. The photoelectric conversion device according to claim 6, wherein the ratio of the channel width to the channel length of the second transistor is larger than the ratio of the channel width to the channel length of the first transistor.

11. 8. The photoelectric conversion device according to claim 7, wherein the ratio of the channel width to the channel length of the second transistor is greater than the ratio of the channel width to the channel length of the first transistor.

12. 9. The photoelectric conversion device according to claim 8, wherein the ratio of the channel width to the channel length of the second transistor is greater than the ratio of the channel width to the channel length of the first transistor.

13. The pixel included in the pixel unit has a floating diffusion that converts the charge generated by the photoelectric conversion element into a signal, the amplifier transistor includes an amplifier transistor that amplifies the signal; 13. The photoelectric conversion device according to claim 1, wherein the analog signal output from the pixel unit is a signal output from the amplification transistor.

14. 14. The photoelectric conversion device according to claim 13, wherein the amplifying transistor is a source follower transistor.

15. the memory unit has a plurality of pixel memories arranged in an array, 14. The photoelectric conversion device according to claim 13, wherein the analog signals output from the plurality of pixels are held in the plurality of pixel memories, respectively.

16. The photoelectric conversion device described in claim 15, characterized in that the first substrate has a first metal portion and a first insulating film, the second substrate has a second metal portion and a second insulating film, and at the bonding surfaces of the first substrate and the second substrate, a bonding portion between the first metal portion and the second metal portion and a bonding portion between the first insulating film and the second insulating film are arranged.

17. An apparatus comprising the photoelectric conversion device according to claim 1, an optical device that guides light to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

18. An apparatus comprising the photoelectric conversion device according to claim 2, an optical device that guides light to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

19. A moving object comprising the photoelectric conversion device according to claim 1, a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device; A moving object characterized by:

20. A moving object comprising the photoelectric conversion device according to claim 2, a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device; A moving object characterized by:

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