CMOS inverter and method for manufacturing the same

Abstract

To provide a CMOS inverter and a method for manufacturing the same capable of achieving miniaturization.SOLUTION: A vertical upright CMOS inverter according to one embodiment of the present invention comprises a base substrate, a p-type semiconductor layer, an n-type semiconductor layer, and a first gate electrode. The p-type semiconductor layer includes a first hole-doped region, a second hole-doped region, and a first channel region. The n-type semiconductor layer includes a first electron-doped region, a second electron-doped region, and a second channel region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a CMOS inverter and a method for manufacturing the same, and more particularly to a CMOS inverter including complementary field effect transistors with a vertical upright channel structure and a method for manufacturing the same. [Background technology]

[0002] CMOS inverters are a core component of modern electronic devices, using two complementary transistors (NMOS and PMOS) to invert the logic state of a signal. CMOS inverters are used as essential components in a variety of digital circuits. With the development of semiconductor devices, various technologies have been proposed to reduce the size and increase the integration density of CMOS inverters.

[0003] However, miniaturization of planar transistors is facing limitations. Moreover, excessive miniaturization can result in short-channel effects as a side effect. Therefore, there is a need to develop technology that realizes CMOS inverters that can achieve miniaturization and high integration. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention is intended to solve the above-mentioned conventional problems, and aims to provide a CMOS inverter and a manufacturing method thereof that can achieve high integration by adopting a structure in which two transistors (NMOS and PMOS) stand upright in the vertical direction.

[0005] Another object of the present invention is to provide a CMOS inverter and a method for manufacturing the same, in which two transistors (NMOS and PMOS) share one gate electrode, thereby achieving miniaturization. [Means for solving the problem]

[0006] A CMOS inverter according to one embodiment of the present invention may include a base substrate, a p-type semiconductor layer, an n-type semiconductor layer, and a first gate electrode.

[0007] The base substrate is parallel to a plane defined by a first direction and a second direction intersecting the first direction.

[0008] The p-type semiconductor layer may be disposed on the base substrate, and may include a first hole-doped region, a second hole-doped region, and a first channel region.

[0009] An n-type semiconductor layer may be disposed on the base substrate, the n-type semiconductor layer may be separated from the p-type semiconductor layer, and the n-type semiconductor layer may include a first electronically doped region, a second electronically doped region, and a second channel region.

[0010] The first gate electrode may be disposed on the base substrate and may have a shape that surrounds the first channel region and the second channel region.

[0011] The first hole-doped region may be disposed adjacent to the base substrate.

[0012] The first channel region may be disposed adjacent to the first hole-doped region in a third direction perpendicular to the first and second directions.

[0013] The second hole-doped region may be disposed adjacent to the first channel region in the third direction.

[0014] The first electron-doped region may be disposed adjacent to the base substrate.

[0015] The second channel region may be disposed adjacent to the first electron-doped region in a third direction.

[0016] The second electron-doped region may be disposed adjacent to the second channel region in the third direction.

[0017] In one embodiment of the present invention, the CMOS inverter may further include a connection metal, which may contact the first hole-doped region and the first electron-doped region.

[0018] In one embodiment of the present invention, the CMOS inverter may further include an insulating layer, a plurality of terminals, and a plurality of connecting wires.

[0019] The insulating layer may be disposed on the base substrate and may cover the p-type semiconductor layer, the n-type semiconductor layer, the connection metal, and the first gate electrode.

[0020] A plurality of terminals may be disposed on the insulating layer, and the plurality of terminals may include a first input terminal, a power terminal, an output terminal, and a ground terminal.

[0021] The plurality of connection wires may be disposed on the base substrate, and may include first to fourth connection wires.

[0022] The first connection wire may be in contact with the first input terminal and the first gate electrode.

[0023] The second connecting wire may contact the power supply terminal and the second hole-doped region.

[0024] The third connection wire may be in contact with the output terminal and the connection metal.

[0025] The fourth connecting wire may be in contact with the ground terminal and the second electron-doped region.

[0026] In one embodiment of the present invention, the cross-sectional area of ​​the p-type semiconductor layer may be greater than the cross-sectional area of ​​the n-type semiconductor layer.

[0027] In one embodiment of the present invention, the CMOS inverter may further include a second gate electrode, the second gate electrode may be disposed on the base substrate, and the second gate electrode may be spaced apart from the third connecting wiring.

[0028] The third connecting wire may be disposed between the first channel region and the second channel region.

[0029] The second gate electrode may have a shape that surrounds the third connection wiring.

[0030] In one embodiment of the present invention, the plurality of terminals may further include a second input terminal.

[0031] The plurality of connecting wires may further include a fifth connecting wire.

[0032] The fifth connecting wire may be in contact with the second input terminal and the second gate electrode.

[0033] In one embodiment of the present invention, the first gate electrode may be in contact with the second gate electrode.

[0034] In one embodiment of the present invention, the CMOS inverter may further include a connection metal, which may contact the second hole-doped region and the second electron-doped region.

[0035] In one embodiment of the present invention, the CMOS inverter may further include an insulating layer, a plurality of terminals, and a plurality of connecting wires.

[0036] The insulating layer may be disposed on the base substrate and may cover the p-type semiconductor layer, the n-type semiconductor layer, the connection metal, and the first gate electrode.

[0037] A plurality of terminals may be disposed on the insulating layer, and the plurality of terminals may include a first input terminal, a power terminal, an output terminal, and a ground terminal.

[0038] The plurality of connection wires may be disposed on a base substrate, and may include first to fourth connection wires.

[0039] The first connection wire may be in contact with the first input terminal and the first gate electrode.

[0040] The second connecting wire may contact the power supply terminal and the first hole-doped region.

[0041] The third connection wire may be in contact with the output terminal and the connection metal.

[0042] The fourth connecting wire may be in contact with the ground terminal and the first electron-doped region.

[0043] A method for manufacturing a CMOS inverter according to an embodiment of the present invention may include a vertical semiconductor layer forming step of forming a first vertical semiconductor layer and a second vertical semiconductor layer on a base substrate; an ion doping step of doping ions into each of the first vertical semiconductor layer and the second vertical semiconductor layer; a gate forming step of forming a gate electrode on the base substrate; a connection metal forming step of forming a connection metal on the base substrate to contact the first vertical semiconductor layer and the second vertical semiconductor layer; an insulating layer forming step of forming an insulating layer to cover the first vertical semiconductor layer, the second vertical semiconductor layer, the first gate electrode, and the connection metal; and a wiring connection step of connecting the first vertical semiconductor layer, the second vertical semiconductor layer, the first gate electrode, and the connection metal to each of a plurality of terminals disposed on the insulating layer.

[0044] The vertical semiconductor layer forming step may include a sacrificial vertical pillar forming step in which sacrificial vertical pillars are formed on the base substrate; a spacer forming step in which spacers covering side surfaces of the sacrificial vertical pillars and an upper surface of the base substrate are formed; a spacer hard mask forming step in which a portion of the spacer is etched to form a spacer hard mask surrounding the side surfaces of the sacrificial vertical pillars; a cutting step in which the spacer hard mask and the sacrificial vertical pillars are cut in a direction perpendicular to the base substrate; a vertical layer forming step in which a portion of the base substrate and the sacrificial vertical pillars are removed to form a first vertical semiconductor layer and a second vertical semiconductor layer; and a spacer hard mask removing step in which the spacer hard mask is removed.

[0045] In one embodiment of the present invention, the ion doping step may include a first hole-doped region forming step of doping the base substrate with first ions having a first energy in a direction perpendicular to the base substrate to form a first hole-doped region, a second hole-doped region forming step of doping the base substrate with second ions having a second energy different from the first energy in a direction perpendicular to the base substrate to form a second hole-doped region, a first electron-doped region forming step of doping the base substrate with third ions having a third energy in a direction perpendicular to the base substrate to form a first electron-doped region, and a second electron-doped region forming step of doping the base substrate with fourth ions having a fourth energy different from the third energy in a direction perpendicular to the base substrate to form a second electron-doped region.

[0046] The first ions and the second ions may include boron (B).

[0047] The third and fourth ions may include arsenic (AS) or phosphine (P).

[0048] In one embodiment of the present invention, the gate formation step may include a masking step of covering top surfaces of the first vertical semiconductor layer and the second vertical semiconductor layer with a mask; a first insulating step of forming an insulating layer covering side surfaces of the first hole-doped region and the first electron-doped region; a gate electrode disposing step of disposing a gate electrode having a shape surrounding the first vertical semiconductor layer and the second vertical semiconductor layer on the insulating layer; and an etching step of etching an overlapping portion of the gate electrode and the second hole-doped region or the second electron-doped region.

[0049] In one embodiment of the present invention, the connection metal formation step may include a masking removal step in which a mask covering the top surfaces of the first vertical semiconductor layer and the second vertical semiconductor layer is removed, and a connection metal contact step in which a connection metal contacting the first hole-doped region and the first electron-doped region is formed. [Brief explanation of the drawings]

[0050] [Figure 1] FIG. 1 is a perspective view showing an example of a CMOS inverter according to an embodiment of the present invention. [Figure 2a] 2 is an exemplary cross-sectional view of a CMOS inverter taken along II' in the embodiment of FIG. 1; [Figure 2b] 2 is an exemplary cross-sectional view of a CMOS inverter taken along line II-II' in FIG. 1 according to an embodiment of the present invention; [Figure 3] 2 is an exemplary diagram showing a CMOS inverter according to an embodiment of the present invention shown in FIG. 1; [Figure 4] 1 is an exemplary diagram showing a cross section of a CMOS inverter according to an embodiment of the present invention; [Figure 5a] 1 is an exemplary diagram showing a cross section of a CMOS inverter according to an embodiment of the present invention; [Figure 5b] 1 is an exemplary diagram showing a cross section of a CMOS inverter according to an embodiment of the present invention; [Figure 6a] 1 is an exemplary diagram showing a cross section of a CMOS inverter according to an embodiment of the present invention; [Figure 6b] 1 is an exemplary diagram showing a cross section of a CMOS inverter according to an embodiment of the present invention; [Figure 6c] 1 is an exemplary diagram showing a cross section of a CMOS inverter according to an embodiment of the present invention; [Figure 7a] 1 is an exemplary diagram showing a cross section of a CMOS inverter according to an embodiment of the present invention; [Figure 7b] 1 is an exemplary diagram showing a cross section of a CMOS inverter according to an embodiment of the present invention; [Figure 7c] 1 is an exemplary diagram showing a cross section of a CMOS inverter according to an embodiment of the present invention; [Figure 8] 1 is an exemplary diagram showing a cross section of a CMOS inverter according to an embodiment of the present invention; [Figure 9] 1 is a flowchart illustrating an example method for manufacturing a CMOS inverter in accordance with an embodiment of the present invention. [Figure 10] 2 is an exemplary view showing a step of forming a vertical semiconductor layer in a method of manufacturing a CMOS inverter according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0051] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In the drawings, the proportions and dimensions of components may be exaggerated in order to effectively explain the technical contents.

[0052] Terms such as "comprise" and "comprise" are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, and should be understood not to preclude the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0053] Furthermore, when a component is described as being "above" it means above or below that component, and does not necessarily mean that it is located on the upper side with respect to the direction of gravity.

[0054] Furthermore, when a component is described as being "connected" or "coupled" to another component, this includes not only the case where the component is directly connected or coupled to the other component, but also the case where the component is indirectly connected or coupled via the other component.

[0055] Furthermore, when describing a component, terms such as "first" and "second" may be used, but these terms are intended to distinguish the component from other components, and should not be used to limit the essence, order, or sequence of the components.

[0056] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In the drawings, the proportions and dimensions of components may be exaggerated in order to effectively explain the technical contents.

[0057] Figure 1 is a perspective view showing an example of a CMOS inverter (CVT) according to an embodiment of the present invention. Figure 2a is an exemplary cross-sectional view of the CMOS inverter (CVT) taken along line I-I' in the embodiment of the present invention shown in Figure 1. Figure 2b is an exemplary cross-sectional view of the CMOS inverter (CVT) taken along line II-II' in the embodiment of the present invention shown in Figure 1.

[0058] Referring to Figures 1, 2a, and 2b, a CMOS inverter (CVT) according to one embodiment of the present invention may include a base substrate (BS), a p-type semiconductor layer (PSC), an n-type semiconductor layer (NSC), and a first gate electrode (GT1).

[0059] The base substrate (BS) is parallel to a plane defined by a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). The base substrate (BS) may include at least one of silicon, germanium, tensile silicon, tensile silicon germanium, or silicon carbide.

[0060] The p-type semiconductor layer (PSC) may be disposed on the base substrate (BS). The p-type semiconductor layer (PSC) may include a first hole-doped region (HD1), a second hole-doped region (HD2), and a first channel region (CH1). The p-type semiconductor layer (PSC) may be electrically connected to a first gate electrode (GT1) and operate as a PMOS transistor.

[0061] The first hole-doped region (HD1) may be disposed adjacent to the base substrate (BS), and may be defined as a drain region of the PMOS transistor.

[0062] The first channel region (CH1) may be disposed adjacent to the first hole-doped region (HD1) in a third direction (DR3) perpendicular to the first direction (DR1) and the second direction (DR2).

[0063] The second hole-doped region (HD2) may be disposed adjacent to the first channel region (CH1) in the third direction (DR3), and may be defined as a source region of the PMOS transistor.

[0064] The n-type semiconductor layer (NSC) may be disposed on the base substrate (BS). The n-type semiconductor layer (NSC) may be separated from the p-type semiconductor layer (PSC). The n-type semiconductor layer (NSC) may include a first electron-doped region (LD1), a second electron-doped region (LD2), and a second channel region (CH2). The n-type semiconductor layer (NSC) may be electrically connected to the first gate electrode (GT1) and operate as an NMOS transistor.

[0065] The first electron-doped region (LD1) may be disposed adjacent to the base substrate (BS), and may be defined as a drain region of the NMOS transistor.

[0066] The second channel region (CH2) may be disposed adjacent to the first electron-doped region (LD1) in the third direction (DR3).

[0067] The second electron-doped region (LD2) may be disposed adjacent to the second channel region (CH2) in the third direction (DR3), and may be defined as a source region of the NMOS transistor.

[0068] Each of the first channel region (CH1) and the second channel region (CH2) may include at least one of silicon, silicon germanium, tensile silicon, tensile silicon germanium, silicon embedded in an insulating layer, silicon carbide, or a Group 3-5 compound semiconductor.

[0069] The first gate electrode (GT1) may be disposed on the base substrate (BS). The first gate electrode (GT1) may have a shape that surrounds the first channel region (CH1) and the second channel region (CH2). The first gate electrode (GT1) may be electrically connected to the first channel region (CH1) and the second channel region (CH2). The first gate electrode (GT1) may include at least one of n-type polysilicon, p-type polysilicon, aluminum, molybdenum, chromium, palladium, platinum, nickel, titanium, tantalum, tungsten, silver, titanium nitride, or tantalum nitride.

[0070] By utilizing the present invention, the p-type semiconductor layer (PSC) and the n-type semiconductor layer (NSC) are arranged vertically, enabling high integration to be achieved. The p-type semiconductor layer (PSC) and the n-type semiconductor layer (NSC) may not each have a gate electrode, and may share the first gate electrode (GT1). This allows the area of ​​the CMOS inverter to be reduced, enabling miniaturization.

[0071] The CMOS inverter (CVT) according to an embodiment of the present invention may further include a gate insulating film. The gate insulating film may be disposed on a base substrate (BS). The gate insulating film may be disposed between a first gate electrode (GT1) and a first channel region (CH1). The gate insulating film may be formed after ions are doped into the p-type semiconductor layer (PSC) and the n-type semiconductor layer (NSC). The gate insulating film may be disposed between the first gate electrode (GT1) and a second channel region (CH2). The gate insulating film may include at least one of an oxide film, a nitride film, an oxynitride film, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, zirconium oxide, a polymer insulating film, lanthanum-doped hafnia, or hafnium zirconium oxide, or may be formed in an air-filled state.

[0072] The CMOS inverter (CVT) according to an embodiment of the present invention may further include a connection metal (CM). The connection metal (CM) may contact the first hole-doped region (HD1) and the first electron-doped region (LD1). The first hole-doped region (HD1) and the first electron-doped region (LD1) may be electrically connected via the connection metal (CM).

[0073] The CMOS inverter (CVT) according to one embodiment of the present invention may further include an insulating layer (DL), a plurality of terminals (PNS), and a plurality of connecting wires (CWS).

[0074] The insulating layer (DL) may be disposed on the base substrate (BS), and may cover the p-type semiconductor layer (PSC), the n-type semiconductor layer (NSC), the connection metal (CM), and the first gate electrode (GT1).

[0075] A plurality of terminals (PNS) may be disposed on the insulating layer (DL), and may include a first input terminal (VIN1), a power supply terminal (VDD), an output terminal (VOUT), and a ground terminal (GND).

[0076] The plurality of connection wires (CWS) may be disposed on the base substrate (BS). The plurality of connection wires (CWS) may include first to fourth connection wires (CW1 to CW4).

[0077] The first connection wiring (CW1) may be in contact with the first input terminal (VIN1) and the first gate electrode (GT1). The first input terminal (VIN1) and the first gate electrode (GT1) may be electrically connected via the first connection wiring (CW1). The CMOS inverter (CVT) may receive an input signal via the first input terminal (VIN1).

[0078] The second connection wiring (CW2) may be in contact with the power supply terminal (VDD) and the second hole-doped region (HD2). The power supply terminal (VDD) and the second hole-doped region (HD2) may be electrically connected via the second connection wiring (CW2). The CMOS inverter (CVT) may receive power via the power supply terminal (VDD).

[0079] The third connection wiring (CW3) may be in contact with the output terminal (VOUT) and the connection metal (CM). The output terminal (VOUT) and the connection metal (CM) may be electrically connected via the third connection wiring (CW3). The CMOS inverter (CVT) may output a signal via the output terminal (VOUT).

[0080] The fourth connection wiring (CW4) may be in contact with the ground terminal (GND) and the second electron-doped region (LD2). The ground terminal (GND) and the second electron-doped region (LD2) may be electrically connected via the fourth connection wiring (CW4). The CMOS inverter (CVT) may be grounded by receiving a reference potential or 0V of the circuit via the ground terminal (GND).

[0081] FIG. 3 is an exemplary diagram showing a circuit diagram of a CMOS inverter (CVT) according to an embodiment of the present invention shown in FIG.

[0082] Referring to Figure 3, a PMOS transistor connected to a power supply terminal (VDD) and an NMOS transistor connected to a ground terminal (GND) may be connected in series. A voltage is applied to the gate of each transistor from a first input terminal (VIN1). The CMOS inverter (CVT) of the present invention may be realized as shown in Figure 3 and may operate as an inverter.

[0083] FIG. 4 is an exemplary diagram showing a cross section of a CMOS inverter (CVT) according to an embodiment of the present invention.

[0084] 2a and 4, the first gate electrode (GT1) may have a shape surrounding the first channel region (CH1) and the second channel region (CH2). As shown in FIG. 2a, the first gate electrode (GT1) may have a circular shape surrounding the first channel region (CH1) and the second channel region (CH2), or as shown in FIG. 4, the first gate electrode (GT1) may have a rectangular shape surrounding the first channel region (CH1) and the second channel region (CH2). The shape of the first gate electrode (GT1) surrounding the first channel region (CH1) and the second channel region (CH2) is not limited to a circular or rectangular shape. The first gate electrode (GT1) may have a circular, semicircular, square, rectangular, or polygonal shape.

[0085] 5a and 5b are exemplary diagrams showing a cutaway cross section of a CMOS inverter (CVT) according to one embodiment of the present invention.

[0086] 5a and 5b, the cross-sectional area of ​​the p-type semiconductor layer (PSC) may be larger than that of the n-type semiconductor layer (NSC). The primary carriers in the p-type semiconductor layer (PSC) may be holes, and the primary carriers in the n-type semiconductor layer (NSC) may be electrons. The electron mobility is higher than that of holes. Thus, the cross-sectional area of ​​the p-type semiconductor layer (PSC) may be larger than that of the n-type semiconductor layer (NSC), and the drive currents of the p-type semiconductor layer (PSC) and the n-type semiconductor layer (NSC) may be the same. By making the drive currents of the p-type semiconductor layer (PSC) and the n-type semiconductor layer (NSC) the same, improved power efficiency, improved performance, reduced heat generation, improved signal integrity, and a uniform electric field distribution can be achieved.

[0087] 6a, 6b, and 6c are exemplary diagrams showing cutaway cross sections of a CMOS inverter (CVT) according to one embodiment of the present invention.

[0088] 6a, 6b, and 6c, the CMOS inverter (CVT) may further include a second gate electrode (GT2). The second gate electrode (GT2) may be disposed on the base substrate (BS). The second gate electrode (GT2) may be separated from the third connection wiring (CW3). The third connection wiring (CW3) may be disposed between the first channel region (CH1) and the second channel region (CH2). The second gate electrode (GT2) may have a shape surrounding the third connection wiring (CW3).

[0089] The plurality of terminals (PNS) may further include a second input terminal (VIN2). The plurality of connecting wires (CWS) may further include a fifth connecting wire (CW5). The fifth connecting wire (CW5) may contact the second input terminal (VIN2) and the second gate electrode (GT2). The second input terminal (VIN2) and the second gate electrode (GT2) may be electrically connected via the fifth connecting wire (CW5). The first gate electrode (GT1) and the second gate electrode (GT2) may operate independently. The first gate electrode (GT1) may operate as a primary gate. The second gate electrode (GT2) may operate as a secondary gate. As a secondary gate, the second gate electrode (GT2) may perform an additional function, such as dynamic threshold voltage adjustment of a transistor.

[0090] 7a, 7b, and 7c are cross-sectional views of a CMOS inverter according to an embodiment of the present invention.

[0091] 7a, 7b, and 7c, the first gate electrode (GT1) may be in contact with the second gate electrode (GT2). The first gate electrode (GT1) and the second gate electrode (GT2) may act as a single gate. By acting as a single gate in a form that completely surrounds the channel, the short channel effect can be effectively suppressed.

[0092] FIG. 8 is an exemplary diagram showing a cross section of a CMOS inverter according to an embodiment of the present invention.

[0093] 8, the second connection wiring (CW2) may be in contact with the power supply terminal (VDD) and the first hole-doped region (HD1). The power supply terminal (VDD) and the first hole-doped region (HD1) may be electrically connected via the second connection wiring (CW2). The first hole-doped region (HD1) may be defined as a source region of the PMOS transistor.

[0094] The connection metal (CM) may be in contact with the second hole-doped region (HD2) and the second electron-doped region (LD2). The second hole-doped region (HD2) and the second electron-doped region (LD2) may be electrically connected through the connection metal (CM). The second hole-doped region (HD2) may be defined as a drain region of a PMOS transistor. The second electron-doped region (LD2) may be defined as a drain region of an NMOS transistor.

[0095] The fourth connection wiring (CW4) may be in contact with the ground terminal (GND) and the first electron-doped region (LD1). The ground terminal (GND) and the first electron-doped region (LD1) may be electrically connected via the fourth connection wiring (CW4). The first electron-doped region (LD1) may be defined as a source region of the NMOS transistor.

[0096] 8 shows the second connection wiring (CW2) and the fourth connection wiring (CW4) respectively arranged outside the first gate electrode (GT1) surrounding the first channel region (CH1) and the second channel region (CH2), but the positions of the second connection wiring (CW2) and the fourth connection wiring (CW4) are not limited to this. The second connection wiring (CW2) and the fourth connection wiring (CW4) may be arranged between the first gate electrode (GT1) and the third connection wiring (CW3). The second connection wiring (CW2) and the fourth connection wiring (CW4) may be arranged so as not to overlap with the first channel region (CH1) and the second channel region (CH2).

[0097] 9 is a flowchart illustrating an example of a method for fabricating a CMOS inverter (S10) according to an embodiment of the present invention. FIG. 10 is a diagram illustrating an example of a vertical semiconductor layer formation step (S100) of the method for fabricating a CMOS inverter (S10) according to an embodiment of the present invention.

[0098] 9 and 10, a method for manufacturing a CMOS inverter (CVT) according to an embodiment of the present invention includes a vertical semiconductor layer forming step (S100) of forming a first vertical semiconductor layer (VSL1) and a second vertical semiconductor layer (VSL2) on a base substrate (BS), an ion doping step (S200) of doping ions into the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2), a gate forming step (S300) of forming a gate electrode on the base substrate (BS), and a gate electrode forming step (S400) of doping the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2) on the base substrate (BS). The method may include a connection metal formation step (S400) of forming a connection metal (CM) in contact with the first vertical semiconductor layer (VSL1), the second vertical semiconductor layer (VSL2), the gate electrode, and the second vertical semiconductor layer (VSL3), an insulating layer formation step (S500) of forming an insulating layer (DL) covering the first vertical semiconductor layer (VSL1), the second vertical semiconductor layer (VSL2), the gate electrode, and the connection metal (CM), and a wiring connection step (S600) of connecting each of the first vertical semiconductor layer (VSL1), the second vertical semiconductor layer (VSL2), the gate electrode, and the connection metal (CM) to each of a plurality of terminals (PNS) arranged on the insulating layer (DL).

[0099] The vertical semiconductor layer forming step (S100) may include a sacrificial vertical pillar forming step (S101) in which sacrificial vertical pillars (SVPs) are formed on the base substrate (BS), a spacer forming step (S102) in which spacers (SPCs) are formed to cover the side surfaces of the sacrificial vertical pillars (SVPs) and the upper surface of the base substrate (BS), a spacer hard mask forming step (S103) in which a portion of the spacer (SPC) is etched to form a spacer hard mask (SHM) surrounding the side surfaces of the sacrificial vertical pillars (SVPs), a cutting step (S104) in which the spacer hard mask (SHM) and the sacrificial vertical pillars (SVPs) are cut in a direction perpendicular to the base substrate (BS), a vertical layer forming step (S105) in which a portion of the base substrate (BS) and the sacrificial vertical pillars (SVPs) are removed to form a first vertical semiconductor layer (VSL1) and a second vertical semiconductor layer (VSL2), and a spacer hard mask removing step (S106) in which the spacer hard mask (SHM) is removed.

[0100] In one embodiment of the present invention, the ion doping step (S200) may include a first hole-doped region forming step of doping the base substrate (BS) with first ions having a first energy in a direction perpendicular to the base substrate (BS) to form a first hole-doped region (HD1), a second hole-doped region forming step of doping the base substrate (BS) with second ions having a second energy different from the first energy in a direction perpendicular to the base substrate (BS) to form a second hole-doped region (HD2), a first electron-doped region forming step of doping the base substrate (BS) with third ions having a third energy in a direction perpendicular to the base substrate (BS) to form a first electron-doped region (LD1), and a second electron-doped region forming step of doping the base substrate (BS) with fourth ions having a fourth energy different from the third energy in a direction perpendicular to the base substrate (BS) to form a second electron-doped region (LD2).

[0101] The ion doping may be performed using at least one of diffusion, solid-phase diffusion, epitaxial growth, selective epitaxial growth, ion implantation, or a subsequent heat treatment. After the ion doping, the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2) may be oxidized, and a gate insulating film may be formed on the outermost surfaces of the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2). The gate insulating film may include at least one of an oxide film, a nitride film, an oxynitride film, aluminum oxide, hafnium oxide, hafnium oxide, hafnium oxynitride, zinc oxide, zirconium oxide, a polymer insulating film, lanthanum-doped hafnia, hafnium zirconium oxide, or an air-filled state.

[0102] The first ions and the second ions may include boron (B). The first vertical semiconductor layer (VSL1) may have P-type semiconductor properties.

[0103] The third ions and the fourth ions may include arsenic (AS) or phosphine (P).The second vertical semiconductor layer (VSL2) may have N-type semiconductor properties.

[0104] In one embodiment of the present invention, the gate formation step (S300) may include a masking step in which upper surfaces of the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2) are covered with a mask; a first insulating step in which an insulating layer (DL) is formed to cover side surfaces of the first hole-doped region (HD1) and the first electron-doped region (LD1); a gate electrode disposing step in which a gate electrode having a shape surrounding the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2) is disposed on the insulating layer (DL); and an etching step in which an overlapping portion of the gate electrode and the second hole-doped region (HD2) or the second electron-doped region (LD2) is etched.

[0105] The gate electrode may include at least one of n-type polysilicon, p-type polysilicon, aluminum, molybdenum, chromium, palladium, platinum, nickel, titanium, tantalum, tungsten, silver, titanium nitride, or tantalum nitride.

[0106] In one embodiment of the present invention, the connection metal formation step (S400) may include a masking removal step in which a mask covering the top surfaces of the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2) is removed, and a connection metal contact step in which a connection metal (CM) is formed to contact the first hole-doped region (HD1) and the first electron-doped region (LD1).

[0107] Although the present invention has been described above with reference to the embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as defined in the appended claims. Furthermore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, and all technical spirits within the scope of the appended claims and equivalents thereof should be construed as being included in the scope of the present invention. [Explanation of symbols]

[0108] CVT: CMOS inverter BS: Base board HD1: first hole-doped region HD2: second hole-doped region CH1: First channel region LD1: First electron doping region LD2: Second electron doping region CH2: Second channel region GT1: First gate electrode PSC: n-type semiconductor layer NSC: n-type semiconductor layer

Claims

1. a base substrate parallel to a plane defined by a first direction and a second direction intersecting the first direction; a p-type semiconductor layer disposed on the base substrate, the p-type semiconductor layer including a first hole-doped region, a second hole-doped region, and a first channel region; an n-type semiconductor layer disposed on the base substrate, spaced apart from the p-type semiconductor layer, the n-type semiconductor layer including a first electron-doped region, a second electron-doped region, and a second channel region; and a first gate electrode disposed on the base substrate and having a shape surrounding the first channel region, the second channel region, and a gate insulating film; the first hole-doped region is disposed adjacent to the base substrate; the first channel region is disposed adjacent to the first hole-doped region in a third direction perpendicular to the first direction and the second direction; the second hole-doped region is disposed adjacent to the first channel region in the third direction; the first electron-doped region is disposed adjacent to the base substrate; the second channel region is disposed adjacent to the first electron-doped region in the third direction; the second electron-doped region is disposed adjacent to the second channel region in the third direction. CMOS inverter.

2. Further comprising a connecting metal; the connecting metal contacts the first hole-doped region and the first electron-doped region; 2. The CMOS inverter of claim 1.

3. an insulating layer disposed on the base substrate and covering the p-type semiconductor layer, the n-type semiconductor layer, the connection metal, and the first gate electrode; a plurality of terminals disposed on the insulating layer; and Further comprising a plurality of connection wires disposed on the base substrate; the plurality of terminals include a first input terminal, a power supply terminal, an output terminal, and a ground terminal; the plurality of connection wirings include first to fourth connection wirings, the first connection wiring is in contact with the first input terminal and the first gate electrode; the second connection wiring contacts the power supply terminal and the second hole-doped region; the third connection wiring is in contact with the output terminal and the connection metal; the fourth connection wiring contacts the ground terminal and the second electron-doped region; 3. The CMOS inverter of claim 2.

4. a cross-sectional area of ​​the p-type semiconductor layer is larger than a cross-sectional area of ​​the n-type semiconductor layer; 4. The CMOS inverter of claim 3.

5. a second gate electrode disposed on the base substrate and spaced apart from the third connection wiring; the third connection wiring is disposed between the first channel region and the second channel region; the second gate electrode has a shape surrounding the third connection wiring; 4. The CMOS inverter of claim 3.

6. the plurality of terminals further includes a second input terminal disposed on the insulating layer; the plurality of connection wirings further includes a fifth connection wiring, the fifth connection wiring is in contact with the second input terminal and the second gate electrode; 6. The CMOS inverter of claim 5.

7. the first gate electrode is in contact with the second gate electrode and completely surrounds the first channel region and the second channel region; 6. The CMOS inverter of claim 5.

8. Further comprising a connecting metal; the connecting metal contacts the second hole-doped region and the second electron-doped region; 2. The CMOS inverter of claim 1.

9. an insulating layer disposed on the base substrate and covering the p-type semiconductor layer, the n-type semiconductor layer, the connection metal, and the first gate electrode; a plurality of terminals disposed on the insulating layer; and Further comprising a plurality of connection wires disposed on the base substrate; the plurality of terminals include a first input terminal, a power supply terminal, an output terminal, and a ground terminal; the plurality of connection wirings include first to fourth connection wirings, the first connection wiring is in contact with the first input terminal and the first gate electrode; the second connection wiring contacts the power supply terminal and the first hole-doped region; the third connection wiring is in contact with the output terminal and the connection metal; the fourth connection wiring contacts the ground terminal and the first electron-doped region; 9. The CMOS inverter of claim 8.

10. forming a vertical semiconductor layer on a base substrate; forming a first vertical semiconductor layer and a second vertical semiconductor layer on the base substrate; an ion doping step of doping ions into the first vertical semiconductor layer and the second vertical semiconductor layer; a gate forming step of forming a first gate electrode on the base substrate; forming a connection metal on the base substrate, the connection metal being in contact with the first vertical semiconductor layer and the second vertical semiconductor layer; forming an insulating layer to cover the first vertical semiconductor layer, the second vertical semiconductor layer, the first gate electrode, and the connection metal; and a wiring connection step of connecting the first vertical semiconductor layer, the second vertical semiconductor layer, the first gate electrode, and the connection metal to a plurality of terminals disposed on the insulating layer, respectively; The vertical semiconductor layer forming step includes: forming a sacrificial vertical pillar on the base substrate; forming spacers to cover the side surfaces of the sacrificial vertical pillars and the top surface of the base substrate; a spacer hard mask forming step in which a portion of the spacer is etched to form a spacer hard mask surrounding a side surface of the sacrificial vertical pillar; a cutting step in which the spacer hard mask and the sacrificial vertical pillars are cut in a direction perpendicular to the base substrate; a vertical layer forming step in which a portion of the base substrate and the sacrificial vertical pillars are removed to form a first vertical semiconductor layer and a second vertical semiconductor layer; The spacer hard mask is removed. A method for manufacturing a CMOS inverter, comprising:

11. The ion doping step includes: forming a first hole-doped region by doping the base substrate with first ions having a first energy in a direction perpendicular to the base substrate; forming a second hole-doped region by doping the base substrate with second ions having a second energy different from the first energy in a direction perpendicular to the base substrate; forming a first electron-doped region by doping the base substrate with third ions having a third energy in a direction perpendicular to the base substrate; forming a second electron-doped region by doping the base substrate with fourth ions having a fourth energy different from the third energy in a direction perpendicular to the base substrate; the first ions and the second ions include boron (B); the third ion and the fourth ion include arsenic (AS) or phosphine (P); 11. The method of manufacturing a CMOS inverter according to claim 10.

12. The gate forming step includes: a masking step of covering upper surfaces of the first vertical semiconductor layer and the second vertical semiconductor layer with a mask; a first insulating step of forming an insulating layer covering sides of the first hole-doped region and the first electron-doped region; a gate electrode disposed on the insulating layer, the gate electrode having a shape surrounding the first vertical semiconductor layer and the second vertical semiconductor layer; an etching step in which a portion of the gate electrode overlapping the second hole-doped region or the second electron-doped region is etched; 12. The method of claim 11, comprising:

13. The step of forming a connection metal is a masking removal step in which the mask covering the upper surfaces of the first vertical semiconductor layer and the second vertical semiconductor layer is removed; and forming a contact metal in contact with the first hole-doped region and the first electron-doped region; 13. The method of claim 12, comprising:

Images