Display device and tiled display device

Abstract

The display device includes a pixel. The pixel includes a first light-emitting element, a second light-emitting element, and a third light-emitting element that are arranged at equal intervals along a first direction, a first pixel electrode that is arranged along the first direction and contacts the first to third light-emitting elements, and a second pixel electrode that is arranged along the first direction in a pair with the first pixel electrode and contacts the first to third light-emitting elements. Each of the first to third light-emitting elements includes a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first and second semiconductor layers, and includes a mesa region in which one of the first and second semiconductor layers is partially exposed by the other one. The mesa region of the first light-emitting element contacts one of the first pixel electrodes.

Description

[Technical field]

[0001] The present invention relates to a display device and a tiled display device. [Background technology]

[0002] With the growing interest in information display and the increasing desire to utilize portable information media, the demand and commercialization of display devices has become increasingly focused. Summary of the Invention [Problem to be solved by the invention]

[0003] Depending on the viewing angle, color mixing may occur. For example, when a display device that displays a full white image is viewed from the side, the image may appear bluish or reddish.

[0004] An object of the present invention is to provide a display device and a tiled display device capable of preventing or reducing color mixing that occurs depending on a viewing angle. [Means for solving the problem]

[0005] A display device according to one or more embodiments of the present invention includes a pixel. The pixel includes a first light emitting element, a second light emitting element, and a third light emitting element arranged at equal intervals from each other along a first direction, a first pixel electrode arranged along the first direction and in contact with the first to third light emitting elements, and a second pixel electrode arranged along the first direction in a pair with the first pixel electrode and in contact with the first to third light emitting elements. Each of the first to third light emitting elements includes a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and includes a mesa region in which one of the first and second semiconductor layers is partially exposed by the other one. The mesa region of the first light emitting element contacts one of the first pixel electrodes, and the mesa region of the second light emitting element contacts one of the second pixel electrodes. The arrangement order of the first and second pixel electrodes in contact with the first light emitting element is reverse to the arrangement order of the first and second pixel electrodes in contact with the second light emitting element.

[0006] Each of the first, second, and third light emitting elements may include an inclined surface formed along an edge of the mesa region, and the inclined surfaces of the first, second, and third light emitting elements may face in the same direction.

[0007] The arrangement order of the first and second pixel electrodes in contact with the third light emitting element may be the same as the arrangement order of the first and second pixel electrodes in contact with the second light emitting element.

[0008] The first to third light-emitting elements may be sequentially arranged along the first direction, and a distance in the first direction between the first pixel electrodes in contact with the first and second light-emitting elements may be different from a distance in the first direction between the first pixel electrodes in contact with the second and third light-emitting elements.

[0009] The distance in the first direction between the first pixel electrodes in contact with the first and second light-emitting elements may be different from the distance in the first direction between the second pixel electrodes in contact with the first and second light-emitting elements.

[0010] The distance in the first direction between the first pixel electrodes in contact with the second and third light-emitting elements may be the same as the distance in the first direction between the second pixel electrodes in contact with the second and third light-emitting elements.

[0011] The first light emitting element may emit red light, and the second light emitting element may emit green or blue light.

[0012] The pixel may further include a first pixel circuit, a second pixel circuit, and a third pixel circuit that respectively supply driving currents to the first to third light-emitting elements via the first pixel electrode, and each of the first to third pixel circuits may include at least one transistor and at least one capacitor.

[0013] Each of the first to third pixel circuits may further include a bridge pattern in contact with the first pixel electrode, and a shape of the bridge pattern of the first pixel circuit may be different from a shape of the bridge pattern of the second pixel circuit.

[0014] The bridge pattern of the first pixel circuit may overlap with the second pixel electrode on a plane, and the bridge pattern of the second pixel circuit may not overlap with the second pixel electrode on a plane.

[0015] The first, second and third pixel circuits may have the same circuit structure.

[0016] The first pixel circuit may be positioned in a second direction based on the first light-emitting element, the second pixel circuit may be positioned in the second direction based on the second light-emitting element, and the third pixel circuit may be positioned in the second direction based on the third light-emitting element, and the second direction may be perpendicular to the first direction.

[0017] Each of the first to third light emitting devices may be a flip chip type micro light emitting diode device.

[0018] A display device according to an embodiment of the present invention includes a pixel. The pixel includes a first light emitting element, a second light emitting element, and a third light emitting element arranged at equal intervals from each other along a first direction, and a first pixel electrode arranged along the first direction and in contact with the first to third light emitting elements, each of the first to third light emitting elements including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and a mesa region in which one of the first and second semiconductor layers is partially exposed by the other one. The mesa region of the first light emitting element is formed in the first semiconductor layer, and the mesa region of the second light emitting element is formed in the second semiconductor layer. The first pixel electrodes are arranged at different intervals along the first direction.

[0019] A tiled display device according to one or more embodiments of the present invention includes a plurality of display devices and a joint portion disposed between the plurality of display devices, and a first display device among the plurality of display devices includes a substrate and a pixel located on a first surface of the substrate. The pixel includes a first light-emitting element, a second light-emitting element, and a third light-emitting element arranged at equal intervals from each other along a first direction, a first pixel electrode arranged along the first direction and in contact with the first to third light-emitting elements, and a second pixel electrode arranged along the first direction in a pair with the first pixel electrode and in contact with the first to third light-emitting elements. Each of the first to third light-emitting elements includes a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and includes a mesa region in which one of the first and second semiconductor layers is partially exposed by the other one. The mesa region of the first light-emitting element contacts one of the first pixel electrodes, and the mesa region of the second light-emitting element contacts one of the second pixel electrodes. The arrangement order of the first and second pixel electrodes in contact with the first light emitting element is reverse to the arrangement order of the first and second pixel electrodes in contact with the second light emitting element.

[0020] Each of the light emitting devices may be a flip chip type micro light emitting diode device.

[0021] The substrate may include glass.

[0022] The first display device may further include a pad arranged on a first surface of the substrate, and a side wiring arranged on the first surface of the substrate, a second surface opposite to the first surface, and one side surface between the first surface and the second surface and connected to the pad.

[0023] The first display device may further include a connecting wire disposed on a second surface of the substrate, and a flexible film connected to the connecting wire via a conductive adhesive member, and the side wire may be connected to the connecting wire.

[0024] The plurality of display devices may be arranged in a matrix form with M rows and N columns. Effect of the Invention

[0025] In the display device according to the embodiment of the present invention, the pixel electrode and the common electrode of at least one of the sub-pixels are swapped and arranged so that light emitting elements having different structures (e.g., light emitting elements having a mesa structure and opposite electrode arrangements) emitting different colors can be arranged in substantially the same direction or shape. Therefore, the light output rate of the light emitting elements becomes uniform for each direction (or each viewing angle), and color mixing phenomenon depending on the viewing angle can be prevented or mitigated.

[0026] The effects of the embodiments of the present invention are not limited to the above-mentioned examples, and various other effects are included in this specification.

[0027] The above and other aspects and features of the embodiments of the present invention will become more apparent from the following detailed description of the embodiments taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 is a plan view showing a display device according to an embodiment. [Diagram 2] FIG. 2 is a diagram illustrating an example of a pixel in FIG. [Diagram 3] FIG. 2 is a diagram illustrating an example of a pixel in FIG. [Figure 4] FIG. 2 is a plan view showing an embodiment of the display device of FIG. [Diagram 5] 5 is a diagram showing a connection relationship between pixel circuits and stages included in the display device of FIG. 4. [Figure 6] 5 is a plan view showing an example of the light emitting region of FIG. 4. [Figure 7] 7 is a cross-sectional view that illustrates an example of a display device taken along the line XX' in FIG. 6. [Figure 8] FIG. 11 is a cross-sectional view that illustrates an example of a display device according to a comparative example. [Figure 9] 5 is a plan view showing an example of the light emitting region of FIG. 4. [Figure 10] 5 is a plan view showing an example of the light emitting region of FIG. 4. [Figure 11] FIG. 5 is a circuit diagram showing an example of the sub-pixel of FIGS. 2 to 4. [Figure 12] FIG. 5 is a layout diagram showing an example of the sub-pixel of FIG. [Figure 13] FIG. 13 is an enlarged view of region A1 in FIG. [Figure 14] FIG. 13 is an enlarged view of region A2 in FIG. [Figure 15] FIG. 13 is an enlarged view of area A3 in FIG. [Figure 16] FIG. 13 is a cross-sectional view taken along line AA' in FIG. [Figure 17] 13 is a cross-sectional view taken along line BB' in FIG. 12. [Figure 18] FIG. 13 is a cross-sectional view taken along line CC' in FIG. [Figure 19] FIG. 13 is a cross-sectional view taken along line DD' in FIG. [Figure 20] 13 is a cross-sectional view taken along line EE' in FIG. 12. [Figure 21] 13 is a cross-sectional view taken along line FF' in FIG. 12. [Figure 22]FIG. 13 is a cross-sectional view taken along line GG' in FIG. [Figure 23] 13 is a cross-sectional view taken along line HH' in FIG. 12. [Figure 24] FIG. 13 is a cross-sectional view taken along line II' in FIG. [Diagram 25] FIG. 5 is a layout diagram showing an example of the sub-pixel of FIG. [Figure 26] FIG. 1 is a perspective view of a tiled display including multiple displays according to one or more embodiments. [Figure 27] FIG. 27 is an enlarged layout diagram showing the AA region in FIG. 26 in detail. [Figure 28] 28 is a cross-sectional view showing an example of a tiled display device taken along line JJ' in FIG. 27. [Figure 29] FIG. 27 is an enlarged layout diagram showing the BB region in detail in FIG. 26. [Diagram 30] 30 is a cross-sectional view showing an example of a tiled display device taken along line NN' in FIG. 29. [Diagram 31] FIG. 1 is a block diagram illustrating a tiled display device according to one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] The advantages and features of the embodiments of the present invention, as well as the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms, and the embodiments are provided to make the present invention complete and to fully convey the scope of the present invention to those skilled in the art to which the present invention pertains, and the present invention is defined only by the claims and their equivalents.

[0030] When elements or layers are referred to as "on" other elements or layers, this includes all cases where other layers or other elements are interposed between the elements or layers. The same reference characters refer to the same components throughout the specification. The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining the embodiments are merely examples, and the present invention is not limited to the details shown in the drawings.

[0031] The "connection" between two components may refer to both an electrical connection and a physical connection, but is not necessarily limited thereto. For example, the "connection" used with reference to a circuit diagram may refer to an electrical connection, and the "connection" used with reference to a cross-sectional view or a plan view may refer to a physical connection.

[0032] Although the terms "first", "second" and the like are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Thus, the first component described below may also be the second component within the technical spirit of the present invention.

[0033] The features of the various embodiments of the present invention may be partially or fully combined or combined with each other, may be technically linked and driven in various ways, and may be implemented independently of each other or may be implemented together in a linked relationship.

[0034] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0035] Figure 1 is a plan view of a display device according to one or more embodiments, Figure 2 is a diagram of an example pixel of Figure 1, and Figure 3 is a diagram of an example pixel of Figure 1.

[0036] Referring to FIG. 1, a display device 10 (or a display panel) according to one or more embodiments is a device for displaying images (e.g., moving images, still images) and can be used as a display screen for a variety of products, including portable electronic devices such as mobile phones, smart phones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and Ultra Mobile PCs (UMPCs), as well as televisions, notebook computers, monitors, billboards, and Internet of Things (IOT).

[0037] The display device 10 may be formed in a rectangular shape having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting with the first direction DR1. A corner where the long side in the first direction DR1 and the short side in the second direction DR2 intersect may be rounded or formed at a right angle to have an appropriate curvature (e.g., a predetermined curvature). The planar shape of the display device 10 is not limited to a rectangle, and may be formed in other polygonal, circular, or elliptical shapes. The display device 10 may be formed flat, but is not limited thereto. For example, the display device 10 may include curved portions having a constant curvature or a varying curvature formed on the left and right edges. The display device 10 may also be formed flexibly so that it can be bent, flexed, bent, folded, or rolled.

[0038] The display device 10 may further include pixels PX, scan lines extending in a first direction DR1, and data lines extending in a second direction DR2 to display an image. The pixels PX may be arranged in the first direction DR1 and the second direction DR2 in the form of a matrix. For example, the pixels PX may be arranged along rows and columns of a matrix in the first direction DR1 and the second direction DR2.

[0039] Each of the pixels PX can include a plurality of sub-pixels SPX1, SPX2, and SPX3, as shown in Figures 2 and 3. In Figures 2 and 3, each of the pixels PX is illustrated as including three sub-pixels SPX1, SPX2, and SPX3, i.e., a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3, but the embodiments of this specification are not limited thereto.

[0040] Each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be connected to one of the data lines and at least one of the scan lines.

[0041] Each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have a rectangular, square, or diamond-shaped planar shape. For example, each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2, as shown in Fig. 2. Alternatively, each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have a square or diamond-shaped planar shape including sides having the same length in the first direction DR1 and the second direction DR2, as shown in Fig. 3.

[0042] As shown in Fig. 2, the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be arranged along the first direction DR1. Alternatively, one of the second subpixel SPX2 and the third subpixel SPX3 and the first subpixel SPX1 may be arranged along the first direction DR1, and the remaining one of the second subpixel SPX2 and the third subpixel SPX3 and the first subpixel SPX1 may be arranged along the second direction DR2. For example, as shown in Fig. 3, the first subpixel SPX1 and the second subpixel SPX2 may be arranged along the first direction DR1, and the first subpixel SPX1 and the third subpixel SPX3 may be arranged along the second direction DR2.

[0043] Alternatively, the second subpixel SPX2 and one of the first subpixel SPX1 and the third subpixel SPX3 may be arranged along the first direction DR1, and the second subpixel SPX2 and the remaining one of the first subpixel SPX1 and the third subpixel SPX3 may be arranged along the second direction DR2. Alternatively, the third subpixel SPX3 and one of the first subpixel SPX1 and the second subpixel SPX2 may be arranged along the first direction DR1, and the remaining one of the first subpixel SPX1 and the second subpixel SPX2 may be arranged along the second direction DR2.

[0044] The first subpixel SPX1 may emit a first light, the second subpixel SPX2 may emit a second light, and the third subpixel SPX3 may emit a third light. Here, the first light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band. The red wavelength band may be a wavelength band of about 600 nm to 750 nm, the green wavelength band may be a wavelength band of about 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of about 370 nm to 460 nm, but the embodiments of the present specification are not limited thereto.

[0045] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include an inorganic light-emitting element having an inorganic semiconductor as a light-emitting element that emits light. For example, the inorganic light-emitting element may be a flip chip type micro LED (Light Emitting Diode), but the embodiments of the present specification are not limited thereto.

[0046] As shown in Fig. 2 and Fig. 3, the area of ​​the first subpixel SPX1, the area of ​​the second subpixel SPX2, and the area of ​​the third subpixel SPX3 may be substantially the same, but the embodiments of the present specification are not limited thereto. At least one of the area of ​​the first subpixel SPX1, the area of ​​the second subpixel SPX2, and the area of ​​the third subpixel SPX3 may be different from the other one. Or, any two of the area of ​​the first subpixel SPX1, the area of ​​the second subpixel SPX2, and the area of ​​the third subpixel SPX3 may be substantially the same, and the remaining one may be different from the two. Or, the area of ​​the first subpixel SPX1, the area of ​​the second subpixel SPX2, and the area of ​​the third subpixel SPX3 may be different from each other.

[0047] Figure 4 is a plan view showing an embodiment of the display device of Figure 1. Figure 5 is a diagram showing a connection relationship between pixel circuits and stages included in the display device of Figure 4. A plurality of stages may constitute at least one gate driver (or scan driver).

[0048] 1 to 5, a display device 10 includes a pixel PX, and the pixel PX may include first to third sub-pixels SPX1 to SPX3.

[0049] The first sub-pixel SPX1 includes a first light-emitting element ED1 and a first pixel circuit PC1, and the first pixel circuit PC1 can supply a driving current to the first light-emitting element ED1. The first pixel circuit PC1 is located in a second direction DR2 with respect to the first light-emitting element ED1, and the first pixel circuit PC1 can be electrically connected to the first light-emitting element ED1 via an anode connection line (see FIG. 6). The second sub-pixel SPX2 includes a second light-emitting element ED2 and a second pixel circuit PC2, and the second pixel circuit PC2 can supply a driving current to the second light-emitting element ED2. The second pixel circuit PC2 is located in the second direction DR2 with respect to the second light-emitting element ED2, and the second pixel circuit PC2 can be electrically connected to the second light-emitting element ED2 via an anode connection line (see FIG. 6). The third sub-pixel SPX3 includes a third light-emitting element ED3 and a third pixel circuit PC3, and the third pixel circuit PC3 can supply a driving current to the third light-emitting element ED3. The third pixel circuit PC3 is located in the second direction DR2 with respect to the third light emitting element ED3, and the third pixel circuit PC3 may be electrically connected to the third light emitting element ED3 via an anode connection line (see FIG. 6). Each of the first to third pixel circuits PC1 to PC3 may include at least one transistor (see “TFT” in FIG. 7) and at least one capacitor (see “C1” in FIG. 7).

[0050] According to one or more embodiments, each of the first to third sub-pixels SPX1 to SPX3 may include two light-emitting elements. For example, each of the first to third sub-pixels SPX1 to SPX3 may include, but is not limited to, a main light-emitting element and a repair light-emitting element. As another example, each of the first to third sub-pixels SPX1 to SPX3 may include three or more light-emitting elements. As will be described later with reference to FIG. 6, the first to third light-emitting elements ED1 to ED3 shown in FIG. 4 may also refer to the electrodes (e.g., anode electrodes and cathode electrodes) of the first to third light-emitting elements ED1 to ED3 in FIG.

[0051] Based on the light-emitting elements ED1, ED2, and ED3, the pixels PX may be arranged to have a uniform pixel pitch. The light-emitting elements ED1, ED2, and ED3 may be arranged along a plurality of pixel rows. For example, the light-emitting elements ED1, ED2, and ED3 may be arranged along the k-th to k+5-th pixel rows PROWk to PROWk+5 (where k is a positive integer). The pixel circuits PC1, PC2, and PC3 may be arranged along a plurality of circuit rows. The pixel circuits PC1, PC2, and PC3 may be arranged along the k-th to k+5-th circuit rows CROWk to CROWk+5.

[0052] The k-th pixel row PROWk may be adjacent to the k-th circuit row CROWk in the opposite direction of the second direction DR2, and the k+1-th pixel row PROWk+1 may be adjacent to the k+1-th circuit row CROWk+1 in the second direction DR2. The k-th and k+1-th circuit rows CROWk, CROWk+1 may be disposed between the k-th and k+1-th pixel rows PROWk, PROWk+1. Similarly, the k+2-th pixel row PROWk+2 may be adjacent to the k+2-th circuit row CROWk+2 in the opposite direction of the second direction DR2, and the k+3-th pixel row PROWk+3 may be adjacent to the k+3-th circuit row CROWk+3 in the second direction DR2. The k+2-th and k+3-th circuit rows CROWk+2, CROWk+3 may be disposed between the k+2-th and k+3-th pixel rows PROWk+2, PROWk+3. Similarly, the k+4th pixel row PROWk+4 may be adjacent to the k+4th circuit row CROWk+4 in the opposite direction of the second direction DR2, and the k+5th pixel row PROWk+5 may be adjacent to the k+5th circuit row CROWk+5 in the second direction DR2. The k+4th and k+5th circuit rows CROWk+4, CROWk+5 may be disposed between the k+4th and k+5th pixel rows PROWk+4, PROWk+5.

[0053] The kth stage STGk may be disposed above the kth circuit row CROWk and the kth pixel row PROWk. The kth stage STGk may supply gate signals to the kth gate line GLk connected to the pixel circuits PC1, PC2, and PC3 of the kth circuit row CROWk. The kth stage STGk may be connected to the kth gate line GLk via a connecting line CL. The kth stage STGk may be connected to the kth gate line GLk via a first connecting line CL1 extending in a first direction DR1 and a second connecting line CL2 extending in a second direction DR2.

[0054] The k+1th stage STGk+1 and the k+2nd stage STGk+2 may be disposed between the k+1th pixel row PROWk+1 and the k+2nd pixel row PROWk+2. The k+1th stage STGk+1 may be disposed below the k+1th circuit row CROWk+1 and the k+1th pixel row PROWk+1. The k+1th stage STGk+1 may supply a gate signal to the k+1th gate line GLk+1 connected to the pixel circuit PC of the k+1th circuit row CROWk+1. The k+1th stage STGk+1 may be connected to the k+1th gate line GLk+1 via a connection line CL.

[0055] The k+2-th stage STGk+2 may be disposed above the k+2-th circuit row CROWk+2 and the k+2-th pixel row PROWk+2. The k+2-th stage STGk+2 may supply a gate signal to the k+2-th gate line GLk+2 connected to the pixel circuit PC of the k+2-th circuit row CROWk+2. The k+2-th stage STGk+2 may be connected to the k+2-th gate line GLk+2 via a connecting line CL.

[0056] The k+3th stage STGk+3 and the k+4th stage STGk+4 may be disposed between the k+3th pixel row PROWk+3 and the k+4th pixel row PROWk+4. The k+3th stage STGk+3 may be disposed below the k+3th circuit row CROWk+3 and the k+3th pixel row PROWk+3. The k+3th stage STGk+3 may supply a gate signal to the k+3th gate line GLk+3 connected to the pixel circuit PC of the k+3th circuit row CROWk+3. The k+3th stage STGk+3 may be connected to the k+3th gate line GLk+3 via a connecting line CL.

[0057] The k+4th stage STGk+4 may be disposed above the k+4th circuit row CROWk+4 and the k+4th pixel row PROWk+4. The k+4th stage STGk+4 may supply a gate signal to the k+4th gate line GLk+4 connected to the pixel circuit PC of the k+4th circuit row CROWk+4. The k+4th stage STGk+4 may be connected to the k+4th gate line GLk+4 via a connecting line CL.

[0058] The k+5th stage STGk+5 may be disposed below the k+5th circuit row CROWk+5 and the k+5th pixel row PROWk+5. The k+5th stage STGk+5 may supply a gate signal to the k+5th gate line GLk+5 connected to the pixel circuit PC of the k+5th circuit row CROWk+5. The k+5th stage STGk+5 may be connected to the k+5th gate line GLk+5 via a connecting line CL.

[0059] The data line DL may include first to third data lines DL1 to DL3. The first data line DL1 may supply a data voltage to a plurality of first pixel circuits PC1 arranged in the same column. The second data line DL2 may supply a data voltage to a plurality of second pixel circuits PC2 arranged in the same column. The third data line DL3 may supply a data voltage to a plurality of third pixel circuits PC3 arranged in the same column.

[0060] Fig. 6 is a plan view showing an example of the light-emitting region of Fig. 4. For convenience of explanation, the light-emitting region EA is simply shown with the first and second contact electrodes ELT1, ELT2 of the light-emitting elements ED1, ED2, ED3 at the center. Fig. 7 is a cross-sectional view showing a schematic example of a display device cut along the line X-X' in Fig. 6.

[0061] 1 to 7, the display device 10 may include a substrate SUB, a buffer film BF, an active layer ACTL, a first gate insulating film GI1, a first gate layer GTL1, a second gate insulating film GI2, a second gate layer GTL2, an interlayer insulating film ILD, a first source metal layer SDL1, a first via layer VIA1, a first protective layer PAS1, a second source metal layer SDL2, a second via layer VIA2, a second protective layer PAS2, a third source metal layer SDL3, a third via layer VIA3, a third protective layer PAS3, a fourth source metal layer SDL4, a fourth via layer VIA4, and a fourth protective layer PAS4.

[0062] The substrate SUB may be a base substrate or a base member for supporting the display device 10. The substrate SUB may be a rigid substrate made of a glass material. Alternatively, the substrate SUB may be a flexible substrate capable of bending, folding, rolling, etc. In this case, the substrate SUB may include an insulating material such as a polymer resin such as polyimide (PI).

[0063] A buffer film BF may be disposed on one surface of the substrate SUB. The buffer film BF may be a film for preventing the penetration of air or moisture. The buffer film BF may be made of a plurality of inorganic films alternately stacked. For example, the buffer film BF may be formed of a multi-layer in which one or more inorganic films selected from the group consisting of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The buffer film BF may be omitted.

[0064] The active layer ACTL may be disposed on the buffer film BF. The active layer ACTL may include a silicon semiconductor such as polycrystalline silicon, single crystal silicon, low-temperature polycrystalline silicon, and amorphous silicon, or may include an oxide semiconductor.

[0065] The active layer ACTL may include a channel CH, a first electrode SE, and a second electrode DE of the thin film transistor TFT. The channel CH of the thin film transistor TFT may be a region overlapping with the gate electrode GE of the thin film transistor TFT in a third direction DR3 that is a thickness direction of the substrate SUB. The first electrode SE of the thin film transistor TFT may be disposed on one side of the channel CH, and the second electrode DE may be disposed on the other side of the channel CH. The first electrode SE and the second electrode DE of the thin film transistor TFT may be regions that do not overlap with the gate electrode GE in the third direction DR3. The first electrode SE and the second electrode DE of the thin film transistor TFT may be regions that are conductive due to ions being doped into a silicon semiconductor or an oxide semiconductor.

[0066] A first gate insulating film GI1 may be disposed on the active layer ACTL and the buffer film BF. The first gate insulating film GI1 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0067] A first gate layer GTL1 may be disposed on the first gate insulating film GI1. The first gate layer GTL1 may include a gate electrode GE of the thin film transistor TFT and a first capacitor electrode CE1. The first gate layer GTL1 may be formed of a single layer or multiple layers (stacked film) made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0068] A second gate insulating film GI2 may be disposed on the first gate layer GTL1 and the first gate insulating film GI1. The second gate insulating film GI2 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0069] A second gate layer GTL2 may be disposed on the second gate insulating film GI2. The second gate layer GTL2 may include a second capacitor electrode CE2. The second capacitor electrode CE2 may configure a first capacitor C1 together with the first capacitor electrode CE1.

[0070] The second gate layer GTL2 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0071] An interlayer insulating film ILD may be disposed on the second gate layer GTL2 and the second gate insulating film GI2. The interlayer insulating film ILD may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0072] A first source metal layer SDL1 including a connection electrode CCE (or a connection pattern) may be disposed on the interlayer insulating film ILD. The first source metal layer SDL1 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0073] The connecting electrode CCE may be connected to the first electrode SE or the second electrode DE of the thin film transistor TFT through a contact hole passing through the interlayer insulating film ILD, the second gate insulating film GI2, and the first gate insulating film GI1.

[0074] A first via layer VIA1 (or a first planarization film) for planarizing steps caused by the active layer ACTL, the first gate layer GTL1, the second gate layer GTL2, and the first source metal layer SDL1 may be formed on the first source metal layer SDL1 and the interlayer insulating film ILD. The first via layer VIA1 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0075] The first protective layer PAS1 (or a first insulating film) may be disposed on the first via layer VIA1. The first protective layer PAS1 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0076] A second source metal layer SDL2 may be disposed on the first protective layer PAS1. The second source metal layer SDL2 may include an anode connection line ACL. The anode connection line ACL may be connected to the connection electrode CCE through a contact hole penetrating the first protective layer PAS1 and the first via layer VIA1. The second source metal layer SDL2 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0077] 4 and 6, the anode connecting lines ACL may extend in a second direction DR2 from the pixel circuits PC1, PC2, and PC3. The anode connecting lines ACL of the sub-pixels SPX1, SPX2, and SPX3 may have substantially the same shape and arrangement.

[0078] According to one or more embodiments, the first via layer VIA1 and the first protective layer PAS1 may be omitted. In this case, the connecting electrode CCE may be included in the anode connecting line ACL or may be omitted. For example, the anode connecting line ACL may be connected to the first electrode SE or the second electrode DE of the thin film transistor TFT through a contact hole penetrating the interlayer insulating film ILD, the second gate insulating film GI2, and the first gate insulating film GI1.

[0079] A second via layer VIA2 for flattening the step may be disposed on the second source metal layer SDL2 and the first protective layer PAS1. The second via layer VIA2 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0080] A second protective layer PAS2 (or a second insulating film) may be disposed on the second via layer VIA2. The second protective layer PAS2 may be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0081] A third source metal layer SDL3 may be formed on the second passivation layer PAS2. The third source metal layer SDL3 may include anode connecting electrodes ACE1, ACE2, and ACE3 (or bridge electrodes, bridge patterns). Each of the anode connecting electrodes ACE1, ACE2, and ACE3 may be connected to the anode connecting line ACL through a contact hole penetrating the second passivation layer PAS2 and the second via layer VIA2. The third source metal layer SDL3 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0082] The first anode connecting electrode ACE1 may have a different shape from the second and third connecting electrodes ACE2, ACE3. The second and third connecting electrodes ACE2, ACE3 may have the same shape and the same arrangement as each other. Compared with the second and third connecting electrodes ACE2, ACE3, the first anode connecting electrode ACE1 may extend further in the first direction DR1. The first anode connecting electrode ACE1 extends from the pixel electrode AND (or the first pixel electrode) to the common electrode COM (or the second pixel electrode) (i.e., from the pixel electrode AND to the common electrode COM adjacent to the pixel electrode AND in the first direction DR1), and the first anode connecting electrode ACE1 may overlap (may overlap) the pixel electrode AND and the common electrode COM in the third direction DR3. The second and third connecting electrodes ACE2, ACE3 may overlap the pixel electrode AND in the third direction DR3 and may not overlap the common electrode COM.

[0083] A third via layer VIA3 for flattening steps may be formed on the third source metal layer SDL3 and the second protective layer PAS2. The third via layer VIA3 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0084] The third protective layer PAS3 may be disposed on the third via layer VIA3. The third protective layer PAS3 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0085] The pixel electrode AND (or the first pixel electrode) and the common electrode COM (or the second pixel electrode) may be disposed on the third passivation layer PAS3. The pixel electrode AND may be called an anode electrode, and the common electrode COM may be called a cathode electrode.

[0086] The pixel electrode AND may be connected to a corresponding one of the anode connecting electrodes ACE1, ACE2, and ACE3 through a contact hole penetrating the third passivation layer PAS3 and the third via layer VIA3. Thus, the pixel electrode AND may be electrically connected to the first electrode SE or the second electrode DE of the thin film transistor TFT. Thus, a pixel voltage or an anode voltage controlled by the thin film transistor TFT may be applied to the pixel electrode AND.

[0087] Similar to the pixel electrode AND, the common electrode COM may be connected to a power line (e.g., a third power line VSL (see FIG. 11)) through a contact hole penetrating the third passivation layer PAS3 and the third via layer VIA3, so that a power voltage of the power line may be applied to the common electrode COM.

[0088] The pixel electrode AND and the common electrode COM may include highly reflective metal materials such as a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a laminated structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0089] The pixel electrodes AND and the common electrode COM may be arranged along a first direction DR1.

[0090] In one or more embodiments, the electrode arrangement or electrode arrangement order (i.e., the order in which the pixel electrode AND and the common electrode COM are arranged) for one of the subpixels SPX1, SPX2, SPX3 may be different from the electrode arrangement for the other of the subpixels SPX1, SPX2, SPX3.

[0091] As shown in FIGS. 6 and 7, the pixel electrode AND of the first subpixel SPX1 may be located in the opposite direction (side) from the common electrode COM of the first subpixel SPX1 in the first direction DR1. Here, the common electrode COM may refer to a portion of the common electrode COM that contacts or overlaps with a light-emitting element (e.g., the first light-emitting element ED1 of the first subpixel SPX1). The pixel electrode AND of the second subpixel SPX2 may be located in the first direction DR1 from the common electrode COM of the second subpixel SPX2. The pixel electrode AND of the third subpixel SPX3 may be located in the first direction DR1 from the common electrode COM of the third subpixel SPX3. That is, the pixel electrode AND and the common electrode COM of the first subpixel SPX1, the common electrode COM and the pixel electrode AND of the second subpixel SPX2, and the common electrode COM and the pixel electrode AND of the third subpixel SPX3 may be sequentially arranged along the first direction DR1.

[0092] Thus, even though the subpixels SPX1, SPX2, and SPX3 are disposed at equal intervals within one light-emitting area EA, the first distance DSA1 between the pixel electrode AND of the first subpixel SPX1 and the pixel electrode AND of the second subpixel SPX2 may be different from the second distance DSA2 between the pixel electrode AND of the second subpixel SPX2 and the pixel electrode AND of the third subpixel SPX3. Here, the first distance DSA1 and the second distance DSA2 may be calculated based on the areal center of the pixel electrode AND, but are not limited thereto. For example, the first distance DSA1 and the second distance DSA2 may be calculated based on the corresponding sides of the pixel electrodes AND. Similarly, the first distance DSC1 between the common electrode COM of the first subpixel SPX1 and the common electrode COM of the second subpixel SPX2 may be different from the second distance DSC2 between the common electrode COM of the second subpixel SPX2 and the common electrode COM of the third subpixel SPX3.

[0093] A first distance DSC1 between the common electrode COM of the first subpixel SPX1 and the common electrode COM of the second subpixel SPX2 may be different from a first distance DSA1 between the pixel electrode AND of the first subpixel SPX1 and the pixel electrode AND of the second subpixel SPX2. In contrast, a second distance DSC2 between the common electrode COM of the second subpixel SPX2 and the common electrode COM of the third subpixel SPX3 may be the same as a second distance DSA2 between the pixel electrode AND of the second subpixel SPX2 and the pixel electrode AND of the third subpixel SPX3.

[0094] A fourth via layer VIA4 (or a bank, a pixel definition film) covering the periphery of the pixel electrode AND and the periphery of the common electrode COM may be disposed on the third protective layer PAS3. The fourth via layer VIA4 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0095] The fourth protective layer PAS4 may be disposed on the fourth via layer VIA4. The fourth protective layer PAS4 may cover the periphery of the pixel electrode AND and the periphery of the common electrode COM. The fourth protective layer PAS4 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0096] The light-emitting elements ED1, ED2, and ED3 can be disposed on the pixel electrodes AND and the common electrode COM that are not covered by the fourth protective layer PAS4.

[0097] FIG. 7 illustrates that each of the light emitting elements ED1, ED2, and ED3 is a flip-chip type micro LED in which the first contact electrode ELT1 and the second contact electrode ELT2 are disposed to face the pixel electrode AND and the common electrode COM. The light emitting elements ED1, ED2, and ED3 may be formed of an inorganic material such as GaN. The length in the first direction DR1, the length in the second direction DR2, and the length in the third direction DR3 of each of the light emitting elements ED1, ED2, and ED3 may be several to several hundred μm. For example, the length in the first direction DR1, the length in the second direction DR2, and the length in the third direction DR3 of each of the light emitting elements ED1, ED2, and ED3 may be approximately 100 μm or less.

[0098] The light emitting elements ED1, ED2, and ED3 may be formed by growing on a semiconductor substrate such as a silicon wafer. Each of the light emitting elements ED1, ED2, and ED3 may be directly transferred from the silicon wafer onto the pixel electrode AND and the common electrode COM of the substrate SUB. Alternatively, each of the light emitting elements ED1, ED2, and ED3 may be transferred onto the pixel electrode AND and the common electrode COM of the substrate SUB through an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicone as a transfer substrate.

[0099] Each of the light emitting elements ED1, ED2, and ED3 may be a light emitting structure including a first semiconductor layer 11, 11_1 (or a first semiconductor), an active layer 12, 12_1, a second semiconductor layer 13, 13_1 (or a second semiconductor), a first contact electrode ELT1, and a second contact electrode ELT2. According to one or more embodiments, the light emitting elements ED1, ED2, and ED3 may further include a base substrate (see "SSUB" in FIG. 28) located at the top. The base substrate may be, but is not limited to, a sapphire substrate.

[0100] The first semiconductor layers 11 and 11_1 may be disposed on one surface of the active layers 12 and 12_1. The first semiconductor layers 11 and 11_1 may be made of GaN doped with a p-type conductivity dopant such as Mg, Zn, Ca, Se, or Ba.

[0101] The active layer 12, 12_1 may be disposed on a portion of one surface of the first semiconductor layer 11, 11_1. The active layer 12, 12_1 may include a material having a single or multiple quantum well structure. When the active layer 12, 12_1 includes a material having a multiple quantum well structure, the active layer 12, 12_1 may have a structure in which a plurality of well layers and barrier layers are alternately stacked. Here, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer 12, 12_1 may have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked, and may include different group III to group V semiconductor materials depending on the wavelength band of the emitted light.

[0102] When the active layers 12 and 12_1 include InGaN, the color of the emitted light may change depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layers 12 and 12_1 may shift to the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the emitted light may shift to the blue wavelength band. For example, the indium (In) content of the active layer 12 of the third light emitting element ED3 of the third subpixel SPX3 may be about 15%, the indium (In) content of the active layer 12 of the second light emitting element ED2 of the second subpixel SPX2 may be about 25%, and the indium (In) content of the active layer 12_1 of the first light emitting element ED1 of the first subpixel SPX1 may be 35% or more. That is, by adjusting the indium (In) content of the active layer 12 or 12_1, the light-emitting element ED1 of the first pixel SPX1 can emit light of a first color (e.g., red), the light-emitting element ED2 of the second pixel SPX2 can emit light of a second color (e.g., green), and the light-emitting element ED3 of the third pixel SPX3 can emit light of a third color (e.g., blue).

[0103] The second semiconductor layer 13, 13_1 may be disposed on the other surface of the active layer 12, 12_1. For example, the second semiconductor layer 13, 13_1 may be made of GaN doped with an n-type conductivity dopant such as Si, Ge, or Sn.

[0104] The first contact electrode ELT1 may be arranged on one surface of the first semiconductor layer 11, 11_1, and the second contact electrode ELT2 may be arranged on one surface of the second semiconductor layer 13, 13_1.

[0105] The first contact electrode ELT1 and the pixel electrode AND may be bonded to each other via a conductive adhesive material such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP), or may be bonded to each other through a soldering process.

[0106] In one or more embodiments, because of the flip chip type, each of the light emitting elements ED1, ED2, ED3 may have a mesa structure. For example, each of the light emitting elements ED1, ED2, ED3 may have a mesa region in which one of the first semiconductor layer 11, 11_1 and the second semiconductor layer 13, 13_1 is partially exposed by the other. For example, in the first light emitting element ED1, the second semiconductor layer 13_1 may have a shape protruding on one surface of the first semiconductor layer 11_1, and one surface of the first semiconductor layer 11_1 may be partially exposed by the second semiconductor layer 13_1. The first contact electrode ELT1 of the first light emitting element ED1 may be disposed on the exposed one surface of the first semiconductor layer 11_1, i.e., in the mesa region. For example, in the second and third light emitting elements ED2, ED3, the first semiconductor layer 11 may have a shape protruding on one surface of the second semiconductor layer 13, and one surface of the second semiconductor layer 13 may be partially exposed by the first semiconductor layer 11. The second contact electrodes ELT2 of the second and third light emitting elements ED2 and ED3 may be disposed on the exposed surface of the second semiconductor layer 13, that is, in the mesa region.

[0107] For reference, the second and third light emitting elements ED2 and ED3 may be manufactured by growing the active layer 12 and the first semiconductor layer 11 on the second semiconductor layer 13. Alternatively, the first light emitting element ED1 may be manufactured by growing the active layer 12_1 and the second semiconductor layer 13_1 on the first semiconductor layer 11_1 to satisfy the indium (In) content of the active layer 12_1. As a result, the first to third light emitting elements ED1 to ED3 have the same shape, but the arrangement of the first and second contact electrodes ELT1 and ELT2 of the first light emitting element ED1 may be different from (for example, may be reversed) the arrangement of the first and second contact electrodes ELT1 and ELT2 of the second and third light emitting elements ED2 and ED3.

[0108] By swapping the pixel electrode AND and the common electrode COM of the first subpixel SPX1, i.e., by designing the arrangement order of the pixel electrode AND and the common electrode COM of the first subpixel SPX1 to be reverse to the arrangement order of the pixel electrodes AND and the common electrodes COM of the second and third subpixels SPX2 and SPX3, the light emitting elements ED1, ED2, and ED3 may be arranged along substantially the same direction and / or in substantially the same shape. For example, in accordance with the mesa structure, an inclined surface may be formed on the edge of each mesa region of the first to third light emitting elements ED1 to ED3, and each inclined surface of the first to third light emitting elements ED1 to ED3 may face substantially the same direction (for example, the first direction DR1). In this case, the light emitting directions (or light emitting characteristics in each direction) of the light emitting elements ED1, ED2, and ED3 become uniform, and color mixing phenomenon occurring depending on the viewing angle (viewing angle) can be mitigated or prevented.

[0109] FIG. 8 is a cross-sectional view that illustrates an example of a display device according to a comparative example.

[0110] 1, 4, and 6 to 8, a display device 10_C according to a comparative example can include a first subpixel SPX1_C, a second subpixel SPX2, and a third subpixel SPX3. The second subpixel SPX2 and the third subpixel SPX3 have been described with reference to Figs. 6 and 7, and the first subpixel SPX1_C is similar to the first subpixel SPX1 in Fig. 6, so that the overlapping description will not be repeated.

[0111] Except for the light emitting elements ED1, ED2, and ED3, the first subpixel SPX1_C, the second subpixel SPX2, and the third subpixel SPX3 may have the same structure as each other. For example, the first anode connecting electrode ACE1_C of the first subpixel SPX1_C may have the same shape and arrangement as the second and third anode connecting electrodes ACE2 and ACE3. In addition, the arrangement order of the pixel electrode AND_C and the common electrode COM_C of the first subpixel SPX1_C may be the same as the arrangement order of the pixel electrodes AND and the common electrode COM of the second and third subpixels SPX2 and SPX3.

[0112] In this case, the first light emitting element ED1 may be arranged in a different direction from the second and third light emitting elements ED2 and ED3 in order to contact the pixel electrode AND_C and the common electrode COM_C. The current movement direction of the first, second and third light emitting elements ED1, ED2 and ED3 is the same (for example, the opposite direction to the first direction DR1), but the directions in which the inclined surfaces of the first to third light emitting elements ED1 to ED3 face may be different.

[0113] Light emitted from each of the inclined surfaces (i.e., inclined surfaces formed at the edge of the mesa region) of the first to third light emitting elements ED1 to ED3 may be obstructed by the contact electrodes ELT1 and ELT2 (and / or bonding material), and thus the light output ratio of the first to third light emitting elements ED1 to ED3 may differ depending on the direction. For example, the light output ratio of the first light emitting element ED1 in the first direction DR1 (e.g., the right side in FIG. 8) may be lower than the light output ratio of the first light emitting element ED1 in the opposite direction to the first direction DR1 (e.g., the left side in FIG. 8). In contrast, the light output ratio of the second and third light emitting elements ED2 and ED3 in the first direction DR1 may be higher than the light output ratio of the second and third light emitting elements ED2 and ED3 in the opposite direction to the first direction DR1. This may cause a color mixing phenomenon depending on the viewing angle. For example, when the display device 10_C is viewed from the left side, the image may appear reddish because the amount of light of the first color (e.g., red) emitted from the first light-emitting element ED1 is relatively large. As another example, when the display device 10_C is viewed from the right side, the image may appear bluish (or cyanish) because the amount of light of the second and third colors emitted from the second and third light-emitting elements ED2 and ED3 is relatively large.

[0114] Therefore, the display device 10 according to one or more embodiments of the present invention includes light-emitting elements ED1, ED2, and ED3 arranged in substantially the same direction by swapping the pixel electrode AND and the common electrode COM of the first sub-pixel SPX1, thereby preventing color mixing due to viewing angle.

[0115] 9 and 10 are plan views showing other examples of the light emitting region of FIG.

[0116] First, referring to Figures 1 to 4, 6, and 9, the electrode arrangement order of the first sub-pixel SPX1_1 (i.e., the order in which the pixel electrode AND and the common electrode COM are arranged) may be different from the electrode arrangement order of the second and third sub-pixels SPX2_1, SPX3_1.

[0117] Based on the pixel electrode AND being positioned in the first direction DR1 from the common electrode COM, in FIG. 6, the pixel electrode AND and the common electrode COM of the first subpixel SPX1 are swapped, and in FIG. 9, the pixel electrodes AND and the common electrode COM of the second and third subpixels SPX2_1, SPX3_1 can be swapped instead of the first subpixel SPX1_1.

[0118] Therefore, the second anode connecting electrode ACE2_1 of the second subpixel SPX2_1 and the third anode connecting electrode ACE3_1 of the third subpixel SPX3_1 may extend further in the first direction DR1 than the first anode connecting electrode ACE1_1 of the first subpixel SPX1_1. Each of the second and third anode connecting electrodes ACE2_1, ACE3_1 may extend from the pixel electrode AND to the common electrode COM (i.e., the common electrode COM adjacent to the pixel electrode AND in the first direction DR1), and each of the second and third anode connecting electrodes ACE2_1, ACE3_1 may overlap the pixel electrode AND and the common electrode COM in the third direction DR3. The first anode connecting electrode ACE1_1 may overlap the pixel electrode AND in the third direction DR3 and not overlap the common electrode COM.

[0119] In this case, the light emitting elements ED1_1, ED2_1, and ED3_1 may be aligned in the same direction as each other, but in the opposite direction to the aligned direction of the light emitting elements ED1, ED2, and ED2 shown in Fig. 7. For example, the inclined surfaces (i.e., the inclined surfaces due to the mesa structure) of the light emitting elements ED1_1, ED2_1, and ED3_1 may be substantially oriented in the opposite direction to the first direction DR1.

[0120] 6 and 10, the electrode arrangement order of the second sub-pixel SPX2_1 (ie, the order in which the pixel electrode AND and the common electrode COM are arranged) may be different from the electrode arrangement order of the first and third sub-pixels SPX1_1 and SPX3.

[0121] On the basis that the pixel electrode AND is located in the first direction DR1 from the common electrode COM, the pixel electrode AND of the second subpixel SPX2_1 may be swapped with the common electrode COM instead of the first subpixel SPX1_1. The first subpixel SPX1_1 (and the first anode connecting electrode ACE1_1) and the second subpixel SPX2_1 (and the second anode connecting electrode ACE1_2) have been described with reference to FIG. 9, so redundant description will not be repeated.

[0122] For example, if the second light-emitting element ED2_1 of the second sub-pixel SPX2_1 emits red light or the structure of the second light-emitting element ED2_1 is opposite to the structures of the first and third light-emitting elements ED1_1 and ED3, the pixel electrode AND of the second sub-pixel SPX2_1 and the common electrode COM can be swapped.

[0123] However, this is not limited to the above. When the structure of the light-emitting element of at least one of the subpixels SPX1_1, SPX2_1, and SPX3 is different from the structure of the remaining light-emitting elements, the electrode arrangement order of the subpixels SPX1_1, SPX2_1, and SPX3 may be different from the electrode arrangement order of the remaining subpixels SPX1_1, SPX2_1, and SPX3. For example, only the electrode arrangement order of the third subpixel SPX3 may be different from the electrode arrangement order of the first and second subpixels SPX1_1 and SPX2_1.

[0124] FIG. 11 is a circuit diagram showing an example of the sub-pixel of FIGS.

[0125] 1 to 4 and 11, pixel circuits of the sub-pixels SPX1, SPX2, and SPX3 may be substantially the same or similar to each other. The sub-pixel SPX may correspond to each of the sub-pixels SPX1, SPX2, and SPX3.

[0126] The sub-pixel SPX may include a light-emitting element ED and a pixel circuit PC that provides a drive current to the light-emitting element ED.

[0127] The pixel circuit PC may be connected to a scan write line GWL, a scan initialization line GIL, a scan control line GCL, a sweep line SWPL, a PWM (Pulse Width Modulation) light emitting line PWEL, a PAM (Pulse Amplitude Modulation) light emitting line PAEL, a data line DL, and a PAM data line RDL. The scan write line GWL, the scan initialization line GIL, the scan control line GCL, the sweep line SWPL, the PWM light emitting line PWEL, and the PAM light emitting line PAEL may be included in the scan lines. The data line DL and the PAM data line RDL may correspond to the gate lines described with reference to FIG. 5 or may be included in the gate lines. The pixel circuit PC may be connected to a first power supply line VDL1 to which a first power supply voltage is applied, a second power supply line VDL2 to which a second power supply voltage is applied, a third power supply line VSL to which a third power supply voltage is applied, an initialization voltage line VIL to which an initialization voltage is applied, and a gate-off voltage line VGHL to which a gate-off voltage is applied.

[0128] The pixel circuit PC may include a first pixel driving unit PDU1 (or a first sub-circuit), a second pixel driving unit PDU2 (or a second sub-circuit), and a third pixel driving unit PDU3 (or a third sub-circuit).

[0129] The light emitting element ED may emit light according to a driving current generated by the second pixel driving unit PDU2. The light emitting element ED may be disposed between the seventeenth transistor T17 and the third power line VSL. A first electrode of the light emitting element ED may be connected to a second electrode of the seventeenth transistor T17, and a second electrode of the light emitting element ED may be connected to the third power line VSL. Here, the first electrode of the light emitting element ED may be an anode electrode, and the second electrode may be a cathode electrode. The light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the light emitting element ED may be, but is not limited to, a micro light emitting diode (Micro LED) made of an inorganic semiconductor.

[0130] The first pixel driver PDU1 may generate a control current based on the data voltage of the data line DL to control the voltage of the third node N3 of the third pixel driver PDU3. The control current of the first pixel driver PDU1 may adjust the pulse width of the voltage applied to the first electrode of the light emitting element ED, and the first pixel driver PDU1 may perform pulse width modulation of the voltage applied to the first electrode of the light emitting element ED. Therefore, the first pixel driver PDU1 may be a pulse width modulation unit (i.e., a PWM unit).

[0131] The first pixel driving unit PDU1 may include first to seventh transistors T1 to T7 and a first capacitor C1.

[0132] The first transistor T1 can control a control current flowing between the first power supply line VDL1 and the third node N3 based on a voltage (eg, a data voltage) applied to the gate electrode.

[0133] The second transistor T2 may be turned on by a scan write signal of the scan write line GWL to supply a data voltage of the data line DL to the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the scan write line GWL, a first electrode may be connected to the data line DL, and a second electrode may be connected to the first electrode of the first transistor T1.

[0134] The third transistor T3 (e.g., T31, T32) may be turned on by a scan initialization signal of the scan initialization line GIL and electrically connect the initialization voltage line VIL to the gate electrode of the first transistor T1. During a period in which the third transistor T3 is turned on, the gate electrode of the first transistor T1 may be discharged to an initialization voltage of the initialization voltage line VIL. A gate-on voltage of the scan initialization signal may be different from the initialization voltage of the initialization voltage line VIL. Since a difference voltage between the gate-on voltage and the initialization voltage is greater than a threshold voltage of the third transistor T3, the third transistor T3 may be stably turned on even after the initialization voltage is applied to the gate electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the gate electrode of the first transistor T1 may stably receive the initialization voltage regardless of the threshold voltage of the third transistor T3.

[0135] The third transistor T3 may include a plurality of transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. The first and second sub-transistors T31 and T32 may prevent the voltage of the gate electrode of the first transistor T1 from leaking through the third transistor T3. The gate electrode of the first sub-transistor T31 may be connected to a scan initialization line GIL, a first electrode may be connected to the gate electrode of the first transistor T1, and a second electrode may be connected to a first electrode of the second sub-transistor T32. The gate electrode of the second sub-transistor T32 may be connected to the scan initialization line GIL, a first electrode may be connected to the second electrode of the first sub-transistor T31, and a second electrode may be connected to an initialization voltage line VIL.

[0136] The fourth transistor T4 may be turned on by a scan write signal on the scan write line GWL to electrically connect the gate electrode of the first transistor T1 to the second electrode of the first transistor T1. Thus, during a period in which the fourth transistor T4 is turned on, the first transistor T1 may operate as a diode (e.g., the first transistor T1 may be diode-connected).

[0137] The fourth transistor T4 may include a plurality of transistors connected in series. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42. The third and fourth sub-transistors T41 and T42 may prevent the voltage of the gate electrode of the first transistor T1 from leaking through the fourth transistor T4. The gate electrode of the third sub-transistor T41 may be connected to a scan write line GWL, a first electrode may be connected to a second electrode of the first transistor T1, and a second electrode may be connected to a first electrode of the fourth sub-transistor T42. The gate electrode of the fourth sub-transistor T42 may be connected to a scan write line GWL, a first electrode may be connected to a second electrode of the third sub-transistor T41, and a second electrode may be connected to a gate electrode of the first transistor T1.

[0138] The fifth transistor T5 may be turned on by a PWM light emitting signal of the PWM light emitting line PWEL to electrically connect the first power supply line VDL1 to a first electrode of the first transistor T1. A gate electrode of the fifth transistor T5 may be connected to the PWM light emitting line PWEL, a first electrode of the fifth transistor T5 may be connected to the first power supply line VDL1, and a second electrode of the fifth transistor T5 may be connected to the first electrode of the first transistor T1.

[0139] The sixth transistor T6 may be turned on by a PWM light emitting signal of the PWM light emitting line PWEL to electrically connect the second electrode of the first transistor T1 to the third node N3 of the third pixel driving unit PDU3. The sixth transistor T6 may have a gate electrode connected to the PWM light emitting line PWEL, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the third node N3 of the third pixel driving unit PDU3.

[0140] The seventh transistor T7 may be turned on by a scan control signal of the scan control line GCL to supply a gate-off voltage of the gate-off voltage line VGHL to the first node N1 connected to the sweep line SWPL. Therefore, during a period in which an initialization voltage is applied to the gate electrode of the first transistor T1 and a period in which the data voltage of the data line DL and the threshold voltage Vth1 of the first transistor T1 are programmed, a voltage change of the gate electrode of the first transistor T1 may be prevented from being reflected in the sweep signal of the sweep line SWPL by the first capacitor C1. The gate electrode of the seventh transistor T7 may be connected to the scan control line GCL, a first electrode may be connected to the gate-off voltage line VGHL, and a second electrode may be connected to the first node N1.

[0141] The first capacitor C1 may be disposed between the gate electrode of the first transistor T1 and a first node N1, with one electrode of the first capacitor C1 being coupled to the gate electrode of the first transistor T1 and the other electrode being coupled to the first node N1.

[0142] The second pixel driver PDU2 may generate a driving current to be supplied to the light emitting element ED based on the PAM data voltage of the PAM data line RDL. The second pixel driver PDU2 may be a pulse amplitude modulation unit (i.e., a PAM unit) that performs pulse amplitude modulation. The second pixel driver PDU2 may be a constant current generator that receives the same PAM data voltage and generates the same driving current regardless of the luminance of the sub-pixels SPX1, SPX2, and SPX3.

[0143] The second pixel driving unit PDU2 may include eighth to fourteenth transistors T8 to T14 and a second capacitor C2.

[0144] The eighth transistor T8 can control the driving current flowing through the light emitting element ED based on the voltage applied to the gate electrode.

[0145] The ninth transistor T9 may be turned on by a scan write signal on the scan write line GWL to supply the PAM data voltage on the PAM data line RDL to a first electrode of the eighth transistor T8. A gate electrode of the eighth transistor T8 may be connected to the scan write line GWL, a first electrode of the eighth transistor T8 may be connected to the PAM data line RDL, and a second electrode of the eighth transistor T8 may be connected to the first electrode of the eighth transistor T8.

[0146] The tenth transistor T10 may be turned on by a scan initialization signal of the scan initialization line GIL to electrically connect the initialization voltage line VIL to the gate electrode of the eighth transistor T8. During a period in which the tenth transistor T10 is turned on, the gate electrode of the eighth transistor T8 may be discharged to the initialization voltage of the initialization voltage line VIL. The gate-on voltage of the scan initialization signal may be different from the initialization voltage of the initialization voltage line VIL. Since the difference voltage between the gate-on voltage and the initialization voltage is greater than the threshold voltage of the tenth transistor T10, the tenth transistor T10 may be stably turned on even after the initialization voltage is applied to the gate electrode of the eighth transistor T8. Therefore, when the tenth transistor T10 is turned on, the gate electrode of the eighth transistor T8 may stably receive the initialization voltage regardless of the threshold voltage of the tenth transistor T10.

[0147] The tenth transistor T10 may include a plurality of transistors connected in series. For example, the tenth transistor T10 may include a fifth sub-transistor T101 and a sixth sub-transistor T102. The fifth and sixth sub-transistors T101 and T102 may prevent the voltage of the gate electrode of the eighth transistor T8 from leaking through the tenth transistor T10. The gate electrode of the fifth sub-transistor T101 may be connected to a scan initialization line GIL, a first electrode may be connected to a gate electrode of the eighth transistor T8, and a second electrode may be connected to a first electrode of the sixth sub-transistor T102. The gate electrode of the sixth sub-transistor T102 may be connected to the scan initialization line GIL, a first electrode may be connected to a second electrode of the fifth sub-transistor T101, and a second electrode may be connected to an initialization voltage line VIL.

[0148] The eleventh transistor T11 may be turned on by a scan write signal on the scan write line GWL to electrically connect the gate electrode of the eighth transistor T8 to the second electrode of the eighth transistor T8, so that the eighth transistor T8 may operate as a diode (e.g., the eighth transistor T8 may be diode-connected) during a period in which the eleventh transistor T11 is turned on.

[0149] The eleventh transistor T11 may include a plurality of transistors connected in series. For example, the eleventh transistor T11 may include a seventh sub-transistor T111 and an eighth sub-transistor T112. The seventh and eighth sub-transistors T111 and T112 may prevent the voltage of the gate electrode of the eighth transistor T8 from leaking through the eleventh transistor T11. The gate electrode of the seventh sub-transistor T111 may be connected to a scan write line GWL, a first electrode may be connected to a second electrode of the eighth transistor T8, and a second electrode may be connected to a first electrode of the eighth sub-transistor T112. The gate electrode of the eighth sub-transistor T112 may be connected to a scan write line GWL, a first electrode may be connected to a second electrode of the seventh sub-transistor T111, and a second electrode may be connected to a gate electrode of the eighth transistor T8.

[0150] The twelfth transistor T12 may be turned on by a PWM light emitting signal of the PWM light emitting line PWEL to electrically connect a first electrode of the eighth transistor T8 to the second power supply line VDL2. A gate electrode of the twelfth transistor T12 may be connected to the PWM light emitting line PWEL, a first electrode of the twelfth transistor T12 may be connected to the first power supply line VDL1, and a second electrode of the twelfth transistor T12 may be connected to the first electrode of the eighth transistor T8.

[0151] The thirteenth transistor T13 may be turned on by a scan control signal of the scan control line GCL to electrically connect the first power line VDL1 to the second node N2. The thirteenth transistor T13 may have a gate electrode connected to the scan control line GCL, a first electrode connected to the first power line VDL1, and a second electrode connected to the second node N2.

[0152] The fourteenth transistor T14 may be turned on by a PWM light emitting signal of the PWM light emitting line PWEL to electrically couple a first electrode of the twelfth transistor T12 to the second node N2. The fourteenth transistor T14 may have a gate electrode connected to the PWM light emitting line PWEL, a first electrode connected to the second power supply line VDL2, and a second electrode connected to the second node N2.

[0153] The second capacitor C2 may be disposed between the gate electrode of the eighth transistor T8 and the second node N2. One electrode of the second capacitor C2 may be coupled to the gate electrode of the eighth transistor T8, and the other electrode may be coupled to the second node N2.

[0154] The third pixel driving unit PDU3 can control a period during which a driving current is supplied to the light emitting element ED based on the voltage of the third node N3.

[0155] The third pixel driving unit PDU3 may include fifteenth to nineteenth transistors T15 to T19 and a third capacitor C3.

[0156] The fifteenth transistor T15 may be turned on based on the voltage of the third node N3. When the fifteenth transistor T15 is turned on, the driving current of the eighth transistor T8 may be supplied to the light emitting element ED. When the fifteenth transistor T15 is turned off, the driving current of the eighth transistor T8 may not be supplied to the light emitting element ED. Therefore, the turn-on period of the fifteenth transistor T15 may be substantially the same as the light emitting period of the light emitting element ED. The gate electrode of the fifteenth transistor T15 may be connected to the third node N3, the first electrode may be connected to the second electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the seventeenth transistor T17.

[0157] The sixteenth transistor T16 may be turned on by a scan control signal on the scan control line GCL to electrically connect the initialization voltage line VIL to the third node N3, so that the third node N3 may be discharged to the initialization voltage of the initialization voltage line VIL during the period in which the sixteenth transistor T16 is turned on.

[0158] The sixteenth transistor T16 may include a plurality of transistors connected in series. For example, the sixteenth transistor T16 may include a ninth sub-transistor T161 and a tenth sub-transistor T162. The ninth and tenth sub-transistors T161 and T162 may prevent the voltage of the third node N3 from leaking through the sixteenth transistor T16. The gate electrode of the ninth sub-transistor T161 may be connected to the scan control line GCL, the first electrode may be connected to the third node N3, and the second electrode may be connected to the first electrode of the tenth sub-transistor T162. The gate electrode of the tenth sub-transistor T162 may be connected to the scan control line GCL, the first electrode may be connected to the second electrode of the ninth sub-transistor T161, and the second electrode may be connected to the initialization voltage line VIL.

[0159] The seventeenth transistor T17 may be turned on by a PAM light emitting signal of the PAM light emitting line PAEL to electrically connect the second electrode of the fifteenth transistor T15 to the first electrode of the light emitting element ED. The seventeenth transistor T17 may have a gate electrode connected to the PAM light emitting line PAEL, a first electrode connected to the second electrode of the fifteenth transistor T15, and a second electrode connected to the first electrode of the light emitting element ED.

[0160] The 18th transistor T18 may be turned on by a scan control signal of the scan control line GCL to electrically connect the initialization voltage line VIL to a first electrode of the light emitting element ED. Therefore, during a period in which the 18th transistor T18 is turned on, the first electrode of the light emitting element ED may be discharged to the initialization voltage of the initialization voltage line VIL. The gate electrode of the 18th transistor T18 may be connected to the scan control line GCL, a first electrode may be connected to the first electrode of the light emitting element ED, and a second electrode may be connected to the initialization voltage line VIL.

[0161] The 19th transistor T19 may be turned on by a test signal of the test signal line TSTL to electrically connect a first electrode of the light emitting element ED to the third power line VSL. A gate electrode of the 19th transistor T19 may be connected to the test signal line TSTL, a first electrode of the 19th transistor T19 may be connected to the first electrode of the light emitting element ED, and a second electrode of the 19th transistor T19 may be connected to the third power line VSL.

[0162] The third capacitor C3 may be disposed between the third node N3 and the initialization voltage line VIL, with one electrode of the third capacitor C3 being coupled to the third node N3 and the other electrode being coupled to the initialization voltage line VIL.

[0163] One of the first electrode and the second electrode of each of the first to nineteenth transistors T1 to T19 may be a source electrode, and the other may be a drain electrode. The semiconductor layer of each of the first to nineteenth transistors T1 to T19 may be made of any one of polysilicon, amorphous silicon, and an oxide semiconductor. When the semiconductor layer of each of the first to nineteenth transistors T1 to T19 is made of polysilicon, it may be formed by a low temperature polysilicon (LTPS) process.

[0164] 11 has been described with a focus on the first through nineteenth transistors T1-T19 being formed as P-type MOSFETs, but the present specification is not so limited. In one or more embodiments, the first through nineteenth transistors T1-T19 may be formed as N-type MOSFETs.

[0165] Fig. 12 is a layout diagram showing an example of the sub-pixel of Fig. 4. Fig. 13 is an enlarged view of an A1 region of Fig. 12. Fig. 14 is an enlarged view of an A2 region of Fig. 12. Fig. 15 is an enlarged view of an A3 region of Fig. 12.

[0166] 4 and 11 to 15, the subpixel SPX in Fig. 12 may correspond to at least one of the subpixels SPX1, SPX2, and SPX3 in Fig. 4. For example, the subpixel SPX in Fig. 12 may correspond to the second and third subpixels SPX2 and SPX3 described with reference to Figs. 4, 6, and 7, respectively, but is not limited thereto.

[0167] The initialization voltage line VIL, the scan initialization line GIL, the scan write line GWL, the PWM emission line PWEL, the first horizontal power line HVDL, the gate-off voltage line VGHL, the sweep line SWPL, the scan control line GCL, the PAM emission line PAEL, the test signal line TSTL, and the third power line VSL can extend in a first direction DR1 and be spaced apart in a second direction DR2.

[0168] The data line DL, the first vertical power line VVDL, and the PAM data line RDL may extend in a second direction DR2 and be spaced apart in a first direction DR1.

[0169] The pixel SPX may include a pixel circuit PC and a light emitting element ED. The pixel circuit PC may include first to nineteenth transistors T1 to T19, first to sixth capacitor electrodes CE1 to CE6, first to sixth gate connecting electrodes GCE1 to GCE6, first and second data connecting electrodes DCE1, DCE2, first to seventh connecting electrodes CCE1 to CCE7, and an anode connecting line ACL.

[0170] The first transistor T1 may include a first channel CH1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first channel CH1 may extend in a first direction DR1. The first channel CH1 may overlap with the first gate electrode G1 in a third direction DR3. The first gate electrode G1 may be connected to the first connecting electrode CCE1 through a first contact hole CT1. The first gate electrode G1 may be integrally formed with the first capacitor electrode CE1. The first gate electrode G1 may overlap with the second capacitor electrode CE2 in the third direction DR3. The first source electrode S1 may be disposed on one side of the first channel CH1, and the first drain electrode D1 may be disposed on the other side of the first channel CH1. The first source electrode S1 may be connected to the second drain electrode D2 and the fifth drain electrode D5. The first drain electrode D1 may be connected to the third sub-source electrode S41 and the sixth source electrode S6. The first source electrode S1 and the first drain electrode D1 do not have to overlap with the first gate electrode G1 in the third direction DR3. The first source electrode S1 and the first drain electrode D1 can overlap with the second capacitor electrode CE2 in the third direction DR3.

[0171] The second transistor T2 may include a second channel CH2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second channel CH2 may overlap with the second gate electrode G2 in the third direction DR3. The second gate electrode G2 may be formed integrally with the first gate connection electrode GCE1. The second source electrode S2 may be disposed on one side of the second channel CH2, and the second drain electrode D2 may be disposed on the other side of the second channel CH2. The second source electrode S2 may be connected to the first data connection electrode DCE1 through the first data contact hole DCT1. The second drain electrode D2 may be connected to the first source electrode S1. The second source electrode S2 and the second drain electrode D2 may not overlap with the second gate electrode G2 in the third direction DR3. The second drain electrode D2 may extend in the second direction DR2. The second drain electrode D2 may be connected to the first source electrode S1.

[0172] The first sub-transistor T31 of the third transistor T3 may include a first sub-channel CH31, a first sub-gate electrode G31, a first sub-source electrode S31, and a first sub-drain electrode D31. The first sub-channel CH31 may overlap the first sub-gate electrode G31 in the third direction DR3. The first sub-gate electrode G31 may be formed integrally with the second gate connecting electrode GCE2. The first sub-source electrode S31 may be disposed on one side of the first sub-channel CH31, and the first sub-drain electrode D31 may be disposed on the other side of the first sub-channel CH31. The first sub-source electrode S31 may be connected to the fourth sub-drain electrode D42, and the first sub-drain electrode D31 may be connected to the second sub-source electrode S32. The first sub-source electrode S31 and the first sub-drain electrode D31 may not overlap the first sub-gate electrode G31. The first sub-source electrode S31 may partially overlap the scan write line GWL in the third direction DR3, and the first sub-drain electrode D31 may partially overlap the initialization voltage line VIL in the third direction DR3.

[0173] The second sub-transistor T32 of the third transistor T3 may include a second sub-channel CH32, a second sub-gate electrode G32, a second sub-source electrode S32, and a second sub-drain electrode D32. The second sub-channel CH32 may overlap the second sub-gate electrode G32 in the third direction DR3. The second sub-gate electrode G32 may be formed integrally with the second gate connection electrode GCE2. The second sub-source electrode S32 may be disposed on one side of the second sub-channel CH32, and the second sub-drain electrode D32 may be disposed on the other side of the second sub-channel CH32. The second sub-source electrode S32 may be connected to the first sub-drain electrode D31, and the second sub-drain electrode D32 may be connected to the initialization voltage line VIL through the first power contact hole VCT1. The second sub-source electrode S32 and the second sub-drain electrode D32 may not overlap the second sub-gate electrode G32. The second sub-source electrode S32 and the second sub-drain electrode D32 may partially overlap the initialization voltage line VIL in the third direction DR3.

[0174] The third sub-transistor T41 of the fourth transistor T4 may include a third sub-channel CH41, a third sub-gate electrode G41, a third sub-source electrode S41, and a third sub-drain electrode D41. The third sub-channel CH41 may overlap the third sub-gate electrode G41 in the third direction DR3. The third sub-gate electrode G41 may be formed integrally with the first gate connecting electrode GCE1. The third sub-source electrode S41 may be disposed on one side of the third sub-channel CH41, and the third sub-drain electrode D41 may be disposed on the other side of the third sub-channel CH41. The third sub-source electrode S41 may be connected to the first drain electrode D1, and the third sub-drain electrode D41 may be connected to the fourth sub-source electrode S42. The third sub-source electrode S41 and the third sub-drain electrode D41 may not overlap the third sub-gate electrode G41.

[0175] The fourth sub-transistor T42 of the fourth transistor T4 may include a fourth sub-channel CH42, a fourth sub-gate electrode G42, a fourth sub-source electrode S42, and a fourth sub-drain electrode D42. The fourth sub-channel CH42 may overlap with the fourth sub-gate electrode G42 in the third direction DR3. The fourth sub-gate electrode G42 may be integrally formed with the first gate connecting electrode GCE1. The fourth sub-source electrode S42 may be disposed on one side of the fourth sub-channel CH42, and the fourth sub-drain electrode D42 may be disposed on the other side of the fourth sub-channel CH42. The fourth sub-source electrode S42 may be connected to the third sub-drain electrode D41, and the fourth sub-drain electrode D42 may be connected to the first sub-source electrode S31. The fourth sub-source electrode S42 and the fourth sub-drain electrode D42 may not overlap with the fourth sub-gate electrode G42.

[0176] The fifth transistor T5 may include a fifth channel CH5, a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5. The fifth channel CH5 may overlap the fifth gate electrode G5 in the third direction DR3. The fifth gate electrode G5 may be formed integrally with the sixth gate connection electrode GCE6. The fifth source electrode S5 may be disposed on one side of the fifth channel CH5, and the fifth drain electrode D5 may be disposed on the other side of the fifth channel CH5. The fifth source electrode S5 may be connected to the first horizontal power line HVDL through the second power contact hole VCT2. The fifth drain electrode D5 may be connected to the first source electrode S1. The fifth source electrode S5 and the fifth drain electrode D5 may not overlap the fifth gate electrode G5 in the third direction DR3. The fifth drain electrode D5 may overlap the extension portion EX of the second capacitor electrode CE2 in the third direction DR3.

[0177] The sixth transistor T6 may include a sixth channel CH6, a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6. The sixth channel CH6 may overlap with the sixth gate electrode G6 in the third direction DR3. The sixth gate electrode G6 may be formed integrally with the sixth gate connecting electrode GCE6. The sixth source electrode S6 may be disposed on one side of the sixth channel CH6, and the sixth drain electrode D6 may be disposed on the other side of the sixth channel CH6. The sixth source electrode S6 may be connected to the first drain electrode D1. The sixth drain electrode D6 may be connected to the fourth connecting electrode CCE4 through a tenth contact hole CT10. The sixth source electrode S6 and the sixth drain electrode D6 may not overlap with the sixth gate electrode G6 in the third direction DR3. The sixth drain electrode D6 may overlap with the second connecting electrode CCE2 and the first horizontal power line HVDL in the third direction DR3.

[0178] The seventh transistor T7 may include a seventh channel CH7, a seventh gate electrode G7, a seventh source electrode S7, and a seventh drain electrode D7. The seventh channel CH7 may overlap with the seventh gate electrode G7 in the third direction DR3. The seventh gate electrode G7 may be integrally formed with the third gate connection electrode GCE3. The seventh gate electrode G7 may overlap with the initialization voltage line VIL in the third direction DR3. The seventh source electrode S7 may be disposed on one side of the seventh channel CH7, and the seventh drain electrode D7 may be disposed on the other side of the seventh channel CH7. The seventh source electrode S7 may be connected to the gate-off voltage line VGHL via a seventh contact hole CT7. The seventh drain electrode D7 may be connected to the sweep line SWPL via a sixth contact hole CT6. The seventh source electrode S7 and the seventh drain electrode D7 may not overlap with the seventh gate electrode G7 in the third direction DR3.

[0179] The eighth transistor T8 may include an eighth channel CH8, an eighth gate electrode G8, an eighth source electrode S8, and an eighth drain electrode D8. The eighth channel CH8 may overlap with the eighth gate electrode G8 in the third direction DR3. The eighth gate electrode G8 may extend in the second direction DR2. The eighth gate electrode G8 may be formed integrally with the third capacitor electrode CE3. The eighth source electrode S8 may be disposed on one side of the eighth channel CH8, and the eighth drain electrode D8 may be disposed on the other side of the eighth channel CH8. The eighth source electrode S8 may be connected to the ninth drain electrode D9 and the twelfth drain electrode D12. The eighth drain electrode D8 may be connected to the seventh sub-source electrode S111. The eighth source electrode S8 and the eighth drain electrode D8 may not overlap with the eighth gate electrode G8 in the third direction DR3.

[0180] The ninth transistor T9 may include a ninth channel CH9, a ninth gate electrode G9, a ninth source electrode S9, and a ninth drain electrode D9. The ninth channel CH9 may overlap with the ninth gate electrode G9 in the third direction DR3. The ninth gate electrode G9 may extend in the second direction DR2. The ninth gate electrode G9 may be integrally formed with the first gate connecting electrode GCE1. The ninth source electrode S9 may be disposed on one side of the ninth channel CH9, and the ninth drain electrode D9 may be disposed on the other side of the ninth channel CH9. The ninth source electrode S9 may be connected to the eighth source electrode S8. The ninth drain electrode D9 may be connected to the second data connecting electrode DCE2 via the third data contact hole DCT3. The ninth source electrode S9 and the ninth drain electrode D9 may not overlap with the ninth gate electrode G9 in the third direction DR3.

[0181] The fifth sub-transistor T101 of the tenth transistor T10 may include a fifth sub-channel CH101, a fifth sub-gate electrode G101, a fifth sub-source electrode S101, and a fifth sub-drain electrode D101. The fifth sub-channel CH101 may overlap the fifth sub-gate electrode G101 in the third direction DR3. The fifth sub-gate electrode G101 may be formed integrally with the second gate connecting electrode GCE2. The fifth sub-source electrode S101 may be disposed on one side of the fifth sub-channel CH101, and the fifth sub-drain electrode D101 may be disposed on the other side of the fifth sub-channel CH101. The fifth sub-source electrode S101 may be connected to the eighth sub-drain electrode D112, and the fifth sub-drain electrode D101 may be connected to the sixth sub-source electrode S102. The fifth sub-source electrode S101 and the fifth sub-drain electrode D101 may not overlap the fifth sub-gate electrode G101. The fifth sub-source electrode S101 may partially overlap the scan write line GWL in the third direction DR3, and the fifth sub-drain electrode D101 may partially overlap the initialization voltage line VIL in the third direction DR3.

[0182] The sixth sub-transistor T102 of the tenth transistor T10 may include a sixth sub-channel CH102, a sixth sub-gate electrode G102, a sixth sub-source electrode S102, and a sixth sub-drain electrode D102. The sixth sub-channel CH102 may overlap with the sixth sub-gate electrode G102 in the third direction DR3. The sixth sub-gate electrode G102 may be formed integrally with the second gate connection electrode GCE2. The sixth sub-source electrode S102 may be disposed on one side of the sixth sub-channel CH102, and the sixth sub-drain electrode D102 may be disposed on the other side of the sixth sub-channel CH102. The sixth sub-source electrode S102 may be connected to the fifth sub-drain electrode D101, and the sixth sub-drain electrode D102 may be connected to the initialization voltage line VIL through the first power contact hole VCT1. The sixth sub-source electrode S102 and the sixth sub-drain electrode D102 may not overlap with the sixth sub-gate electrode G102. The sixth sub-source electrode S102 and the sixth sub-drain electrode D102 may partially overlap with the initialization voltage line VIL in the third direction DR3.

[0183] The seventh sub-transistor T111 of the eleventh transistor T11 may include a seventh sub-channel CH111, a seventh sub-gate electrode G111, a seventh sub-source electrode S111, and a seventh sub-drain electrode D111. The seventh sub-channel CH111 may overlap with the seventh sub-gate electrode G111 in the third direction DR3. The seventh sub-gate electrode G111 may be formed integrally with the first gate connecting electrode GCE1. The seventh sub-source electrode S111 may be disposed on one side of the seventh sub-channel CH111, and the seventh sub-drain electrode D111 may be disposed on the other side of the seventh sub-channel CH111. The seventh sub-source electrode S111 may be connected to the eighth drain electrode D8, and the seventh sub-drain electrode D111 may be connected to the eighth sub-source electrode S112. The seventh sub-source electrode S111 and the seventh sub-drain electrode D111 may not overlap with the seventh sub-gate electrode G111.

[0184] The eighth sub-transistor T112 of the eleventh transistor T11 may include an eighth sub-channel CH112, an eighth sub-gate electrode G112, an eighth sub-source electrode S112, and an eighth sub-drain electrode D112. The eighth sub-channel CH112 may overlap with the eighth sub-gate electrode G112 in the third direction DR3. The eighth sub-gate electrode G112 may be formed integrally with the first gate connecting electrode GCE1. The eighth sub-source electrode S112 may be disposed on one side of the eighth sub-channel CH112, and the eighth sub-drain electrode D112 may be disposed on the other side of the eighth sub-channel CH112. The eighth sub-source electrode S112 may be connected to the seventh sub-drain electrode D111, and the eighth sub-drain electrode D112 may be connected to the fifth sub-source electrode S101. The eighth sub-source electrode S112 and the eighth sub-drain electrode D112 may not overlap with the eighth sub-gate electrode G112.

[0185] The twelfth transistor T12 may include a twelfth channel CH12, a twelfth gate electrode G12, a twelfth source electrode S12, and a twelfth drain electrode D12. The twelfth channel CH12 may overlap with the twelfth gate electrode G12 in the third direction DR3. The twelfth gate electrode G12 may be integrally formed with the sixth gate connecting electrode GCE6. The twelfth source electrode S12 may be disposed on one side of the twelfth channel CH12, and the twelfth drain electrode D12 may be disposed on the other side of the twelfth channel CH12. The twelfth source electrode S12 may be connected to the fifth connecting electrode CCE5 via the eleventh contact hole CT11. The twelfth drain electrode D12 may be connected to the eighth source electrode S8. The twelfth source electrode S12 and the twelfth drain electrode D12 may not overlap with the twelfth gate electrode G12 in the third direction DR3.

[0186] The thirteenth transistor T13 may include a thirteenth channel CH13, a thirteenth gate electrode G13, a thirteenth source electrode S13, and a thirteenth drain electrode D13. The thirteenth channel CH13 may overlap with the thirteenth gate electrode G13 in the third direction DR3. The thirteenth gate electrode G13 may be integrally formed with the third gate connecting electrode GCE3. The thirteenth source electrode S13 may be disposed on one side of the thirteenth channel CH13, and the thirteenth drain electrode D13 may be disposed on the other side of the thirteenth channel CH13. The thirteenth source electrode S13 may be connected to the first horizontal power line HVDL via the second power contact hole VCT2. The thirteenth drain electrode D13 may be connected to the second connecting electrode CCE2 via the third contact hole CT3. The thirteenth source electrode S13 and the thirteenth drain electrode D13 may not overlap with the thirteenth gate electrode G13 in the third direction DR3.

[0187] The fourteenth transistor T14 may include a fourteenth channel CH14, a fourteenth gate electrode G14, a fourteenth source electrode S14, and a fourteenth drain electrode D14. The fourteenth channel CH14 may overlap with the fourteenth gate electrode G14 in the third direction DR3. The fourteenth gate electrode G14 may be integrally formed with the sixth gate connecting electrode GCE6. The fourteenth source electrode S14 may be disposed on one side of the fourteenth channel CH14, and the fourteenth drain electrode D14 may be disposed on the other side of the fourteenth channel CH14. The fourteenth source electrode S14 may be connected to the fifth connecting electrode CCE5 via an eleventh contact hole CT11. The fourteenth drain electrode D14 may be connected to the second connecting electrode CCE2 via a fourth contact hole CT4. The fourteenth source electrode S14 and the fourteenth drain electrode D14 may not overlap with the fourteenth gate electrode G14 in the third direction DR3.

[0188] The fifteenth transistor T15 may include a fifteenth channel CH15, a fifteenth gate electrode G15, a fifteenth source electrode S15, and a fifteenth drain electrode D15. The fifteenth channel CH15 may overlap with the fifteenth gate electrode G15 in the third direction DR3. The fifteenth gate electrode G15 may be formed integrally with the fifth capacitor electrode CE5. The fifteenth source electrode S15 may be disposed on one side of the fifteenth channel CH15, and the fifteenth drain electrode D15 may be disposed on the other side of the fifteenth channel CH15. The fifteenth source electrode S15 may be connected to the eighth drain electrode D8. The fifteenth drain electrode D15 may be connected to the seventeenth source electrode S17. The fifteenth source electrode S15 and the fifteenth drain electrode D15 may not overlap with the fifteenth gate electrode G15 in the third direction DR3.

[0189] The ninth sub-transistor T161 of the sixteenth transistor T16 may include a ninth sub-channel CH161, a ninth sub-gate electrode G161, a ninth sub-source electrode S161, and a ninth sub-drain electrode D161. The ninth sub-channel CH161 may overlap with the ninth sub-gate electrode G161 in the third direction DR3. The ninth sub-gate electrode G161 may be integrally formed with the third gate connecting electrode GCE3. The ninth sub-source electrode S161 may be disposed on one side of the ninth sub-channel CH161, and the ninth sub-drain electrode D161 may be disposed on the other side of the ninth sub-channel CH161. The ninth sub-source electrode S161 may be connected to the fourth connecting electrode CCE4 through a tenth contact hole CT10, and the ninth sub-drain electrode D161 may be connected to the tenth sub-source electrode S162. The ninth sub-source electrode S161 and the ninth sub-drain electrode D161 do not have to overlap with the ninth sub-gate electrode G161.

[0190] The tenth sub-transistor T162 of the sixteenth transistor T16 may include a tenth sub-channel CH162, a tenth sub-gate electrode G162, a tenth sub-source electrode S162, and a tenth sub-drain electrode D162. The tenth sub-channel CH162 may overlap with the tenth sub-gate electrode G162 in the third direction DR3. The tenth sub-gate electrode G162 may be integrally formed with the third gate connection electrode GCE3. The tenth sub-source electrode S162 may be disposed on one side of the tenth sub-channel CH162, and the tenth sub-drain electrode D162 may be disposed on the other side of the tenth sub-channel CH162. The tenth sub-source electrode S162 may be connected to the ninth sub-drain electrode D161, and the tenth sub-drain electrode D162 may be connected to the initialization voltage line VIL via a ninth contact hole CT9. The tenth sub-source electrode S162 and the tenth sub-drain electrode D162 may not overlap the tenth sub-gate electrode G162.

[0191] The 17th transistor T17 may include a 17th channel CH17, a 17th gate electrode G17, a 17th source electrode S17, and a 17th drain electrode D17. The 17th channel CH17 may overlap with the 17th gate electrode G17 in the third direction DR3. The 17th gate electrode G17 may be formed integrally with the fifth gate connecting electrode GCE5. The 17th source electrode S17 may be disposed on one side of the 17th channel CH17, and the 17th drain electrode D17 may be disposed on the other side of the 17th channel CH17. The 17th source electrode S17 may be connected to the 15th drain electrode D15. The 17th drain electrode D17 may be connected to the seventh connecting electrode CCE7 via a 16th contact hole CT16. The 17th source electrode S17 and the 17th drain electrode D17 may not overlap with the 17th gate electrode G17 in the third direction DR3.

[0192] The 18th transistor T18 may include an 18th channel CH18, an 18th gate electrode G18, an 18th source electrode S18, and an 18th drain electrode D18. The 18th channel CH18 may overlap with the 18th gate electrode G18 in the third direction DR3. The 18th gate electrode G18 may be integrally formed with the third gate connecting electrode GCE3. The 18th source electrode S18 may be disposed on one side of the 18th channel CH18, and the 18th drain electrode D18 may be disposed on the other side of the 18th channel CH18. The 18th source electrode S18 may be connected to the initialization voltage line VIL via a ninth contact hole CT9. The 18th drain electrode D18 may be connected to the seventh connecting electrode CCE7 via a sixteenth contact hole CT16. The 18th source electrode S18 and the 18th drain electrode D18 may not overlap with the 18th gate electrode G18 in the third direction DR3.

[0193] The 19th transistor T19 may include a 19th channel CH19, a 19th gate electrode G19, a 19th source electrode S19, and a 19th drain electrode D19. The 19th channel CH19 may overlap with the 19th gate electrode G19 in the third direction DR3. The 19th gate electrode G19 may be connected to the test signal line TSTL via a 23rd contact hole CT23. The 19th source electrode S19 may be disposed on one side of the 19th channel CH19, and the 19th drain electrode D19 may be disposed on the other side of the 19th channel CH19. The 19th source electrode S19 may be connected to the third connecting electrode CCE3 via a 21st contact hole CT21. The 19th drain electrode D19 may be connected to the third power line VSL via a 24th contact hole CT24. The 19th source electrode S19 and the 19th drain electrode D19 may not overlap with the 19th gate electrode G19 in the third direction DR3.

[0194] The first capacitor electrode CE1 may be integrally formed with the first gate electrode G1. The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 in the third direction DR3. The first capacitor electrode CE1 may be one electrode of the first capacitor C1, and the second capacitor electrode CE2 may be the other electrode of the first capacitor C1.

[0195] The second capacitor electrode CE2 includes a hole exposing the first gate electrode G1, and the first connecting electrode CCE1 may be connected to the first gate electrode G1 through a first contact hole CT1.

[0196] The second capacitor electrode CE2 may include an extension EX extending in the second direction DR2. The extension EX of the second capacitor electrode CE2 may cross the PWM emission line PWEL and the first horizontal voltage line HVDL. The extension EX of the second capacitor electrode CE2 may be connected to the sweep line SWPL through a fifth contact hole CT5.

[0197] The third capacitor electrode CE3 may be formed integrally with the eighth gate electrode G8. The fourth capacitor electrode CE4 may overlap the third capacitor electrode CE3 in the third direction DR3. The third capacitor electrode CE3 may be one electrode of the second capacitor C2, and the fourth capacitor electrode CE4 may be the other electrode of the second capacitor C2.

[0198] The fourth capacitor electrode CE4 includes a hole exposing the eighth gate electrode G8, and the sixth connecting electrode CCE6 may be connected to the eighth gate electrode G8 through a twelfth contact hole CT12 in the hole.

[0199] The fifth capacitor electrode CE5 may be integrally formed with the fourth gate connecting electrode GCE4 and the fifteenth gate electrode G15. The sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR3. The fifth capacitor electrode CE5 may be one electrode of the third capacitor C3, and the sixth capacitor electrode CE6 may be the other electrode of the third capacitor C3. The sixth capacitor electrode CE6 may be connected to the initialization voltage line VIL via an eighteenth contact hole CT18.

[0200] The first gate connection electrode GCE1 may be connected to the scan write line GWL through the first gate contact hole GCT1 and the third gate contact hole GCT3. The second gate connection electrode GCE2 may be connected to the scan initialization line GIL through the second gate contact hole GCT2. The third gate connection electrode GCE3 may be connected to the scan control line GCL through the eighth contact hole CT8. The fourth gate connection electrode GCE4 may be connected to the fourth connection electrode CCE4 through the seventeenth contact hole CT17. The fifth gate connection electrode GCE5 may be connected to the PAM emission line PAEL through the nineteenth contact hole CT19. The sixth gate connection electrode GCE6 may be connected to the PWM emission line PWEL through the fourteenth contact hole CT14.

[0201] The first data connecting electrode DCE1 may be connected to the second source electrode S2 through the first data contact hole DCT1 and to the data line DL through the second data contact hole DCT2. The second data connecting electrode DCE2 may be connected to the ninth source electrode S9 through the third data contact hole DCT3 and to the PAM data line RDL through the fourth data contact hole DCT4.

[0202] The first connecting electrode CCE1 may extend in a second direction DR2, may be connected to the first gate electrode G1 through a first contact hole CT1, and may be connected to the first sub-source electrode S31 and the fourth sub-drain electrode D42 through a second contact hole CT2.

[0203] The second connecting electrode CCE2 may extend in the first direction DR1 and may be connected to the thirteenth drain electrode D13 through the third contact hole CT3, to the fourteenth drain electrode D14 through the fourth contact hole CT4, and to the fourth capacitor electrode CE4 through the fifteenth contact hole CT15.

[0204] The third connecting electrode CCE3 may be connected to the nineteenth source electrode S19 through a twenty-first contact hole CT21 and may be connected to the anode connecting line ACL through a twenty-second contact hole CT22.

[0205] The fourth connecting electrode CCE4 may extend in the first direction DR1, may be connected to the sixth drain electrode D6 and the ninth sub-source electrode S161 through a tenth contact hole CT10, and may be connected to the fourth gate connecting electrode GCE4 through a seventeenth contact hole CT17.

[0206] The fifth connecting electrode CCE5 may extend in the first direction DR1. The fifth connecting electrode CCE5 may be connected to the twelfth source electrode S12 and the fourteenth source electrode S14 through an eleventh contact hole CT11, and may be connected to the fourth capacitor electrode CE4 through a fourth power contact hole VDCT4.

[0207] The sixth connecting electrode CCE6 may extend in the second direction DR2. The sixth connecting electrode CCE6 may be connected to the third capacitor electrode CE3 through a twelfth contact hole CT12, and may be connected to the fifth sub-source electrode S101 and the eighth sub-drain electrode D112 through a thirteenth contact hole CT13.

[0208] The seventh connecting electrode CCE7 may be connected to the seventeenth drain electrode D17 and the eighteenth drain electrode D18 through a sixteenth contact hole CT16. The seventh connecting electrode CCE7 may be connected to the anode connecting line ACL through a twentieth contact hole CT20.

[0209] The second power connecting electrode VDCE may extend in a second direction DR2 and may be connected to the fifth connecting electrode CCE5 through a fourth power contact hole VCT4.

[0210] The anode connecting line ACL may extend in the second direction DR2 and may be connected to the seventh connecting electrode CCE7 through a twentieth contact hole CT20 and to the third connecting electrode CCE3 through a twenty-second contact hole CT22.

[0211] 6, the anode connecting electrode ACE may overlap the anode connecting line ACL in the third direction DR3 and may be connected to the anode connecting line ACL through a first electrode contact hole ECT1. The anode connecting electrode ACE may be connected to the pixel electrode AND through a second electrode contact hole ECT2. The pixel electrode AND may be connected to the first contact electrode ELT1 of the light emitting element ED.

[0212] 6 to 10, the anode connecting electrodes ACE may have different shapes for each of the sub-pixels SPX1, SPX2, and SPX3. Corresponding to the anode connecting electrodes ACE, the arrangement order of the pixel electrodes AND and the common electrodes COM may also be changed for each of the sub-pixels SPX1, SPX2, and SPX3.

[0213] FIG. 16 is a cross-sectional view taken along line A-A' in FIG. 12. FIG. 17 is a cross-sectional view taken along line B-B' in FIG. 12. FIG. 18 is a cross-sectional view taken along line C-C' in FIG. 12. FIG. 19 is a cross-sectional view taken along line D-D' in FIG. 12. FIG. 20 is a cross-sectional view taken along line E-E' in FIG. 12. FIG. 21 is a cross-sectional view taken along line F-F' in FIG. 12. FIG. 22 is a cross-sectional view taken along line G-G' in FIG. 12. FIG. 23 is a cross-sectional view taken along line H-H' in FIG. 12. FIG. 24 is a cross-sectional view taken along line I-I' in FIG. 12.

[0214] With reference to Figures 7 and 12 to 24, the cross-sectional structure of the display device 10 has been described with reference to Figure 7, and the arrangement of the semiconductor pattern and conductive pattern in the subpixel SPX has been described with reference to Figures 12 to 15, so duplicate explanations will not be repeated.

[0215] The substrate SUB can support the display device 10. A buffer film BF can be disposed on the substrate SUB.

[0216] The active layer ACTL (see FIG. 7) may be disposed on the buffer film BF. The active layer ACTL may include first to nineteenth channels CH1 to CH19, first to nineteenth source electrodes S1 to S19, and first to nineteenth drain electrodes D1 to D19 of the first to nineteenth transistors T1 to T19.

[0217] The first to nineteenth channels CH1 to CH19 may overlap with the first to nineteenth gate electrodes G1 to G19, respectively, in the third direction DR3. The first to nineteenth source electrodes S1 to S19 and the first to nineteenth drain electrodes D1 to D19 may be regions of a silicon semiconductor or an oxide semiconductor doped with ions or impurities to have conductivity.

[0218] The first gate insulating film GI1 can be disposed on the active layer ACTL. The first gate insulating film GI1 can insulate the first to nineteenth channels CH1 to CH19 from the first to nineteenth gate electrodes G1 to G19, respectively.

[0219] The first gate layer GTL1 (see FIG. 7) may be disposed on the first gate insulating film GI1. The first gate layer GTL1 may include first to nineteenth gate electrodes G1 to G19, a first capacitor electrode CE1, a third capacitor electrode CE3, a fifth capacitor electrode CE5, and first to fifth gate connecting electrodes GCE1 to GCE5.

[0220] The second gate insulating film GI2 can be disposed on the first gate layer GTL1. The second gate insulating film GI2 can insulate the first gate layer GTL1 and the second gate layer GTL2 (see FIG. 7).

[0221] The second gate layer GTL2 may be disposed on the second gate insulating film GI2. The second gate layer GTL2 may include a second capacitor electrode CE2, a fourth capacitor electrode CE4, and a sixth capacitor electrode CE6.

[0222] An interlayer dielectric film ILD may be disposed on the second gate layer GTL2. The interlayer dielectric film ILD may insulate the first source metal layer SDL1 (see FIG. 7) and the second gate layer GTL2.

[0223] The first source metal layer SDL1 may be disposed on the interlayer insulating film ILD. The first source metal layer SDL1 may include an initialization voltage line VIL, a scan initialization line GIL, a scan write line GWL, a PWM light emitting line PWEL, a first horizontal power supply line HVDL, a gate-off voltage line VGHL, a sweep line SWPL, a scan control line GCL, a PAM light emitting line PAEL, a test signal line TSTL, and a third power supply line VSL. The first source metal layer SDL1 may include first and second data connecting electrodes DCE1 and DCE2 and first to seventh connecting electrodes CCE1 to CCE7.

[0224] The scan write line GWL may be connected to the first gate connecting electrode GCE1 through a first gate contact hole GCT1 and a third gate contact hole GCT3 penetrating the second gate insulating film GI2 and the interlayer insulating film ILD (see FIG. 16 and FIG. 20). The scan initialization line GIL may be connected to the second gate connecting electrode GCE2 through a second gate contact hole GCT2 penetrating the second gate insulating film GI2 and the interlayer insulating film ILD (see FIG. 17). The PWM emission line PWEL may be connected to the sixth gate connecting electrode GCE6 through a fourteenth contact hole CT14 penetrating the second gate insulating film GI2 and the interlayer insulating film ILD (see FIG. 23). The scan control line GCL may be connected to the third gate connecting electrode GCE3 through an eighth contact hole CT8 penetrating the second gate insulating film GI2 and the interlayer insulating film ILD (see FIG. 19). The PAM light emitting line PAEL may be connected to the fifth gate connecting electrode GCE5 through a nineteenth contact hole CT19 penetrating the second gate insulating film GI2 and the interlayer insulating film ILD (see FIG. 23).

[0225] The initialization voltage line VIL may be connected to the second sub-drain electrode D32 and the sixth sub-drain electrode D102 through a first power contact hole VCT1 that penetrates the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 17). The initialization voltage line VIL may be connected to the tenth sub-drain electrode D162 and the eighteenth drain electrode D18 through a ninth contact hole CT9 that penetrates the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 19). The initialization voltage line VIL may also be connected to the sixth capacitor electrode CE6 through an eighteenth contact hole CT18 that penetrates the interlayer insulating film ILD. The first horizontal power line HVDL may be connected to the fifth source electrode S5 and the thirteenth source electrode S13 through a second power contact hole VCT2 that penetrates the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 18). The gate-off voltage line VGHL may be connected to the seventh source electrode S7 through a seventh contact hole CT7 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 19). The test signal line TSTL may be connected to the nineteenth gate electrode G19 through a twenty-third contact hole CT23 penetrating the second gate insulating film GI2 and the interlayer insulating film ILD (see FIG. 24). The third power line VSL may be connected to the nineteenth drain electrode D19 through a twenty-fourth contact hole CT24 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD.

[0226] The first data connecting electrode DCE1 may be connected to the second source electrode S2 through a first data contact hole DCT1 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 16). The second data connecting electrode DCE2 may be connected to the ninth source electrode S9 through a third data contact hole DCT3 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 20).

[0227] The first connecting electrode CCE1 may be connected to the first gate electrode G1 via a first contact hole CT1 penetrating the second gate insulating film GI2 and the interlayer insulating film ILD, and may be connected to the first sub-source electrode S31 and the fourth sub-drain electrode D42 via a second contact hole CT2 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 17).

[0228] The second connecting electrode CCE2 may be connected to the thirteenth drain electrode D13 via a third contact hole CT3 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 18), connected to the fourteenth drain electrode D14 via a fourth contact hole CT4 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD, and connected to the fourth capacitor electrode CE4 via a fifteenth contact hole CT15 penetrating the interlayer insulating film ILD (see FIG. 22).

[0229] The third connecting electrode CCE3 may be connected to the nineteenth source electrode S19 through a twenty-first contact hole CT21 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 24).

[0230] The fourth connecting electrode CCE4 may be connected to the ninth sub-source electrode S161 via a tenth contact hole CT10 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 19), and may be connected to the fourth gate connecting electrode GCE4 via a seventeenth contact hole CT17 penetrating the second gate insulating film GI2 and the interlayer insulating film ILD (see FIG. 23).

[0231] The fifth connecting electrode CCE5 may be connected to the twelfth source electrode S12 and the fourteenth source electrode S14 through an eleventh contact hole CT11 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 21).

[0232] The sixth connecting electrode CCE6 may be connected to the eighth gate electrode G8 via a twelfth contact hole CT12 penetrating the second gate insulating film GI2 and the interlayer insulating film ILD, and may be connected to the fifth sub-source electrode S101 and the eighth sub-drain electrode D112 via a thirteenth contact hole CT13 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 21).

[0233] The seventh connecting electrode CCE7 may be connected to the seventeenth drain electrode D17 and the eighteenth drain electrode D18 through a sixteenth contact hole CT16 penetrating the first gate insulating film GI1, the second gate insulating film GI2, and the interlayer insulating film ILD (see FIG. 22).

[0234] A first via layer VIA1 may be disposed on the first source metal layer SDL1, and a first protective layer PAS1 may be disposed on the first via layer VIA1.

[0235] The second source metal layer SDL2 (see FIG. 7) may be disposed on the first passivation layer PAS1. The second source metal layer SDL2 may include a data line DL, a first vertical power line VVDL, and a PAM data line RDL. The second source metal layer SDL2 may also include an anode connecting line ACL and a second power connecting electrode VDCE.

[0236] The data line DL may be connected to the first data connecting electrode DCE1 through a second data contact hole DCT2 penetrating the first passivation layer PAS1 and the first via layer VIA1 (see FIG. 16). The PAM data line RDL may be connected to the second data connecting electrode DCE2 through a fourth data contact hole DCT4 penetrating the first passivation layer PAS1 and the first via layer VIA1 (see FIG. 20). The first vertical power line VVDL may be connected to the first horizontal power line HVDL through a third power contact hole VCT3 penetrating the first passivation layer PAS1 and the first via layer VIA1 (see FIG. 18). The third power contact hole VCT3 may overlap the second power contact hole VCT2 in the third direction DR3. The area of ​​the third power contact hole VCT3 may be larger than the area of ​​the second power contact hole VCT2.

[0237] The anode connecting line ACL may be connected to the seventh connecting electrode CCE7 through a twentieth contact hole CT20 penetrating the first protective layer PAS1 and the first via layer VIA1, and may be connected to the third connecting electrode CCE3 through a 22nd contact hole CT22 penetrating the first protective layer PAS1 and the first via layer VIA1 (see FIG. 24). The second power connecting electrode VDCE may be connected to the fifth connecting electrode CCE5 through a fourth power contact hole VCT4 penetrating the first protective layer PAS1 and the first via layer VIA1 (see, for example, FIG. 21).

[0238] A second via layer VIA2 may be disposed on the second source metal layer SDL2, and a second protective layer PAS2 may be disposed on the second via layer VIA2.

[0239] The third source metal layer SDL3 (see FIG. 7) may be disposed on the second passivation layer PAS2. The third source metal layer SDL3 may include a first sub-power line VDL21. The first sub-power line VDL21 may be connected to the second power connecting electrode VDCE through a fifth power contact hole VCT5 penetrating the second passivation layer PAS2 and the second via layer VIA2 (see FIG. 21). In addition, the third source metal layer SDL3 may include an anode connecting electrode ACE. The anode connecting electrode ACE may be connected to the anode connecting line ACL through a first electrode contact hole ECT1 penetrating the second passivation layer PAS2 and the second via layer VIA2 (see FIG. 24).

[0240] A third via layer VIA3 may be disposed on the third source metal layer SDL3, and a third protective layer PAS3 may be disposed on the third via layer VIA3.

[0241] The electrode layer may be disposed on the third passivation layer PAS3. The electrode layer may include a second sub-power line VDL22, a third sub-power line VDL23, a first pixel electrode AND1, and a second pixel electrode AND2. The third sub-power line VDL23 overlaps with the second sub-power line VDL22 in the third direction DR3, and the third sub-power line VDL23 and the second sub-power line VDL22 may form a common electrode COM (see, for example, FIG. 7 and FIG. 23). The second sub-power line VDL22 and the first pixel electrode AND1 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The second pixel electrode AND2 overlaps with the first pixel electrode AND1 in the third direction DR3 to form one pixel electrode AND (see FIG. 7). The third sub-power line VDL23 and the second pixel electrode AND2 may include a transparent conductive material (TCO) such as ITO or IZO.

[0242] A fourth protective layer PAS4 may be disposed on the electrode layer. As shown in FIG. 7, a fourth via layer VIA4 may be further disposed between the fourth protective layer PAS4 and the electrode layer.

[0243] The light emitting element ED may be disposed on the pixel electrode AND that is not covered by the fourth protective layer PAS4. The first contact electrode ELT1 may be disposed between the light emitting element ED and the pixel electrode AND to electrically connect the light emitting element ED and the pixel electrode AND.

[0244] FIG. 25 is a layout diagram showing an example of the sub-pixel of FIG.

[0245] 4, 11, 12, and 25, the subpixel SPX_1 of FIG. 25 may correspond to at least one of the subpixels SPX1, SPX2, and SPX3 of FIG. 4. For example, the subpixel SPX_1 of FIG. 25 may correspond to, but is not limited to, the first subpixel SPX1 described with reference to FIGS. 4, 6, and 7. Except for the shape of the anode connecting electrode ACE_1 and the arrangement of the first and second contact electrodes ELT1 and ETL2, the subpixel SPX_1 of FIG. 25 is substantially the same as the subpixel SPX of FIG. 12, and therefore a duplicated description will not be repeated.

[0246] 6, the anode connecting electrode ACE_1 may overlap the anode connecting line ACL in the third direction DR3 and may be connected to the anode connecting line ACL through the first electrode contact hole ECT1. In addition, the anode connecting electrode ACE_1 may extend in the first direction DR1 and overlap the pixel electrode AND and the common electrode COM in the third direction DR3.

[0247] The anode connecting electrode ACE_1 may be connected to the pixel electrode AND through a second electrode contact hole ECT2.

[0248] FIG. 26 is a perspective view of a tiled display including multiple displays according to one or more embodiments.

[0249] 26, the tiled display device TD may include a plurality of display devices 10_1, 10_2, 10_3, 10_4 and a joint portion SM. For example, the tiled display device TD may include a first display device 10_1, a second display device 10_2, a third display device 10_3, and a fourth display device 10_4.

[0250] The plurality of display devices 10_1, 10_2, 10_3, and 10_4 may be arranged in a lattice pattern. The plurality of display devices 10_1, 10_2, 10_3, and 10_4 may be arranged in a matrix pattern with M (M is a positive integer) rows and N (N is a positive integer) columns. For example, the first display device 10_1 and the second display device 10_2 may be adjacent to each other in a first direction DR1. The first display device 10_1 and the third display device 10_3 may be adjacent to each other in a second direction DR2. The third display device 10_3 and the fourth display device 10_4 may be adjacent to each other in the first direction DR1. The second display device 10_2 and the fourth display device 10_4 may be adjacent to each other in the second direction DR2.

[0251] However, the number and arrangement of the multiple display devices 10_1, 10_2, 10_3, and 10_4 in the tiled display device TD are not limited to those shown in Fig. 26. The number and arrangement of the display devices 10_1, 10_2, 10_3, and 10_4 in the tiled display device TD can be determined according to the respective sizes of the display device 10 and the tiled display device TD and the shape of the tiled display device TD.

[0252] The display devices 10_1, 10_2, 10_3, and 10_4 may have the same size as each other, but are not limited to this. For example, the display devices 10_1, 10_2, 10_3, and 10_4 may have different sizes from each other.

[0253] Each of the plurality of display devices 10_1, 10_2, 10_3, and 10_4 may be rectangular including a long side and a short side. The plurality of display devices 10_1, 10_2, 10_3, and 10_4 may be arranged with their long sides or short sides connected to each other. Some or all of the plurality of display devices 10_1, 10_2, 10_3, and 10_4 may be arranged at the edge of the tiled display device TD and form one side of the tiled display device TD. At least one of the plurality of display devices 10_1, 10_2, 10_3, and 10_4 may be arranged at at least one corner of the tiled display device TD and form two adjacent sides of the tiled display device TD. At least one of the plurality of display devices 10_1, 10_2, 10_3, and 10_4 may be surrounded by other display devices.

[0254] Each of the plurality of display devices 10_1, 10_2, 10_3, and 10_4 may be substantially the same as the display device 10 described with reference to Figures 1 to 5. Therefore, a description of each of the plurality of display devices 10_1, 10_2, 10_3, and 10_4 will be omitted.

[0255] The connecting portion SM may include a coupling member or an adhesive member. In this case, the multiple display devices 10_1, 10_2, 10_3, and 10_4 may be connected to each other via the coupling member or adhesive member of the connecting portion SM. The connecting portion SM may be disposed between the first display device 10_1 and the second display device 10_2, between the first display device 10_1 and the third display device 10_3, between the second display device 10_2 and the fourth display device 10_4, and between the third display device 10_3 and the fourth display device 10_4.

[0256] FIG. 27 is an enlarged layout diagram showing the details of the AA region in FIG.

[0257] 27, the joint portion SM may have a planar shape of a cross, a crucifix, or a plus sign in the central region of the tiled display device TD where the first display device 10_1, the second display device 10_2, the third display device 10_3, and the fourth display device 10_4 are adjacent to each other. The joint portion SM may be disposed between the first display device 10_1 and the second display device 10_2, between the first display device 10_1 and the third display device 10_3, between the second display device 10_2 and the fourth display device 10_4, and between the third display device 10_3 and the fourth display device 10_4.

[0258] The first display device 10_1 may include first pixels PX1 arranged in a matrix form along a first direction DR1 and a second direction DR2 to display an image. The second display device 10_2 may include second pixels PX2 arranged in a matrix form along the first direction DR1 and the second direction DR2 to display an image. The third display device 10_3 may include third pixels PX3 arranged in a matrix form along the first direction DR1 and the second direction DR2 to display an image. The fourth display device 10_4 may include fourth pixels PX4 arranged in a matrix form along the first direction DR1 and the second direction DR2 to display an image.

[0259] The minimum distance between adjacent first pixels PX1 in the first direction DR1 may be defined as a first horizontal separation distance GH1, and the minimum distance between adjacent second pixels PX2 in the first direction DR1 may be defined as a second horizontal separation distance GH2. The first horizontal separation distance GH1 and the second horizontal separation distance GH2 may be substantially equal to each other.

[0260] A seam SM may be disposed between the adjacent first pixel PX1 and second pixel PX2 in the first direction DR1. The minimum distance GG1 between the adjacent first pixel PX1 and second pixel PX2 in the first direction DR1 may be the sum of the minimum distance GHS1 between the first pixel PX1 and the seam SM in the first direction DR1, the minimum distance GHS2 between the second pixel PX2 and the seam SM in the first direction DR1, and the width GSM1 of the seam SM in the first direction DR1.

[0261] In the first direction DR1, the minimum distance GG1 between the first pixel PX1 and the second pixel PX2 adjacent to each other, the first horizontal separation distance GH1, and the second horizontal separation distance GH2 may be substantially the same. Therefore, the minimum distance GHS1 between the first pixel PX1 and the junction SM in the first direction DR1 may be smaller than the first horizontal separation distance GH1, and the minimum distance GHS2 between the second pixel PX2 and the junction SM in the first direction DR1 may be smaller than the second horizontal separation distance GH2. Also, the width GSM1 of the junction SM in the first direction DR1 may be smaller than the first horizontal separation distance GH1 or the second horizontal separation distance GH2.

[0262] The minimum distance between adjacent third pixels PX3 in the first direction DR1 may be defined as a third horizontal separation distance GH3, and the minimum distance between adjacent fourth pixels PX4 in the first direction DR1 may be defined as a fourth horizontal separation distance GH4. The third horizontal separation distance GH3 and the fourth horizontal separation distance GH4 may be substantially the same.

[0263] A seam SM may be disposed between the neighboring third pixel PX3 and fourth pixel PX4 in the first direction DR1. The minimum distance GG4 between the neighboring third pixel PX3 and fourth pixel PX4 in the first direction DR1 may be the sum of the minimum distance GHS3 between the third pixel PX3 and the seam SM in the first direction DR1, the minimum distance GHS4 between the fourth pixel PX4 and the seam SM in the first direction DR1, and the width GSM1 of the seam SM in the first direction DR1.

[0264] The minimum distance GG4, the third horizontal separation distance GH3, and the fourth horizontal separation distance GH4 between the neighboring third pixel PX3 and fourth pixel PX4 in the first direction DR1 may be substantially the same. Therefore, the minimum distance GHS3 between the third pixel PX3 and the seam SM in the first direction DR1 may be smaller than the third horizontal separation distance GH3, and the minimum distance GHS4 between the fourth pixel PX4 and the seam SM in the first direction DR1 may be smaller than the fourth horizontal separation distance GH4. Also, the width GSM1 of the seam SM in the first direction DR1 may be smaller than the third horizontal separation distance GH3 or the fourth horizontal separation distance GH4.

[0265] The minimum distance between adjacent first pixels PX1 in the second direction DR2 may be defined as a first vertical separation distance GV1, and the minimum distance between adjacent third pixels PX3 in the second direction DR2 may be defined as a third vertical separation distance GV3. The first vertical separation distance GV1 and the third vertical separation distance GV3 may be substantially the same.

[0266] A junction portion SM may be disposed between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2. The minimum distance GG2 between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2 may be the sum of the minimum distance GVS1 between the first pixel PX1 and the junction portion SM in the second direction DR2, the minimum distance GVS3 between the third pixel PX3 and the junction portion SM in the second direction DR2, and the width GSM2 of the junction portion SM in the second direction DR2.

[0267] The minimum distance GG2 between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2, the first vertical separation distance GV1, and the third vertical separation distance GV3 may be substantially the same. Therefore, the minimum distance GVS1 between the first pixel PX1 and the seam SM in the second direction DR2 may be smaller than the first vertical separation distance GV1, and the minimum distance GVS3 between the third pixel PX3 and the seam SM in the second direction DR2 may be smaller than the third vertical separation distance GV3. Also, the width GSM2 of the seam SM in the second direction DR2 may be smaller than the first vertical separation distance GV1 or the third vertical separation distance GV3.

[0268] The minimum distance between adjacent second pixels PX2 in the second direction DR2 may be defined as a second vertical separation distance GV2, and the minimum distance between adjacent fourth pixels PX4 in the second direction DR2 may be defined as a fourth vertical separation distance GV4. The second vertical separation distance GV2 and the fourth vertical separation distance GV4 may be substantially the same.

[0269] A seam SM may be disposed between the second pixel PX2 and the fourth pixel PX4 that are adjacent to each other in the second direction DR2. The minimum distance GG3 between the second pixel PX2 and the fourth pixel PX4 that are adjacent to each other in the second direction DR2 may be the sum of the minimum distance GVS2 between the second pixel PX2 and the seam SM in the second direction DR2, the minimum distance GVS4 between the fourth pixel PX4 and the seam SM in the second direction DR2, and the width GSM2 of the seam SM in the second direction DR2.

[0270] The minimum distance GG3 between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR2, the second vertical separation distance GV2, and the fourth vertical separation distance GV4 may be substantially the same. Therefore, the minimum distance GVS2 between the second pixel PX2 and the seam SM in the second direction DR2 may be smaller than the second vertical separation distance GV2, and the minimum distance GVS4 between the fourth pixel PX4 and the seam SM in the second direction DR2 may be smaller than the fourth vertical separation distance GV4. Also, the width GSM2 of the seam SM in the second direction DR2 may be smaller than the second vertical separation distance GV2 or the fourth vertical separation distance GV4.

[0271] As shown in FIG. 27, in order to prevent a seam SM from being visible between images displayed by multiple display devices 10_1, 10_2, 10_3, and 10_4, the minimum distance between pixels of adjacent display devices may be substantially the same as the minimum distance between each pixel of the display devices.

[0272] FIG. 28 is a cross-sectional view showing an example of a tiled display device taken along line JJ' in FIG.

[0273] 28, the first display device 10_1 includes a first display module DPM1 and a first front cover COV1, and the second display device 10_2 includes a second display module DPM2 and a second front cover COV2.

[0274] Each of the first display module DPM1 and the second display module DPM2 includes a substrate SUB, a thin film transistor layer TFTL, and a light emitting element layer EML. The thin film transistor layer TFTL and the light emitting element layer EML have already been described in detail with reference to Fig. 7. In Fig. 28, the description overlapping with Fig. 7 will be omitted.

[0275] The substrate SUB may include a first surface 41 on which the thin film transistor layer TFTL is disposed, a second surface 42 opposite to the first surface, and a first side surface 43 disposed between the first surface 41 and the second surface 42. The first surface 41 may be a front or top surface of the substrate SUB, and the second surface 42 may be a back or bottom surface of the substrate SUB.

[0276] The substrate SUB may further include chamfered surfaces 44_1, 44_2 disposed between the first surface 41 and the first side surface 43 and between the second surface 42 and the first side surface 43. The thin film transistor layer TFTL and the light emitting element layer EML may not be disposed on the chamfered surfaces 44_1, 44_2. The chamfered surfaces 44_1, 44_2 can prevent the substrate SUB of the first display device 10_1 and the substrate of the second display device 10_2 from colliding with each other and being damaged.

[0277] The chamfered surfaces 44_1 and 44_2 may also be disposed between the first surface 41 and each of the other side surfaces excluding the first side surface 43, and between the second surface 42 and each of the other side surfaces excluding the first side surface 43. For example, when the first display device 10_1 and the second display device 10_2 have a rectangular planar shape as shown in Fig. 26, the chamfered surfaces 44_1 and 44_2 may be disposed between the first surface 41 and each of the second side surface, the third side surface, and the fourth side surface, and between the second surface 42 and each of the second side surface, the third side surface, and the fourth side surface.

[0278] The first front cover COV1 may be disposed on the chamfered surfaces 44_1, 44_2 of the substrate SUB. That is, the first front cover COV1 may protrude beyond the substrate SUB in the first direction DR1 and the second direction DR2. Therefore, the distance GSUB between the substrate SUB of the first display device 10_1 and the substrate SUB of the second display device 10_2 may be greater than the distance GCOV between the first front cover COV1 and the second front cover COV2.

[0279] Each of the first front cover COV1 and the second front cover COV2 may include an adhesive member 51, a light transmittance adjusting layer 52 disposed on the adhesive member 51, and an anti-glare layer 53 disposed on the light transmittance adjusting layer 52.

[0280] The adhesive member 51 of the first front cover COV1 serves to attach the light emitting element layer EML of the first display module DPM1 to the first front cover COV1. The adhesive member 51 of the second front cover COV2 serves to attach the light emitting element layer EML of the second display module DPM2 to the second front cover COV2. The adhesive member 51 may be a transparent adhesive member that allows light to pass through. For example, the adhesive member 51 may be an optically clear adhesive film or an optically clear resin.

[0281] The anti-glare layer 53 may be designed to diffusely reflect external light to prevent the external light from being directly reflected and reducing the visibility of the image. Therefore, the anti-glare layer 53 may increase the contrast ratio of the images displayed by the first display device 10_1 and the second display device 10_2.

[0282] The light transmittance adjusting layer 52 may be designed to reduce the transmittance of external light or light reflected from the first display module DPM1 and the second display module DPM2, thereby preventing the distance GSUB between the substrate SUB of the first display module DPM1 and the substrate SUB of the second display module DPM2 from being visible from the outside.

[0283] The anti-glare layer 53 may be realized as a polarizing plate, and the light transmittance adjusting layer 52 may be realized as a phase retardation layer, but the embodiments of the present specification are not limited thereto.

[0284] An example of a tiled display device cut along lines K-K', L-L', and M-M' in Figure 27 is substantially the same as the example of a tiled display device cut along line J-J' described with reference to Figure 28, so a description thereof will be omitted.

[0285] Fig. 29 is an enlarged layout diagram showing the details of the BB region in Fig. 26. For convenience of explanation, Fig. 29 shows the pad PAD and the first pixel PX1 arranged on the upper side of the first display device 10_1. The second display device 10_2, the third display device 10_3, and the fourth display device 10_4 have substantially the same configuration as the first display device 10_1, so that the overlapping explanations will be omitted.

[0286] 29, a pad PAD may be disposed at an upper edge of the first display device 10_1. When the data lines (see "DL" in FIG. 5 or FIG. 30) of the first display device 10_1 extend in the second direction DR2, the pad PAD may be disposed at the upper and lower edges of the first display device 10_1. Or, when the data lines of the first display device 10_1 extend in the first direction DR1, the pad PAD may be disposed at the left and right edges of the first display device 10_1.

[0287] Each of the pads PAD may be coupled to a data line on the upper surface of the substrate SUB. Also, each of the pads PAD may be coupled to a side wiring (see "SSL" in FIG. 30). The side wiring may be disposed on the upper surface, one side surface, and the lower surface (or back surface) of the substrate SUB. The side wiring SSL may be coupled to a connection wiring (see "CCL" in FIG. 30) on the lower surface of the substrate SUB.

[0288] Figure 30 is a cross-sectional view showing an example of a tiled display device cut along line N-N' in Figure 29. In Figure 30, the same components as those in the cross-sectional views shown in Figures 28 and 7 are denoted by the same reference numerals, and explanations that overlap with Figures 28 and 7 will be omitted.

[0289] 30, the pad PAD may be disposed on the first protective layer PAS1. A part of the pad PAD may be exposed and not covered by the third protective layer PAS3 (and / or the second protective layer PSA2) and the fourth protective layer PAS4. The pad PAD may include the same material as the pixel electrode AND and the common electrode COM. For example, the pad PAD may include a highly reflective metal material such as a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a laminated structure of APC alloy and ITO (ITO / APC / ITO).

[0290] The first source metal layer SDL1 (see, for example, FIG. 7) may include a data line DL. The data line DL may be disposed on an interlayer insulating film ILD. That is, the data line DL may be disposed in the same layer as the connecting electrode CCE1 and may include the same material.

[0291] The pad PAD can be connected to the data line DL via a third contact hole CT35 that penetrates the first via layer VIA1, the first protective layer PAS1, and, according to an embodiment, the third via layer VIA3 (and / or the second via layer VIA2), and the third protective layer PAS3 (and / or the second protective layer PAS2).

[0292] The interconnect wiring CCL may be disposed on the lower surface of the substrate SUB. The interconnect wiring CCL may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0293] The fifth via layer VIA5 may be disposed on a portion of the connecting wiring CCL. The fifth via layer VIA5 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0294] A fifth protective layer PAS5 may be disposed on the fifth via layer VIA5. The fifth protective layer PAS5 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0295] The side wiring SSL may be disposed on the edge of the upper surface, the side surface, and the edge of the lower surface of the substrate SUB. One end of the side wiring SSL may be connected to the pad PAD. One end of the side wiring SSL may be connected to the pad PAD via a 36th contact hole CT36 penetrating the fourth protective layer PAS4. The other end of the side wiring SSL may be connected to the connecting wiring CCL.

[0296] The side wiring SSL can be arranged on the side of the substrate SUB, the side of the buffer film BF, the side of the first gate insulation film GI1, the side of the second gate insulation film GI2, the side of the interlayer insulation film ILD, the side of the first protective layer PAS1, and the side of the third via layer VIA3 (and / or the second via layer VIA2).

[0297] Since the pad PAD formed on the upper edge of the substrate SUB and the connecting wiring CCL formed on the lower edge of the substrate SUB are connected via the side wiring SSL, a first coating pattern PR and a second coating pattern OC surrounding the edge region EDG may be formed to protect the side wiring SSL exposed to the outside from moisture and oxygen and to prevent it from being visible to the user.

[0298] The flexible film FPCB may be disposed on the lower surface of the fifth protective layer PAS5. The flexible film FPCB may be connected to the connection wiring CCL through the fifth via layer VIA5 and the 37th contact hole CT37 penetrating the fifth protective layer PAS5 by using a conductive adhesive material CAM. A source driving circuit for supplying a data voltage to the data line DL may be disposed on the lower surface of the flexible film FPCB. The conductive adhesive material CAM may be an anisotropic conductive film or an anisotropic conductive paste.

[0299] As described above, in the first display device 10_1, the source driving circuit of the flexible film FPCB disposed under the substrate SUB can be connected to the data line DL via the connection wiring CCL, the side wiring SSL, and the pad PAD. That is, since the source driving circuit is disposed on the substrate SUB, the non-display area NDA can be eliminated, and the pixels PX can be formed even on the edge of the substrate SUB.

[0300] 31 is a block diagram illustrating a tiled display device according to one or more embodiments, which shows a first display device 10_1 and a host system HOST for ease of explanation.

[0301] Referring to FIG. 31, a tiled display device TD according to one or more embodiments may include a host system HOST, a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, a speaker 240, a user input unit 250, a hard drive disk (HDD) 260, a network communication unit 270, a UI generation unit 280, and a control unit 290.

[0302] The host system HOST may be embodied as any one of a television system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer, a mobile phone system, and a tablet.

[0303] A user's command may be input to the host system HOST in various forms. For example, the host system HOST may receive a command by touch input from the user. Alternatively, the host system HOST may receive a command by keyboard input or button input from a remote controller.

[0304] The host system HOST can receive an input of original video data corresponding to an original image from the outside. The host system HOST can divide the original video data into the number of display devices. For example, the host system HOST can divide the original video data into first video data corresponding to the first image, second video data corresponding to the second image, third video data corresponding to the third image, and fourth video data corresponding to the fourth image, corresponding to the first display device 10_1, the second display device 10_2, the third display device 10_3, and the fourth display device 10_4. The host system HOST can transmit the first video data to the first display device 10_1, the second video data to the second display device 10_2, the third video data to the third display device 10_3, and the fourth video data to the fourth display device 10_4.

[0305] The first display device 10_1 can display a first image according to the first video data, the second display device 10_2 can display a second image according to the second video data, the third display device 10_3 can display a third image according to the third video data, and the fourth display device 10_4 can display a fourth image according to the fourth video data, allowing the user to view an original image in which the first to fourth images displayed on the first to fourth display devices 10_1, 10_2, 10_3, and 10_4 are combined.

[0306] The first display device 10_1 may include a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, a speaker 240, a user input unit 250, a HDD 260, a network communication unit 270, a UI generation unit 280, and a control unit 290.

[0307] The broadcast tuning unit 210 can tune to a desired frequency (e.g., a predetermined channel frequency) under the control of the control unit 290 and receive a broadcast signal of the corresponding channel through an antenna. The broadcast tuning unit 210 can include a channel detection module and an RF demodulation module.

[0308] The broadcast signal demodulated by the broadcast tuning unit 210 is processed by the signal processing unit 220 and output to the display unit 230 and the speaker 240. Here, the signal processing unit 220 may include a demultiplexer 221, a video decoder 222, a video processing unit 223, an audio decoder 224, and an additional data processing unit 225.

[0309] The demultiplexer 221 separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal, and additional data are restored by a video decoder 222, an audio decoder 224, and an additional data processor 225, respectively. At this time, the video decoder 222, the audio decoder 224, and the additional data processor 225 restore the signals to a decoding format corresponding to the encoding format used when the broadcast signal was transmitted.

[0310] In one or more embodiments, the decoded video signal is converted by the video processing unit 223 to match the vertical frequency, resolution, screen ratio, etc., of the display unit 230 output standard, and the decoded audio signal is output to the speaker 240.

[0311] The display unit 230 may include a display panel on which an image is displayed, and a panel driver that controls driving of the display panel.

[0312] The user input unit 250 can receive a signal transmitted by the host system HOST. The user input unit 250 can be provided to input data for the user to select and input commands related to communication with other display devices as well as data related to channel selection, UI (User Interface) menu selection and operation transmitted by the host system HOST.

[0313] The HDD 260 stores various software programs including an OS program, recorded broadcast programs, videos, photos, and other data, and may be a storage medium such as a hard disk or a non-volatile memory.

[0314] The network communication unit 270 is for short-range communication with the host system HOST and other display devices, and can be embodied as a communication module including an antenna pattern that can embody mobile communication, data communication, Bluetooth, RF, Ethernet, etc.

[0315] The network communication unit 270 can also transmit and receive wireless signals to and from at least one of a base station, an external terminal, and a server on a mobile communication network constructed in accordance with a technical standard or communication method for mobile communication (e.g., Global System for Mobile communication (GSM), Code Division Multi Access (CDMA), Code Division Multi Access 2000 (CDMA2000), Enhanced Voice-Data Optimized or Enhanced Voice-Data Only (EV-DO), Wideband CDMA (WCDMA (registered trademark)), High Speed ​​Downlink Packet Access (HSDPA), High Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), Long Term Evolution-Advanced (LTE-A), 5G, etc.) via an antenna pattern described later.

[0316] The network communication unit 270 can also transmit and receive wireless signals over a communication network using wireless Internet technologies via an antenna pattern, which will be described later. Examples of wireless Internet technologies include WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, DLNA (Digital Living Network Alliance), WiBro (Wireless Broadband), WiMAX (World Interoperability for Microwave Access), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), and LTE-A (Long Term Evolution-Advanced), and the antenna pattern transmits and receives data according to at least one wireless Internet technology, including Internet technologies not listed above.

[0317] The UI generating unit 280 generates a UI menu for communication with the host system HOST and other display devices, and can be realized by an algorithm code and an on-screen display (OSD) integrated circuit (IC). The UI menu for communication with the host system HOST and other display devices DV2 to DV4 can be a menu for specifying a destination digital TV with which communication is desired and for selecting a desired function.

[0318] The control unit 290 is responsible for overall control of the first display device 10_1 and communication control between the host system HOST and the second to fourth display devices 10_2, 10_3, and 10_4, and can be embodied by an MCU (Micro Controller Unit) that stores the corresponding algorithm code for control and executes the stored algorithm code.

[0319] The control unit 290 controls the transmission of the corresponding control command and data to the host system HOST and the second to fourth display devices 10_2, 10_3, and 10_4 via the network communication unit 270 in accordance with the input and selection of the user input unit 250. Of course, when an appropriate control command (e.g., a predetermined control command) and data are input from the host system HOST and the second to fourth display devices 10_2, 10_3, and 10_4, the operation is performed according to the corresponding control command.

[0320] In one or more embodiments, the block diagram of the second display device 10_2, the block diagram of the third display device 10_3, and the block diagram of the fourth display device 10_4 are substantially identical to the block diagram of the first display device 10_1 described with reference to FIG. 31, so their descriptions are omitted.

[0321] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or those having ordinary knowledge in the art that the present invention can be modified and changed in various ways without departing from the spirit and technical scope of the present invention as described in the claims below.

[0322] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims

1. A pixel, the pixel comprising: a first light emitting element, a second light emitting element, and a third light emitting element arranged at equal intervals along a first direction; a first pixel electrode arranged along the first direction and in contact with the first, second, and third light emitting elements; a second pixel electrode arranged in the first direction in a pair with the first pixel electrode and in contact with the first, second, and third light emitting elements; Each of the first to third light emitting elements includes a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and includes a mesa region in which one of the first and second semiconductor layers is partially exposed by the other one of the first and second semiconductor layers; the mesa region of the first light emitting element contacts one of the first pixel electrodes; the mesa region of the second light emitting element contacts one of the second pixel electrodes; A display device, wherein an arrangement order of the first and second pixel electrodes in contact with the first light emitting element is reverse to an arrangement order of the first and second pixel electrodes in contact with the second light emitting element.

2. Each of the first to third light emitting elements includes an inclined surface formed along an edge of the mesa region, The display device according to claim 1 , wherein the inclined surfaces of the first to third light emitting elements face in the same direction.

3. The display device of claim 1 , wherein an arrangement order of the first and second pixel electrodes in contact with the third light emitting element is the same as an arrangement order of the first and second pixel electrodes in contact with the second light emitting element.

4. The first, second and third light emitting elements are sequentially arranged along the first direction, 2. The display device of claim 1, wherein the distance in the first direction between the first pixel electrodes in contact with the first and second light-emitting elements is different from the distance in the first direction between the first pixel electrodes in contact with the second and third light-emitting elements.

5. 2. The display device of claim 1, wherein the distance in the first direction between the first pixel electrodes in contact with the first and second light-emitting elements is different from the distance in the first direction between the second pixel electrodes in contact with the first and second light-emitting elements.

6. 6. The display device of claim 5, wherein the distance in the first direction between the first pixel electrodes in contact with the second and third light-emitting elements is the same as the distance in the first direction between the second pixel electrodes in contact with the second and third light-emitting elements.

7. The display device according to claim 1 , wherein the first light emitting element emits red light, and the second light emitting element emits green or blue light.

8. the pixel further includes a first pixel circuit, a second pixel circuit, and a third pixel circuit that supply driving currents to the first to third light emitting elements via the first pixel electrode, respectively; The display device according to claim 1 , wherein each of the first to third pixel circuits includes at least one transistor and at least one capacitor.

9. Each of the first, second, and third pixel circuits further includes a bridge pattern in contact with the first pixel electrode, The display device according to claim 8 , wherein a shape of the bridge pattern of the first pixel circuit is different from a shape of the bridge pattern of the second pixel circuit.

10. The display device according to claim 9 , wherein the bridge pattern of the first pixel circuit overlaps with the second pixel electrode on a plane, and the bridge pattern of the second pixel circuit does not overlap with the second pixel electrode on a plane.

11. The display device according to claim 8 , wherein the first, second and third pixel circuits have the same circuit structure.

12. the first pixel circuit is located in a second direction with respect to the first light emitting element, the second pixel circuit is located in the second direction with respect to the second light emitting element, and the third pixel circuit is located in the second direction with respect to the third light emitting element, The display device of claim 11 , wherein the second direction is perpendicular to the first direction.

13. The display device of claim 1 , wherein each of the first to third light emitting elements is a flip-chip type micro light emitting diode element.

14. A pixel, the pixel comprising: a first light emitting element, a second light emitting element, and a third light emitting element arranged at equal intervals along a first direction; a first pixel electrode arranged along the first direction and in contact with the first, second, and third light emitting elements; Each of the first to third light emitting elements includes a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and includes a mesa region in which one of the first and second semiconductor layers is partially exposed by the other one of the first and second semiconductor layers; the mesa region of the first light emitting element is formed in the first semiconductor layer; the mesa region of the second light emitting element is formed in the second semiconductor layer; The first pixel electrodes are arranged at different intervals along the first direction.

15. A display device includes a plurality of display devices and a joint portion located between the plurality of display devices, A first display device of the plurality of display devices is A substrate; a pixel disposed on the first surface of the substrate; The pixel is a first light emitting element, a second light emitting element, and a third light emitting element arranged at equal intervals along a first direction; a first pixel electrode arranged along the first direction and in contact with the first, second, and third light emitting elements; a second pixel electrode arranged in the first direction in a pair with the first pixel electrode and in contact with the first, second, and third light emitting elements; Each of the first to third light emitting elements includes a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and includes a mesa region in which one of the first and second semiconductor layers is partially exposed by the other one of the first and second semiconductor layers; the mesa region of the first light emitting element contacts one of the first pixel electrodes; the mesa region of the second light emitting element contacts one of the second pixel electrodes; A tiled display device, wherein an arrangement order of the first and second pixel electrodes in contact with the first light emitting element is reverse to an arrangement order of the first and second pixel electrodes in contact with the second light emitting element.

16. The tiled display device according to claim 15, wherein each of the light-emitting elements is a flip-chip type micro light-emitting diode element.

17. The tiled display of claim 15 , wherein the substrate comprises glass.

18. The first display device is a pad disposed on a first surface of the substrate; 16. The tiled display device of claim 15, further comprising: a first surface of the substrate, a second surface opposite to the first surface, and a side wiring disposed on one side between the first surface and the second surface and connected to the pad.

19. The first display device is a connecting wire disposed on a second surface of the substrate; and a flexible film connected to the connecting wire via a conductive adhesive member, The tiled display device of claim 18 , wherein the side wirings are connected to the connecting wirings.

20. The tiled display device of claim 15, wherein the plurality of display devices are arranged in a matrix form with M rows and N columns.

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