Method and apparatus for reducing processor load - Patents.com

Abstract

The navigation receiver receives global navigation satellite system signals and processes the signals in a manner that reduces the load on a processor used in the navigation receiver. The navigation receiver includes a plurality of components assembled and configured to detect and respond to events, such as the occurrence of a signal, using relaxotic signals that reduce the load on the processor of the navigation receiver.

Description

[Technical field]

[0001] The present disclosure relates generally to methods for processing signals from various Global Navigation Satellite Systems (GNSS), such as GPS or GLONASS, and more particularly to methods for reducing processor load. [Background technology]

[0002] The speed of the processor in a global navigation satellite system receiver must be sufficient so that occurring events, such as signal generation, can be detected by the processor and responded to accordingly. If the processor is too slow or overloaded, it cannot process events in a timely manner.

[0003] US Patent No. 8,401,546 B2 relates to a universal acquisition and tracking device for a Global Navigation Satellite System (GNSS). The acquisition and tracking device is described as having channels that process input signals over 1 ms intervals and generate time frames (code epochs) that are input to a local interrupt manager. A global time signal at a rate of 1 ms (Global 1ms) is also generated to serve as an interrupt signal. The global interrupt manager distributes the global time signal to each of a number of channel processors, collects accumulated data from each of the channel processors including at least one of a number of correlation signals, a sample carrier, and a code phase signal, and transfers the accumulated data to a computer host for further processing. Correlations are constantly accumulated and "dumped" to an interrupt handler local interrupt module for processing at a rate of 1 ms, while feedback signals are updated at the end of specified total coherent and non-coherent integration periods.

[0004] US Patent No. 8,331,422 B2 relates to a method and apparatus for acquisition, tracking and transfer using weak GPS / GNSS signals with sub-microsecond time transfer. The method and apparatus provide high sensitivity GPS / GNSS signal acquisition in a fixed GPS / GNSS receiver. A control algorithm and apparatus is provided in which a 1 ms correlation of an input signal, a pseudorandom noise (PRN) code signal and an output signal of a numerically controlled oscillator (NCO) is generated and a 20 ms symbol is output. The frequency uncertainty due to the apparent Doppler shift is divided into a number of consecutive frequency bins and the uncertainty of the location of the navigation data bit boundary is divided into equally spaced trial bit boundary locations. For example, Doppler shift compensation is generated by correction at a rate of 1 Hz / sec or less.

[0005] Although these patents describe configurations that cause the processor to operate based on specific intervals, these configurations do not reduce the load on the processor. What is needed is a method and apparatus that reduces the load on the processor so that it can process signals in a timely manner. Summary of the Invention

[0006] In one embodiment, a GNSS receiver (also referred to as a "navigation receiver") includes an RF path configured to receive Global Navigation Satellite System (GNSS) signals from an antenna and transmit the GNSS signals over an intermediate frequency. The analog-to-digital converter (ADC) receives the GNSS signal at the intermediate frequency from the RF path and is adapted to sample the GNSS signal at the frequency CLKnav. The time scale generator is configured to generate a tick signal and a relax tick signal. The channel configured to receive the GNSS signal from the ADC includes an intermediate frequency numerically controlled oscillator (NCO) configured to generate pulses at an intermediate frequency and an intermediate frequency phase. The channel also includes a code rate NCO configured to generate a code rate NCO signal having a code rate NCO phase and a code rate NCO frequency. The channel also includes a code generator configured to generate a code signal based on the code rate NCO frequency. The channel also includes a strobe generator configured to generate a strobe signal based on the code rate NCO phase and a shape of the code signal, an integration period counter configured to generate an integration period signal based on the code rate NCO frequency, and a commutator configured to receive the GNSS signal from the ADC. The channel also includes a correlator configured to multiply the signal output from the commutator and code generator with an intermediate frequency phase from the intermediate frequency NCO to generate a first product and configured to store the first product during an integration period. The correlator is also configured to multiply the signal output from the commutator, the strobe signal, and the intermediate frequency phase from the intermediate frequency NCO to generate a second product, and is configured to store the second product during the integration period. The navigation receiver also includes a CPU that controls the navigation receiver and reads the data from the correlator. A method for operating a navigation receiver is also described. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 illustrates a Global Navigation Satellite System (GNSS) receiver in one embodiment. [Diagram 2] FIG. 2 shows details of the time scale generator shown in FIG. [Diagram 3] FIG. 3 shows a detail of one of the channels shown in FIGS. [Figure 4] FIG. 4 shows details of the correlator shown in FIG. [Diagram 5]FIG. 5 illustrates a time diagram showing the relationship between ticks (ie, clock pulse signals), integration period signals, and data in the primary and secondary buffers in one embodiment. [Figure 6] FIG. 6 shows a timing diagram showing the relationship of tick, read, process, and write operations in one embodiment. [Figure 7] FIG. 7 illustrates a time diagram showing the relationship of ticks, relax ticks (i.e., ticks that are generated based on and occur after a clock pulse), and read, process, and write operations in one embodiment. [Figure 8] FIG. 8 illustrates a GNSS receiver in which relax ticks are generated and utilized in one embodiment. [Figure 9] FIG. 9 shows details of the time scale generator shown in FIG. [Figure 10] FIG. 10 shows details of the channels shown in FIGS. [Figure 11] FIG. 11 illustrates a method for operating a navigation receiver in one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The speed of the processor in a global navigation satellite system receiver must be sufficient so that occurrences, such as the generation of a signal, can be detected by the processor and responded to accordingly. This detection and response is necessary in order to generate raw measurements. To correctly generate the raw measurements, control values ​​must be updated at the intermediate frequency and code frequency in accordance with the tick signal (i.e., clock pulse). Specifically, the control values ​​must be updated in accordance with events that occur at precisely known times. The integral of the code frequency and intermediate frequency over the time of use is used to generate the code and phase measurements. Any errors in the time of use of the new intermediate frequency and code frequency will accumulate errors in the raw measurements.

[0009] The control signals are programmable and are generated by a tracking algorithm executed by the CPU. The control signals are written to one or more channels at specific times. The control signals perform actions (e.g. update / copy) that are initiated based on a known tick signal (e.g. an occurring clock pulse). This restriction on actions initiated based on a known tick signal applies to the strict real-time requirements of the program components of the GNSS receiver. Furthermore, the generation of control signals that last longer than one tick in terms of duration (e.g. the time between two adjacent ticks in time) can be interrupted by various tasks such as component reading from the channel correlator and data exchange tasks in the communication subsystem. The duration of the actions performed during a tick cannot be longer than one code duration (1 / 1023000=977ms) minus the time required to read data from the channel to the CPU memory.

[0010] Relax ticks can be added to allow more time for certain actions to occur. Relax ticks are ticks that are generated to occur after the ticks that would normally occur based on the clock pulse. For example, ticks output from a clock at a rate of twice per second would provide a tick frequency of 2 Hz. Relax ticks are generated so that ticks generated by the clock occur and the relax tick occurs later (for example, later than the next clock tick after the original tick generated by the clock), providing a tick frequency of 1 Hz. Adding relax ticks, which are delayed in frequency relative to the start of generation of the control signal by a period beyond the time at which the ticks generated from the clock pulse occur, and by a multiple of the clock pulse, can significantly reduce the execution time requirements of the signal tracking algorithm and eliminate the extra overhead required to provide guaranteed new values. Relax ticks are generated less frequently than ticks.

[0011] FIG. 1 shows a global navigation satellite system receiver having an antenna 100 that receives signals input to RF paths 101(1...N). Each of the RF paths 101(1...N) transmits a signal to a respective analog-to-digital converter (ADC) 102(1...N). The output of the ADC 102(1...N) is input to a channel 103(1,2,...N). It should be noted that the ADC 102(1...N) and the channel 103(1,2,...N) may be collectively referred to herein as the ADC 102 and the channel 103. Other similarly numbered components may be collectively referred to in the same manner. The channel 103(1,2,...N) is also connected to a time scale generator 104. The channel 103(1,2,...N) receives a tick signal S107 from the time scale generator 104. The tick signal is also sent from the timescale generator 104 to a central processing unit (CPU) 105 (also referred to as a "processor"), which can send information to and receive information from a user 109 via a communication module 106.

[0012] In one embodiment, CPU 105 controls channel 103 and timescale generator 104. In one embodiment, the receiver shown in Figure 1 operates as follows: Before receiver operation, CPU 105 adjusts timescale generator 104. Timescale generator 104 generates tick signals S107 (ticks) at equal time intervals.

[0013] Satellite signals are received by antenna 100, pass through RF path 101 and ADC 102, and are input to channel 103. Channel 103 processes the signal from ADC 102. Timescale generator 104 generates clock cycles (ticks). CPU 105 controls channel 103 and timescale generator 104. CPU 105 processes information received from channel 103 when tick signal S107 is available and information received via communication module 106, and transmits generated data to user 109 via communication module 106. In one embodiment, ADC 102, channel 103, and timescale generator 104 run on clock CLKnav.

[0014] Figure 2 shows details of the timescale generator 104 shown in Figure 1. In one embodiment, the timescale generator 104 comprises a clock counter 300 in communication with the CPU 105 and a threshold unit 301. In one embodiment, the timescale generator 104 operates as follows.

[0015] Before the operation of the time scale generator 104 starts, the CPU 105 assigns a threshold value to the threshold unit 301. Before the operation starts, the value of the clock counter 300 is 0. The value of the clock counter 300 increases by 1 with each pulse of the clock CLKnav. The value of the clock counter 300 is sent to the input of the threshold unit 301. If the value is equal to the threshold value assigned to the threshold unit 301 by the CPU 105, the output of the threshold unit 301 is 1. If the value of the clock counter 300 is not equal to the threshold value, the output of the threshold unit 301 is 0. The output signal from the threshold unit 301 is input as an interrupt to the CPU 105, the clock counter 300, and the channel 103. If the output signal of the threshold unit 301 is equal to 1, the clock counter 300 is reset (e.g. set to 0) at the next clock. The tick signal S107 is the output signal of the threshold unit of the clock counter 301.

[0016] Figure 3 shows details of the channel 103 shown in Figures 1 and 2. In one embodiment, the channel 103 includes a code rate numerically controlled oscillator (NCO) referred to as CRNCO 200, a code generator 201, an intermediate frequency NCO (IFNCO) 202, an integration period counter 203, a commutator 204, a correlator 205, an integration period signal S 206, an update frequency CRNCO 207, an update shift phase CRNCO 208, an update lock phase CRNCO 209, an update frequency IFNCO 210, an update shift phase IFNCO 211, an update lock phase IFNCO 212, an update The new frequency CRNCO signal S207, the updated shift phase CRNCO signal S208, the updated lock phase CRNCO signal S209, the updated frequency IFNCO signal S210, the updated shift phase IFNCO signal S211, the updated lock phase IFNCO signal S212, the strobe generator 213, the code frequency signal S215, the code phase signal S216, the COS cosine signal S217, the SIN sine signal S218, the code (PRN code signal) S219, and the strobe signal S220. The updated CRNCOs 207, 208, and 209 and the updated IFNCOs 210, 211, and 212 are also called units.

[0017] In one embodiment, the CPU 105 controls and / or receives data from the CRNCO 200, the code generator 201, the IFNCO 202, the integration period counter 203, the commutator 204, the correlator 205, the update frequency CRNCO 207, the update shift phase CRNCO 208, the update lock phase CRNCO 209, the update frequency IFNCO 210, the update shift phase IFNCO 211, the update lock phase IFNCO 212, and the strobe generator 213.

[0018] In one embodiment, signals are sent between the components as follows: An updated frequency CRNCO signal S207 is output from the updated frequency CRNCO 207 and sent to the input of the CRNCO 200. An updated shifted phase CRNCO signal S208 is output from the updated shifted phase CRNCO 208 and sent to the input of the CRNCO 200. An updated locked phase CRNCO signal S209 is output from the updated locked phase CRNCO 209 and sent to the input of the CRNCO 200.

[0019] An update frequency IFNCO signal S210 is output from the update frequency IFNCO 210 and sent to an input of the IFNCO 202. An update shifted phase signal IFNCOS 211 is output from the update shifted phase IFNCO 211 and sent to an input of the IFNCO 202. An update locked phase IFNCO signal S212 is output from the update locked phase IFNCO 212 and sent to an input of the IFNCO 202. The signals S207, S208, S209, S210, S211, S212 are also referred to as update signals.

[0020] In one embodiment, CPU 105 controls CRNCO 200. CPU 105 assigns code frequency, interface registers and a value to CRNCO 200 and updates / copies data from the interface register to a buffer (running at clock frequency CLKnav) based on signal S207. CPU 105 inputs the code phase shift to the interface register, and the code phase shift from the interface register is added to the current code phase based on signal S208, and the code phase shift in the interface register is set equal to 0. CPU 104 copies the current state of the code phase in a code lock phase register in CRNCO 200, and this value is updated based on signal S209.

[0021] In one embodiment, CPU 105 controls IFNCO 202 as follows: CPU 105 inputs the intermediate frequency into the interface register, assigns a value to IFNCO 202, and updates / copies data from the interface register to a buffer register (running at clock frequency CLKnav) based on signal S210. CPU 105 inputs the intermediate frequency phase shift into the interface register, and based on signal S211, the intermediate frequency phase shift from the interface register is added to the current intermediate frequency phase, and the intermediate frequency phase shift in the interface register is set equal to 0. CPU 105 copies the current intermediate frequency phase in IFNCO 202 to the intermediate frequency lock phase, and this value is updated based on signal S212.

[0022] When the CPU 105 writes a new value in the code frequency interface register in the CRNCO 200, an instant signal is generated in unit 207. When the CPU 105 writes a new value in the code phase shift interface register in the CRNCO 200, an instant signal is generated in unit 208. When the CPU 105 writes a new value in the code frequency lock phase register in the CRNCO 200, an instant signal is generated in unit 209. When the CPU 105 writes a new value in the intermediate frequency interface register in the IFNCO 202, an instant signal is generated in unit 210. When the CPU 105 writes a new value in the intermediate frequency phase shift interface register in the IFNCO 202, an instant signal is generated in unit 211. When the CPU 105 writes a new value in the intermediate frequency lock phase interface register in the IFNCO 202, an instant signal is generated in unit 212. The instant signals are one clock cycle CLKnav.

[0023] In one embodiment, the CPU 105 controls units 207, 208, 209, 210, 211, 212, at whose outputs the update signals are generated. Each unit 207, 208, 209, 210, 211, 212 has its own / independent control.

[0024] In one embodiment, the tick signal S107 and the integration period signal S206 are provided to the outputs of each of the units 207, 208, 209, 210, 211, and 212. A single clock / one clock signal can cause the units 207, 208, 209, 210, 211, and 212 to output update signals.

[0025] In one embodiment, the instant signal is generated and output from one of the CPU control units 207, 208, 209, 210, 211, 212 after a value is written to a corresponding one of the registers in the control units described below. The integration period signal S206 is an end of integration period signal and is generated by the integration period counter 203. The tick signal S107 is generated by the time scale generator 104. Table 1 shows the output signals of the units 207, 208, 209, 210, 211, 212 based on the signal from the CPU 105.

[0026] [Table 1]

[0027] Based on the tick signal S107, the current state of the integration period counter 203 is copied into the integration period counter lock state register.

[0028] The lock status of the integration period counter, the intermediate frequency lock phase in the IFNCO 202, and the lock phase register in the CRNCO 200 are used for the pseudo-range calculation and operate based on the tick signal S107. The IFNCO 202 generates and outputs two signals, a cosine signal and a sine signal.

[0029] In one embodiment, the initial setup of the channel shown in Figure 3 is as follows: Before starting operation of the channel of Figure 3, CPU 105 adjusts the code generator 201, commutator 204, units 209, 212, strobe generator 213, and also performs the following operations: CPU 105 sets the code frequency in CRNCO 200. If necessary, CPU 105 assigns a code phase shift in CRNCO 200. CPU 105 selects units 207, 208 as update and tick signals S107. CPU 105 sets the intermediate frequency in IFNCO 202. If necessary, CPU 105 sets the intermediate frequency phase shift in IFNCO 202. CPU 105 selects the outputs of units 210 and 211 as update and tick signals S107. CPU 105 sets the duration of the integration period S206 in integration period counter 203.

[0030] In one embodiment, the operation of the channel shown in Figure 3 is as follows: The tick signal S107 output from the time scale generator 104 is input to the update frequency CRNCO 207, the update shift phase CRNCO 208, the update lock phase CRNCO 209, the update frequency IFNCO 210, the update shift phase IFNCO 211, the update lock phase IFNCO 212, the integration period counter 203, the correlator 205, and the CPU 105. The CRNCO 200 generates a code frequency based on the tick signal S107. The code frequency S215 is output from the CRNCO 200 and input to the code generator 201, at which frequency a code signal S219 is generated. The code frequency output from the CRNCO 200 is input to the integration period counter 203, and the integration period signal S206 counts out the required duration at the received code frequency. The code signal S219 from the code generator 201 is input to the correlator 205 and the strobe generator 213. The code phase signal S216 from the output of the CRNCO 200 is input to a strobe generator 213. The strobe generator 213 generates a strobe signal S220 which is input to the correlator 205.

[0031] In one embodiment, the integration period signal S206 output from the integration period counter 203 is input to the correlator 205, the frequency update CRNCO 207, the shift phase update CRNCO 208, the lock phase update CRNCO 209, the frequency update IFNCO 210, the shift phase update IFNCO 211, the lock phase update IFNCO 212, and the CPU 105.

[0032] In one embodiment, the IFNCO 202 generates an intermediate frequency based on the tick signal S 107. The intermediate frequency phase signals output from the IFNCO 202 (signals COS S217 and SIN S218) are input to the correlator 205.

[0033] In one embodiment, the digitized signal is output from the ADC 102 and input to a commutator 204. One of the selected signals output from the commutator 204 is input to a correlator 205.

[0034] Figure 4 shows details of the correlator 205 shown in Figure 3. In one embodiment, the correlator 205 includes multiplication units 400, 401, 402, 403, 404, 405, an accumulator I (Acc I) 406, an accumulator Q (Acc Q) 407, an accumulator dl (Acc dl) 408, an accumulator dQ (Acc dQ) 409, a primary buffer I 410, a primary buffer Q 411, a primary buffer dl 412, a primary buffer dQ 413, a secondary buffer I 414, a secondary buffer Q 415, a secondary buffer dl 416, and a secondary buffer dQ 417.

[0035] In the correlator 205, the intermediate frequency phase signal (signals COS S217 and SIN S218) from the IFNCO 202 is multiplied by the digital signal output from the commutator 204 and the code signal S219 output from the code generator 201. In the correlator 205, the intermediate frequency phase signal (signals COS S217 and SIN S218) from the IFNCO 202 is multiplied by the digital signal output from the commutator 204 and the strobe signal S220 output from the strobe generator 213.

[0036] The multiplication results accumulate and are stored for a period based on the integration period signal S206. The stored values ​​are copied to primary buffers 410, 411, 412, 413 in the correlator 205 and set to zero according to the integration period signal S206. The correlator 205 generates the components I, Q, dI, dQ that are read by the CPU 105. Values ​​are copied from the primary buffers 410 / 411 / 412 / 413 to secondary buffers 414, 415, 416, 417 based on the tick signal S107.

[0037] In one embodiment, the CPU 105 performs the following changes / assignments / reads as required during operation: change the code frequency in the CRNCO 200, assign a code phase shift in the CRNCO 200, change the control of units 207, 208, 209, 210, 211, 212, change the intermediate frequency in the IFNCO 202, assign an intermediate frequency phase shift in the IFNCO 202, read the code frequency lock phase register in the CRNCO 200, read the intermediate frequency lock phase register in the IFNCO 202, read the lock status register of the integration period counter 203, read the primary buffers 410, 411, 412, 413 in the correlator 205, and read the secondary buffers 414, 415, 416, 417 in the correlator 205.

[0038] In one embodiment, the operation of the strobe generator 213 is as described in U.S. Patent No. 7,764,226 with respect to the universal strobe generator 500 shown in Figure 2. U.S. Patent No. 7,764,226 is incorporated herein by reference.

[0039] In one embodiment, the correlator shown in FIG. 4 operates as follows. The digital signal output from commutator 204 and the cosine signal S217 output from IFNCO 202 are input to a multiplication unit 400 where the signals are multiplied. The digital signal output from the commutator 204 and the sine signal S218 output from the IFNCO 202 are input to a multiplication unit 401 where the signals are multiplied. The result of the multiplication by unit 400 and the code signal S219 from the code generator 201 are input to a multiplication unit 402 where the signals are multiplied. The result of the multiplication by unit 401 and the code signal S219 from the code generator 201 are input to a multiplication unit 403 where the signals are multiplied. The result of the multiplication by unit 400 and the strobe signal S220 from strobe generator 213 are input to multiplication unit 404 where the signals are multiplied. The result of the multiplication by unit 401 and the strobe signal S220 from strobe generator 213 are input to multiplication unit 405 where the signals are multiplied. The integration period signal S206 output from the integration period counter 203 is sent to the inputs of units 406, 407, 408, 409, 410, 411, 412, and 413. The result of the multiplication by unit 402 is input to accumulator I406 where it is stored for the duration of integration period signal S206. The result of the multiplication by unit 403 is input to accumulator Q407 and stored while integration period signal S206 is active. The result of the multiplication by unit 404 is input to an accumulator dI 408 and stored while the integration period signal S206 is active. The result of the multiplication by unit 405 is input to accumulator dQ 409 and stored while integration period signal S206 is active.

[0040] In one embodiment, based on the integration period signal S206, the stored value from accumulator I406 is copied to primary buffer 1410, the value stored in accumulator I406 is set to a value of zero, the value stored in accumulator I407 is copied to primary buffer Q411, the value stored in accumulator I407 is set to a value of zero, the value stored in accumulator I408 is copied to primary buffer dl412, the value stored in accumulator I408 is set to a value of zero, and the value stored in accumulator I409 is copied to primary buffer dQ413, and the value stored in accumulator I409 becomes a value of zero.

[0041] In one embodiment, based on the tick signal S107 and the integration period signal S206, values ​​in primary buffer I410 are copied to secondary buffer I414, values ​​from primary buffer Q411 are copied to secondary buffer Q415, values ​​in primary buffer dI412 are copied to secondary buffer dI416, and values ​​in primary buffer dQ413 are copied to secondary buffer dQ417.

[0042] In one embodiment, CPU 105 reads values ​​from primary buffer I 410, primary buffer Q 411, primary buffer dI 412, primary buffer dQ 413, secondary buffer I 414, secondary buffer Q 415, secondary buffer dI 416, and secondary buffer dQ 417. The period of tick signal S107 is selected to be a value less than the smallest integration period signal S206 used. Storing values ​​in secondary buffers 414, 415, 416, 417 for the period of an active tick signal S107 ensures that these values ​​are read even if the values ​​in primary buffers 410, 411, 412, 413 are changed (these values ​​are updated according to integration period signal S206).

[0043] 5 shows a timing diagram showing the relationship between the tick signal S107, the integration period S206, and the data in the primary and secondary buffers. If the values ​​change in the channel 103 in the primary buffers 410, 411, 412, 413 during the tick signal S107, new components are written in the correlators 205, I, Q, dI, dQ based on the integration period signal S206. Based on the tick signal S107, the values ​​from the primary buffers 410, 411, 412, 413 are copied to the secondary buffers 414, 415, 416, 417. The values ​​from the units 414, 415, 416, 417 are read once during the next period of the tick signal S107, and the values ​​read from the units 414, 415, 416, 417 are processed by the CPU 105.

[0044] FIG. 6 shows a timing diagram illustrating the relationship of tick, read, process, and write operations. In one embodiment, the update of the control values ​​for the intermediate frequency and the code frequency is based on the generation of the tick. Specifically, the accurate generation of the raw data must be based on events occurring at precise known times. The integral of the code frequency and the intermediate frequency over the time of use is used to form a replica in the correlator 205 of the channel 103, which is used to generate the code and phase measurements. Errors in the time application and / or use of the new values ​​of the intermediate frequency and the code frequency result in the accumulation of errors in the raw data.

[0045] In one embodiment, the control signals themselves are programmable and are generated by a tracking algorithm in the CPU 105. In one embodiment, the control signals are written in the interface registers of the channel 103 at specific times. They are written from the tick signal (e.g., updated and / or copied from the interface registers in the CRNCO 200 and IFNCO 202 to the buffer registers). This restriction is applicable to strict real-time requirements for the program components of the GNSS receiver. Furthermore, the generation of the control signals may last longer than one tick period and may be interrupted by various tasks such as reading from the channel 103, data exchange tasks, etc. The period for forming a tick event cannot be longer than the storage period of one code period (e.g., 1 / 1023000=977 ms).

[0046] In one embodiment, adding a relax tick event that is delayed by one or more ticks to the start of generation of the control signals at the code frequency and intermediate frequency can reduce the execution time requirements of the signal tracking algorithm and avoid unnecessary overhead to ensure the use of new control values ​​for IFNCO and CRNCO. Figure 7 shows a timing diagram illustrating the relationship of relax tick, read, process, and write operations.

[0047] FIG. 8 illustrates a receiver in which relax ticks are generated and utilized in one embodiment. The receiver illustrated in FIG. 8 has a configuration similar to that of the receiver illustrated in FIG. 1. However, some of the receiver configuration illustrated in FIG. 8 differs from the corresponding configuration of the receiver illustrated in FIG. 1. The different configurations / signals in FIG. 8 are identified by the term "modifications." These differences enable the receiver in FIG. 8 to generate and utilize relax ticks. The differences between the receiver illustrated in FIG. 8 and the receiver illustrated in FIG. 1 are as follows: Channel 103(1 … N) is the corrected channel 110 (1 … N). Time scale generator 104 is replaced by modified time scale generator 111. Relax tick signal S108 is output from modified time scale generator 111. Relax tick signal S108 is output as an interrupt signal to modified channel 110 (1 … N) and input to the CPU 105.

[0048] Figure 9 shows details of the modified timescale generator 111 shown in Figure 8. In one embodiment, the modified timescale generator 111 includes a relax tick counter 302, a threshold relax tick counter 303, and an AND gate 304.

[0049] In one embodiment, the modified timescale generator 111 operates as follows: Before operation, the CPU 105 assigns a threshold in the threshold clock counter 301 and assigns a threshold in the relax tick counter 303. Also before operation, the clock counter 300 and the relax tick counter 302 are at a value of 0. The clock counter 300 increments by 1 every clock CLKnav.

[0050] The current value of clock counter 300 is input to unit 301. If the value of clock counter 300 is equal to a threshold value of unit 301 assigned by CPU 105, unit 301 outputs a value of 1, otherwise unit 301 outputs a value of 0. The output of unit 301 is input as an interrupt signal to channel 103, clock counter 300, relax tick counter 302, AND gate 304, and CPU 105. If the output value of unit 301 is a value of 1, clock counter 300 is reset at the next clock (i.e., clock counter 300 is set equal to a value of 0 at the next clock).

[0051] Tick ​​signal S107 is the output of threshold clock counter 301. When tick signal S107 is available, relax tick counter 302 increments a value of 1. The value of relax tick counter 302 is input to the input of unit 303. If the value in relax tick counter 302 is equal to a relax tick counter 303 threshold assigned by CPU 105, unit 303 outputs a value of 1, otherwise unit 303 outputs a value of 0. The output of unit 303 is input to AND gate 304. If the output signal of unit 303 and tick signal S107 are available, AND gate 304 outputs a value of 1, otherwise AND gate 304 outputs a value of 0. The output of unit 304 is input to modified channel 110, relax tick counter 302, and CPU 105 as an interrupt signal. If unit 304 outputs a value of 1, then unit 302 is reset at the next clock (ie, unit 302 is set equal to a value of 0).

[0052] The relax tick signal S108 is output from the AND gate 304. The CPU 105 can read the value of the unit 302. During operation of the modified time scale generator 111, the CPU 105 can change the threshold of the relax tick counter 303 if necessary.

[0053] Figure 10 shows details of the modified channel 110 shown in Figures 8 and 9. The modified channel 110 comprises the signals and configuration of channel 103 with the following differences: The update frequency CRNCO 207 is replaced by a modified update frequency CRNCO 2070 . The update phase-shift CRNCO 208 is replaced by a modified update phase-shift CRNCO 2080 . The update lock phase CRNCO 209 is replaced by a modified update lock phase CRNCO 2090 . The update frequency IFNCO 210 is replaced by a modified update frequency IFNCO 2100 . The update phase shift IFNCO 211 is replaced by a modified update phase shift IFNCO 2110 . The update lock phase IFNCO 212 is replaced by a modified update lock phase IFNCO 2120 . A modified CRNCO frequency update signal S2070 is output from the modified update frequency CRNCO 2070. A modified CRNCO phase shift update signal S2080 is output from the modified update phase shift CRNCO 2080. A modified CRNCO lock phase update signal S2090 is output from the modified update lock phase CRNCO2090. A modified IFNCO frequency update signal S2100 is output from the modified update frequency IFNCO 2100. A modified IFNCO phase shift update signal S2110 is output from the modified update phase shift IFNCO 2110. The modified IFNCO lock phase update signal S2120 is a modified output from the update lock phase IFNCO2120. The lock counter update signal S2140 is output from the update lock counter 2140.

[0054] In one embodiment, the CPU 105 controls the CRNCO 200 as follows: The CPU 105 sets the code frequency in an interface register and updates and / or copies the value in the CRNCO 200 from the interface register to a buffer (running with clock CLKnav) using signal S2070. The CPU 105 places the code phase shift in the interface register and copies the data from the interface register to a buffer register (running with clock CLKnav), where the code phase shift from the buffer register is added to the current code phase based on signal S2080, and the code phase shift in the buffer register is set equal to 0. The current state of the code phase in the CRNCO 200 is copied to a register of locked code phase, and the value is updated using signal S2090.

[0055] In one embodiment, CPU 105 controls IFNCO 202 as follows: CPU 105 sets the intermediate frequency in an interface register, and the value of IFNCO 202 is updated and / or copied from the interface register to a buffer (running with clock CLKnav) by signal S2100. CPU 105 sets the intermediate frequency phase shift in an interface register, and copies the data from the interface register to a buffer register (running with clock CLKnav), and the intermediate frequency phase shift from the buffer register is added to the current intermediate frequency phase by signal S2110, and the intermediate frequency phase shift in the buffer register is set to a value of 0. CPU 105 copies the current state of the intermediate frequency phase of IFNCO 202 in an intermediate frequency lock phase register, and the value is updated by signal S2120.

[0056] When the CPU 105 writes a new value in the code frequency interface register in the CRNCO 200, an immediate signal is generated in unit 2070 which runs on the clock CLKnav. When the CPU 105 writes a new value in the code phase shift interface register in the CRNCO 200, an immediate (phase shift) signal is generated in unit 2080 which runs on the clock CLKnav. When the CPU 105 writes a new value in the lock-phase interface register in the CRNCO 200, an immediate (lock-phase) signal is generated in unit 2090 which runs on the clock CLKnav. When the CPU 105 writes a new value in the intermediate frequency interface register in the IFNCO 202, an immediate signal is generated in unit 2100 which runs on the clock CLKnav. When the CPU 105 writes a new value in the intermediate frequency (phase shift) interface register in the IFNCO 202, an immediate signal is generated in unit 2110 running on the clock CLKnav. When the CPU 105 writes a new value in the interface register of the intermediate frequency lock phase in the IFNCO 202 , an immediate signal is generated in unit 2120 .

[0057] In one embodiment, the CPU 105 controls units 2070, 2080, 2090, 2100, 2110, and 2120, from which the update signals are output. Each unit 2070, 2080, 2090, 2100, 2110, and 2120 has its own independent control.

[0058] The tick signal S107, the relax tick signal S108 and the integration period signal S206 are provided at the output of each unit 2070, 2080, 2090, 2100, 2110 and 2120. The next one clock signal can be the update signal at the output of the units 2070, 2080, 2090, 2100, 2110 and 2120. The immediate signal is the signal generated after writing in the register. The integration period signal S206 is the signal identifying the end of the integration period and is generated by the integration period counter 203. The tick signal S107 is the signal generated by the time scale generator 111. The relax tick signal S108 is generated by the time scale generator 111. The control of the units 2070, 2080, 2090, 2100, 2110 and 2120 and the signals output by these units based on the control signals are shown in Table 2. [Table 2]

[0059] The CPU 105 controls the unit 2140 to output the update signal. The unit 2140 also outputs a tick signal S107 and a relax tick signal S108. The next one clock signal can be the update signal output from the unit 2140. The tick signal S107 is a signal generated by the modified time scale generator 111. The relax tick signal S108 is a signal generated by the modified time scale generator 111.

[0060] The current state of the integration period counter 203 is copied into the lock integration period register by the lock counter update signal S2140. The controls of unit 2140 and the signals output by unit 2140 are shown in Table 3. [Table 3]

[0061] In one embodiment, the IFNCO 202 outputs two signals: COS S217 and SIN S218.

[0062] In one embodiment, the initial setup of the receiver shown in Figure 10 is as follows: Before the receiver starts operation, CPU 105 performs the following operations: CPU 105 sets the code frequency in CRNCO 200. If necessary, CPU 105 also sets the code phase shift in CRNCO 200. CPU 105 selects tick signal S107 as the update signal for units 2070 and 2080. CPU 105 sets the intermediate frequency in IFNCO 202. If necessary, CPU 105 also sets the intermediate frequency phase shift in IFNCO 202. CPU 105 selects tick signal S107 as the update signal for units 2100 and 2110. CPU 105 adjusts code generator 201 and sets integration period signal S206 in integration period counter 203. CPU 105 adjusts commutator 204, units 2090, 2120, 2140 and strobe generator 213.

[0063] 10 operates as follows: The tick signal S107 output from the corrected time scale generator 111 is input to a corrected CRNCO frequency update 2070, a corrected CRNCO phase shift update 2080, a corrected CRNCO lock phase update 2090, a corrected IFNCO frequency update 2100, a corrected IFNCO phase shift update 2110, a corrected IFNCO lock phase update 2120, a lock counter update unit 2140, and a correlator 205.

[0064] In one embodiment, the relax tick signal S108 from the output of the modified time scale generator 111 is input to a modified CRNCO frequency update 2070, a modified CRNCO phase shift update 2080, a modified CRNCO lock phase update 2090, a modified IFNCO frequency update 2100, a modified IFNCO phase shift update 2110, a modified IFNCO lock phase update 2120, and a lock counter update unit 2140.

[0065] The CRNCO 200 generates a code frequency based on the tick signal S 107. A code frequency signal S215 is output from the CRNCO 200 and input to the code generator 201, which generates a code signal S219 at this frequency. The code frequency output from CRNCO 200 is input to integration period counter 203, and the allotted duration of integration period signal S206 is counted out at this frequency. The code signal S219 from the code generator 201 is input to the correlator 205 and the strobe generator 213. The code phase signal S216 output from the CRNCO 200 is input to the strobe generator 213. The strobe generator 213 generates a strobe signal S220 which is input to the correlator 205. The integration period signal S206 from the output of the integration period counter 203 is input to the correlator 205, the corrected CRNCO frequency update 2070, the corrected CRNCO phase shift update 2080, the corrected CRNCO lock phase update 2090, the corrected IFNCO frequency update 2100, the corrected IFNCO phase shift update 2110, the corrected IFNCO lock phase update 2120, the lock counter update unit 2140, and the CPU 105.

[0066] The IFNCO 202 generates an intermediate frequency according to the tick signal S107. The intermediate frequency phases (e.g., COS S217 and SIN S218 signals) are output from the unit IFNCO 202 and input to the correlator 205. The digital signal output from the ADC 102 is input to the commutator 204. One of the selected digital signals output from the commutator 204 is input to the correlator 205.

[0067] In the correlator 205 , the intermediate frequency phase from the IFNCO 202 is multiplied by the digital signal output from the commutator 204 and the code signal S 219 output from the code generator 201 .

[0068] In the correlator 205 , the intermediate frequency phase from the unit IFNCO 202 is multiplied by the digital signal output from the commutator 204 and by the strobe signal S 220 output from the strobe generator 213 .

[0069] The multiplication results are accumulated and stored for the duration of the integration period signal S206. Based on the integration period signal S206, the stored values ​​are copied and zeroed into primary buffers 410, 411, 412, 413 of the correlator 205. The correlator 205 generates the components I, Q, dI, dQ that are read by the CPU 105. From the primary buffers 410, 411, 412, 413, the values ​​are copied to secondary buffers 414, 415, 416, 417 based on the tick signal S107.

[0070] After initiating the modified channel 110, the CPU 105 selects the relax tick signal S108 as the update signal for the units 2070, 2080, 2100, and 2110. If necessary, the CPU 105 performs the following operations: change the code frequency in the CRNCO 200, set the code phase shift in the CRNCO 200, change the controls in units 2070, 2080, 2090, 2100, 2110, 2120, 2140, change the intermediate frequency in the IFNCO 202, set the intermediate frequency phase shift in the IFNCO 202, read the code frequency lock phase register in the CRNCO 200, read the intermediate frequency lock phase register in the IFNCO 202, read the lock status register in the integration period counter 203, read the primary buffers 410, 411, 412, 413 in the correlator 205, and read the secondary buffers 414, 415, 416, 417 in the correlator 205. In one embodiment, all update signals run on the clock CLKnav.

[0071] 11 shows a flow chart of a method 1100 of operating a navigation receiver in one embodiment. The steps of the method are performed by the components of the navigation receiver as described above. The method begins at step 1102 where a GNSS signal is received. In one embodiment, the signal is received in an RF path from an antenna. In one embodiment, the GNSS signal is transmitted from the RF path at an intermediate frequency. In step 1104, the GNSS signal is sampled at the frequency CLKnav. In one embodiment, the GNSS signal is sampled by an ADC that receives the GNSS signal from the RF path. The tick signal and the relax tick signal are generated at step 1106. In one embodiment, the tick signal and the relax tick signal are generated by a time scale generator. A pulse is generated at an intermediate frequency and an intermediate frequency phase in step 1108. In one embodiment, the pulse is generated by an IFNCO. A code rate NCO signal is generated at step 1110. In one embodiment, the code rate NCO signal is generated by a code rate NCO and has a frequency and a phase. A code signal is generated based on the code rate NCO frequency at step 1112. In one embodiment, the code signal is generated by a code generator. A strobe signal is generated based on the code rate NCO phase and the shape of the code signal in step 1114. In one embodiment, the strobe signal is generated by a strobe generator. An integration period signal is generated based on the code rate NCO phase in step 1116. In one embodiment, the integration period signal is generated by an integration period counter. In step 1118, the signals are multiplied to generate a first product. In one embodiment, the signal to be multiplied comprises a signal output from a commutator that receives the GNSS signal from the ADC. The signal to be multiplied also includes a signal output from a code generator and an intermediate frequency phase from the IFNCO. In one embodiment, the first product is stored after it is generated. In step 1120, the signals are multiplied to generate a second product. In one embodiment, the signals multiplied comprise the signal output from the commutator, the strobe signal, and the intermediate frequency phase from the intermediate frequency NCO. In one embodiment, the second product is stored after it is generated. In step 1122, the navigation receiver is controlled based on the tick signal, the relax tick signal, the first product, and the second product.

[0072] The foregoing Detailed Description is to be understood in all respects as illustrative and not restrictive, and the scope of the inventive concepts disclosed herein is to be determined to the full extent permitted by the patent laws. It is to be understood that the embodiments shown and described herein are merely illustrative of the principles of the inventive concepts, and that various modifications may be made by those skilled in the art without departing from the scope and spirit of the inventive concepts. Those skilled in the art could implement various other feature combinations without departing from the scope and spirit of the inventive concepts.

Claims

1. 1. A navigation receiver comprising: an RF path configured to receive Global Navigation Satellite System (GNSS) signals from an antenna and transmit the GNSS signals at an intermediate frequency; an analog-to-digital converter (ADC) configured to receive the GNSS signal at the intermediate frequency from the RF path and sample the GNSS signal at a frequency CLKnav; a time scale generator configured to generate a tick signal and a relax tick signal; a channel configured to receive the GNSS signal from the ADC; a CPU for controlling the navigation receiver to read data from the correlator; Preparation, The channel comprises: an intermediate frequency numerically controlled oscillator (NCO) configured to generate pulses at an intermediate frequency and an intermediate frequency phase; a code rate NCO (CRNCO) configured to generate a code rate NCO signal having a code rate NCO phase and a code rate NCO frequency; a code generator configured to generate a code signal based on the code rate NCO frequency; a strobe generator configured to generate a strobe signal based on the code rate NCO phase and a shape of the code signal; an integration period counter configured to generate an integration period signal based on the code rate NCO frequency; a commutator configured to receive the GNSS signal from the ADC; the correlator configured to multiply the signal output from the commutator, the signal output from the code generator, and the intermediate frequency phase from the intermediate frequency NCO to generate a first product and configured to store the first product during an integration period; and the correlator configured to multiply the signal output from the commutator, the strobe signal, and the intermediate frequency phase from the intermediate frequency NCO to generate a second product and configured to store the second product during the integration period. Navigation receiver.

2. the CRNCO is further configured to generate the code rate NCO frequency based on one of an instantaneous signal output from an update CRNCO, the integration period signal, the relax tick signal, and the tick signal.

2. The navigation receiver according to claim 1.

3. the CRNCO is further configured to generate a code rate NCO phase shift based on one of an instantaneous signal output from an update CRNCO, the integration period signal, the relax tick signal, and the tick signal.

2. The navigation receiver according to claim 1.

4. an update lock phase CRNCO in communication with the CRNCO; the update lock phase CRNCO is configured to generate a CRNCO lock phase update signal based on one of an instantaneous signal output from an update CRNCO, the integration period signal, the relax tick signal, and the tick signal.

2. The navigation receiver according to claim 1.

5. an intermediate frequency NCO frequency update signal is selected from one of an instantaneous signal output from an update IFNCO, the integration period signal, the relax tick signal, and the tick signal; 2. The navigation receiver according to claim 1.

6. an intermediate frequency NCO phase shift update signal is selected from one of the tick signal, the relax tick signal, the integration period signal, and an intermediate signal update IFNCO; 2. The navigation receiver according to claim 1.

7. an update frequency IFNCO configured to generate an intermediate frequency NCO frequency update signal that causes a current intermediate frequency phase to be locked in the intermediate frequency NCO; the intermediate frequency NCO frequency update signal is based on one of an instantaneous signal output from an update IFNCO, the integration period signal, the relax tick signal, and the tick signal; 2. The navigation receiver according to claim 1.

8. the CPU is configured to copy a code frequency signal to a buffer register of the code rate NCO based on an update signal; 2. The navigation receiver according to claim 1.

9. The CPU is configured to copy an intermediate frequency control signal to an interface register of a buffer register in the intermediate frequency NCO based on an update signal.

2. The navigation receiver according to claim 1.

10. the code rate NCO further configured to phase shift a code rate NCO code phase based on the update signal.

2. The navigation receiver according to claim 1.

11. the intermediate frequency NCO is further configured to phase shift an intermediate frequency in the intermediate frequency NCO based on an update signal.

2. The navigation receiver according to claim 1.

12. the CPU is configured to store a value of a primary buffer in the correlator over an integration period; 2. The navigation receiver according to claim 1.

13. the CPU is configured to copy data from a primary buffer based on the tick signal and store the data from the primary buffer in a secondary buffer.

2. The navigation receiver according to claim 1.

14. the period of the relax tick signal is a multiple of the period of the tick signal; 2. The navigation receiver according to claim 1.

15. 1. A method of operating a navigation receiver, comprising: receiving a GNSS signal; Sampling the GNSS signal at a frequency CLKnav; generating a tick signal and a relax tick signal; generating pulses at an intermediate frequency and an intermediate frequency phase; generating a code rate NCO signal having a code rate NCO phase and a code rate NCO frequency; generating a code signal based on the code rate NCO frequency; generating a strobe signal based on the code rate NCO phase and a shape of the code signal; generating an integration period signal based on the code rate NCO frequency; multiplying a signal output from a commutator receiving the sampled GNSS signal, the code signal, and the intermediate frequency phase to generate a first product that is stored during a time period identified by the integration period signal; multiplying a signal output from a commutator receiving the sampled GNSS signal, the strobe signal, and the intermediate frequency phase to generate a second product that is stored during a period identified by the integration period signal; and controlling the navigation receiver based on the tick signal, the relax tick signal, the first product, and the second product. How to operate a navigation receiver.

16. generating the code rate NCO frequency by a code rate NCO based on one of an instantaneous signal output from one of an update code rate NCO or an update IF NCO, the integration period signal, the relax tick signal, and the tick signal; The method of claim 15.

17. generating a code rate NCO phase shift by a code rate NCO based on one of an instantaneous signal output from one of an update code rate NCO or an update IF NCO, the integration period signal, the relax tick signal, and the tick signal; The method of claim 15.

18. 1. A navigation receiver comprising: means for receiving GNSS signals; means for sampling the GNSS signals at a frequency CLKnav; means for generating a tick signal and a relax tick signal; means for generating pulses at an intermediate frequency and an intermediate frequency phase; means for generating a code rate NCO signal having a code rate NCO phase and a code rate NCO frequency; means for generating a code signal based on the code rate NCO frequency; means for generating a strobe signal based on the code rate NCO phase and the shape of the code signal; means for generating an integration period signal based on the code rate NCO frequency; means for multiplying a signal output from a commutator receiving the sampled GNSS signal, the code signal, and the intermediate frequency phase to generate a first product; means for storing said first product during a period identified by said integration period signal; means for multiplying a signal output from a commutator receiving the sampled GNSS signal, the strobe signal, and the intermediate frequency phase to generate a second product; means for storing said second product during a period identified by said integration period signal; and means for controlling a GNSS receiver based on the tick signal, the relax tick signal, the first product, and the second product. Navigation receiver.

19. means for generating the code rate NCO frequency based on one of an instantaneous signal output from an update CRNCO, the integration period signal, the relax tick signal, and the tick signal; 20. The navigation receiver of claim 18.

20. means for generating the code rate NCO phase based on one of an instantaneous signal output from an update CRNCO, the integration period signal, the relax tick signal, and the tick signal; 20. The navigation receiver of claim 18.

21. generating an intermediate frequency NCO frequency by an intermediate frequency NCO based on one of an instantaneous signal output from an update IFNCO, the integration period signal, the relax tick signal, and the tick signal; The method of claim 15.

22. generating an intermediate frequency NCO phase shift by an intermediate frequency NCO based on one of an instantaneous signal output from an update IFNCO, the integration period signal, the relax tick signal, and the tick signal; The method of claim 15.

23. means for generating an intermediate frequency NCO frequency based on one of an instantaneous signal output from an update IFNCO, the integration period signal, the relax tick signal, and the tick signal; 20. The navigation receiver of claim 18.

24. means for generating an intermediate frequency NCO phase shift based on one of an instantaneous signal output from an update IFNCO, the integration period signal, the relax tick signal, and the tick signal; 20. The navigation receiver of claim 18.

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