Display device

Abstract

A display device is provided, comprising a first substrate including a display region and a non-display region, sub-pixels including light-emitting elements disposed on the first substrate, a first bank surrounding the sub-pixels, a color control structure disposed on the light-emitting elements in an area surrounded by the first bank, a color filter layer disposed on the color control structure, a second bank surrounding the display region, and a color dam disposed on the second bank, the color dam including a first color dam and a second color dam disposed on the second bank, the first color dam and the second color dam comprising different materials from each other.

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] Display devices are becoming increasingly important with the development of multimedia, and various types of display devices, such as organic light emitting displays (OLEDs) and liquid crystal displays (LCDs), are being used.

[0003] 2. Description of the Related Art A self-luminous display device includes a light-emitting element that emits light and is used to display an image. The self-luminous display device may be an organic light-emitting display device that uses an organic material as a light-emitting substance for the light-emitting element, or an inorganic light-emitting display device that uses an inorganic material as a light-emitting substance. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE DISCLOSURE An object of the present invention is to provide a display device including a structure capable of preventing overflow of organic substances made of different materials.

[0005] The object of the present invention is not limited to the above-mentioned objects, and other technical objects not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] According to one embodiment for solving the above problem, a display device includes a first substrate including a display region and a non-display region surrounding the display region, a plurality of sub-pixels including a plurality of light-emitting elements arranged on the first substrate in the display region, a first bank surrounding the sub-pixels in the display region, a plurality of color control structures arranged within a region surrounded by the first bank on the light-emitting elements of the plurality of sub-pixels, a plurality of color filter layers arranged on the color control structure, a second bank arranged apart from the first bank and surrounding the display region in the non-display region, and a plurality of color dams arranged on the second bank, the color dams including a first color dam arranged on a first portion of the second bank arranged on a first side of the display region, and a second color dam arranged on a second portion of the second bank arranged on a second side opposite the first side of the display region, the first color dam and the second color dam comprising different materials from each other.

[0007] The plurality of sub-pixels may include a first sub-pixel and a second sub-pixel spaced apart in one direction from the first sub-pixel, the plurality of color control structures may include a first wavelength conversion layer disposed in the first sub-pixel and a translucent layer disposed in the second sub-pixel, and the plurality of color filter layers may include a first color filter layer disposed on the first wavelength conversion layer and a second color filter layer disposed on the translucent layer.

[0008] The first color dam and the second color dam may be spaced apart in the one direction, the display area may be disposed between the first color dam and the second color dam, the first color dam may include the same material as the first color filter layer, and the second color dam may include the same material as the second color filter layer.

[0009] The subpixel further includes a third subpixel disposed between the first subpixel and the second subpixel, the plurality of color control structures further includes a second wavelength conversion layer disposed in the third subpixel, the plurality of color filter layers further includes a third color filter layer disposed on the second wavelength conversion layer, and the display device further includes a third color dam disposed on the first color dam, and the third color dam and the third color filter layer may include the same material.

[0010] The width of the third color dam may be greater than the width of the first color dam, and an outer surface of the first color dam may be covered by the third color dam.

[0011] The liquid crystal display may further include a plurality of color patterns overlapping the first bank, the color patterns including a first color pattern including a same material as the first color filter layer, a second color pattern including a same material as the second color filter layer, and a third color pattern including a same material as the third color filter layer, and the first color pattern may overlap the second color filter layer and the third color filter layer, respectively, in a plan view.

[0012] The first color dam and the second color dam may be spaced apart in the one direction, the display area may be disposed between the first color dam and the second color dam, the first color dam may include the same material as the second color filter layer, and the second color dam may include the same material as the first color filter layer.

[0013] The color control structures may further include a first capping layer disposed on the first bank and the second bank, a low refractive index layer disposed on the first capping layer, and a second capping layer disposed on the low refractive index layer, wherein the first color dam and the second color dam are disposed on the second capping layer.

[0014] The pixel may further include a planarization layer disposed between the second capping layer and the plurality of color filter layers, and the first color dam and the second color dam may each be disposed directly on the planarization layer above the second bank.

[0015] The liquid crystal display may further include a light blocking member disposed on the planarization layer and overlapping the first bank, and an overcoat layer disposed on the light blocking member and the plurality of color filter layers.

[0016] The first substrate may include a via layer disposed in the display region and the non-display region, a third bank disposed on the via layer and spaced apart from the second bank in the non-display region and surrounding the second bank, and a first valley portion disposed between the first bank and the second bank in the non-display region and penetrating the via layer.

[0017] The first color dam may be arranged in multiple numbers and disposed on portions of the second bank and the third bank that are disposed on the first side of the display area, and the second color dam may be arranged in multiple numbers and disposed on portions of the second bank and the third bank that are disposed on the second side of the display area.

[0018] The semiconductor device may further include a plurality of bank partitions disposed directly on the via layer between the first bank and the first valley.

[0019] The first bank and the second bank each may include a base layer and a top layer disposed on the base layer, the top layer having a greater width than the base layer.

[0020] The sub-pixel may include a plurality of electrodes spaced apart from one another and extending in one direction, and the plurality of light-emitting elements may be disposed on the plurality of electrodes spaced apart from one another.

[0021] The light emitting element may include a first electrode disposed on the first substrate, an organic layer disposed on the first electrode, and a second electrode disposed on the organic layer.

[0022] A display device according to one embodiment for solving the above problem includes a display area, a non-display area surrounding the display area, a plurality of sub-pixels disposed in the display area and arranged in a first direction and a second direction intersecting the first direction, the sub-pixels including a first electrode, a second electrode spaced apart from the first electrode, and a plurality of light-emitting elements having first and second ends disposed on the first and second electrodes, a first bank extending in the first and second directions in the display area and surrounding the plurality of sub-pixels, a plurality of color control structures disposed in the area surrounded by the first bank, a plurality of color filter layers disposed on the color control structure, the first bank includes a first valley portion spaced apart from the bank and arranged to surround the first bank, a second bank in the non-display region spaced apart from the first valley portion and arranged to surround the first valley portion, a third bank in the non-display region spaced apart from the second bank and arranged to surround the second bank, a plurality of first color dams extending in the first direction in a first dam region in the non-display region adjacent to a first side of the display region in the second direction, and a plurality of second color dams arranged to extend in the first direction in a second dam region in the non-display region adjacent to a second side of the display region in the second direction, the plurality of first color dams and the plurality of second color dams comprising different materials from each other.

[0023] The plurality of first color dams may overlap the second bank and the third bank disposed in the first dam region, and the plurality of second color dams may overlap the second bank and the third bank disposed in the second dam region.

[0024] The plurality of color filter layers may include a plurality of first color filter layers, a plurality of second color filter layers spaced apart from the plurality of first color filter layers in the second direction, and a plurality of third color filter layers spaced apart from the plurality of second color filter layers in the second direction, the first color filter layers, the second color filter layers, and the third color filter layers being adjacently arranged along the second direction, the plurality of first color dams may include the same material as the third color filter layers, and the plurality of second color dams may include the same material as the first color filter layers.

[0025] The display may further include a third color dam disposed on the second color dam, the third color dam including the same material as the second color filter layer.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effect of the Invention

[0027] The display device according to an embodiment may include a plurality of color dams disposed in a non-display area as a structure disposed in an outer periphery of a display area. The color dams may include the same material as any one of the color filter layers of the display device, and the color dams disposed in different outer peripheries may include different materials. The display device may include different color dams formed together in a process for forming different color filter layers, and the display device may include a minimum number of processes to prevent overflow of organic materials.

[0028] The effects of the embodiments are not limited to the above examples, and a wider variety of effects are included in the present specification. [Brief description of the drawings]

[0029] [Figure 1] 1 is a schematic plan view of a display device according to an embodiment; [Diagram 2] FIG. 2 is a plan view illustrating one pixel of a display device according to an embodiment. [Diagram 3] 3 is a cross-sectional view taken along line N1-N1' in FIG. 2. [Figure 4] 3 is a cross-sectional view taken along line N2-N2' in FIG. 2. [Diagram 5] 1 is a schematic diagram of a light-emitting device according to one embodiment. [Figure 6] 1 is a cross-sectional view of a display device according to an embodiment. [Figure 7] 1 is a schematic diagram showing banks arranged in a display area and a non-display area of ​​a display device according to an embodiment; [Figure 8] 8 is a cross-sectional view taken along the line A1-A1' in FIG. 7. [Figure 9] 8 is a cross-sectional view taken along the line A2-A2' in FIG. 7. [Figure 10] 2 is a schematic diagram showing an arrangement of color filter layers and color dams in a display device according to an embodiment; [Figure 11] 4 is a schematic diagram illustrating an area where a mask process for forming a first color filter layer and a first color dam of a display device according to an embodiment is performed. [Figure 12] 4 is a schematic diagram illustrating an area where a mask process is performed for forming a second color filter layer of a display device according to an embodiment. [Figure 13] 4 is a schematic diagram illustrating an area where a mask process for forming a third color filter layer and a second color dam of a display device according to an embodiment is performed. [Figure 14] FIG. 11 is a cross-sectional view of a display device according to another embodiment. [Figure 15] 15 is a cross-sectional view showing an outer casing of the display device of FIG. 14. [Figure 16] 11 is a cross-sectional view illustrating an outer periphery of a display device according to another embodiment. [Figure 17] 11 is a schematic diagram showing an arrangement of color filter layers and color dams in a display device according to another embodiment. [Figure 18] 18 is a cross-sectional view showing an outer periphery of the display device of FIG. 17. [Figure 19] 18 is a cross-sectional view showing an outer periphery of the display device of FIG. 17. [Figure 20] FIG. 11 is a cross-sectional view of a display device according to another embodiment. [Figure 21] 21 is a cross-sectional view showing the outer periphery of the display device of FIG. 20. [Figure 22] 11 is a cross-sectional view illustrating an outer periphery of a display device according to another embodiment. [Figure 23] 11 is a cross-sectional view illustrating an outer periphery of a display device according to another embodiment. [Figure 24] FIG. 11 is a plan view illustrating a sub-pixel of a display device according to another embodiment. [Diagram 25] 25 is a cross-sectional view taken along line N3-N3' in FIG. 24. [Figure 26] 25 is a cross-sectional view taken along line N4-N4' in FIG. 24. [Figure 27] FIG. 11 is a plan view illustrating a sub-pixel of a display device according to another embodiment. [Figure 28] 28 is a cross-sectional view taken along line N5-N5' in FIG. 27. [Figure 29] 28 is a cross-sectional view taken along line N6-N6' in FIG. 27. [Diagram 30] 28 is a cross-sectional view taken along line N7-N7' in FIG. 27. [Diagram 31] FIG. 11 is a cross-sectional view of a display device according to another embodiment. [Diagram 32] 32 is a cross-sectional view showing the outer periphery of the display device of FIG. 31. [Diagram 33] 11 is a cross-sectional view illustrating an outer periphery of a display device according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] The advantages and features of the present invention, as well as the methods for achieving them, will become clear from the detailed description of the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be realized in various different forms. The present embodiments are provided merely to complete the disclosure of the present invention and to fully inform those skilled in the art of the invention of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0031] When an element or layer is referred to as "on" another element or layer, this includes the case where it is directly on top of or has other layers or elements intervening therebetween. Similarly, when it is referred to as "below," "left," or "right," this includes the case where it is directly adjacent to another element or has other layers or materials intervening therebetween. Like reference numbers refer to like elements throughout the specification.

[0032] Although the terms "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that the first component referred to below may be the second component within the technical concept of the present invention.

[0033] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0034] FIG. 1 is a schematic plan view of a display device according to an embodiment.

[0035] 1, a display device 10 displays moving images or still images. The display device 10 may refer to any electronic device that provides a display screen. For example, the display device 10 may include a television, a notebook computer, a monitor, a billboard, the Internet of Things, a mobile phone, a smartphone, a tablet PC (Personal Computer), an electronic watch, a smart watch, a watch phone, a head mounted display, a mobile communication terminal, an electronic organizer, an electronic book, a PMP (Portable Multimedia Player), a navigation system, a game console, a digital camera, a camcorder, and the like that provide a display screen.

[0036] The display device 10 includes a display panel that provides a display screen. Examples of the display panel include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, a field emission display panel, etc. In the following, an inorganic light emitting diode display panel is used as an example of the display panel, but the present invention is not limited thereto and may be applied to other display panels as long as the same technical concept is applicable.

[0037] The shape of the display device 10 may vary in various ways. For example, the display device 10 may have a rectangular shape with a long width, a rectangular shape with a long height, a square, a rectangle with rounded corners (apexes), other polygonal shapes, a circle, etc. For example, the shape of the display area DPA of the display device 10 may also be similar to the overall shape of the display device 10. FIG 1 illustrates a display device 10 having a rectangular shape with a long length in the second direction DR2.

[0038] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA is an area where a screen is displayed, and the non-display area NDA is an area where a screen is not displayed. The display area DPA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DPA may generally occupy the center of the display device 10.

[0039] The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a row and column direction. The shape of each pixel PX may be a rectangle or a square on a plane, but is not limited thereto, and may be a rhombus with each side tilted in one direction. The pixels PX may be arranged in a stripe or island shape. For example, each pixel PX may include one or more light-emitting elements that emit light in a specific wavelength band to display a specific color.

[0040] A non-display area NDA may be arranged around the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may have a rectangular shape, and the non-display area NDA may be arranged adjacent to the four sides of the display area DPA. The non-display area NDA may form a bezel of the display device 10. In each non-display area NDA, wiring or a circuit driver included in the display device 10 may be arranged, or an external device may be mounted.

[0041] Fig. 2 is a plan view showing one pixel of a display device according to an embodiment. Fig. 2 shows the planar arrangement of electrodes (RME; RME1, RME2) arranged in one pixel PX of a display device 10, bank patterns BP1, BP2 and a lower bank layer LBN, a plurality of light-emitting elements ED, and connecting electrodes (CNE; CNE1, CNE2).

[0042] Referring to FIG. 2, each pixel PX of the display device 10 may include a plurality of sub-pixels SPXn. For example, one pixel PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 may emit light of a first color, the second sub-pixel SPX2 may emit light of a second color, and the third sub-pixel SPX3 may emit light of a third color. For example, the first color may be blue, the second color may be green, and the third color may be red. However, this is not limited thereto, and each sub-pixel SPXn may emit light of the same color. In one embodiment, each sub-pixel SPXn may emit blue light. Although the drawing illustrates an example in which one pixel PX includes three sub-pixels SPXn, this is not limited thereto, and the pixel PX may include a greater number of sub-pixels SPXn.

[0043] Each sub-pixel SPXn of the display device 10 may include a light-emitting area EMA and a non-light-emitting area. The light-emitting area EMA may be an area in which the light-emitting element ED is disposed and in which light of a specific wavelength band is emitted. The non-light-emitting area may be an area in which the light-emitting element ED is not disposed and in which the light emitted from the light-emitting element ED does not reach and thus is not emitted.

[0044] The light emitting region EMA may include a region where the light emitting element ED is arranged and a region adjacent to the light emitting element ED where light emitted from the light emitting element ED is output. For example, the light emitting region EMA may also include a region where the light emitted from the light emitting element ED is reflected or refracted by another member and output. A plurality of light emitting elements ED are arranged in each sub-pixel SPXn, and the light emitting region EMA may be formed by including the region where the light emitting elements ED are arranged and the region adjacent thereto.

[0045] 2, the light emitting regions EMA of the sub-pixels SPXn have a uniform area, but are not limited thereto. In some embodiments, the light emitting regions EMA of the sub-pixels SPXn may have different areas depending on the color or wavelength band of light emitted from the light emitting element ED disposed in the corresponding sub-pixel.

[0046] Each sub-pixel SPXn may further include a sub-region SA arranged in a non-light-emitting region. The sub-region SA of the corresponding sub-pixel SPXn may be arranged on the other side of the light-emitting region EMA in the first direction DR1, i.e., below the light-emitting region EMA. The light-emitting regions EMA and the sub-regions SA may be alternately arranged along the first direction DR1, and the sub-regions SA may be arranged between the light-emitting regions EMA of different sub-pixels SPXn spaced apart in the first direction DR1. For example, the light-emitting regions EMA and the sub-regions SA may be alternately arranged in the first direction DR1, and the light-emitting regions EMA and the sub-regions SA may be repeatedly arranged in the second direction DR2. However, the light-emitting regions EMA and the sub-regions SA in a plurality of pixels PX may have an arrangement different from that of FIG. 2.

[0047] Since no light emitting element ED is arranged in the sub-region SA, no light is emitted therefrom, but a part of the electrode RME arranged in each sub-pixel SPXn may be arranged therein. The electrodes RME arranged in different sub-pixels SPXn may be arranged to be separated from each other by a separation portion ROP of the sub-region SA.

[0048] The wiring and circuit elements of the circuit layer may be connected to the first to third sub-pixels SPX1, SPX2, and SPX3, respectively. However, the wiring and circuit elements may not be arranged corresponding to the area occupied by each sub-pixel SPXn or the light-emitting area EMA, but may be arranged within one pixel PX regardless of the position of the light-emitting area EMA.

[0049] The lower bank layer LBN may be disposed to surround the plurality of subpixels SPXn, and the light-emitting region EMA and subregion SA. The lower bank layer LBN may be disposed at the boundary between the subpixels SPXn adjacent in the first direction DR1 and the second direction DR2, and may also be disposed at the boundary between the light-emitting region EMA and subregion SA. The subpixels SPXn, the light-emitting region EMA, and the subregion SA of the display device 10 may be regions separated by the arrangement of the lower bank layer LBN. The intervals between the plurality of subpixels SPXn, the light-emitting region EMA, and the subregion SA may vary depending on the width of the lower bank layer LBN.

[0050] The lower bank layer LBN may be arranged in a lattice pattern over the entire display area DPA, including portions extending in the first direction DR1 and the second direction DR2 on a plane. The lower bank layer LBN may be arranged across the boundaries of each subpixel SPXn to separate adjacent (or neighboring) subpixels SPXn. For example, the lower bank layer LBN may be arranged to surround the light emitting area EMA and the subarea SA arranged for each subpixel SPXn to separate them.

[0051] Fig. 3 is a cross-sectional view taken along line N1-N1' in Fig. 2. Fig. 4 is a cross-sectional view taken along line N2-N2' in Fig. 2. Fig. 3 shows a cross section across both ends (or first / second ends, or opposite ends) of the light-emitting element ED arranged in the first sub-pixel SPX1 and the electrode contact holes CTD, CTS, and Fig. 4 shows a single plane across both ends of the light-emitting element ED arranged in the first sub-pixel SPXn and the contact portions CT1, CT2.

[0052] 3 and 4 in conjunction with Fig. 2, the display device 10 may include a first substrate SUB, and a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers disposed on the first substrate SUB. The semiconductor layer, the conductive layer, and the insulating layer may respectively constitute a circuit layer and a display element layer of the display device 10.

[0053] The first substrate SUB may be an insulating substrate. The first substrate SUB may be made of an insulating material such as glass, quartz, or polymer resin. For example, the first substrate SUB may be a rigid substrate, or may be a flexible substrate capable of bending, folding, rolling, etc. The first substrate SUB may include a display area DPA and a non-display area NDA surrounding the display area DPA, and the display area DPA may include a light-emitting area EMA and a sub-area SA that is a part of the non-light-emitting area.

[0054] The first conductive layer may be disposed on the first substrate SUB. The first conductive layer includes a lower metal layer BML, which is disposed to overlap the active layer ACT1 of the first transistor T1. The lower metal layer BML may function to prevent light from being incident on the active layer ACT1 of the first transistor, or to stabilize the electrical characteristics of the first transistor T1 by being electrically connected to the first active layer ACT1. However, the lower metal layer BML may be omitted.

[0055] A buffer layer BL may be disposed on the lower metal layer BML and the first substrate SUB. The buffer layer BL is formed on the first substrate SUB to protect the transistors of the pixels PX from moisture that may penetrate through the first substrate SUB, which is susceptible to moisture permeation, and can perform a surface planarization function.

[0056] The semiconductor layer is disposed on the buffer layer BL. The semiconductor layer may include a first active layer ACT1 of the first transistor T1 and a second active layer ACT2 of the second transistor T2. The first active layer ACT1 and the second active layer ACT2 may be disposed to partially (or entirely) overlap a first gate electrode G1 and a second gate electrode G2 of a second conductive layer, respectively, which will be described later.

[0057] The semiconductor layer may include polycrystalline silicon, single crystal silicon, an oxide semiconductor, and the like. In another embodiment, the semiconductor layer may include polycrystalline silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0058] Although the drawing illustrates an example in which one first transistor T1 and one second transistor T2 are arranged in the sub-pixel SPXn of the display device 10, this is not limited thereto, and the display device 10 may include a greater number of transistors.

[0059] The first gate insulating layer GI is disposed on the semiconductor layer and the buffer layer BL. The first gate insulating layer GI can serve as a gate insulating film for each of the transistors T1 and T2.

[0060] The second conductive layer is disposed on the first gate insulating layer GI. The second conductive layer may include a first gate electrode G1 of the first transistor T1 and a second gate electrode G2 of the second transistor T2. The first gate electrode G1 may be disposed to overlap a channel region of the first active layer ACT1 in a third direction DR3 that is a thickness direction, and the second gate electrode G2 may be disposed to overlap a channel region of the second active layer ACT2 in the third direction DR3 that is a thickness direction. Although not shown in the drawing, the second conductive layer may further include one electrode of a storage capacitor.

[0061] The first interlayer insulating layer IL1 is disposed on the second conductive layer. The first interlayer insulating layer IL1 functions as an insulating film between the second conductive layer and another layer disposed thereon, and can protect the second conductive layer.

[0062] The third conductive layer is disposed on the first interlayer insulating layer IL1. The third conductive layer may include a first voltage line VL1 and a second voltage line VL2 disposed in the display area DPA, a first conductive pattern CDP1, and source electrodes S1, S2 and drain electrodes D1, D2 of the transistors T1, T2. For example, the third conductive layer may further include another electrode of the storage capacitor.

[0063] The first voltage line VL1 may receive a high potential voltage (or a first power supply voltage) transmitted to the first electrode RME1, and the second voltage line VL2 may receive a low potential voltage (or a second power supply voltage) transmitted to the second electrode RME2. A portion of the first voltage line VL1 may contact the first active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. The first voltage line VL1 may serve as a first drain electrode D1 of the first transistor T1. The second voltage line VL2 may be directly connected to a second electrode RME2, which will be described later.

[0064] The first conductive pattern CDP may contact the first active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. The first conductive pattern CDP may contact the lower metal layer BML through another contact hole. The first conductive pattern CDP may serve as a first source electrode S1 of the first transistor T1. For example, the first conductive pattern CDP may be connected to a first electrode RME1 or a first connecting electrode CNE1, which will be described later. The first transistor T1 may transfer a first power supply voltage applied from a first voltage wiring VL1 to the first electrode RME1 or the first connecting electrode CNE1.

[0065] The second source electrode S2 and the second drain electrode D2 may be in contact with the second active layer ACT2 of the second transistor T2 through contact holes penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI, respectively.

[0066] The first protective layer PV1 is disposed on the third conductive layer. The first protective layer PV1 can function as an insulating film between the third conductive layer and other layers to protect the third conductive layer.

[0067] The above-mentioned buffer layer BL, first gate insulating layer GI, first interlayer insulating layer IL1, and first protective layer PV1 are made of a plurality of inorganic layers alternately stacked. For example, the buffer layer BL, first gate insulating layer GI, first interlayer insulating layer IL1, and first protective layer PV1 are made of silicon oxide (Silicon Oxide, SiO x ), Silicon Nitride (SiN x ), Silicon Oxynitride (SiO x N y ) may be laminated as a double layer, or may be laminated as a multilayer in which these are alternately laminated. However, without being limited thereto, the buffer layer BL, the first gate insulating layer GI, the first interlayer insulating layer IL1, and the first protective layer PV1 may be formed of a single inorganic layer including the insulating material described above. In addition, in some embodiments, the first interlayer insulating layer IL1 may be made of an organic insulating material such as polyimide (PI).

[0068] The second conductive layer and the third conductive layer may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, but are not limited thereto.

[0069] The via layer VIA is disposed on the third conductive layer in the display area DPA. The via layer VIA may include an organic insulating material, such as polyimide (PI), to compensate for a step caused by the lower conductive layer and to form a flat upper surface. However, in some embodiments, the via layer VIA may be omitted.

[0070] On the via layer VIA, bank patterns BP1, BP2, a plurality of electrodes (RME; RME1, RME2), a lower bank layer LBN, a plurality of light emitting elements ED, and a plurality of connecting electrodes (CNE; CNE1, CNE2) are arranged as a display element layer. Also, a plurality of insulating layers PAS1, PAS2, PAS3 may be arranged on the via layer VIA.

[0071] A plurality of bank patterns BP1 and BP2 may be disposed in the light emitting region EMA of each sub-pixel SPXn. The bank patterns BP1 and BP2 may have a shape that has a certain width in the second direction DR2 and extends in the first direction DR1.

[0072] For example, the bank patterns BP1 and BP2 may include a first bank pattern BP1 and a second bank pattern BP2 spaced apart from each other in the second direction DR2 in the light emitting region EMA of each sub-pixel SPXn. The first bank pattern BP1 may be disposed on one side of the second direction DR2 at the center of the light emitting region EMA, i.e., on the left side, and the second bank pattern BP2 may be disposed on the other side of the second direction DR2 at the center of the light emitting region EMA, i.e., on the right side, spaced apart from the first bank pattern BP1. The first bank pattern BP1 and the second bank pattern BP2 may be alternately disposed along the second direction DR2 and may be disposed in an island pattern in the display area DPA. A plurality of light emitting elements ED may be disposed between the first bank pattern BP1 and the second bank pattern BP2.

[0073] The first bank pattern BP1 and the second bank pattern BP2 have the same length in the first direction DR1, but may be shorter than the length in the first direction DR1 of the light emitting region EMA surrounded by the lower bank layer LBN. The first bank pattern BP1 and the second bank pattern BP2 may be separated from a portion of the lower bank layer LBN extending in the second direction DR2. However, without being limited thereto, the bank patterns BP1 and BP2 may be integrated with the lower bank layer LBN or may partially overlap with a portion of the lower bank layer LBN extending in the second direction DR2. In this case, the length in the first direction DR1 of the bank patterns BP1 and BP2 may be the same as or longer than the length in the first direction DR1 of the light emitting region EMA surrounded by the lower bank layer LBN.

[0074] The first bank pattern BP1 and the second bank pattern BP2 may have the same width in the second direction DR2. However, the present invention is not limited thereto, and they may have different widths. For example, one bank pattern may have a width larger than the other bank patterns, and the bank pattern with the larger width may be disposed across the light emitting region EMA of another sub-pixel SPXn adjacent in the second direction DR2. In this case, the bank patterns disposed across the light emitting regions EMA may have the second bank pattern BP2 overlapping a portion of the lower bank layer LBN that extends in the first direction DR1 in the thickness direction. In the drawings, the case where two bank patterns BP1 and BP2 are disposed for each sub-pixel SPXn with the same width is illustrated, but the present invention is not limited thereto. The number and shape of the bank patterns BP1 and BP2 may vary depending on the number or arrangement structure of the electrodes RME.

[0075] A plurality of bank patterns BP1, BP2 may be disposed on the via layer VIA. For example, the bank patterns BP1, BP2 may be disposed directly on the via layer VIA and may have a structure in which at least a portion of the bank patterns BP1, BP2 protrude from the upper surface of the via layer VIA. The protruding portions of the bank patterns BP1, BP2 may have inclined or curved sides, and light emitted from the light emitting element ED may be reflected by the electrode RME disposed on the bank patterns BP1, BP2 and emitted toward the upper portion of the via layer VIA. Unlike the example of the drawing, the bank patterns BP1, BP2 may have a semicircular or semielliptical shape with a curved outer surface in a cross-sectional view. The bank patterns BP1, BP2 may include an organic insulating material such as polyimide (PI), but are not limited thereto.

[0076] The electrodes (RME; RME1, RME2) have a shape extending in one direction and are arranged for each sub-pixel SPXn. The electrodes RME1, RME2 may extend in a first direction DR1 and be arranged in the light-emitting region EMA and sub-region SA of the sub-pixel SPXn, and may be spaced apart from each other in a second direction DR2. The electrodes RME are electrically connected to a light-emitting element ED described later, but are not limited thereto and may not be electrically connected to the light-emitting element ED.

[0077] The display device 10 may include a first electrode RME1 and a second electrode RME2 disposed in each subpixel SPXn. The first electrode RME1 is disposed on the left side of the center of the light emitting region EMA, and the second electrode RME2 is disposed on the right side of the center of the light emitting region EMA, spaced apart from the first electrode RME1 in the second direction DR2. The first electrode RME1 may be disposed on a first bank pattern BP1, and the second electrode RME2 may be disposed on a second bank pattern BP2. The first electrode RME1 and the second electrode RME2 may be partially disposed in the corresponding subpixel SPXn and subregion SA beyond the lower bank layer LBN. The first electrode RME1 and the second electrode RME2 of different subpixels SPXn may be spaced apart from each other based on a separation part ROP located in the subregion SA of any one of the subpixels SPXn.

[0078] In the drawings, two electrodes RME are illustrated extending in the first direction DR1 for each sub-pixel SPXn, but the present invention is not limited thereto. For example, the display device 10 may have a larger number of electrodes RME arranged in one sub-pixel SPXn, or the electrode RME may be partially bent to have different widths depending on the position.

[0079] The first electrode RME1 and the second electrode RME2 may be disposed at least on the inclined side surfaces of the bank patterns BP1, BP2. In one embodiment, the width of the plurality of electrodes RME measured in the second direction DR2 may be smaller than the width of the bank patterns BP1, BP2 measured in the second direction DR2, and the distance between the first electrode RME1 and the second electrode RME2 in the second direction DR2 may be smaller than the distance between the bank patterns BP1, BP2. At least a portion of the first electrode RME1 and the second electrode RME2 may be disposed directly on the via layer VIA, and they may be disposed on the same plane.

[0080] The light emitting element ED disposed between the bank patterns BP1 and BP2 may emit light toward both ends, and the emitted light may be directed toward the electrode RME disposed on the bank patterns BP1 and BP2. Each electrode RME may have a structure in which a portion disposed on the bank patterns BP1 and BP2 reflects light emitted from the light emitting element ED. The first electrode RME1 and the second electrode RME2 are disposed to cover at least one side of the bank patterns BP1 and BP2, and may reflect light emitted from the light emitting element ED.

[0081] Each electrode RME may directly contact the third conductive layer through the electrode contact holes CTD, CTS in a portion overlapping the lower bank layer LBN between the light emitting region EMA and the sub-region SA. The first electrode contact hole CTD may be formed in a region where the lower bank layer LBN and the first electrode RME1 overlap, and the second electrode contact hole CTS may be formed in a region where the lower bank layer LBN and the second electrode RME2 overlap. The first electrode RME1 may contact the first conductive pattern CDP through the first electrode contact hole CTD penetrating the via layer VIA and the first protective layer PV1. The second electrode RME2 may contact the second voltage wiring VL2 through the second electrode contact hole CTS penetrating the via layer VIA and the first protective layer PV1. The first electrode RME1 may be electrically connected to the first transistor T1 through the first conductive pattern CDP to apply a first power supply voltage thereto, and the second electrode RME2 may be electrically connected to the second voltage wiring VL2 to apply a second power supply voltage thereto. However, the present invention is not limited thereto. In another embodiment, the electrodes RME1 and RME2 may not be electrically connected to the voltage wirings VL1 and VL2 of the third conductive layer, and a connecting electrode CNE, which will be described later, may be directly connected to the third conductive layer.

[0082] The plurality of electrode RMEs may include conductive materials with high reflectivity. For example, the electrode RME may include metals such as silver (Ag), copper (Cu), aluminum (Al), etc., or may include alloys including aluminum (Al), nickel (Ni), lanthanum (La), etc., or may include layers of metals such as titanium (Ti), molybdenum (Mo), and niobium (Nb) and the alloys. In some embodiments, the electrode RME may include a bilayer or multilayer structure including an alloy including aluminum (Al) and at least one metal layer including titanium (Ti), molybdenum (Mo), and niobium (Nb).

[0083] Without being limited thereto, each electrode RME may further include a transparent conductive material. For example, each electrode RME may include materials such as ITO, IZO, ITZO, etc. In some embodiments, each electrode RME may have a structure in which a transparent conductive material and a metal layer having high reflectivity are laminated in one or more layers, or may be formed as a single layer including them. For example, each electrode RME may have a laminate structure such as ITO / Ag / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO. The electrode RME is electrically connected to the light emitting element ED and may reflect a portion of light emitted from the light emitting element ED toward the upper direction of the first substrate SUB.

[0084] The first insulating layer PAS1 may be disposed over the entire display area DPA and over the via layer VIA and the plurality of electrodes RME. The first insulating layer PAS1 can protect the plurality of electrodes RME and at the same time insulate different electrodes RME from each other. In particular, the first insulating layer PAS1 is disposed to cover the electrodes RME before the lower bank layer LBN is formed, thereby preventing the electrodes RME from being damaged in the process of forming the lower bank layer LBN. The first insulating layer PAS1 can also prevent the light emitting element ED disposed thereon from being damaged by direct contact with other members.

[0085] In an exemplary embodiment, the first insulating layer PAS1 may have a step formed between the electrodes RME spaced apart in the second direction DR2 such that a portion of the upper surface is recessed. The light emitting element ED may be disposed on the upper surface of the first insulating layer PAS1 where the step is formed, and a space may be formed between the light emitting element ED and the first insulating layer PAS1.

[0086] The lower bank layer LBN may be disposed on the first insulating layer PAS1. The lower bank layer LBN may include portions extending in the first direction DR1 and the second direction DR2 and may surround each subpixel SPXn. The lower bank layer LBN may surround and separate the light emitting region EMA and subregion SA of each subpixel SPXn, and may surround the outermost portion of the display region DPA to separate the display region DPA from the non-display region NDA. The lower bank layer LBN is disposed over the entire display region DPA to form a lattice pattern, and the regions in the display region DPA where the lower bank layer LBN opens may be the light emitting region EMA and the subregion SA.

[0087] The lower bank layer LBN may have a constant height, similar to the bank patterns BP1 and BP2. In some embodiments, the lower bank layer LBN may have a higher upper surface height than the bank patterns BP1 and BP2, and may have a thickness equal to or greater than the bank patterns BP1 and BP2. The lower bank layer LBN may prevent ink from overflowing into the adjacent sub-pixel SPXn during an inkjet printing process in the manufacturing process of the display device 10. The lower bank layer LBN may include an organic insulating material such as polyimide, similar to the bank patterns BP1 and BP2.

[0088] A plurality of light emitting elements ED may be disposed in the light emitting area EMA. The light emitting elements ED may be disposed between the bank patterns BP1 and BP2 and may be arranged spaced apart from each other in the first direction DR1. In one embodiment, the plurality of light emitting elements ED may have a shape extending in one direction, and both ends may be disposed on different electrodes RME. The length of the light emitting elements ED may be longer than the distance between the electrodes RME spaced apart in the second direction DR2. The light emitting elements ED may generally be arranged such that their extension direction is perpendicular to the first direction DR1 in which the electrodes RME extend. However, the present invention is not limited thereto, and the light emitting elements ED may be arranged such that their extension direction is in the second direction DR2 or in a direction oblique thereto.

[0089] A plurality of light-emitting elements ED may be disposed on the first insulating layer PAS1. The light-emitting elements ED may have a shape extending in one direction, and may be disposed such that the extending direction is parallel to the upper surface of the first substrate SUB. As described below, the light-emitting element ED may include a plurality of semiconductor layers disposed along the extending direction, and the plurality of semiconductor layers may be sequentially disposed along a direction parallel to the upper surface of the first substrate SUB. However, this is not limited thereto, and when the light-emitting element ED has another structure, the plurality of semiconductor layers may be disposed in a direction perpendicular to the first substrate SUB.

[0090] The light emitting element ED arranged in each sub-pixel SPXn can emit light of different wavelength bands depending on the material of the semiconductor layer described above, but is not limited thereto, and the light emitting element ED arranged in each sub-pixel SPXn can include a semiconductor layer made of the same material and emit light of the same color.

[0091] The light emitting device ED may be in contact with the connecting electrodes (CNE: CNE1, CNE2) and electrically connected to the electrode RME and the conductive layer under the via layer VIA, and may emit light of a specific wavelength band when an electrical signal is applied.

[0092] The second insulating layer PAS2 may be disposed on the plurality of light-emitting elements ED, the first insulating layer PAS1, and the lower bank layer LBN. The second insulating layer PAS2 includes a pattern portion extending in the first direction DR1 between the bank patterns BP1, BP2 and disposed on the plurality of light-emitting elements ED. The pattern portion is disposed to partially surround the outer surface of the light-emitting element ED, and may not cover both sides or both ends of the light-emitting element ED. The pattern portion may form a linear or island pattern in each sub-pixel SPXn in a plan view. The pattern portion of the second insulating layer PAS2 may protect the light-emitting element ED and at the same time fix the light-emitting element ED during the manufacturing process of the display device 10. The second insulating layer PAS2 may be disposed to fill a space between the light-emitting element ED and the first insulating layer PAS1 therebelow. A portion of the second insulating layer PAS2 may be disposed on the upper portion of the lower bank layer LBN and in the sub-region SA.

[0093] A plurality of connecting electrodes (CNE; CNE1, CNE2) may be disposed on the plurality of electrodes RME and the bank patterns BP1, BP2. Each of the plurality of connecting electrodes CNE may have a shape extending in one direction and may be disposed apart from each other. Each connecting electrode CNE may contact the light emitting element ED and be electrically connected to the third conductive layer.

[0094] The plurality of connecting electrodes CNE may include a first connecting electrode CNE1 and a second connecting electrode CNE2 disposed in each sub-pixel SPXn. The first connecting electrode CNE1 may have a shape extending in a first direction DR1 and may be disposed on the first electrode RME1 or the first bank pattern BP1. The first connecting electrode CNE1 may be disposed from the light emitting region EMA to the sub-region SA across the lower bank layer LBN, partially overlapping with the first electrode RME1. The second connecting electrode CNE2 may have a shape extending in the first direction DR1 and may be disposed on the second electrode RME2 or the second bank pattern BP2. The second connecting electrode CNE2 may be disposed from the light emitting region EMA to the sub-region SA across the lower bank layer LBN, partially overlapping with the second electrode RME2. The first connecting electrode CNE1 and the second connecting electrode CNE2 may be in contact with the light emitting element ED, and may be electrically connected to the electrode RME or a conductive layer thereunder.

[0095] For example, the first connecting electrode CNE1 and the second connecting electrode CNE2 may be disposed on side surfaces of the second insulating layer PAS2 and may be in contact with the light emitting element ED. The first connecting electrode CNE1 may partially overlap the first electrode RME1 and may be in contact with one end of the light emitting element ED. The second connecting electrode CNE2 may partially overlap the second electrode RME2 and may be in contact with the other end of the light emitting element ED. The multiple connecting electrodes CNE are disposed across the light emitting region EMA and the sub-region SA. The connecting electrode CNE may be in contact with the light emitting element ED at a portion disposed in the light emitting region EMA and may be electrically connected to the third conductive layer at a portion disposed in the sub-region SA.

[0096] According to an embodiment, in the display device 10, each connecting electrode CNE may be in contact with the electrode RME through contact portions CT1 and CT2 arranged in the sub-region SA. The first connecting electrode CNE1 may be in contact with the first electrode RME1 through a first contact portion CT1 penetrating the first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 in the sub-region SA. The second connecting electrode CNE2 may be in contact with the second electrode RME2 through a second contact portion CT2 penetrating the first insulating layer PAS1 and the second insulating layer PAS2 in the sub-region SA. Each connecting electrode CNE may be electrically connected to the third conductive layer through each electrode RME. The first connecting electrode CNE1 may be electrically connected to the first transistor T1 to receive a first power supply voltage, and the second connecting electrode CNE2 may be electrically connected to the second voltage wiring VL2 to receive a second power supply voltage. Each connecting electrode CNE may be in contact with the light emitting element ED in the light emitting region EMA to transmit a power supply voltage to the light emitting element ED.

[0097] However, the present invention is not limited thereto. In some embodiments, the plurality of connecting electrodes CNE may be in direct contact with the third conductive layer, or may be electrically connected to the third conductive layer via a pattern other than the electrode RME.

[0098] The connecting electrode CNE may include a conductive material, for example, ITO, IZO, ITZO, aluminum (Al), etc. For example, the connecting electrode CNE may include a transparent conductive material, and light emitted from the light emitting device ED may be transmitted through the connecting electrode CNE and emitted.

[0099] The third insulating layer PAS3 is disposed on the second connecting electrode CNE2 and the second insulating layer PAS2. The third insulating layer PAS3 may be disposed entirely on the second insulating layer PAS2 to cover the second connecting electrode CNE2, and the first connecting electrode CNE1 may be disposed on the third insulating layer PAS3. The third insulating layer PAS3 may be disposed entirely on the via layer VIA except for the region where the first connecting electrode CNE1 is disposed. The third insulating layer PAS3 may insulate the first connecting electrode CNE1 from the second connecting electrode CNE2 so that they do not come into direct contact with each other.

[0100] Although not shown in the drawing, another insulating layer may be further disposed on the third insulating layer PAS3 and the first connecting electrode CNE1. The insulating layer may function to protect the components disposed on the first substrate SUB from the external environment.

[0101] The above-mentioned first insulating layer PAS1, second insulating layer PAS2, and third insulating layer PAS3 may each include an inorganic insulating material or an organic insulating material. As an example, the first insulating layer PAS1, second insulating layer PAS2, and third insulating layer PAS3 may each include an inorganic insulating material, or the first insulating layer PAS1 and the third insulating layer PAS3 may include an inorganic insulating material, while the second insulating layer PAS2 may include an organic insulating material. The first insulating layer PAS1, second insulating layer PAS2, and third insulating layer PAS3 may each, or at least one of them may be formed in a structure in which a plurality of insulating layers are alternately or repeatedly stacked. In an exemplary embodiment, the first insulating layer PAS1, second insulating layer PAS2, and third insulating layer PAS3 may each be formed of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiO x N y The first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 may be made of the same material, or may be made of parts that are the same and parts that are different materials, or may be made of different materials.

[0102] FIG. 5 is a schematic diagram of a light-emitting device according to one embodiment.

[0103] 5, the light emitting device ED may be a light emitting diode, and more specifically, the light emitting device ED may be an inorganic light emitting diode having a size of nanometer to micrometer and made of an inorganic material. The light emitting device ED may be aligned between two electrodes facing each other, where a polarity is formed when an electric field is formed between the two electrodes in a specific direction.

[0104] The light emitting device ED according to an embodiment may have a shape extending in one direction. The light emitting device ED may have a shape of a cylinder, a rod, a wire, a tube, etc. However, the shape of the light emitting device ED is not limited thereto, and the light emitting device ED may have various shapes, such as a polygonal prism shape such as a regular cube, a rectangular cube, or a hexagonal prism shape, or a shape extending in one direction with an outer surface partially inclined.

[0105] The light emitting element ED may include a semiconductor layer doped with a dopant of any conductivity type (e.g., p-type or n-type). The semiconductor layer may emit light of a specific wavelength band when an electrical signal applied from an external power source is transmitted to the semiconductor layer. The light emitting element ED may include a first semiconductor layer 31, a second semiconductor layer 32, a light emitting layer 36, an electrode layer 37, and an insulating film 38.

[0106] The first semiconductor layer 31 may be an n-type semiconductor. The first semiconductor layer 31 may be an Al x Ga y In 1-x-y The first semiconductor layer 31 may include a semiconductor material having a chemical formula of 0≦x≦1, 0≦y≦1, 0≦x+y≦1. For example, the first semiconductor layer 31 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant doped in the first semiconductor layer 31 may be Si, Ge, Sn, etc.

[0107] The second semiconductor layer 32 is disposed on the first semiconductor layer 31 with the light emitting layer 36 therebetween. The second semiconductor layer 32 may be a p-type semiconductor, and the second semiconductor layer 32 may be Al x Ga y In 1-x-y The second semiconductor layer 32 may include a semiconductor material having a chemical formula of 0≦x≦1, 0≦y≦1, 0≦x+y≦1. For example, the second semiconductor layer 32 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant doped in the second semiconductor layer 32 may be Mg, Zn, Ca, Ba, etc.

[0108] Meanwhile, in the drawings, the first semiconductor layer 31 and the second semiconductor layer 32 are shown as being composed of one layer, but are not limited thereto. Depending on the material of the light emitting layer 36, the first semiconductor layer 31 and the second semiconductor layer 32 may further include more layers, for example, a clad layer or a tensile strain barrier reducing (TSBR) layer. For example, the light emitting device ED may further include another semiconductor layer disposed between the first semiconductor layer 31 and the light emitting layer 36, or between the second semiconductor layer 32 and the light emitting layer 36. The semiconductor layer disposed between the first semiconductor layer 31 and the light emitting layer 36 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, InN, and SLs doped with an n-type dopant, and the semiconductor layer disposed between the second semiconductor layer 32 and the light emitting layer 36 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant.

[0109] The light emitting layer 36 is disposed between the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a material having a single or multiple quantum well structure. When the light emitting layer 36 includes a material having a multiple quantum well structure, the light emitting layer 36 may have a structure in which a barrier layer and a well layer are alternately stacked. The light emitting layer 36 may emit light by combining electron-hole pairs in response to an electrical signal applied through the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a material such as AlGaN, AlGaInN, InGaN, etc. In particular, when the light emitting layer 36 has a multiple quantum well structure in which a barrier layer and a well layer are alternately stacked, the barrier layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN, InGaN, or AlInN.

[0110] The light emitting layer 36 may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately laminated, and may include different Group 3 to Group 5 semiconductor materials depending on the wavelength band of the emitted light. The light emitted by the light emitting layer 36 is not limited to light in the blue wavelength band, and may also emit light in the red or green wavelength band depending on the case.

[0111] The electrode layer 37 may be an Ohmic connection electrode, but is not limited thereto, and may be a Schottky connection electrode. The light emitting device ED may include at least one electrode layer 37. The light emitting device ED may include one or more electrode layers 37, but is not limited thereto, and the electrode layer 37 may be omitted.

[0112] The electrode layer 37 can reduce resistance between the light emitting element ED and the electrode or the connecting electrode when the light emitting element ED is electrically connected to the electrode or the connecting electrode in the display device 10. The electrode layer 37 can include a conductive metal. For example, the electrode layer 37 can include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

[0113] The insulating film 38 is disposed so as to surround the outer surfaces of the plurality of semiconductor layers and electrode layers described above. For example, the insulating film 38 is disposed so as to surround at least the outer surface of the light emitting layer 36, but both ends in the longitudinal direction of the light emitting element ED may be formed so as to be exposed. Also, the insulating film 38 may be formed so that the upper surface in cross section is rounded in a region adjacent to at least one end of the light emitting element ED.

[0114] The insulating film 38 is made of a material having insulating properties, such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), Aluminum Nitride (AlN x ), aluminum oxide (AlOx In the drawings, the insulating film 38 is illustrated as being formed as a single layer, but is not limited thereto, and in some embodiments, the insulating film 38 may be formed as a multi-layer structure in which multiple layers are stacked.

[0115] The insulating film 38 can protect the semiconductor layer and the electrode layer of the light emitting element ED. If the insulating film 38 is in direct contact with an electrode through which an electrical signal is transmitted to the light emitting element ED, the insulating film 38 can prevent an electrical short circuit that may occur in the light emitting layer 36. In addition, the insulating film 38 can prevent a decrease in the luminous efficiency of the light emitting element ED.

[0116] In addition, the outer surface of the insulating film 38 may be surface-treated. The light emitting elements ED may be aligned by being sprayed on the electrodes in a dispersed state in a certain ink. Here, in order to keep the light emitting elements ED dispersed in the ink without agglomerating with other adjacent light emitting elements ED, the surface of the insulating film 38 may be hydrophobically or hydrophilically treated.

[0117] According to an embodiment, the display device 10 may further include color control structures ("TPL", "WCL1", "WCL2" in FIG. 6) and color filter layers ("CFL1", "CFL2", "CFL3" in FIG. 6) disposed on the light-emitting element ED. Light emitted from the light-emitting element ED may be emitted via the color control structures TPL, WCL1, WCL2 and color filter layers CFL1, CFL2, CFL3, and even if the same type of light-emitting element ED is disposed for each sub-pixel SPXn, the color of the emitted light may be different for each sub-pixel SPXn.

[0118] FIG. 6 is a cross-sectional view of a display device according to an embodiment.

[0119] 6, the display device 10 may include a light emitting element ED disposed on a first substrate SUB, and color control structures TPL, WCL1, WCL2 and color filter layers CFL1, CFL2, CFL3 disposed thereon. The display device 10 may further include a number of layers disposed between the color control structures TPL, WCL1, WCL2 and the color filter layers CFL1, CFL2, CFL3. The layers disposed on the light emitting element ED of the display device 10 will be described below.

[0120] The fourth insulating layer PAS4 may be disposed on the third insulating layer PAS3, the connecting electrodes CNE1, CNE2, and the lower bank layer LBN. The fourth insulating layer PAS4 may protect layers disposed on the first substrate SUB. However, the fourth insulating layer PAS4 may be omitted.

[0121] The first bank BNL1, color control structures TPL, WCL1, WCL2, light blocking member BM, and color filter layers CFL1, CFL2, CFL3 may be disposed on the fourth insulating layer PAS4. In addition, a plurality of capping layers CPL1, CPL2 and low refractive index layers LRL may be disposed between the color control structures TPL, WCL1, WCL2 and the color filter layers CFL1, CFL2, CFL3, and an overcoat layer OC may be disposed on the color filter layers CFL1, CFL2, CFL3.

[0122] The display device 10 may include a plurality of light-transmitting regions TA1, TA2, and TA3 in which color filter layers CFL1, CFL2, and CFL3 are disposed and from which light is emitted, and a light-shielding region BA between the light-transmitting regions TA1, TA2, and TA3 from which light is not emitted. The light-transmitting regions TA1, TA2, and TA3 may be located corresponding to a portion of the light-emitting region EMA of each sub-pixel SPXn, and the light-shielding region BA may be a region other than the light-transmitting regions TA1, TA2, and TA3. As will be described later, the light-transmitting regions TA1, TA2, and TA3 and the light-shielding region BA may be divided by a light-shielding member BM.

[0123] The first bank BNL1 may be arranged to overlap the lower bank layer LBN on the fourth insulating layer PAS4. The first bank BNL1 may include portions extending in the first direction DR1 and the second direction DR2 and may be arranged in a lattice pattern. The first bank BNL1 may surround a portion where the light emitting area EMA or the light emitting element ED is arranged. The first bank BNL1 may form an area where the color control structures TPL, WCL1, and WCL2 are arranged.

[0124] The color control structures TPL, WCL1, and WCL2 may be disposed in an area surrounded by the first bank BNL1 on the fourth insulating layer PAS4. The color control structures TPL, WCL1, and WCL2 may be disposed in the light-transmitting areas TA1, TA2, and TA3 surrounded by the first bank BNL1 to form an island-shaped pattern in the display area DPA. However, this is not limited thereto, and the color control structures TPL, WCL1, and WCL2 may each extend in one direction and be disposed across multiple sub-pixels SPXn to form a linear pattern.

[0125] In an embodiment in which the light-emitting element ED of each subpixel SPXn emits blue light of the third color, the color control structures TPL, WCL1, and WCL2 may include a first wavelength conversion layer WCL1 arranged in the first subpixel SPX1 corresponding to the first light-transmitting region TA1, a second wavelength conversion layer WCL2 arranged in the second subpixel SPX2 corresponding to the second light-transmitting region TA2, and a light-transmitting layer TPL arranged in the third subpixel SPX3 corresponding to the third light-transmitting region TA3.

[0126] The first wavelength conversion layer WCL1 may include a first base resin BRS1 and a first wavelength conversion material WCP1 disposed in the first base resin BRS1. The second wavelength conversion layer WCL2 may include a second base resin BRS2 and a second wavelength conversion material WCP2 disposed in the second base resin BRS2. The first wavelength conversion layer WCL1 and the second wavelength conversion layer WCL2 convert the wavelength of the third color blue light incident on the light emitting element ED and transmit it. The first wavelength conversion layer WCL1 and the second wavelength conversion layer WCL2 further include a scatterer SCP contained in each base resin, and the scatterer SCP can increase the wavelength conversion efficiency.

[0127] The transparent layer TPL may include a third base resin BRS3 and a scatterer SCP disposed in the third base resin BSR3. The transparent layer TPL transmits the third color blue light incident on the light emitting element ED while maintaining the wavelength. The scatterer SCP of the transparent layer TPL may play a role in adjusting the emission path of the light emitted through the transparent layer TPL. The transparent layer TPL may not include a wavelength conversion material.

[0128] The scatterers SCP can be metal oxide particles or organic particles. The metal oxides include titanium oxide (TiO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 ), zinc oxide (ZnO) or tin oxide (SnO 2 ) and the like can be exemplified as the organic particle material, and acrylic resins or urethane resins can be exemplified as the organic particle material.

[0129] The first to third base resins BRS1, BRS2, ​​and BRS3 may include a light-transmitting organic material. For example, the first to third base resins BRS1, BRS2, ​​and BRS3 may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first to third base resins BRS1, BRS2, ​​and BRS3 may all be made of the same material, but are not limited thereto.

[0130] The first wavelength conversion material WCP1 may convert the third color blue light into the first color red light, and the second wavelength conversion material WCP2 may convert the third color blue light into the second color green light. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 may be quantum dots, quantum rods, phosphors, etc. The quantum dots may include group IV nanocrystals, II-VI compound nanocrystals, III-V compound nanocrystals, IV-VI nanocrystals, or a combination thereof.

[0131] In some embodiments, the color control structures TPL, WCL1, and WCL2 may be formed by an inkjet printing process or a photoresist process. The color control structures TPL, WCL1, and WCL2 may be formed by spraying or applying the materials constituting the color control structures TPL, WCL1, and WCL2 in the area surrounded by the first bank BNL1, followed by drying or exposure and development processes. As an example, in an embodiment in which the color control structures TPL, WCL1, and WCL2 are formed by an inkjet printing process, the upper surfaces of the layers of the color control structures TPL, WCL1, and WCL2 may be curved so that the edge portions adjacent to the first bank BNL1 are higher than the center portions. However, the present invention is not limited to this. In an embodiment in which the color control structures TPL, WCL1, and WCL2 are formed by a photoresist process, the upper surfaces of each layer of the color control structures TPL, WCL1, and WCL2 may be formed flat and the edge portions adjacent to the first bank BNL1 may be parallel to the upper surface of the first bank BNL1, or, unlike the drawing, the central portions of the color control structures TPL, WCL1, and WCL2 may be formed higher.

[0132] The light emitting element ED of each sub-pixel SPXn may emit the same third color blue light, and the light emitted from each sub-pixel SPXn may be light of different colors. For example, the light emitted from the light emitting element ED arranged in the first sub-pixel SPX1 is incident on the first wavelength conversion layer WCL1, the light emitted from the light emitting element ED arranged in the second sub-pixel SPX2 is incident on the second wavelength conversion layer WCL2, and the light emitted from the light emitting element ED arranged in the third sub-pixel SPX3 is incident on the transparent layer TPL. The light incident on the first wavelength conversion layer WCL1 is converted into red light, the light incident on the second wavelength conversion layer WCL2 is converted into green light, and the light incident on the transparent layer TPL can be transmitted as the same blue light without wavelength conversion. Although each sub-pixel SPXn includes the light emitting element ED emitting light of the same color, it can emit light of different colors depending on the arrangement of the color control structures TPL, WCL1, and WCL2 arranged thereon.

[0133] The first capping layer CPL1 may be disposed on the color control structures TPL, WCL1, WCL2 and the first bank BNL1. The first capping layer CPL1 may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color control structures TPL, WCL1, WCL2. The first capping layer CPL1 may include an inorganic insulating material.

[0134] The low refractive layer LRL may be disposed on the first capping layer CPL1. The low refractive layer LRL is an optical layer that recycles light that has passed through the color control structures TPL, WCL1, and WCL2, and can improve the light output efficiency and color purity of the display device 10. The low refractive layer LRL is made of an organic material having a low refractive index, and can compensate for steps formed by the color control structures TPL, WCL1, and WCL2 and the first bank BNL1.

[0135] The second capping layer CPL2 is disposed on the low refractive layer LRL and can prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the low refractive layer LRL. The second capping layer CPL2 may include an inorganic insulating material, similar to the first capping layer CPL1.

[0136] The light blocking member BM may be disposed on the second capping layer CPL2. The light blocking member BM may be formed in a lattice pattern to partially expose one surface of the second capping layer CPL2. In the display device 10, the light blocking member BM may be disposed to cover the sub-region SA of each sub-pixel SPXn in addition to the lower bank layer LBN and the first bank BNL1 in a plan view. The regions where the light blocking member BM is not disposed may be light-transmitting regions TA1, TA2, and TA3 where color filter layers CFL1, CFL2, and CFL3 are disposed and light is emitted, and the region where the light blocking member BM is disposed may be a light blocking region BA where light emission is blocked.

[0137] The light blocking member BM is made of an organic material capable of absorbing light. The light blocking member BM can reduce color distortion caused by reflection of external light by absorbing external light. For example, the light blocking member BM is made of a material used as a black matrix of the display device 10 and can absorb all visible light wavelengths.

[0138] In some embodiments, the display device 10 may omit the light blocking member BM and replace it with a material that absorbs light of a specific wavelength among visible light wavelengths and transmits light of other specific wavelengths. The light blocking member BM may be replaced with a color pattern containing the same material as at least one of the color filter layers CFL1, CFL2, and CFL3. For example, a color pattern containing the material of one of the color filter layers may be arranged in the area where the light blocking member BM is arranged, or a structure in which multiple color patterns are stacked may be provided.

[0139] The color filter layers CFL1, CFL2, and CFL3 may be disposed on one surface of the second capping layer CPL2. The color filter layers CFL1, CFL2, and CFL3 may be disposed on the second capping layer CPL2 in a region where the light blocking member BM is opened. The different color filter layers CFL1, CFL2, and CFL3 are disposed apart from each other with the light blocking member BM therebetween, but are not limited thereto. In some embodiments, the color filter layers CFL1, CFL2, and CFL3 may be partially disposed on the light blocking member BM and spaced apart from each other on the light blocking member BM, and in other embodiments, the color filter layers CFL1, CFL2, and CFL3 may partially overlap each other.

[0140] The color filter layers CFL1, CFL2, and CFL3 may include a first color filter layer CFL1 disposed in the first sub-pixel SPX1, a second color filter layer CFL2 disposed in the second sub-pixel SPX2, and a third color filter layer CFL3 disposed in the third sub-pixel SPX3. The color filter layers CFL1, CFL2, and CFL3 may be formed in a linear pattern disposed in a plurality of light-transmitting regions TA1, TA2, and TA3 or a plurality of light-emitting regions EMA. However, the present invention is not limited thereto. The color filter layers CFL1, CFL2, and CFL3 may be disposed corresponding to each of the light-transmitting regions TA1, TA2, and TA3 to form an island pattern.

[0141] The color filter layers CFL1, CFL2, and CFL3 may include colorants such as dyes or pigments that absorb light in a wavelength band other than a specific wavelength band. The color filter layers CFL1, CFL2, and CFL3 are disposed for each sub-pixel SPXn and can transmit only a portion of light incident on the color filter layers CFL1, CFL2, and CFL3 in the corresponding sub-pixel SPXn. Only light transmitted through the color filter layers CFL1, CFL2, and CFL3 can be selectively displayed in each sub-pixel SPXn of the display device 10. In an exemplary embodiment, the first color filter layer CFL1 may be a red color filter layer, the second color filter layer CFL2 may be a green color filter layer, and the third color filter layer CFL3 may be a blue color filter layer. Light emitted from the light emitting element ED may pass through the color control structures TPL, WCL1, and WCL2 and be emitted through the color filter layers CFL1, CFL2, and CFL3.

[0142] The overcoat layer OC may be disposed on the color filter layers CFL1, CFL2, CFL3 and the light blocking member BM. The overcoat layer OC may be disposed over the entire display area DPA, and a portion of the overcoat layer OC may be disposed in the non-display area NDA. The overcoat layer OC may include an organic insulating material and protect the members disposed in the display area DPA from the outside.

[0143] The display device 10 according to one embodiment includes color control structures TPL, WCL1, and WCL2 and color filter layers CFL1, CFL2, and CFL3 arranged on the top of the light-emitting element ED, and can display light of different colors even if the same type of light-emitting element ED is arranged in each sub-pixel SPXn.

[0144] For example, the light emitting element ED disposed in the first sub-pixel SPX1 emits blue light of the third color, and the light may pass through the fourth insulating layer PAS4 and enter the first wavelength conversion layer WCL1. The first base resin BRS1 of the first wavelength conversion layer WCL1 is made of a transparent material, and a part of the light may pass through the first base resin BRS1 and enter the first capping layer CPL1 disposed thereon. However, at least a part of the light may be incident on the scatterer SCP and the first wavelength conversion material WCP1 disposed in the first base resin BRS1, and the light may be scattered and converted in wavelength to enter the first capping layer CPL1 as red light. The light incident on the first capping layer CPL1 passes through the low refractive index layer LRL and the second capping layer CPL2 and enters the first color filter layer CFL1, and the first color filter layer CFL1 may block the transmission of light other than red light. Therefore, red light may be emitted from the first sub-pixel SPX1.

[0145] Similarly, light emitted from the light-emitting element ED arranged in the second sub-pixel SPX2 can pass through the fourth insulating layer PAS4, the second wavelength conversion layer WCL2, the first capping layer CPL1, the low refractive layer LRL, the second capping layer CPL2 and the second color filter layer CFL2 and be emitted as green light.

[0146] The light emitting element ED disposed in the third sub-pixel SPX3 emits a third color blue light, which may pass through the fourth insulating layer PAS4 and enter the transparent layer. The third base resin BRS3 of the transparent layer TPL is made of a transparent material, and a part of the light may pass through the third base resin BRS3 and enter the first capping layer CPL1 disposed thereon. The light that enters the first capping layer CPL1 passes through the low refractive layer LRL and the second capping layer CPL2 and enters the third color filter layer CFL3, and the third color filter layer CFL3 can block the transmission of light other than blue light. Therefore, blue light can be emitted from the third sub-pixel SPX3.

[0147] Fig. 7 is a schematic diagram showing banks arranged in a display area and a non-display area of ​​a display device according to an embodiment. Fig. 8 is a cross-sectional view taken along line A1-A1' in Fig. 7. Fig. 9 is a cross-sectional view taken along line A2-A2' in Fig. 7. Fig. 7 shows a planar arrangement of multiple banks BNL1, BNL2, and BNL3 arranged in a display area DPA and a non-display area NDA of a display device 10.

[0148] 8 and 9 show cross sections of a portion of the display area DPA and non-display area NDA in the second direction DR2 in the outer periphery of the display device 10. Fig. 8 shows a left outer periphery, which is one side in the second direction DR2, of the outer periphery of the display device 10, and Fig. 9 shows a right outer periphery, which is the other side in the second direction DR2, of the outer periphery of the display device 10. In Figs. 8 and 9, the multiple conductive layers and semiconductor layers of the display area DPA are simply shown as a circuit layer CCL, and the electrode RME, light emitting element ED, and connecting electrode CNE, etc., arranged in each sub-pixel SPXn are simply shown as a light emitting element layer EDL. The explanation of these structures is the same as that described above with reference to Figs. 2 to 4.

[0149] 7 to 9 in conjunction with FIG. 6, the display device 10 may include a first bank BNL1 including a portion arranged on the outer periphery of the display area DPA, a first valley portion VA1 arranged in the non-display area NDA and surrounding the display area DPA, and a second bank BNL2 and a third bank BNL3.

[0150] The first bank BNL1 may extend in a first direction DR1 and a second direction DR2 in the display area DPA. For example, the first bank BNL1 may be disposed to surround a portion in which a plurality of pixels PX are disposed at an outer periphery of the display area DPA. Although only a portion of the first bank BNL1 disposed at the outermost periphery of the display area DPA is shown in FIG. 7, the first bank BNL1 may be disposed to extend in the first direction DR1 or the second direction DR2 across the display area DPA and may also be disposed at the boundary of each sub-pixel SPXn. The first bank BNL1 may separate the display area DPA and the non-display area NDA, and may also separate different sub-pixels SPXn from each other.

[0151] In the non-display area NDA, a second bank BNL2 and a third bank BNL3 may be arranged, spaced apart from the first bank BNL1 and surrounding the display area DPA. The second bank BNL2 may be arranged spaced apart from the first bank BNL1 at a fixed distance, and the third bank BNL3 may be spaced apart from the second bank BNL2 at a fixed distance. In other words, the display area DPA may be arranged inside the area surrounded by the second bank BNL2, and the second bank BNL2 may be arranged inside the third bank BNL3.

[0152] As described above, the display device 10 may have a structure in which a plurality of layers are sequentially stacked on one first substrate SUB. Some layers of the display device 10 are made of organic materials and may be formed by a process in which the organic materials are directly sprayed onto the first substrate SUB. Since the organic materials have fluidity and may flow, the organic materials sprayed onto the display area DPA may flow and overflow into the non-display area NDA. The second bank BNL2 and the third bank BNL3 may prevent the organic materials from overflowing beyond the non-display area NDA.

[0153] The display device 10 according to the embodiment may include a first valley portion VA1 disposed between the first bank BNL1 and the second bank BNL2 in the non-display area NDA. The second bank BNL2 and the first bank BNL1 have a shape that protrudes upward, while the first valley portion VA1 may be formed by a portion of a lower layer being recessed. The first valley portion VA1 forms an intaglio and embossed pattern together with the second bank BNL2 and the first bank BNL1, and may prevent an organic material sprayed on the display area DPA from overflowing into the non-display area NDA.

[0154] A light emitting element layer EDL including a plurality of electrodes RME, a light emitting element ED, and a connecting electrode CNE is disposed in the display area DPA. The light emitting element layer EDL is disposed on a via layer VIA in the display area DPA, and a plurality of insulating layers PAS_S disposed across the display area DPA and the non-display area NDA may be disposed on the via layer VIA. Although not clearly shown in the drawings, the plurality of insulating layers PAS_S may include a first insulating layer PAS1 disposed under the light emitting element ED, and a second insulating layer PAS2 and a third insulating layer PAS3 disposed over the light emitting element ED. Some of the plurality of insulating layers PAS_S may be sequentially stacked on the via layer VIA in the non-display area NDA.

[0155] The fourth insulating layer PAS4 also covers the light-emitting element layer EDL and may be disposed across the display area DPA and the non-display area NDA. The fourth insulating layer PAS4 may be disposed on the light-emitting element layer EDL in the display area DPA and directly on the other insulating layer PAS_S in the non-display area NDA.

[0156] In addition, the first capping layer CPL1 and the second capping layer CPL2 may also be disposed extending to the non-display area NDA as the sealing structures disposed on the color control structures WCL1, WCL2, and TPL. The first capping layer CPL1 may be partially disposed directly on the fourth insulating layer PAS4, and the other partially disposed directly on the first bank BNL1, the second bank BNL2, and the third bank BNL3. The second capping layer CPL2 is disposed on the first capping layer CPL1 with the low refractive layer LRL interposed therebetween. Unlike the display area DPA, the low refractive layer LRL does not extend over the entire surface of the non-display area NDA, so the second capping layer CPL2 may be partially disposed directly on the first capping layer CPL1.

[0157] As described above, the low refractive layer LRL may be made of an organic material and disposed over the entire surface of the display area DPA. In the process of applying the organic material onto the first capping layer CPL1, the organic material may overflow into the non-display area NDA beyond the first bank BNL1 disposed at the outermost portion of the display area DPA. In particular, the display device 10 may include one first substrate SUB, on which a plurality of layers may be formed by successive processes. In this process, the organic material that overflows into the undesired area of ​​the non-display area NDA may remain as foreign matter in a subsequent process. The display device 10 according to an embodiment includes a structure having an intaglio and embossed pattern shape disposed in the non-display area NDA, thereby preventing the organic material that overflows into the display area NDA from spreading further into the undesired area.

[0158] The display device 10 may include a first valley portion VA1, a second bank BNL2, and a third bank BNL3 disposed in the non-display area NDA. The first valley portion VA1 may have an intaglio pattern shape recessed into the lower surface of the via layer VIA, and the second bank BNL2 and the third bank BNL3 may have relief pattern shapes protruding upward from the upper surface of the via layer VIA.

[0159] The first valley portion VA1 may surround the display area DPA in a plan view and be spaced apart from the first bank BNL1. The first valley portion VA1 may have a first width W1 and may penetrate the first via layer VIA1, and some layers disposed on the via layer VIA may be disposed inside the first valley portion VA1. For example, among the plurality of insulating layers PAS_S disposed directly on the via layer VIA, the first insulating layer PAS1 disposed under the light-emitting element ED may be disposed in the first valley portion VA1 and may directly contact the inner sidewall of the first valley portion VA1 of the via layer VIA. The fourth insulating layer PAS4 disposed on the plurality of insulating layers PAS_S in the non-display area NDA and the first capping layer CPL1, a portion of which is disposed directly on the fourth insulating layer PAS4, may also be partially disposed inside the first valley portion VA1. The insulating layers PAS_S, the fourth insulating layer PAS4, and the first capping layer CPL1 may include an inorganic insulating material, and may be disposed along the step formed by the first valley portion VA1 in the via layer VIA. By disposing the same inorganic insulating material as the insulating layers PAS_S, the fourth insulating layer PAS4, and the first capping layer CPL1 in the first valley portion VA1, it is possible to prevent external moisture from penetrating into the circuit layer CCL exposed by the first valley portion VA1.

[0160] The low refractive layer LRL may be disposed on the first capping layer CPL1, and a portion of the low refractive layer LRL may be disposed in the non-display area NDA beyond the first bank BNL1. The low refractive layer LRL may also be disposed on the first valley portion VA1, and a portion of the low refractive layer LRL may be disposed so as to fill the step formed by the first valley portion VA1. In the process of forming the low refractive layer LRL, the organic material constituting the low refractive layer LRL may fill the step formed by the first valley portion VA1 while flowing beyond the display area DPA into the non-display area NDA, and the first valley portion VA1 may prevent the organic material from overflowing excessively. The low refractive layer LRL may be disposed up to the second bank BNL2 while filling the first valley portion VA1.

[0161] The second bank BNL2 and the third bank BNL3 may be spaced apart from each other and may surround and be spaced apart from the first valley portion VA1. The first valley portion VA1, the second bank BNL2, and the third bank BNL3 may be sequentially spaced apart from each other along a direction toward the outer edge of the non-display area NDA based on the first bank BNL1. Unlike the first valley portion VA1, the second bank BNL2 and the third bank BNL3 may be directly disposed on the fourth insulating layer PAS4 and have a shape that protrudes upward. The second bank BNL2 and the third bank BNL3 have a relief pattern shape, thereby preventing the low refractive layer LRL from overflowing to the outer edge of the non-display area NDA.

[0162] According to an embodiment, the widths of the second bank BNL2 and the third bank BNL3 may be the same, and the first width W1 of the first valley portion VA1 may be larger than the second width W2 of the second bank BNL2 and the third bank BNL3 in the cross-sectional view. The second bank BNL2 and the third bank BNL3 may be formed in the same process after forming the light-emitting element layer EDL and the fourth insulating layer PAS4 in the display area DPA. The second bank BNL2 and the third bank BNL3 may differ from each other only in their positions, and may have the same shape and material, and in particular may have the same width W2 in the cross-sectional view.

[0163] The first valley portion VA1 may be disposed closer to the display area DPA than the second bank BNL2 and the third bank BNL3, and may be a primary structure for preventing overflow of the low refractive layer LRL. The first valley portion VA1 may have a width larger than the second bank BNL2 and the third bank BNL3 to prevent overflow of the organic material of the low refractive layer LRL to the maximum extent. The second bank BNL2 and the third bank BNL3 have a width smaller than the first valley portion VA1, but have a certain width and a embossed pattern shape, thereby preventing the organic material from overflowing beyond the first valley portion VA1 to the outermost side of the non-display area NDA.

[0164] In addition, the first bank BNL1 may be formed in the same process as the second bank BNL2 and the third bank BNL3. The first bank BNL1 may be directly disposed on the fourth insulating layer PAS4 by overlapping with the lower bank layer LBN, and may surround the innermost portion of the display area DPA and be disposed in a lattice pattern on the inner side. However, according to an embodiment, the third width W3, which is the width in a cross-sectional view of the first bank BNL1, may be equal to or smaller than the second width W2 of the second bank BNL2. The first bank BNL1 may separate the sub-pixels SPXn adjacent to each other in the display area DPA and form a space in which the color control structures TPL, WCL1, and WCL2 are disposed. The second bank BNL2 and the third bank BNL3 are structures for preventing overflow of the low refractive layer LRL, and their uses may be different from those of the first bank BNL1. That is, the first bank BNL1, the second bank BNL2, and the third bank BNL3 are disposed directly on the fourth insulating layer PAS4, and therefore may be formed by the same process or may have different widths depending on their functions. As structures for preventing overflow of organic materials, the second bank BNL2 and the third bank BNL3 disposed in the non-display area NDA may have the same or larger width than the first bank BNL1.

[0165] The overcoat layer OC is disposed in the display area DPA to cover the color filter layer CFL and the light blocking member BM, and a portion of the overcoat layer OC may also be disposed in the non-display area NDA. Similar to the low refractive layer LRL, the overcoat layer OC may be made of an organic material, which may cause an overflow problem on the color filter layer CFL and the second capping layer CPL2. The display device 10 according to the embodiment may further include color dams CBN1 and CBN2 disposed on the second bank BNL2 and the third bank BNL3 as structures for preventing overflow of the overcoat layer OC.

[0166] The color dams CBN1, CBN2 may be disposed on the second bank BNL2 and the third bank BNL3, respectively. The color dams CBN1, CBN2 may be disposed on one of the second bank BNL2 and the third bank BNL3 at a left outer portion and a right outer portion, which are both sides in the second direction DR2, of the outer portion of the display device 10. For example, the color dams CBN1, CBN2 may include a plurality of first color dams CBN1 disposed on the second bank BNL2 and the third bank BNL3 of the left outer portion (shown in FIG. 8) of the display device 10, and a plurality of second color dams CBN2 disposed on the second bank BNL2 and the third bank BNL3 of the right outer portion (shown in FIG. 9) of the display device 10. Adjacent color dams CBN1 and CBN2 in the outer periphery of one side of the display device 10 may be spaced apart from each other in the second direction DR2, and each color dam CBN1 and CBN2 may be disposed to extend in the first direction DR1 on the second bank BNL2 or the third bank BNL3. The multiple color dams CBN1 and CBN2 may form a linear pattern in the non-display area NDA.

[0167] Just as the second bank BNL2 and the third bank BNL3 each prevent the low refractive layer LRL arranged under the second capping layer CPL2 from overflowing into the non-display area NDA, the color dams CBN1 and CBN2 can prevent the overcoat layer OC arranged on the second capping layer CPL2 from overflowing into the non-display area NDA. The color dams CBN1 and CBN2 are each disposed directly on the second capping layer CPL2 and can have a embossed pattern having a certain thickness and a certain width.

[0168] In an embodiment, the first color dam CBN1 and the second color dam CBN2 may each have a width measured in the second direction DR2 smaller than the second width W2 of the second bank BNL2, and may also have a thickness smaller than the second bank BNL2. The color dams CBN1 and CBN2 may have a size for preventing an organic material from overflowing from a layer disposed on the second capping layer CPL2. The second bank BNL2 and the third bank BNL3 disposed under the second capping layer CPL2 are structures for preventing the low refractive layer LRL and the overcoat layer OC from overflowing, while the color dams CBN1 and CBN2 may have a relatively small size as structures for preventing the overcoat layer OC from overflowing.

[0169] According to an embodiment, the color dams CBN1, CBN2 may be formed in the same process as a part of the color filter layers CFL1, CFL2, CFL3, including the same material. Since the color dams CBN1, CBN2 and the color filter layers CFL1, CFL2, CFL3 are disposed directly on the second capping layer CPL2, they may be formed in the same process if they include the same material. However, the color dams CBN1, CBN2 and the color filter layers CFL1, CFL2, CFL3 may be disposed in different regions and perform different roles, and may be disposed in different planes. For example, the color filter layers CFL1, CFL2, CFL3 may be disposed in the light-transmitting regions TA1, TA2, TA3 of the display device 10 and formed in a linear or island pattern, and the color dams CBN1, CBN2 may be disposed in the non-display region NDA and formed in a linear pattern.

[0170] According to an embodiment, the first color dam CBN1 disposed on the left outer edge of the display device 10 may include a different material from the second color dam CBN2 disposed on the right outer edge. The first color dam CBN1 may include the same material as the first color filter layer CFL1, and the second color dam CBN2 may include the same material as the third color filter layer CFL3. In the display device 10, one pixel PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3, which may be sequentially arranged in a second direction DR2. In the display area DPA of the display device 10, a plurality of pixels PX may be arranged in the first direction DR1 and the second direction DR2, and the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may also be repeatedly arranged in the first direction DR1 and the second direction DR2. The first, second and third subpixels SPX1, SPX2 and SPX3 arranged in the display area DPA are arranged in equal numbers and, when they are repeatedly arranged in the second direction DR2, the subpixel SPXn arranged most adjacent to the left non-display area NDA of the display area DPA may be the first subpixel SPX1, and the subpixel SPXn arranged most adjacent to the right non-display area NDA may be the third subpixel SPX3. Correspondingly, a first color filter layer CFL1 may be arranged on the subpixel SPXn arranged most adjacent to the left non-display area NDA of the display area DPA, and a third color filter layer CFL3 may be arranged on the subpixel SPXn arranged most adjacent to the right non-display area NDA.

[0171] As described above, the color dams CBN1, CBN2 may be formed in the same process using the same material as any one of the color filter layers CFL1, CFL2, CFL3. The first color dam CBN1 disposed on the left outer edge may include the same material as the color filter layer disposed closest thereto, for example, the first color filter layer CFL1, and the second color dam CBN2 disposed on the right outer edge may include the same material as the color filter layer disposed closest thereto, for example, the third color filter layer CFL3.

[0172] FIG. 10 is a schematic diagram showing an arrangement of color filter layers and color dams in a display device according to an embodiment.

[0173] 10 in conjunction with FIGS. 7 to 9, the display area DPA of the display device 10 may include a plurality of areas AA1, AA2, and AA3, and the non-display area NDA may include a plurality of dam areas DMA1 and DMA2. For example, the display device 10 may include a first dam area DMA1 disposed on the left side, which is one side in the second direction DR2, of the non-display area NDA, and a second dam area DMA2 disposed on the right side, which is the other side in the second direction DR2. The display area DPA may include a first area AA1 and a second area AA2 disposed on the outermost side in the second direction DR2 of the display area DPA, and a plurality of third areas AA3 that are inner areas between the first area AA1 and the second area AA2, as a plurality of areas AA1, AA2, and AA3 divided according to areas where the same color filter layers CFL1, CFL2, and CFL3 are repeatedly arranged. A plurality of color filter layers CFL1, CFL2, CFL3 may be arranged in the first area AA1, the second area AA2, and the third area AA3, respectively, and different color dams CBN1, CBN2 may be arranged in the first dam area DMA1 and the second dam area DMA2, respectively.

[0174] In the first area AA1, the second area AA2, and the third area AA3, a first color filter layer CFL1, a second color filter layer CFL2, and a third color filter layer CFL3 may be sequentially arranged in the second direction DR2. The different areas AA1, AA2, and AA3 may be areas divided according to areas where the repeatedly arranged color filter layers CFL1, CFL2, and CFL3 are arranged. Each of the areas AA1, AA2, and AA3 may be an area where a pair of a first color filter layer CFL1, a second color filter layer CFL2, and a third color filter layer CFL3 is arranged, and among them, the first area AA1 and the second area AA2 may be areas arranged on the outermost side in the second direction DR2 of the display area DPA, and the third area AA3 may be an area arranged on the inner side.

[0175] The first dam region DMA1 may be disposed in the left non-display region NDA and adjacent to the first region AA1 of the display region DPA. The color filter layer disposed on the left side of the first region AA1 is the first color filter layer CFL1, and the first color dams CBN1 disposed in the first dam region DMA1 may each include the same material as the first color filter layer CFL1. The second dam region DMA2 may be disposed in the right non-display region NDA and adjacent to the second region AA2 of the display region DPA. The color filter layer disposed on the right side of the second region AA2 is the third color filter layer CFL3, and the second color dams CBN2 disposed in the second dam region DMA2 may each include the same material as the third color filter layer CFL3. In the manufacturing process of the display device 10, the first color dam CBN1 disposed in the first dam region DMA1 may be formed in the same process as the first color filter layer CFL1 disposed in the first region AA1, and the second color dam CBN2 disposed in the second dam region DMA2 may be formed in the same process as the third color filter layer CFL3 disposed in the second region AA2.

[0176] In an exemplary embodiment, the color filter layers CFL1, CFL2, and CFL3 and the color dams CBN1 and CBN2 may be formed by a patterning process using a mask. Since the color filter layers CFL1, CFL2, and CFL3 and the color dams CBN1 and CBN2 include different materials, they may be formed by different mask processes. For example, the display device 10 may first form the first color filter layer CFL1, and then form the second color filter layer CFL2 in another process, and form the third color filter layer CFL3 in another process.

[0177] Also, each of the color filter layers CFL1, CFL2, and CFL3 may be formed in a plurality of processes rather than in a single process over the entire surface of the display device 10. Some of the first color filter layers CFL1 disposed in the plurality of regions AA1, AA2, and AA3 of the display region DPA may be formed in different processes. The first color filter layer CFL1 disposed in the first region AA1 and a portion of the third region AA3 may be formed in a different process from the first color filter layer CFL1 disposed in the other portion of the third region AA3, and the first color filter layer CFL1 disposed in the other third region AA3 and the second region AA2. Similarly, the second color filter layer CFL2 and the third color filter layer CFL3 disposed in the plurality of regions AA1, AA2, and AA3 may be formed in different mask processes.

[0178] According to an embodiment, the color dams CBN1, CBN2 may be formed together with the corresponding color filter layers CFL1, CFL2, CFL3 in a mask process for forming the color filter layers CFL1, CFL2, CFL3 arranged in the outermost region of the display area DPA among a plurality of mask processes for forming the color filter layers CFL1, CFL2, CFL3. For example, the first color dam CBN1 may be formed together with the first color filter layer CFL1 in a mask process for forming the first color filter layer CFL1 arranged in the first region AA1, and the second color dam CBN2 may be formed together with the third color filter layer CFL3 in a mask process for forming the third color filter layer CFL3 arranged in the second region AA2.

[0179] Fig. 11 is a schematic view showing an area where a mask process is performed for forming a first color filter layer and a first color dam in a display device according to an embodiment, Fig. 12 is a schematic view showing an area where a mask process is performed for forming a second color filter layer in a display device according to an embodiment, and Fig. 13 is a schematic view showing an area where a mask process is performed for forming a third color filter layer and a second color dam in a display device according to an embodiment.

[0180] 11 to 13, a plurality of mask processes may be performed to form different color filter layers CFL1, CFL2, and CFL3 in the display device 10. In some of the processes for forming the color filter layers CFL1, CFL2, and CFL3, color dams CBN1 and CBN2 of dam regions DMA1 and DMA2 may be formed together with the color filter layers CFL1, CFL2, and CFL3.

[0181] A plurality of mask processes for forming the first color filter layer CFL1 may be performed over the first dam region DMA1 and the display region DPA. In the plurality of mask processes, a first mask process may be performed on the first mask region MLR1 including the first dam region DMA1 and a portion of the first region AA1. In the first mask process, the first color dam CBN1 in the first dam region DMA1 and the first color filter layer CFL1 in the first region AA1 may be formed simultaneously. Subsequent second to fourth mask processes may be performed on the second mask region MLR2, the third mask region MLR3, and the fourth mask region MLR4 including the regions in which the first color filter layer CFL1 is disposed in the other regions AA2 and AA3 except for the first region AA1 from the display region DPA, respectively.

[0182] Similarly, a plurality of mask processes for forming the third color filter layer CFL3 may be performed across the second dam region DMA2 and the display region DPA. In the plurality of mask processes, a fourth mask process may be performed on a fourth mask region MLB4 including the second dam region DMA2 and a portion of the second region AA2. In the fourth mask process, the second color dam CBN2 in the second dam region DMA2 and the third color filter layer CFL3 in the second region AA2 may be formed simultaneously. The previous first to third mask processes may be performed on the first mask region MLB1, the second mask region MLB2, and the third mask region MLB3 including the regions where the third color filter layer CFL3 is to be disposed in the other regions AA1 and AA3 except for the second region AA2 from the display region DPA, respectively.

[0183] On the other hand, the mask process for forming the second color filter layer CFL2 may be performed only in the display region DPA. In the mask process, the first to third mask processes may be performed in the first mask region MLG1, the second mask region MLG2, and the third mask region MLG3 including the regions in which the second color filter layer CFL2 is disposed in the first to third regions AA1 to AA3, respectively.

[0184] In an embodiment, the mask regions where the mask processes are performed may have the same area. For example, the first to fourth mask regions MLR1, MLR2, MLR3, and MLR4 where the mask processes for forming the first color filter layer CFL1 are performed may have the same width. The first to fourth mask regions MLR1, MLR2, MLR3, and MLR4 may have a width that divides the first dam region DMA1 and the display region DPA at equal intervals. Similarly, the first to fourth mask regions MLB1, MLB2, MLB3, and MLB4 where the mask processes for forming the third color filter layer CFL3 are performed may have the same width. The first to fourth mask regions MLB1, MLB2, MLB3, and MLB4 may have a width that divides the second dam region DMA2 and the display region DPA at equal intervals. On the other hand, the first to third mask regions MLG1, MLG2, and MLG3 in which a mask process for forming the second color filter layer CFL2 is performed may have widths that divide the display region DPA at equal intervals.

[0185] As described above, a plurality of color filter layers CFL1, CFL2, CFL3 are repeatedly arranged in each of the areas AA1, AA2, AA3 of the display area DPA, and the masking processes for forming these layers can be performed in mask areas having the same width using mask layers having the same width. In addition to forming the color filter layers CFL1, CFL2, CFL3 in the display area DPA, in order to form color dams CBN1, CBN2 containing the same material as the color filter layers CFL1, CFL2, CFL3 in the dam areas DMA1, DMA2, it may be necessary to design the mask areas and mask layers in which each masking process is performed.

[0186] In the display device 10, the color dams CBN1, CBN2 disposed in the first dam region DMA1 and the second dam region DMA2 may be formed by a process for forming different color filter layers CFL1, CFL2, CFL3, respectively. In order to form the different color dams CBN1, CBN2, the process for forming the first color filter layer CFL1 and the third color filter layer CFL3 may include one more mask process than the process for forming the second color filter layer CFL2. In the display device 10 according to the embodiment, the color filter layers CFL1, CFL2, CFL3 and the color dams CBN1, CBN2 may be formed by adding a minimum number of mask processes, thereby reducing the number of manufacturing processes.

[0187] Other embodiments of the display device 10 will be described below with reference to other drawings.

[0188] 14 is a cross-sectional view of a display device according to another embodiment of the present invention, and FIG 15 is a cross-sectional view of an outer periphery of the display device of FIG 14. As shown in FIG.

[0189] 14 and 15, a display device 10_1 according to an embodiment may further include a planarization layer PNL disposed on the second capping layer CPL2. This embodiment differs from the embodiment of FIGS. 6 and 8 in that the display device 10_1 further includes a planarization layer PNL. Hereinafter, a description of the overlapping contents will be omitted and differences will be mainly described.

[0190] The planarization layer PNL may be disposed over the entire surface of the display area DPA and the non-display area NDA on the second capping layer CPL2. The planarization layer PNL may overlap the color control structures TPL, WCL1, and WCL2 in the display area DPA, and may also be disposed over the second bank BNL2 and the third bank BNL3 in the non-display area NDA. The light blocking member BM, the multiple color filter layers CFL1, CFL2, and CFL3, and the color dams CBN1 and CBN2 may be disposed directly on the planarization layer PNL, respectively.

[0191] The planarization layer PNL can protect members arranged on the first substrate SUB in addition to the plurality of capping layers CPL1, CPL2 and the low refractive layer LRL, and can partially compensate for steps caused by these. In particular, the planarization layer PNL compensates for steps formed by the color control structures TPL, WCL1, WCL2 and the first bank BNL1 thereunder in the display area DPA, and the light blocking member BM and the color filter layers CFL1, CFL2, CFL3 arranged thereon can be formed on a flat surface.

[0192] FIG. 16 is a cross-sectional view showing an outer periphery of a display device according to another embodiment.

[0193] 16, a display device 10_2 according to an embodiment may further include a third color dam CBN3 disposed on each of the first color dams CBN1. This embodiment differs from the embodiment of FIG. 15 in that the display device 10_2 further includes a third color dam CBN3 covering the first color dam CBN1. Hereinafter, a description of the overlapping contents will be omitted and differences will be mainly described.

[0194] The third color dam CBN3 may be disposed on the first color dam CBN1. The third color dam CBN3 may be disposed on the second bank BNL2 and the third bank BNL3 in the left outer periphery of the display device 10 or in the first dam region DMA1. Although not shown in the drawings, the third color dam CBN3 may also be disposed in the first dam region DMA1 to extend in the first direction DR1, and adjacent third color dams CBN3 may be spaced apart from each other in the second direction DR2.

[0195] The third color dam CBN3 may be formed to have a width greater than that of the first color dam CBN1 and completely cover the outer surface of the first color dam CBN1, but is not limited thereto. The third color dam CBN3 may have a width equal to or smaller than that of the first color dam CBN1, and the third color dam CBN3 may be disposed only on the upper surface of the first color dam CBN1. In this case, the side surface of the first color dam CBN1 may be exposed.

[0196] According to one embodiment, the third color dam CBN3 may include the same material as the second color filter layer CFL2. Like the first color dam CBN1, the third color dam CBN3 may be formed together with the second color filter layer CFL2 disposed in the first area AA1 during the process of forming the second color filter layer CFL2.

[0197] The second color dam CBN2 may contain a blue color material as the same material as the third color filter layer CFL3. The second color dam CBN2 containing the blue color material can absorb a part of the reflected light due to the light incident from the outside and reduce the reflected light due to the external light. Similarly, the first color dam CBN1 and the third color dam CBN3 may contain a red color material and a green color material as the same material as the first color filter layer CFL1 and the second color filter layer CFL2, respectively. The first color dam CBN1 and the third color dam CBN3 are stacked on each other in the thickness direction and can absorb a part of the reflected light due to the light incident from the outside and reduce the reflected light due to the external light, similar to the second color dam CBN2 containing the blue color material.

[0198] 17 is a schematic diagram showing an arrangement of color filter layers and color dams in a display device according to another embodiment, and FIGS. 18 and 19 are cross-sectional views showing an outer periphery of the display device of FIG.

[0199] 17 to 19, in a display device 10_3 according to an embodiment, the first color dam CBN1 may include the same material as the third color filter layer CFL3, and the second color dam CBN2 may include the same material as the first color filter layer CFL1. This embodiment differs from the embodiment of FIGS. 8 to 13 in that the first color dam CBN1 and the second color dam CBN2 include opposite materials. Hereinafter, a description of the overlapping contents will be omitted, and the differences will be mainly described.

[0200] 8 to 13, the first color dam CBN1 may include the same material as the most adjacent first color filter layer CFL1 among the color filter layers CFL1, CFL2, and CFL3 in the first area AA1, and the second color dam CBN2 may include the same material as the most adjacent third color filter layer CFL3 among the color filter layers CFL1, CFL2, and CFL3 in the second area AA2. However, this is not limited thereto, and when the first color dam CBN1 and the second color dam CBN2 include different materials, it does not matter which color filter layer CFL1, CFL2, or CFL3 they include the same material as.

[0201] For example, the first color dam CBN1 may include the same material as the third color filter layer CFL3, which is the most distant among the color filter layers CFL1, CFL2, and CFL3 in the first region AA1, and the second color dam CBN2 may include the same material as the first color filter layer CFL1, which is the most distant among the color filter layers CFL1, CFL2, and CFL3 in the second region AA2. In the display device 10_3 of the present embodiment, in the mask process for forming each color filter layer CFL1, CFL2, and CFL3, the mask regions in which the repeated processes are performed may have the same width, and the color dams CBN1 and CBN2 that can prevent the overflow of the organic material may be formed by adding the minimum number of processes. The detailed description regarding this is the same as above.

[0202] 20 is a cross-sectional view of a display device according to another embodiment of the present invention, and FIG 21 is a cross-sectional view showing an outer periphery of the display device of FIG 20. As shown in FIG.

[0203] 20 and 21, a display device 10_4 according to an embodiment may be configured with a plurality of color patterns CP1, CP2, and CP3, without the light blocking member BM. This embodiment differs from the embodiment of FIG. 14 in that the light blocking member BM is replaced with the color patterns CP1, CP2, and CP3.

[0204] The color patterns CP1, CP2, and CP3 may be formed in a lattice pattern substantially the same as the light blocking member BM in Fig. 14. However, the color patterns CP1, CP2, and CP3 may be formed integrally with the color filter layers CFL1, CFL2, and CFL3 by using the same material. Different color patterns CP1, CP2, and CP3 are stacked on top of each other in the light blocking area BA, and light transmission may be blocked in the stacked area.

[0205] The first color pattern CP1 may include the same material as the first color filter layer CFL1 and may be disposed in the light blocking area BA. The first color pattern CP1 may be disposed directly on the second capping layer CPL2 in the light blocking area BA, and may be integrated with the first color filter layer CFL1 in the light blocking area BA adjacent to the first light-transmitting area TA1 of the first sub-pixel SPX1.

[0206] The second color pattern CP2 may include the same material as the second color filter layer CFL2 and may be disposed in the light-shielding region BA. The second color pattern CP2 may be disposed directly on the first color pattern CP1 in the light-shielding region BA and may be integrated with the second color filter layer CFL2 in the light-shielding region BA adjacent to the second light-transmitting region TA2 of the second sub-pixel SPX2. Similarly, the third color pattern CP3 may include the same material as the third color filter layer CFL3 and may be disposed in the light-shielding region BA. The third color pattern CP3 may be disposed directly on the second color pattern CP2 in the light-shielding region BA and may be integrated with the third color filter layer CFL3 in the light-shielding region BA adjacent to the third light-transmitting region TA3 of the third sub-pixel SPX3.

[0207] In the display device 10_4, the first color pattern CP1, the second color pattern CP2, and the third color pattern CP3 may be arranged to overlap at least one of the color filter layers CFL1, CFL2, and CFL3 containing different color materials in the region overlapping the first bank BNL1. For example, the first color pattern CP1 may be arranged to overlap the second color filter layer CFL2 and the third color filter layer CFL3, the second color pattern CP2 may be arranged to overlap the first color filter layer CFL1 and the third color filter layer CFL3, and the third color pattern CP3 may be arranged to overlap the first color filter layer CFL1 and the second color filter layer CFL2. The region overlapping the first bank BNL1 can function as a light blocking member BM by the color patterns CP1, CP2, and CP3 and the color filter layers CFL1, CFL2, and CFL3 containing different color materials overlapping each other.

[0208] The first color dams CBN1 may be formed in the same process as the first color pattern CP1 and may have the same shape as the first color pattern CP1. The first color dams CBN1 may have substantially the same shape as the first color pattern CP1 disposed between the second color filter layer CFL2 and the third color filter layer CFL3. The second color dams CBN2 may be formed in the same process as the third color pattern CP3 and may have the same shape as the third color pattern CP3 disposed on the second color pattern CP2.

[0209] The display device 10_4 according to the present embodiment has a structure in which a plurality of color patterns CP1, CP2, and CP3 are stacked, and serves the same role as the light blocking member BM, thereby preventing color mixing between adjacent regions due to materials containing different color materials. In addition, the color patterns CP1, CP2, and CP3 contain the same material as the color filter layers CFL1, CFL2, and CFL3, so that the external light or reflected light transmitted through the light blocking region BA can have a specific color wavelength band. The eye color sensibility of the user's eyes varies depending on the color of light, and in particular, light in the blue wavelength band is less sensitively recognized by the user than light in the green wavelength band and light in the red wavelength band. By omitting the light blocking member BM in the light blocking region BA and disposing the color patterns CP1, CP2, and CP3, the light transmission is blocked, and at the same time, the sensitivity of the reflected light recognized by the user is relatively low, and a part of the light flowing in from the outside of the display device 10 can be absorbed to reduce the reflected light due to the external light.

[0210] 22 and 23 are cross-sectional views showing an outer periphery of a display device according to another embodiment.

[0211] 22, the display device 10_5 according to an embodiment may further include a plurality of bank partitions BMW disposed between the first bank BNL1 and the first valley portion VA1. The plurality of bank partitions BMW are structures forming a relief pattern, and together with the first bank BNL1, the first valley portion VA1, the second bank BNL2, and the third bank BNL3, may prevent the organic material of the low refractive layer LRL from overflowing. This embodiment differs from the embodiments of FIGS. 14 and 15 in that it further includes a plurality of bank partitions BMW disposed in the non-display area NDA. Hereinafter, a duplicated description will be omitted, and the differences will be mainly described.

[0212] A plurality of bank partitions BMW may be disposed between the first bank BNL1 and the first valley portion VA1. The first valley portion VA1 may be disposed closer to the second bank BNL2 than to the first bank BNL1, and a plurality of bank partitions BMW may be disposed therebetween to more effectively prevent overflow of organic materials.

[0213] Although not shown in the drawings, the bank partitions BMW may be disposed spaced apart from and surrounding the first bank BNL1, similar to the second bank BNL2. Different bank partitions BMW may be disposed spaced apart from each other, and the bank partitions BMW disposed on the outer side may surround the bank partitions BMW disposed on the inner side.

[0214] The bank partitions BMW may be formed in the same process as the second bank BNL2. The bank partitions BMW may be disposed directly on the fourth insulating layer PAS4, and the first capping layer CPL1 may be disposed directly on the bank partitions BMW. The bank partitions BMW may be disposed in the non-display area NDA between the first bank BNL1 and the first valley portion VA1, and may partially overlap the light blocking member BM. The bank partitions BMW may have a relief pattern shape protruding upward on the via layer VIA, and may prevent the organic material of the low refractive layer LRL from overflowing together with the first valley portion VA1.

[0215] The bank partitions BMW may have a width smaller than the other banks BNL1, BNL2, and BNL3. The bank partitions BMW may be disposed in a relatively narrow region between the first valley portion VA1 and the first bank BNL1. The bank partitions BMW are formed in the same process as the second bank BNL2, but the size of the bank partitions BMW may be adjusted according to the space of the display device 10_5.

[0216] 23, in a display device 10_6 according to an embodiment, the first bank BNL1, the second bank BNL2, and the third bank BNL3 may each include a plurality of layers BNL_L, BNL_U. The first bank BNL1, the second bank BNL2, and the third bank BNL3 may each include a base layer BNL_L and an upper layer BNL_U disposed on the base layer BNL_L. Different from the embodiment of FIG. 8 and FIG. 9, in this embodiment, the plurality of color control structures TPL, WCL1, and WCL2 are formed by a photoresist process, and the plurality of banks BNL1, BNL2, and BNL3 may have a relatively low height.

[0217] The base layer BNL_L of the first bank BNL1, the second bank BNL2 and the third bank BNL3 may be disposed directly on the fourth insulating layer PAS4, and the top layer BNL_U may be disposed directly on the base layer BNL_L. The top layer BNL_U may be formed to have a width greater than the base layer BNL_L to completely cover the outer surface of the base layer BNL_L. However, this is not limited to this. The top layer BNL_U may have the same width as the base layer BNL_L or a width smaller than the base layer BNL_L, and the top layer BNL_U may be disposed only on the upper surface of the base layer BNL_L. In this case, the side surface of the base layer BNL_L may be exposed.

[0218] In one embodiment, the display device 10_6 has color control structures TPL, WCL1, and WCL2 formed by a photoresist process, and the first bank BNL1, the second bank BNL2, and the third bank BNL3 may have a structure in which a base layer BNL_L and an upper layer BNL_U are stacked. Unlike the embodiment of Figures 8 and 9, the first bank BNL1, the second bank BNL2, and the third bank BNL3 may have a relatively low height, and each layer of the color control structures TPL, WCL1, and WCL2 may be formed with a flat upper surface. The upper surfaces of the color control structures TPL, WCL1, and WCL2 may be formed parallel to the upper surface of the first bank BNL1.

[0219] Fig. 24 is a plan view illustrating a sub-pixel of a display device according to another embodiment, Fig. 25 is a cross-sectional view taken along line N3-N3' in Fig. 24, and Fig. 26 is a cross-sectional view taken along line N4-N4' in Fig. 24.

[0220] Fig. 24 shows a planar arrangement of electrodes (RME; RME1, RME2, RME3, RME4), bank patterns BP1, BP2, BP3 and a lower bank layer LBN, a plurality of light-emitting elements ED, and connecting electrodes (CNE; CNE1, CNE2, CNE3, CNE4, CNE5) arranged in one pixel PX of the display device 10. Fig. 25 shows a cross section across both ends of light-emitting elements (ED; ED1, ED2, ED3, ED4) arranged on different electrodes RME, and Fig. 26 shows a cross section across a plurality of contact portions CT1, CT2, CT3, CT4.

[0221] 24 to 26, the display device 10 according to an embodiment may include a greater number of electrodes (RME; RME1, RME2, RME3, RME4), bank patterns BP1, BP2, BP3, light emitting elements (ED; ED1, ED2, ED3, ED4), and connecting electrodes (CNE; CNE1, CNE2, CNE3, CNE4, CNE5). The display device 10 according to the present embodiment differs from the embodiment of FIG. 4 in that it includes a greater number of electrodes and light emitting elements per sub-pixel SPXn. Below, overlapping content will be omitted and differences will be mainly described.

[0222] The bank patterns BP1, BP2, and BP3 may further include a third bank pattern BP3 disposed between the first bank pattern BP1 and the second bank pattern BP2. The first bank pattern BP1 may be disposed to the left of the center of the light emitting area EMA, the second bank pattern BP2 may be disposed to the right of the center of the light emitting area EMA, and the third bank pattern BP3 may be disposed at the center of the light emitting area EMA. The third bank pattern BP3 may have a width measured in the second direction DR2 larger than that of the first bank pattern BP1 and the second bank pattern BP2. The interval between each of the bank patterns BP1, BP2, and BP3 in the second direction DR2 may be larger than the interval between each of the electrodes RME. The first bank pattern BP1 may be disposed to partially overlap the first electrode RME1, and the second bank pattern BP2 may be disposed to partially overlap the fourth electrode RME4. The third bank pattern BP3 may be disposed to partially overlap the second electrode RME2 and the third electrode RME3. Each electrode RME can be arranged so that at least a portion of it does not overlap with the bank patterns BP1, BP2, and BP3.

[0223] The multiple electrodes RME arranged for each sub-pixel SPXn may further include a third electrode RME3 and a fourth electrode RME4 in addition to the first electrode RME1 and the second electrode RME2.

[0224] The third electrode RME3 may be disposed between the first electrode RME1 and the second electrode RME2, and the fourth electrode RME4 may be disposed spaced apart from the third electrode RME3 in the second direction DR2 with the second electrode RME2 therebetween. The plurality of electrodes RME may be sequentially disposed from the left side to the right side of the subpixel SPXn, including the first electrode RME1, the third electrode RME3, the second electrode RME2, and the fourth electrode RME4. The electrodes RME may face each other at a distance in the second direction DR2. The plurality of electrodes RME may be spaced apart from the electrodes RME of other subpixels SPXn adjacent to each other in the first direction DR1 by the separation portion ROP of the subregion SA.

[0225] Of the multiple electrodes RME, the first electrode RME1 and the second electrode RME2 are in contact with the lower first conductive pattern CDP1 and the second voltage wiring VL2 via electrode contact holes CTD, CTS arranged in the lower part of the lower bank layer LBN, respectively, whereas the third electrode RME3 and the fourth electrode RME4 do not have to be in contact with each other.

[0226] The first insulating layer PAS1 may be disposed in a similar structure to the above-described embodiment. The first insulating layer PAS1 may be disposed over the entire display area DPA and cover the electrodes RME and the bank patterns BP1, BP2, and BP3.

[0227] The light-emitting elements ED may be disposed between the bank patterns BP1, BP2, and BP3, or on different electrodes RME. Some of the light-emitting elements ED may be disposed between the first bank pattern BP1 and the third bank pattern BP3, and other parts may be disposed between the third bank pattern BP3 and the second bank pattern BP2. According to an embodiment, the light-emitting elements ED may include a first light-emitting element ED1 and a third light-emitting element ED3 disposed between the first bank pattern BP1 and the third bank pattern BP3, and a second light-emitting element ED2 and a fourth light-emitting element ED4 disposed between the third bank pattern BP3 and the second bank pattern BP2. The first light-emitting element ED1 and the third light-emitting element ED3 may be disposed on the first electrode RME1 and the third electrode RME3, respectively, and the second light-emitting element ED2 and the fourth light-emitting element ED4 may be disposed on the second electrode RME2 and the fourth electrode RME4, respectively. The first light-emitting element ED1 and the second light-emitting element ED2 may be arranged adjacent to the lower side of the light-emitting region EMA of the corresponding sub-pixel SPXn or adjacent to the sub-region SA, and the third light-emitting element ED3 and the fourth light-emitting element ED4 may be arranged adjacent to the upper side of the light-emitting region EMA of the corresponding sub-pixel SPXn.

[0228] However, each light emitting device ED may be classified not according to the position where it is arranged in the light emitting area EMA, but according to the connection relationship with the connecting electrode CNE described later. Each light emitting device ED may contact different connecting electrodes CNE at both ends depending on the arrangement structure of the connecting electrodes CNE, and may be classified into different light emitting devices ED depending on the type of the connecting electrodes CNE that it contacts.

[0229] The multiple connecting electrodes CNE may further include a first connecting electrode CNE1 arranged on the first electrode RME1 and a second connecting electrode CNE2 arranged on the second electrode RME2, as well as a third connecting electrode CNE3, a fourth connecting electrode CNE4 and a fifth connecting electrode CNE5 arranged across the multiple electrodes RME.

[0230] Unlike the embodiment of FIGS. 4 to 6, the first connecting electrode CNE1 and the second connecting electrode CNE2 may each have a relatively short length extending in the first direction DR1. The first connecting electrode CNE1 and the second connecting electrode CNE2 may be disposed on the lower side with respect to the center of the light emitting region EMA. The first connecting electrode CNE1 and the second connecting electrode CNE2 may be disposed across the light emitting region EMA and the sub-region SA of the corresponding sub-pixel SPXn, and may directly contact the electrode RME through contact portions CT1 and CT2 formed in the sub-region SA. The first connecting electrode CNE1 may directly contact the first electrode RME1 through a first contact portion CT1 penetrating the first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 in the sub-region SA, and the second connecting electrode CNE2 may contact the second electrode RME2 through a second contact portion CT2 penetrating the first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 in the sub-region SA.

[0231] The third connecting electrode CNE3 may include a first extension CN_E1 disposed on the third electrode RME3, a second extension CN_E2 disposed on the first electrode RME1, and a first connecting portion CN_B1 connecting the first extension CN_E1 and the second extension CN_E2. The first extension CN_E1 may face the first connecting electrode CNE1 in the second direction DR2, and the second extension CN_E2 may be spaced apart from the first connecting electrode CNE1 in the first direction DR1. The first extension CN_E1 may be disposed below the light emitting region EMA of the corresponding subpixel SPXn, and the second extension CN_E2 may be disposed above the light emitting region EMA. The first extension CN_E1 and the second extension CN_E2 may be disposed within the light emitting region EMA. The first connecting portion CN_B1 may be disposed across the first electrode RME1 and the third electrode RME3 in the center of the light emitting region EMA. The third connecting electrode CNE3 generally has a shape extending in the first direction DR1, but may be bent in the second direction DR2 and thus extend again in the first direction DR1.

[0232] The fourth connecting electrode CNE4 may include a third extension CN_E3 disposed on the fourth electrode RME4, a fourth extension CN_E4 disposed on the second electrode RME2, and a second connecting portion CN_B2 connecting the third extension CN_E3 and the fourth extension CN_E4. The third extension CN_E3 may face the second connecting electrode CNE2 in the second direction DR2 and the fourth extension CN_E4 may be separated from the second connecting electrode CNE2 in the first direction DR1. The third extension CN_E3 may be disposed below the light emitting region EMA of the corresponding subpixel SPXn, and the fourth extension CN_E4 may be disposed above the light emitting region EMA. The third extension CN_E3 and the fourth extension CN_E4 may be disposed within the light emitting region EMA. The second connecting portion CN_B2 may be disposed adjacent to the center of the light emitting region EMA across the second electrode RME2 and the fourth electrode RME4. The fourth connecting electrode CNE4 generally has a shape extending in the first direction DR1, but may have a shape bent in the second direction DR2 and then extending again in the first direction DR1.

[0233] The fifth connecting electrode CNE5 may include a fifth extension CN_E5 disposed on the third electrode RME3, a sixth extension CN_E6 disposed on the fourth electrode RME4, and a third connecting portion CN_B3 connecting the fifth extension CN_E5 and the sixth extension CN_E6. The fifth extension CN_E5 may face the second extension CN_E2 of the third connecting electrode CNE3 in the second direction DR2, and the sixth extension CN_E6 may face the fourth extension CN_E4 of the fourth connecting electrode CNE4 in the second direction DR2. The fifth extension CN_E5 and the sixth extension CN_E6 may be disposed above the light emitting region EMA, and the third connecting portion CN_B3 may be disposed across the third electrode RME3, the second electrode RME2, and the fourth electrode RME4. The fifth connecting electrode CNE5 may be disposed in a shape surrounding the fourth extension CN_E4 of the fourth connecting electrode CNE4 in a plan view.

[0234] The third connecting electrode CNE3 may be in direct contact with the third electrode RME3 via a third contact portion CT3 that penetrates the first insulating layer PAS1 and the second insulating layer PAS2 in the sub-region SA, and the fourth connecting electrode CNE4 may be in contact with the fourth electrode RME4 via a fourth contact portion CT4 that penetrates the first insulating layer PAS1 and the second insulating layer PAS2 in the sub-region SA.

[0235] However, the present invention is not limited thereto. In some embodiments, the display device 10 may have a portion of the connecting electrode CNE directly connected to the third conductive layer. For example, the first connecting electrode CNE1 and the second connecting electrode CNE2, which are the first type connecting electrodes, may each be directly connected to the third conductive layer and may not be electrically connected to the electrode RME. The second type connecting electrode and the third type connecting electrode may also not be electrically connected to the electrode RME and may only be connected to the light emitting element ED.

[0236] The first connecting electrode CNE1 and the second connecting electrode CNE2 are first type connecting electrodes connected to the electrodes RME1 and RME2 directly connected to the third conductive layer, the third connecting electrode CNE3 and the fourth connecting electrode CNE4 are second type connecting electrodes connected to the electrodes RME3 and RME4 not connected to the third conductive layer, and the fifth connecting electrode CNE5 may be a third type connecting electrode not connected to the electrode RME. The fifth connecting electrode CNE5 is not connected to the electrode RME and is in contact with the light emitting element ED, and may form an electrical connecting circuit of the light emitting element ED together with the other connecting electrodes CNE.

[0237] The third connecting electrode CNE3 and the fourth connecting electrode CNE4, which are the second type connecting electrodes, may be connecting electrodes whose electrode extensions extending in the first direction DR1 are not aligned with each other in the second direction DR2, and the fifth connecting electrode CNE5, which is the third type connecting electrode, may be a connecting electrode whose electrode extensions extending in the first direction DR1 are aligned with each other in the second direction DR2. The third connecting electrode CNE3 and the fourth connecting electrode CNE4 extend in the first direction DR1 but have a bent shape, and the fifth connecting electrode CNE5 may have a shape that surrounds a part of the other connecting electrodes.

[0238] In accordance with the arrangement of the connecting electrodes CNE, the light emitting elements ED may be classified into different light emitting elements ED according to the connecting electrodes CNE with which both ends are in contact. The first light emitting element ED1 and the second light emitting element ED2 may have a first end in contact with a first type connecting electrode and a second end in contact with a second type connecting electrode. The first light emitting element ED1 may be in contact with the first connecting electrode CNE1 and the third connecting electrode CNE3, and the second light emitting element ED2 may be in contact with the second connecting electrode CNE2 and the fourth connecting electrode CNE4. The third light emitting element ED3 and the fourth light emitting element ED4 may have a first end in contact with a second type connecting electrode and a second end in contact with a third type connecting electrode. The third light emitting element ED3 may be in contact with the third connecting electrode CNE3 and the fifth connecting electrode CNE5, and the fourth light emitting element ED4 may be in contact with the fourth connecting electrode CNE4 and the fifth connecting electrode CNE5.

[0239] The light emitting elements ED may be connected in series via the connecting electrodes CNE. The display device 10 according to the present embodiment may include a larger number of light emitting elements ED for each sub-pixel SPXn and may be connected in series, thereby increasing the amount of light emitted per unit area.

[0240] Fig. 27 is a plan view showing a sub-pixel of a display device according to another embodiment. Fig. 28 is a cross-sectional view taken along line N5-N5' in Fig. 27. Fig. 29 is a cross-sectional view taken along line N6-N6' in Fig. 27. Fig. 30 is a cross-sectional view taken along line N7-N7' in Fig. 27.

[0241] Fig. 27 shows a planar arrangement of electrodes (RME; RME1, RME2) arranged in one pixel PX of the display device 10, bank patterns BP1, BP2 and lower bank layer LBN, multiple light-emitting elements ED, and connecting electrodes (CNE; CNE1, CNE2, CNE3). Fig. 28 shows a cross section across both ends of light-emitting elements (ED; ED1, ED2) arranged on different electrodes RME. Fig. 29 and Fig. 30 show cross sections across multiple electrode contact holes CTD, CTS, CTA, and contact portions CT1, CT2.

[0242] 27 to 30, the display device 10 according to the embodiment has different structures of the electrode RME, the connecting electrode CNE, and the bank patterns BP1 and BP2 from the above-described embodiment. In the following, the same contents as the above-described embodiment will be omitted, and the differences will be mainly described.

[0243] The bank patterns BP1, BP2 have a shape extending in the first direction DR1, but may have different widths measured in the second direction DR2, and any one of the bank patterns BP1, BP2 may be disposed across the sub-pixels SPXn adjacent to each other in the second direction DR2. For example, the bank patterns BP1, BP2 may include a first bank pattern BP1 disposed in the light emitting region EMA of each sub-pixel SPXn, and a second bank pattern BP2 disposed across the light emitting regions EMA of different sub-pixels SPXn.

[0244] The first bank pattern BP1 is disposed at the center of the light emitting region EMA, and the second bank pattern BP2 is disposed spaced apart from the first bank pattern BP1. The first bank pattern BP1 and the second bank pattern BP2 may be alternately disposed along the second direction DR2. A light emitting element ED may be disposed between the first bank pattern BP1 and the second bank pattern BP2.

[0245] The first bank pattern BP1 and the second bank pattern BP2 have the same length in the first direction DR1 but may have different widths measured in the second direction DR2. A portion of the lower bank layer LBN extending in the first direction DR1 may overlap the second bank pattern BP2 in the thickness direction. The first bank pattern BP1 may be arranged to overlap the first electrode RME1, and the second bank pattern BP2 may be arranged to overlap the electrode branch portions RM_B1, RM_B2 of the second electrode RME2 and the lower bank layer LBN.

[0246] The first bank pattern BP1 and the second bank pattern BP2 have the same length in the first direction DR1 but may have different widths measured in the second direction DR2. A portion of the lower bank layer LBN extending in the first direction DR1 may overlap the second bank pattern BP2 in the thickness direction. The bank patterns BP1 and BP2 may be arranged in an island pattern over the entire display area DPA.

[0247] The electrodes RME include a first electrode RME1 disposed at the center of each subpixel SPXn, and a second electrode RME2 disposed across different subpixels SPXn. The first electrode RME1 and the second electrode RME2 generally have a shape extending in the first direction DR1, but the shapes of the portions disposed in the light-emitting region EMA may be different from each other.

[0248] The first electrode RME1 may be disposed at the center of the subpixel SPXn, and a portion disposed in the light emitting region EMA may be disposed on the first bank pattern BP1. The first electrode RME1 may extend from the subregion SA in the first direction DR1 to the subregion SA of another subpixel SPXn. The first electrode RME1 may have a shape in which the width measured in the second direction DR2 varies depending on the position, and at least a portion overlapping with the first bank pattern BP1 in the light emitting region EMA may have a width larger than that of the first bank pattern BP1.

[0249] The second electrode RME2 may include a portion extending in the first direction DR1 and a portion branching in the vicinity of the light emitting area EMA. In one embodiment, the second electrode RME2 may include an electrode stem RM_S extending in the first direction DR1, and a plurality of electrode branch portions RM_B1, RM_B2 branching from the electrode stem RM_S, bending in the second direction DR2, and then extending again in the first direction DR1. The electrode stem RM_S may be arranged to overlap with a portion of the lower bank layer LBN extending in the first direction DR1, and may be arranged on one side of the second direction DR2 of the sub-region SA. The electrode branch portions RM_B1, RM_B2 may branch from the electrode stem RM_S arranged in the portion extending in the first direction DR1 and the portion extending in the second direction DR2 of the lower bank layer LBN, and be bent to both sides of each other in the second direction DR2. The electrode branch portions RM_B1 and RM_B2 may be disposed across the light emitting region EMA in the first direction DR1 and bent again to be integrated and connected to the electrode trunk RM_S. That is, the electrode branch portions RM_B1 and RM_B2 of the second electrode RME2 may branch at the upper side of the light emitting region EMA of any one of the sub-pixels SPXn and then be connected to each other again at the lower side.

[0250] The second electrode RME2 may include a first electrode branch portion RM_B1 disposed on the left side of the first electrode RME1 and a second electrode branch portion RM_B2 disposed on the right side of the first electrode RME1. The electrode branches RM_B1 and RM_B2 included in one second electrode RME2 are respectively disposed in the light emitting regions EMA of the sub-pixels SPXn adjacent to each other in the second direction DR2, and different electrode branches RM_B1 and RM_B2 of the second electrode RME2 may be disposed in one sub-pixel SPXn. The first electrode branch portion RM_B1 of the second electrode RME2 may be disposed on the left side of the first electrode RME1, and the second electrode branch portion RM_B2 of the other second electrode RME2 may be disposed on the right side of the first electrode RME1.

[0251] Each of the electrode branch portions RM_B1, RM_B2 of the second electrode RME2 may overlap one side of the second bank pattern BP2. The first electrode branch portion RM_B1 may partially overlap the second bank pattern BP2 arranged on the left side of the first bank pattern BP1, and the second electrode branch portion RM_B2 may partially overlap the second bank pattern BP2 arranged on the right side of the first bank pattern BP1. Both sides of the first electrode RME1 may face, at a distance, different electrode branch portions RM_B1, RM_B2 of the different second electrode RME2, and the interval between the first electrode RME1 and each of the electrode branch portions RM_B1, RM_B2 may be smaller than the interval between the different bank patterns BP1, BP2.

[0252] The width of the first electrode RME1 measured in the second direction DR2 may be greater than the widths of the electrode trunk RM_S and the electrode branch portions RM_B1, RM_B2 of the second electrode RME2. The first electrode RME1 may be wider than the first bank pattern BP1 and overlap both sides, whereas the second electrode RME2 may be formed with a relatively smaller width such that the electrode branch portions RM_B1, RM_B2 overlap only one side of the second bank pattern BP2.

[0253] The first electrode RME1 may contact the first conductive pattern CDP of the third conductive layer through the first electrode contact hole CTD at a portion overlapping the portion of the lower bank layer LBN extending in the second direction DR2. The second electrode RME2 may contact the second voltage wiring VL2 of the third conductive layer through the second electrode contact hole CTS at the electrode trunk RM_S. The first electrode RME1 is arranged such that a portion arranged in the sub-region SA overlaps with the first contact portion CT1, and the second electrode RME2 includes a portion at the electrode trunk RM_S that protrudes in the second direction DR2 and is arranged in the sub-region SA, and the protruding portion may overlap with the second contact portion CT2.

[0254] Of the first electrode RME1 and the second electrode RME2, the first electrode RME1 may be disposed up to the separation parts ROP1, ROP2 of the sub-region SA, whereas the second electrode RME2 may not be separated by the sub-region SA. One second electrode RME2 may include a plurality of electrode trunk parts RM_S and electrode branch parts RM_B1, RM_B2, extend in the first direction DR1, and have a branched shape near the light emitting region EMA of each sub-pixel SPXn. The first electrode RME1 may be disposed between the separation parts ROP1, ROP2 disposed in different sub-regions SA1, SA2 of each sub-pixel SPXn, and disposed across the light emitting region EMA.

[0255] According to an embodiment, the display device 10 may include a line connecting electrode EP disposed in a first sub-region SA1 among a plurality of sub-regions SA1 and SA2 of each sub-pixel SPXn and disposed between first electrodes RME1 of different sub-pixels SPXn. The line connecting electrode EP may not be disposed in a second sub-region SA of the sub-pixel SPXn, and the first electrodes RME1 of other sub-pixels SPXn adjacent in the first direction DR1 may be spaced apart from each other. Among the plurality of sub-pixels SPXn, the sub-pixel SPXn shown in FIG. 27 may have a first sub-region SA1 in which the line connecting electrode EP is disposed disposed above the light-emitting region EMA, and a second sub-region SA2 in which the line connecting electrode EP is disposed below the light-emitting region EMA. On the other hand, the sub-pixel SPXn adjacent in the first direction DR1 to the sub-pixel SPXn in FIG. 27 may have a first sub-region SA1 in which the line connecting electrode EP is disposed disposed below the light-emitting region EMA, and a second sub-region SA2 in which the line connecting electrode EP is disposed above the light-emitting region EMA.

[0256] The first electrode RME1 may be separated from the line connecting electrode EP with a first separation part ROP1 in the first sub-region SA1. Two first separation parts ROP1 may be arranged in one first sub-region SA1, and the line connecting electrode EP may be separated from the first electrode RME1 arranged in the corresponding sub-pixel SPXn with a lower first separation part ROP1 in between, and may be separated from the first electrode RME1 arranged in the other sub-pixel SPXn with an upper first separation part ROP1 in between. One second separation part ROP2 is arranged in the second sub-region SA2, and different first electrodes RME1 may be separated in the first direction DR1.

[0257] In one embodiment, the wiring connection electrode EP may be connected to the first voltage wiring VL1 of the third conductive layer through the third electrode contact hole CTA penetrating the via layer VIA. The first electrode RME1 is formed in a state of being connected to the wiring connection electrode EP, and an electrical signal applied to position the light emitting element ED may be applied to the first electrode RME1 from the first voltage wiring VL1 through the wiring connection electrode EP. In a process of positioning the light emitting element ED, signals are applied to the first voltage wiring VL1 and the second voltage wiring VL2, which may be transferred to the first electrode RME1 and the second electrode RME2, respectively.

[0258] In addition, the second electrode contact hole CTS may be disposed in a different position relative to the third electrode contact hole CTA described later. The second electrode contact hole CTS may be disposed in a portion of the lower bank layer LBN surrounding the second sub-region SA2, and the third electrode contact hole CTA may be disposed in the first sub-region SA1. This is because the second electrode contact hole CTS and the third electrode contact hole CTA expose the upper surfaces of the voltage wirings VL1 and VL2 that are different from each other, and the positions of the electrode contact holes may be determined accordingly.

[0259] The lower bank layer LBN may surround the light emitting region EMA and the sub-regions SA1 and SA2 in the same manner as in the above-described embodiment. However, in an embodiment in which the display device 10 includes the sub-regions SA1 and SA2 that are separated from each other, the regions surrounded by the lower bank layer LBN may be separated from each other. The lower bank layer LBN is similar to the above-described embodiment except that it surrounds the sub-regions SA1 and SA2 that are different from each other.

[0260] The light-emitting elements ED may be disposed on different electrodes RME between different bank patterns BP1, BP2. The light-emitting elements ED may include a first light-emitting element ED1 having both ends disposed on the first electrode RME1 and the second electrode branch portion RM_B2 of the second electrode RME2, and a second light-emitting element ED2 having both ends disposed on the first electrode RME1 and the first electrode branch portion RM_B1 of the other second electrode RME2. The first light-emitting element ED1 may be disposed on the right side of the first electrode RME1, and the second light-emitting element ED2 may be disposed on the left side of the first electrode RME1. The first light-emitting element ED1 may be disposed on the first electrode RME1 and the second electrode RME2, and the second light-emitting element ED2 may be disposed on the first electrode RME1 and the second electrode RME2.

[0261] The multiple connecting electrodes (CNE; CNE1, CNE2, CNE3) may include a first connecting electrode CNE1, a second connecting electrode CNE2, and a third connecting electrode CNE3.

[0262] The first connecting electrode CNE1 may have a shape extending in a first direction DR1 and be disposed on the first electrode RME1. A portion of the first connecting electrode CNE1 disposed on the first bank pattern BP1 may overlap the first electrode RME1 and extend from there in the first direction DR1 to the first sub-region SA1 located above the light emitting region EMA, passing over the lower bank layer LBN. The first connecting electrode CNE1 may contact the first electrode RME1 in the first sub-region SA1 via a first contact portion CT1.

[0263] The second connecting electrode CNE2 may have a shape extending in the first direction DR1 and be disposed on the second electrode RME2. A portion of the second connecting electrode CNE2 disposed on the second bank pattern BP2 may overlap the second electrode RME2 and extend from there in the first direction DR1 to the first sub-region SA1 located above the light emitting region EMA, passing over the lower bank layer LBN. The second connecting electrode CNE2 may contact the second electrode RME2 in the first sub-region SA1 via the second contact portion CT2.

[0264] In addition, in the subpixel SPXn of Figure 27 and the subpixel SPXn adjacent to it in the first direction DR1, the first connecting electrode CNE1 and the second connecting electrode CNE2 may be in contact with the first electrode RME1 and the second electrode RME2, respectively, via contact portions CT1 and CT2 arranged in the second subregion SA2.

[0265] The third connecting electrode CNE3 may include extensions CN_E1 and CN_E2 extending in a first direction DR1, and a first connecting portion CN_B1 connecting the extensions CN_E1 and CN_E2. The first extension CN_E1 faces the first connecting electrode CNE1 in the light emitting region EMA and is disposed on the second electrode branch portion RM_B2 of the second electrode RME2, and the second extension CN_E2 faces the second connecting electrode CNE2 in the light emitting region EMA and is disposed on the first electrode RME1. The first connecting portion CN_B1 may extend in the second direction DR2 on the lower bank layer LBN disposed below the light emitting region EMA to connect the first extension CN_E1 and the second extension CN_E2. The third connecting electrode CNE3 is disposed on the light emitting region EMA and the lower bank layer LBN, and may not be directly connected to the electrode RME. The second electrode branch portion RM_B2 arranged at the bottom of the first extension portion CN_E1 is electrically connected to the second voltage wiring VL2, but the second power supply voltage applied to the second electrode branch portion RM_B2 does not need to be transmitted to the third connecting electrode CNE3.

[0266] 31 is a cross-sectional view of a display device according to another embodiment, and FIG 32 is a cross-sectional view showing an outer periphery of the display device of FIG 31.

[0267] 31 and 32, a display device 10_7 according to an embodiment may include an organic light emitting device, unlike the display device 10 described above with reference to FIGS. 2 to 6. In the display device 10_7, the bank patterns BP1 and BP2, the electrodes RME, the light emitting device ED, and the connecting electrode CNE arranged on the via layer VIA may be replaced with other layers or electrodes. Hereinafter, the same content as the embodiment of FIGS. 2 to 6 will be omitted, and the differences will be mainly described.

[0268] The display device 10_7 may include a plurality of anode electrodes AE1, AE2, and AE3 disposed on the via layer VIA, a pixel defining film 150, an organic layer OL, and a cathode electrode CE. The display device 10_7 may also include an encapsulation layer 170 disposed on the cathode electrode CE.

[0269] A plurality of anode electrodes AE1, AE2, and AE3 may be disposed on the via layer VIA. The first anode electrode AE1 may be disposed in the first sub-pixel SPX1, the second anode electrode AE2 may be disposed in the second sub-pixel SPX2, and the third anode electrode AE3 may be disposed in the third sub-pixel SPX3.

[0270] In some embodiments, the widths or areas of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be different from each other. Exemplarily, the width of the first anode electrode AE1 may be larger than the width of the second anode electrode AE2, and the width of the second anode electrode AE2 may be smaller than the width of the first anode electrode AE1 but larger than the width of the third anode electrode AE3. Or, the area of ​​the first anode electrode AE1 may be larger than the area of ​​the second anode electrode AE2, and the area of ​​the second anode electrode AE2 may be smaller than the area of ​​the first anode electrode AE1 but larger than the area of ​​the third anode electrode AE3. However, the present invention is not limited thereto, and the area of ​​the first anode electrode AE1 may be smaller than the area of ​​the second anode electrode AE2, and the area of ​​the third anode electrode AE3 may be larger than the areas of the second anode electrode AE2 and the first anode electrode AE1. Alternatively, in some cases, the widths or areas of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be substantially the same as one another.

[0271] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may include a material having high reflectivity. For example, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be a metal layer including a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, and Cr. In other embodiments, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may further include a metal oxide layer laminated on the metal layer. In an exemplary embodiment, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may have a bilayer structure such as ITO / Ag, Ag / ITO, ITO / Mg, or ITO / MgF, or a multilayer structure such as ITO / Ag / ITO.

[0272] The pixel defining film 150 may be disposed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The pixel defining film 150 may include an opening exposing the first anode electrode AE1, an opening exposing the second anode electrode AE2, and an opening exposing the third anode electrode AE3.

[0273] In some embodiments, the pixel defining layer 150 may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamides resin, a polyimides resin, an unsaturated polyesters resin, a polyphenylenes resin, a polyphenylenesulfides resin, or benzocyclobutene (BCB).

[0274] The organic layer OL may be disposed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. In some embodiments, the organic layer OL may have the shape of a continuous film formed across the sub-pixels SPXn and their boundaries.

[0275] The cathode electrode CE may be disposed on the organic layer OL. In some embodiments, the cathode electrode CE may be semi-transparent or transparent. When the cathode electrode CE is semi-transparent, the cathode electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, or a compound or mixture thereof, such as a mixture of Ag and Mg. When the cathode electrode CE has a thickness of several tens to several hundreds of angstroms, the cathode electrode CE may be semi-transparent.

[0276] When the cathode electrode CE has a transparent property, the cathode electrode CE may include a transparent conductive oxide (TCO). For example, the cathode electrode CE may include a W x O x (tungsten oxide), TiO 2 (Titanium oxide), ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), MgO (magnesium oxide), etc.

[0277] The first anode electrode AE1, the organic layer OL, and the cathode electrode CE may constitute a first organic light emitting element ED1, the second anode electrode AE2, the organic layer OL, and the cathode electrode CE may constitute a second organic light emitting element ED2, and the third anode electrode AE3, the organic layer OL, and the cathode electrode CE may constitute a third organic light emitting element ED3. Light emitted from each of the organic light emitting elements ED1, ED2, and ED3 may be incident on the color control structures TPL, WCL1, and WCL2 thereon.

[0278] The encapsulation layer 170 may be disposed on the light emitting element ED to cover the third insulating layer PAS3 and the connecting electrodes CNE1, CNE2. The encapsulation layer 170 may be disposed on the entire surface of the first substrate SUB to completely cover the components disposed on the first substrate SUB.

[0279] The encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175, which are sequentially stacked on the third insulating layer PAS3. The first encapsulation layer 171 and the third encapsulation layer 175 may include an inorganic insulating material, and the second encapsulation layer 173 may include an organic insulating material. For example, the first encapsulation layer 171 and the third encapsulation layer 175 may each include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride (SiO x N y ), lithium fluoride, etc. The second sealing layer 173 may include at least one of an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, and a perylene resin, etc. However, the structure and materials of the sealing layer 170 are not limited to those described above, and the laminated structure and materials may be modified in various ways.

[0280] The first bank BNL1 and the color control structures TPL, WCL1, WCL2 may each be disposed on the encapsulation layer 170. The first bank BNL1 may be disposed so as to overlap the pixel definition film 150 on the encapsulation layer 170, and the color control structures TPL, WCL1, WCL2 may be disposed within a region surrounded by the first bank BNL1 on the encapsulation layer 170. Capping layers CPL1, CPL2, a low refractive layer LRL, a planarization layer PNL, a light blocking member BM, a color filter layer CFL, and an overcoat layer OC may be disposed on the first bank BNL1 and the color control structures TPL, WCL1, WCL2 in the same manner as described above.

[0281] In an embodiment in which the display device 10_7 includes the organic light emitting elements ED1, ED2, and ED3, the second bank BNL2 and the third bank BNL3 in the non-display area NDA may each be disposed directly on the third encapsulation layer 175 of the encapsulation layer 170. The first encapsulation layer 171 may be disposed directly on an inner sidewall of the first valley portion VA1 disposed between the first bank BNL1 and the second bank BNL2, and the step due to the first valley portion VA1 may be filled with the second encapsulation layer 173. In addition, a portion of the first capping layer CPL1 may be disposed directly on the third encapsulation layer 175 of the encapsulation layer 170. However, the present invention is not limited to this.

[0282] FIG. 33 is a cross-sectional view showing an outer periphery of a display device according to another embodiment.

[0283] Referring to FIG. 33, the display device 10_8 according to an embodiment may further include an upper cover layer UCL disposed on the overcoat layer OC. The upper cover layer UCL is disposed on the top layer of the display device 10_8, and may protect the display device 10_8 from external impact or perform an optical function for light emitted from the display device 10_8 or light incident from the outside. As an example, the upper cover layer UCL may be an optical film that prevents a decrease in visibility due to external light reflection. In an embodiment in which the upper cover layer UCL is an optical film, the upper cover layer UCL may include a retardation film and a coating layer that protects the retardation film. The upper cover layer UCL may include a layer made of a cellulose resin such as triacetyl cellulose, a polyester resin, or the like, but is not limited thereto.

[0284] The upper cover layer UCL may be disposed on the overcoat layer OC and on the display area DPA and non-display area NDA of the display device 10_8. The upper cover layer UCL may have an area similar to that of the first substrate SUB in a plan view, and may completely cover the display area DPA and non-display area NDA as shown in the drawings. However, the upper cover layer UCL is not limited thereto, and may cover only the display area DPA or only a portion of the display area DPA and non-display area NDA.

[0285] In an embodiment in which the upper cover layer UCL is disposed to completely cover the non-display area NDA, a space may be formed below the upper cover layer UCL. The outermost portion of the display device 10_8 where the second bank BNL2 and the third bank BNL3 are disposed may be lower in height than the overcoat layer OC, and a space may be formed between the upper cover layer UCL and the second bank BNL2 and the third bank BNL3. The space may be filled with a filling material, but is not limited thereto. The space below the upper cover layer UCL may not be filled with a filling material, and an air layer may be formed.

[0286] Although the embodiment of the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiment is illustrative in all respects and is not limiting.

Claims

1. a first substrate including a display area and a non-display area surrounding the display area; a plurality of sub-pixels each including a plurality of light-emitting elements disposed on the first substrate in the display region; a first bank surrounding the subpixels in the display area; a plurality of color control structures disposed within an area surrounded by the first bank over the light emitting elements of the plurality of subpixels; a plurality of color filter layers disposed on the color control structure; a second bank disposed apart from the first bank and surrounding the display area in the non-display area; and a plurality of color dams disposed on the second bank; the color dams include a first color dam disposed on a first portion of the second bank disposed on a first side of the display area, and a second color dam disposed on a second portion of the second bank disposed on a second side opposite the first side of the display area, The first color dam and the second color dam comprise different materials.

2. The plurality of sub-pixels include a first sub-pixel and a second sub-pixel spaced apart from the first sub-pixel in one direction, The plurality of color control structures include a first wavelength conversion layer disposed in the first sub-pixel and a light transmitting layer disposed in the second sub-pixel; The display device of claim 1 , wherein the plurality of color filter layers include a first color filter layer disposed on the first wavelength conversion layer, and a second color filter layer disposed on the light-transmitting layer.

3. The first color dam and the second color dam are spaced apart in the one direction, the display area is disposed between the first color dam and the second color dam; the first color dam comprises the same material as the first color filter layer; The display device of claim 2 , wherein the second color dam comprises the same material as the second color filter layer.

4. the sub-pixel further includes a third sub-pixel disposed between the first sub-pixel and the second sub-pixel, The plurality of color control structures further includes a second wavelength conversion layer disposed in the third sub-pixel; the plurality of color filter layers further includes a third color filter layer disposed on the second wavelength conversion layer; The display device further includes a third color dam disposed on the first color dam; The display device of claim 3 , wherein the third color dam and the third color filter layer comprise the same material.

5. the width of the third color dam is greater than the width of the first color dam; The display device of claim 4 , wherein an outer surface of the first color dam is covered by the third color dam.

6. further comprising a plurality of color patterns overlapping the first bank; the color patterns include a first color pattern including a same material as the first color filter layer, a second color pattern including a same material as the second color filter layer, and a third color pattern including a same material as the third color filter layer; The display device according to claim 4 , wherein the first color pattern overlaps with the second color filter layer and the third color filter layer in a plan view.

7. The first color dam and the second color dam are spaced apart in the one direction, the display area is disposed between the first color dam and the second color dam; the first color dam comprises the same material as the second color filter layer; The display device of claim 2 , wherein the second color dam comprises the same material as the first color filter layer.

8. a first capping layer disposed on the plurality of color control structures, the first bank, and the second bank; a low refractive layer disposed on the first capping layer; and further comprising a second capping layer disposed on the low refractive index layer; 2. The display device of claim 1, wherein the first color dam and the second color dam are disposed on the second capping layer.

9. a planarization layer disposed between the second capping layer and the plurality of color filter layers; 9. The display device of claim 8, wherein the first color dam and the second color dam are disposed directly on the planarization layer above the second bank, respectively.

10. 10. The display device of claim 9, further comprising: a light blocking member disposed on the planarization layer and overlapping the first bank; and an overcoat layer disposed on the light blocking member and the plurality of color filter layers.

11. a via layer disposed on the first substrate in the display region and the non-display region; a third bank disposed on the via layer and spaced apart from the second bank in the non-display region to surround the second bank; and The display device according to claim 8 , further comprising a first valley portion disposed between the first bank and the second bank in the non-display region and penetrating the via layer.

12. the first color dam is disposed in a plurality of portions on the second bank and the third bank that are disposed on the first side of the display area; The display device according to claim 11 , wherein a plurality of the second color dams are arranged, and the second color dams are arranged on portions of the second bank and the third bank that are arranged on the second side of the display region.

13. The display device of claim 11 , further comprising a plurality of bank partitions disposed directly on the via layer between the first bank and the first valley.

14. each of the first bank and the second bank includes a base layer and a top layer disposed on the base layer; The display device of claim 8 , wherein the top layer has a greater width than the base layer.

15. The sub-pixel includes a plurality of electrodes extending in one direction and spaced apart from each other, The display device according to claim 1 , wherein the plurality of light-emitting elements are arranged on a plurality of electrodes spaced apart from each other.

16. The display device according to claim 1 , wherein the light-emitting element includes a first electrode disposed on the first substrate, an organic layer disposed on the first electrode, and a second electrode disposed on the organic layer.

17. a display area and a non-display area surrounding the display area; a plurality of sub-pixels disposed in the display region and arranged in a first direction and a second direction intersecting the first direction, the sub-pixels including a first electrode, a second electrode spaced apart from the first electrode, and a plurality of light-emitting elements having first and second ends disposed on the first and second electrodes; a first bank extending in the first direction and the second direction in the display region and surrounding the plurality of sub-pixels; a plurality of color control structures disposed within an area enclosed by the first bank; a plurality of color filter layers disposed on the color control structure; a first valley portion disposed in the non-display region so as to be spaced apart from the first bank and to surround the first bank; a second bank disposed in the non-display region so as to be spaced apart from the first valley portion and to surround the first valley portion; a third bank disposed in the non-display region so as to be spaced apart from the second bank and to surround the second bank; a plurality of first color dams extending in the first direction in a first dam region of the non-display region adjacent to a first side of the display region in the second direction; and a second dam region adjacent to a second side of the display region in the second direction in the non-display region, the second dam region extending in the first direction; The first and second color dams comprise different materials.

18. the first color dams overlap the second bank and the third bank disposed in the first dam region; The display device of claim 17 , wherein the plurality of second color dams overlap the second bank and the third bank arranged in the second dam region.

19. The plurality of color filter layers include a plurality of first color filter layers, a plurality of second color filter layers spaced apart from the plurality of first color filter layers in the second direction, and the plurality of second color filter layers and a plurality of third color filter layers spaced apart in the second direction; the first color filter layer, the second color filter layer, and the third color filter layer are adjacently disposed along the second direction; the plurality of first color dams include the same material as the third color filter layer; 20. The display device of claim 17, wherein the plurality of second color dams comprises the same material as the first color filter layer.

20. a third color dam disposed on the second color dam; 20. The display device of claim 19, wherein the third color dam comprises the same material as the second color filter layer.

Images