Display device

Abstract

A display device according to an embodiment includes a first sub-pixel and a second sub-pixel emitting different light from each other, the first sub-pixel including a first anode pad electrode and a second anode pad electrode spaced apart from each other on a plane, a first cathode pad electrode spaced apart from the first anode pad electrode and the second anode pad electrode on a plane, and a first light-emitting element including a first sub-light-emitting element arranged on the first anode pad electrode and the cathode pad electrode, and a second sub-light-emitting element arranged on the second anode pad electrode and the cathode pad electrode. An area of ​​the first cathode pad electrode is larger than an area of ​​the first anode pad electrode or an area of ​​the second anode pad electrode. The first sub-light-emitting element and the second sub-light-emitting element emit light in different periods from each other. The first sub-light-emitting element and the second sub-light-emitting element emit light of the same (color).

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] With the development of the information society, the demands for display devices for displaying images are becoming more and more diverse. The display devices may be flat panel display devices such as liquid crystal displays, field emission displays, light emitting displays, etc.

[0003] The light emitting display device may include an organic light emitting display device including an organic light emitting diode element as a light emitting element, or an light emitting diode display device including an inorganic light emitting diode element such as an LED (Light Emitting Diode) as a light emitting element. As the temperature of the inorganic light emitting diode increases due to heat generation of the inorganic light emitting diode element, the light emitting efficiency of the inorganic light emitting diode element decreases. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENTLY PREFERRED EMBODIMENTS An object of the present invention is to provide a display device capable of reducing or preventing a decrease in the luminance of an inorganic light emitting diode element due to heat generation from the inorganic light emitting diode element.

[0005] The object of the present invention is not limited to the above-mentioned objects, and other technical objects not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] A display device according to an embodiment for solving the above problem includes a first sub-pixel and a second sub-pixel emitting different lights from each other, the first sub-pixel including a first anode pad electrode and a second anode pad electrode spaced apart from each other on a plane, a first cathode pad electrode spaced apart from the first anode pad electrode and the second anode pad electrode on a plane, and a first light-emitting element including a first sub-light-emitting element arranged on the first anode pad electrode and the cathode pad electrode, and a second sub-light-emitting element arranged on the second anode pad electrode and the cathode pad electrode. An area of ​​the first cathode pad electrode is larger than an area of ​​the first anode pad electrode or an area of ​​the second anode pad electrode. The first sub-light-emitting element and the second sub-light-emitting element emit light in different periods from each other. The first sub-light-emitting element and the second sub-light-emitting element emit light of the same (color).

[0007] The first cathode pad electrode may have a length in one direction greater than a length in one direction of the first anode pad electrode or a length in one direction of the second anode pad electrode.

[0008] The second sub-pixel may include a third anode pad electrode, a second cathode pad electrode disposed away from the third anode pad electrode, and a second light-emitting element disposed over the third anode pad electrode and the second cathode pad electrode.

[0009] The area of ​​the first cathode pad electrode may be larger than the area of ​​the second cathode pad electrode.

[0010] The first cathode pad electrode may have a length in one direction greater than a length in one direction of the second cathode pad electrode.

[0011] The first sub-pixel and the second sub-pixel may include a third sub-pixel that emits light different from each other, and the third sub-pixel may include a fourth anode pad electrode, a third cathode pad electrode that is disposed apart from the third anode pad electrode on a plane, and a third light-emitting element that is disposed on the fourth anode pad electrode and the third cathode pad electrode.

[0012] The area of ​​the first cathode pad electrode may be larger than the area of ​​the third cathode pad electrode.

[0013] The first cathode pad electrode may have a length in one direction greater than a length in one direction of the third cathode pad electrode.

[0014] The first and second sub light emitting elements may emit a first light, the second light emitting element may emit a second light, and the third light emitting element may emit a third light.

[0015] The first light may be red light, the second light may be green light, and the third light may be blue light.

[0016] According to an embodiment of the present invention, a display device includes a first data wiring to which a first data voltage is applied, a second data wiring to which a second data voltage is applied, a first light emission control wiring to which a first light emission control signal is applied, a second light emission control wiring to which a second light emission control signal is applied, and a first sub-pixel connected to the first data wiring, the second data wiring, the first light emission control wiring, and the second light emission control wiring, The first sub-pixel includes a first light emitting element including a first sub light emitting element and a second sub light emitting element emitting a first light, a first pixel driver generating a control current in response to the first data voltage of the first data wiring, a second pixel driver generating a first driving current applied to the first sub light emitting element or the second sub light emitting element in response to the second data voltage of the second data wiring, and a third pixel driver controlling a period for applying the first driving current to the first sub light emitting element or the second sub light emitting element in response to the control current of the first pixel driver. The third pixel driving unit includes a first transistor for supplying the first driving current to the first light emitting element in response to the first light emitting control signal and a second transistor for supplying the first driving current to the second light emitting element in response to the second light emitting control signal. The first light emitting control signal has a gate-on voltage during an Nth frame period and a gate-off voltage during an N+1th frame period. The second light emitting control signal has the gate-off voltage during the Nth frame period and the gate-on voltage during the N+1th frame period.

[0017] The first sub-pixel may further include a first initialization signal wiring to which a first initialization signal is applied and an initialization voltage wiring to which an initialization voltage is applied. The first sub-pixel may further include a third transistor that supplies the initialization voltage to a first electrode of the first sub light-emitting element in response to the first initialization signal, and a fourth transistor that supplies the initialization voltage to a first electrode of the second light-emitting element in response to the first initialization signal.

[0018] The pixel may further include a light emitting signal wiring to which a light emitting signal is applied, and a second sub-pixel connected to the light emitting signal wiring and the first initialization signal wiring, The second sub-pixel may include a second light emitting element emitting a second light, a fifth transistor supplying a second driving current to the second light emitting element in response to the first light emitting signal, and a sixth transistor supplying the initialization voltage to a first electrode of the second light emitting element in response to the first initialization signal.

[0019] The first light may be red light and the second light may be green light or blue light.

[0020] According to an embodiment of the present invention, a display device includes a first data wiring to which a first data voltage is applied, a second data wiring to which a second data voltage is applied, a first light-emitting signal wiring to which a first light-emitting signal is applied, a second light-emitting signal wiring to which a second light-emitting signal is applied, and a first sub-pixel connected to the first data wiring, the second data wiring, the first light-emitting signal wiring, and the second light-emitting signal wiring, The first sub-pixel includes a first light-emitting element including a first sub-light-emitting element and a second sub-light-emitting element emitting a first light, a first pixel driver generating a control current in response to the first data voltage of the first data wiring, a second pixel driver generating a drive current applied to the first sub-light-emitting element or the second sub-light-emitting element in response to the second data voltage of the second data wiring, and a third pixel driver controlling a period for applying the first drive current to the first sub-light-emitting element or the second sub-light-emitting element in response to the control current of the first pixel driver. The third pixel driving unit includes a first transistor for supplying a first driving current to the first sub light emitting element in response to the first light emitting signal, and a second transistor for supplying the first driving current to the second light emitting element in response to the second light emitting signal. One frame period includes a plurality of light emitting periods, and the first transistor and the second transistor are turned on during different light emitting periods among the plurality of light emitting periods.

[0021] The first transistor may be turned on during odd-numbered light-emitting periods of the plurality of light-emitting periods, and the second transistor may be turned on during even-numbered light-emitting periods of the plurality of light-emitting periods.

[0022] During odd-numbered light-emitting periods of the plurality of light-emitting periods, the first light-emitting signal may have a gate-on voltage and the second light-emitting signal may have a gate-off voltage, and during even-numbered light-emitting periods of the plurality of light-emitting periods, the second light-emitting signal may have the gate-on voltage and the first light-emitting signal may have the gate-off voltage.

[0023] The first sub-pixel may further include a first initialization signal wiring to which a first initialization signal is applied and an initialization voltage wiring to which an initialization voltage is applied. The first sub-pixel may further include a third transistor for supplying the initialization voltage to a first electrode of the first sub light-emitting element in response to the first initialization signal, and a fourth transistor for supplying the initialization voltage to a first electrode of the second light-emitting element in response to the first initialization signal.

[0024] The pixel may further include a second sub-pixel connected to the first light-emitting signal wiring and the second light-emitting signal wiring, the second sub-pixel may include a second light-emitting element emitting a second light, a fifth transistor supplying a second driving current to the second light-emitting element in response to the first light-emitting signal, and a sixth transistor supplying the second driving current to the second light-emitting element in response to the second light-emitting signal.

[0025] The second sub-pixel may further include a first initialization signal line to which a first initialization signal is applied and an initialization voltage line to which an initialization voltage is applied. The second sub-pixel may further include a seventh transistor configured to supply the initialization voltage to the first electrode of the second light-emitting element in response to the first initialization signal.

[0026] The first light may be red light and the second light may be green light or blue light.

[0027] Specific details of other embodiments are included in the detailed description and drawings. Effect of the Invention

[0028] According to the display device according to the embodiment, the sub-pixel emitting red light includes a first sub-light-emitting element and a second sub-light-emitting element that emit light for different periods. As a result, the emission period of the first sub-light-emitting element and the emission period of the second sub-light-emitting element of the first sub-pixel emitting red light can be reduced to half that of the emission period of the light-emitting element of the sub-pixel emitting green light or blue light. As a result, the heat generation amount of the first sub-light-emitting element and the heat generation amount of the second sub-light-emitting element can be reduced, and the temperature of the first sub-light-emitting element and the temperature of the second sub-light-emitting element can be reduced. As a result, it is possible to reduce or prevent a decrease in the emission luminance of the first sub-light-emitting element and the second sub-light-emitting element due to the heat generation of the first sub-light-emitting element and the second sub-light-emitting element that emit red light.

[0029] The effects of the embodiments are not limited to the above-mentioned examples, and more diverse effects are included in the present specification. [Brief description of the drawings]

[0030] [Figure 1] 1 is a plan view showing a display device according to an embodiment. [Diagram 2] FIG. 2 is an illustrative diagram showing an example of a pixel in FIG. [Diagram 3] 1. FIG. 4 is a diagram illustrating still another example of the pixel in FIG. [Figure 4] 1 is a block diagram showing a display device according to an embodiment. [Diagram 5] 1 is a graph showing luminous efficiency as a function of temperature of a first light emitting element, a second light emitting element, and a third light emitting element according to an embodiment. [Figure 6] 4 is an equivalent circuit diagram illustrating a first sub-pixel according to an embodiment. FIG. [Figure 7] FIG. 4 is an equivalent circuit diagram illustrating a second sub-pixel according to an embodiment. [Figure 8] FIG. 11 is an equivalent circuit diagram illustrating a third sub-pixel according to an embodiment. [Figure 9]FIG. 2 is a diagram showing an example of the operation of the display device during the N-th to (N+2)-th frame periods. [Figure 10] 11 is yet another exemplary diagram illustrating an operation of the display device during the Nth to (N+2)th frame periods. [Figure 11] FIG. 11 is a waveform diagram showing a kth scan initialization signal, a kth scan write signal, a kth scan control signal, a kth PWM light-emitting signal, a kth PAM light-emitting signal, a kth sweep signal, a voltage of a third node, a light-emitting timing of a light-emitting element, a first light-emitting control signal, and a second light-emitting control signal applied to a first sub-pixel arranged on a kth row line in an Nth and N+1th frame period according to an embodiment. [Figure 12] FIG. 11 is a timing diagram illustrating the kth sweep signal, the voltage of the gate electrode of the first transistor, the turn-on timing of the first transistor, and the turn-on timing of the fifteenth transistor during the fifth and sixth periods according to one embodiment. [Figure 13] 12 is a circuit diagram showing the operation of the first sub-pixel during a first period, a second period, a third period, a fifth period, and a sixth period of the Nth frame period of FIG. 11. FIG. [Figure 14] 12 is a circuit diagram showing the operation of the first sub-pixel during a first period, a second period, a third period, a fifth period, and a sixth period of the Nth frame period of FIG. 11. FIG. [Figure 15] 12 is a circuit diagram showing the operation of the first sub-pixel during a first period, a second period, a third period, a fifth period, and a sixth period of the Nth frame period of FIG. 11. FIG. [Figure 16] 12 is a circuit diagram showing the operation of the first sub-pixel during a first period, a second period, a third period, a fifth period, and a sixth period of the Nth frame period of FIG. 11. FIG. [Figure 17] 12 is a circuit diagram showing an operation of the first sub-pixel during a sixth period of the (N+1) frame period of FIG. 11. FIG. [Figure 18] 12 is a circuit diagram showing an operation of the second subpixel during a sixth period between the Nth frame period and the (N+1)th frame period in FIG. 11. FIG. [Figure 19] FIG. 2 is a layout diagram illustrating a pixel according to an embodiment. [Figure 20] FIG. 2 is a layout diagram illustrating a pixel according to an embodiment. [Figure 21] FIG. 20 is an enlarged layout diagram showing in detail area A of FIG. 19. [Figure 22] FIG. 20 is an enlarged layout diagram showing in detail area B of FIG. 19. [Figure 23] FIG. 21 is an enlarged layout diagram showing the details of region A in FIG. 20. [Figure 24] FIG. 20 is an enlarged layout diagram showing in detail area C of FIG. 19. [Diagram 25] FIG. 20 is an enlarged layout diagram showing in detail area D in FIG. 19. [Figure 26] FIG. 21 is an enlarged layout diagram showing in detail area C of FIG. 20. [Figure 27] 22 is a cross-sectional view showing an example of a display panel taken along the line AA' in FIG. 21. [Figure 28] 24 is a cross-sectional view showing an example of a display panel taken along line BB' in FIGS. 21 and 23. FIG. [Figure 29] 4 is an equivalent circuit diagram illustrating a first sub-pixel according to an embodiment. FIG. [Diagram 30] FIG. 4 is an equivalent circuit diagram illustrating a second sub-pixel according to an embodiment. [Diagram 31] FIG. 11 is an equivalent circuit diagram illustrating a third sub-pixel according to an embodiment. [Diagram 32] FIG. 11 is a waveform diagram showing a period during which the kth scan initialization signal, the kth scan write signal, the kth scan control signal, the kth PWM light-emitting signal, the kth PAMA light-emitting signal, the kth PAMB light-emitting signal, and the kth sweep signal are applied to a first sub-pixel arranged on the kth row line in an Nth frame period according to an embodiment, the voltage of the third node, and the driving current applied to the light-emitting element are applied. [Diagram 33] 1 is an exemplary diagram showing a PAMA luminescence signal output unit and a PAMB luminescence signal output unit according to an embodiment; [Diagram 34] FIG. 4 is a waveform diagram illustrating the PAMA clock signal and the PAMB clock signal according to one embodiment. [Diagram 35]1 is a perspective view illustrating a tiled display device including a plurality of display devices according to an embodiment. [Diagram 36] FIG. 36 is an enlarged layout diagram showing in detail area E of FIG. 35. [Figure 37] 37 is a cross-sectional view showing an example of a tiled display device taken along the line EE' in FIG. 36. [Figure 38] FIG. 36 is an enlarged layout diagram showing the F region in detail in FIG. [Figure 39] 39 is a cross-sectional view showing an example of a tiled display device taken along II' in FIG. 38. [Diagram 40] FIG. 1 is a block diagram showing a tiled display device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The advantages and features of the present invention, as well as the methods for achieving the same, will become clear from the detailed description of the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be realized in various different forms. The embodiments are provided merely to complete the disclosure of the present invention and to fully inform those skilled in the art of the invention of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0032] When elements or layers are referred to as being "on" other elements or layers, this includes all cases where other layers or other elements are directly on or between the other elements. The same reference numerals refer to the same components throughout the specification. The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining the embodiments are merely illustrative, and the present invention is not limited to the illustrated matters.

[0033] Although the terms "first" and "second" are used to describe various components, it is of course not intended that these components be limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is of course possible for the first component referred to below to be the second component within the technical spirit of the present invention.

[0034] The respective features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or in conjunction with each other.

[0035] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0036] Fig. 1 is a plan view illustrating a display device according to an embodiment, Fig. 2 is a diagram illustrating an example of a pixel of Fig. 1, Fig. 3 is a diagram illustrating another example of the pixel of Fig. 1.

[0037] 1 to 3, the display device 10 is a device for displaying moving images and still images, and can be used as a display screen for a variety of products, including portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, and Ultra Mobile PCs (UMPCs), as well as televisions, notebook computers, monitors, billboards, and Internet of Things (IOT).

[0038] The display panel 100 may be formed as a rectangular plane having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting with the first direction DR1. A corner where the long side in the first direction DR1 and the short side in the second direction DR2 intersect may be rounded or formed at a right angle to have a predetermined curvature. The plane shape of the display panel 100 is not limited to a rectangle, and may be formed as other polygonal, circular, or elliptical shapes. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may include curved portions formed on the left and right edges and having a constant curvature or a varying curvature. In addition, the display panel 100 may be formed flexibly so that it can be bent, warped, bent, folded, or rolled.

[0039] The display panel 100 may further include pixels PX, scan lines extending in a first direction DR1, and data lines extending in a second direction DR2 to display an image. The pixels PX may be arranged in a matrix in the first direction DR1 and the second direction DR2.

[0040] Each of the pixels PX may include a number of sub-pixels RP, GP, and BP, as shown in Figures 2 and 3. Figures 2 and 3 illustrate that each of the pixels PX includes three sub-pixels RP, GP, and BP, i.e., a first sub-pixel RP, a second sub-pixel GP, and a third sub-pixel BP, but the embodiments of the present specification are not limited thereto.

[0041] The first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be connected to one of the data lines and at least one of the scan lines.

[0042] Each of the first subpixel RP, the second subpixel GP, and the third subpixel BP may have a rectangular, square, or diamond-shaped planar shape. For example, each of the first subpixel RP, the second subpixel GP, and the third subpixel BP may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2 as shown in Fig. 2. Alternatively, each of the first subpixel RP, the second subpixel GP, and the third subpixel BP may have a square or diamond-shaped planar shape including sides having the same length in the first direction DR1 and the second direction DR2 as shown in Fig. 3.

[0043] As shown in Fig. 2, the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be arranged in a first direction DR1. Alternatively, one of the second sub-pixel GP and the third sub-pixel BP and the first sub-pixel RP may be arranged in the first direction DR1, and the remaining one of the second sub-pixel GP and the first sub-pixel RP may be arranged in the second direction DR2. For example, as shown in Fig. 3, the first sub-pixel RP and the second sub-pixel GP may be arranged in the first direction DR1, and the first sub-pixel RP and the third sub-pixel BP may be arranged in the second direction DR2.

[0044] Alternatively, one of the first sub-pixel RP and the third sub-pixel BP and the second sub-pixel GP may be arranged in the first direction DR1, and the remaining one and the second sub-pixel GP may be arranged in the second direction DR2. Alternatively, one of the first sub-pixel RP and the second sub-pixel GP and the third sub-pixel BP may be arranged in the first direction DR1, and the remaining one and the third sub-pixel BP may be arranged in the second direction DR2.

[0045] The first sub-pixel RP may include a first light-emitting element that emits a first light (e.g., light of a first color), the second sub-pixel GP may include a second light-emitting element that emits a second light (e.g., light of a second color), and the third sub-pixel BP may include a third light-emitting element that emits a third light (e.g., light of a third color). Here, the first light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band. The red wavelength band may be a wavelength band of approximately 600 nm to 750 nm, the green wavelength band may be a wavelength band of approximately 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of approximately 370 nm to 460 nm, but the embodiments of the present specification are not limited thereto.

[0046] Each of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may include an inorganic light-emitting element having an inorganic semiconductor as a light-emitting element that emits light. For example, the inorganic light-emitting element may be a flip chip type micro LED (Light Emitting Diode), but the embodiment of the present specification is not limited thereto.

[0047] As shown in Fig. 2 and Fig. 3, the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be substantially the same, but the embodiment of the present specification is not limited thereto. At least one of the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be different from the other one. Alternatively, any two of the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be substantially the same, and the remaining one may be different from the two. Alternatively, the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be different from each other.

[0048] FIG. 4 is a block diagram illustrating a display device according to an embodiment.

[0049] 4, the display device 10 includes a display panel 100, a scan driver 110, a source driver 200, a timing controller 300, and a power supply 400. The display panel 100 includes a scan driver 110, a source driver 200, a timing controller 300, and a power supply 400.

[0050] The display area DA of the display panel 100 may include sub-pixels RP, GP, BP that display images, scan write wiring GWL connected to the sub-pixels RP, GP, BP, scan initialization wiring GIL, scan control wiring GCL, sweep signal wiring SWPL, PWM (Pulse Width Modulation) light-emitting wiring PWEL, PAM (Pulse Amplitude Modulation) light-emitting wiring PAEL, PWM data wiring DL, a first PAM data wiring RDL, a second PAM data wiring GDL, and a third PAM data wiring BDL.

[0051] The scan write line GWL, the scan initialization line GIL, the scan control line GCL, the sweep signal line SWPL, the PWM light emission line PWEL, and the PAM light emission line PAEL may extend in a first direction DR1 and be arranged (placed) in a second direction DR2 intersecting the first direction DR1. The PWM data line DL, the first PAM data line RDL, the second PAM data line GDL, and the third PAM data line BDL may extend in the second direction DR2 and be arranged (placed) in the first direction DR1. The first PAM data lines RDL may be electrically connected to each other, the second PAM data lines GDL may be electrically connected to each other, and the third PAM data lines BDL may be electrically connected to each other.

[0052] Each of the sub-pixels RP, GP, and BP may be connected to one of the scan write lines GWL, one of the scan initialization lines GIL, one of the scan control lines GCL, one of the sweep signal lines SWPL, one of the PWM light emission lines PWEL, and one of the PAM light emission lines PAEL. Each of the first sub-pixels RP may be connected to one of the PWM data lines DL and one of the first PAM data lines RDL. Each of the second sub-pixels GP may be connected to one of the PWM data lines DL and one of the second PAM data lines GDL. Each of the third sub-pixels BP may be connected to one of the PWM data lines DL and one of the third PAM data lines BDL.

[0053] A scan driver 110 for applying signals to the scan write line GWL, the scan initialization line GIL, the scan control line GCL, the sweep signal line SWPL, the PWM light emission line PWEL, and the PAM light emission line PAEL may be disposed in the non-display area NDA of the display panel 100. In FIG. 4, the scan driver 110 is illustrated as being disposed on the periphery of one side of the display panel 100, but is not limited thereto. The scan driver 110 may be disposed on both edges of the display panel 100.

[0054] The scan driver 110 may include a first scan signal driver 111 , a second scan signal driver 112 , a sweep signal driver 113 , a light emission signal output unit 114 , and a light emission control signal output unit 115 .

[0055] The first scan signal driver 111 may receive a first scan drive control signal GDCS1 from the timing controller 300. The first scan signal driver 111 may output a scan initialization signal to the scan initialization line GIL and a scan write signal to the scan write line GWL in response to the first scan drive control signal GDCS1. That is, the first scan signal driver 111 may output two scan signals, i.e., a scan initialization signal and a scan write signal.

[0056] The second scan signal driver 112 may receive a second scan drive control signal GDCS2 from the timing control unit 300. The second scan signal driver 112 may output a scan control signal to the scan control line GCL in response to the second scan drive control signal GDCS2.

[0057] The sweep signal driving unit 113 may receive the first light-emitting control signal ECS1 and the sweep control signal SPCS from the timing control unit 300. The sweep signal driving unit 113 may output a PWM light-emitting signal to the PWM light-emitting wiring PWEL and a sweep signal to the sweep signal wiring SWPL in response to the first light-emitting control signal ECS1. That is, the sweep signal driving unit 113 may output both the PWM light-emitting signal and the sweep signal.

[0058] The light emission signal output unit 114 may receive an input of a second light emission control signal ECS2 from the timing control unit 300. The light emission signal output unit 114 may output a PAM light emission signal to the PAM light emission wiring PAEL in response to the second light emission control signal ECS2.

[0059] The light emission control signal output unit 115 may receive a third light emission control signal ECS3 from the timing control unit 300. The light emission control signal output unit 115 may output a light emission control signal to the light emission control wiring (RCL1, RCL2 in FIG. 6) in response to the third light emission control signal ECS3. The light emission control wiring (RCL1, RCL2 in FIG. 6) may be connected to the first sub-pixel RP, but may not be connected to the second sub-pixel GP and the third sub-pixel BP.

[0060] The timing controller 300 receives digital video data DATA and a timing signal TS. The timing controller 300 may generate a scan timing control signal STCS for controlling the operation timing of the scan driver 110 in response to the timing signal TS. The scan timing control signal STCS may generate a first scan drive control signal GDCS1, a second scan drive control signal GDSC2, a first light emission control signal ECS1, a second light emission control signal ECS2, a third light emission control signal ECS3, and a sweep control signal SWCS. The timing controller 300 may also generate a source control signal DCS for controlling the operation timing of the source driver 200.

[0061] The timing controller 300 outputs the first scan drive control signal GDCS1, the second scan drive control signal GDSC2, the first light emission control signal ECS1, the second light emission control signal ECS2, the third light emission control signal ECS3, and the sweep control signal SWCS to the scan driver 110. The timing controller 300 outputs a source control signal DCS for the digital video data DATA to the source driver 200.

[0062] The source driver 200 converts the digital video data DATA into an analog PWM data voltage and outputs it to the PWM data line DL. Thus, the sub-pixels RP, GP, and BP are selected by a scan write signal from the scan driver 110, and the PWM data voltage can be supplied to the selected sub-pixels RP, GP, and BP.

[0063] The power supply unit 400 may output a first PAM data voltage to the first PAM data line RDL in common, a second PAM data voltage to the second PAM data line GDL in common, and a third PAM data voltage to the third PAM data line BDL in common. The power supply unit 400 may generate a plurality of power supply voltages and output them to the display panel 100.

[0064] The power supply unit 400 may output a first power supply voltage VDD1, a second power supply voltage VDD2, a third power supply voltage VSS, an initialization voltage VINT, a gate-on voltage VGL, and a gate-off voltage VGH to the display panel 100. The first power supply voltage VDD1 and the second power supply voltage VDD2 may be high potential driving voltages for driving the light emitting elements of the sub-pixels RP, GP, and BP. The initialization voltage VINT may be a low potential driving voltage for driving the light emitting elements of the sub-pixels RP, GP, and BP. The initialization voltage VINT and the gate-off voltage VGH may be applied to the sub-pixels RP, GP, and BP, respectively, and the gate-on voltage VGL and the gate-off voltage VGH may be applied to the scan driver 110.

[0065] Each of the source driver 200, the timing controller 300, and the power supply 400 may be formed as an integrated circuit, or the source driver 200 may be formed as a plurality of integrated circuits.

[0066] FIG. 5 is a graph showing the luminous efficiency as a function of temperature of the first light emitting element and the third light emitting element according to an embodiment.

[0067] In Fig. 5, the X-axis shows the temperature of the first light-emitting element and the third light-emitting element, and the Y-axis shows the relative emission luminance ratio of the first light-emitting element and the third light-emitting element. In Fig. 5, when the temperature of the first light-emitting element and the third light-emitting element is 25 degrees, the emission luminance of the first light-emitting element and the third light-emitting element is calculated as 100%.

[0068] 5, each of the first and third light emitting elements emits light by a driving current and thereby emits heat, that is, each of the first and third light emitting elements is exposed to heat when driven.

[0069] The emission luminance ratio of the first light-emitting element changes significantly according to temperature changes. For example, when the temperature of the first light-emitting element is -20 degrees, the first light-emitting element has an emission luminance ratio of approximately 160%. In comparison, when the temperature of the first light-emitting element is 120 degrees, the first light-emitting element has an emission luminance ratio of approximately 40%. In other words, even if the same driving current is applied to the first light-emitting element, the emission luminance ratio of the first light-emitting element differs by approximately 120% in the temperature range from -20 degrees to 120 degrees.

[0070] The emission luminance ratio of the third light emitting element changes slightly according to temperature change. For example, when the same driving current is applied to the third light emitting element, the emission luminance ratio of the third light emitting element varies in the temperature range of approximately -20 degrees to 120 degrees.

[0071] 5, the first light emitting element is compared with the third light emitting element, and the second light emitting element is not mentioned, but the (change in) emission luminance ratio of the second light emitting element in response to temperature change may be smaller than the (change in) emission luminance ratio of the first light emitting element in response to temperature change. That is, since the first light emitting element is more sensitive to temperature change than the second and third light emitting elements, it is necessary to maintain the temperature of the first light emitting element low.

[0072] FIG. 6 is an equivalent circuit diagram showing a first sub-pixel according to still another embodiment.

[0073] 6, the first subpixel RP according to an embodiment may be connected to the kth (k is a positive integer) scan write line GWLk, the kth scan initialization line GILk, the kth scan control line GCLk, the kth sweep signal line SWPLk, the kth PWM light emission line PWELk, the kth PAM light emission line PAELk, the first light emission control line RCL1, and the second light emission control line RCL2. The first subpixel RP may also be connected to the jth PWM data line DLj and the first PAM data line RDL. The first subpixel RP may also be connected to the first power supply line VDL1 to which the first power supply voltage VDD1 is applied, the second power supply line VDL2 to which the second power supply voltage VDD2 is applied, the third power supply line VSL to which the third power supply voltage VSS is applied, the initialization voltage line VIL to which the initialization voltage VINT is applied, and the gate-off voltage line VGHL to which the gate-off voltage VGH is applied. For convenience of explanation, the j-th PWM data line DLj may be referred to as a first data line, and the first PAM data line RDL may be referred to as a second data line.

[0074] The first sub-pixel RP may include a first light-emitting element REL including a first sub-light-emitting element REL1 and a second sub-light-emitting element REL2, a first pixel driving unit PDU1, a second pixel driving unit PDU2, and a third pixel driving unit PDU3.

[0075] Each of the first and second sub-light-emitting elements REL1 and REL2 emits a first light in response to a driving current Ids generated by the second pixel driving unit PDU2. The first sub-light-emitting element REL1 may be disposed between the nineteenth transistor T19 and the third power wiring VSL, and the second sub-light-emitting element REL2 may be disposed between the twentieth transistor T20 and the third power wiring VSL. A first electrode of the first sub-light-emitting element REL1 may be coupled to a second electrode of the nineteenth transistor T19, and a second electrode of the first sub-light-emitting element REL1 may be coupled to the third power wiring VSL. A first electrode of the second sub-light-emitting element REL2 may be coupled to a second electrode of the twentieth transistor T20, and a second electrode of the second sub-light-emitting element REL2 may be coupled to the third power wiring VSL.

[0076] The first electrode of each of the first and second sub-light-emitting elements REL1 and REL2 may be an anode electrode, and the second electrode of each of the first and second sub-light-emitting elements REL1 and REL2 may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. For example, each of the first and second sub-light-emitting elements REL1 and REL2 may be, but is not limited to, a micro light-emitting diode made of an inorganic semiconductor.

[0077] The first pixel driving unit PDU1 generates a control current Ic in response to the jth PWM data voltage of the jth PWM data line DLj to control the voltage of the third node N3 of the third pixel driving unit PDU3. Since the pulse width of the driving current Ids flowing through the first light emitting element REL can be adjusted by the control current Ic of the first pixel driving unit PDU1, the first pixel driving unit PDU1 can be a pulse width modulation unit PWM unit that performs pulse width modulation of the driving current Ids flowing through the first light emitting element REL.

[0078] The first pixel driving unit PDU1 may include first to seventh transistors T1 to T7 and a first capacitor PC1.

[0079] The first transistor T1 controls a control current Ic flowing between the second electrode and the first electrode in response to a PWM data voltage applied to the gate electrode.

[0080] The second transistor T2 is turned on by a k-th scan write signal of the k-th scan write line GWLk to supply a PWM data voltage of the j-th PWM data line DLj to the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the k-th scan write line GWLk, the first electrode may be connected to the j-th PWM data line DLj, and the second electrode may be connected to the first electrode of the first transistor T1.

[0081] The third transistor T3 is turned on by the kth scan initialization signal of the kth scan initialization line GILk and connects the initialization voltage line VIL to the gate electrode of the first transistor T1. Thus, during a period in which the third transistor T3 is turned on, the gate electrode of the first transistor T1 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. At this time, the gate-on voltage VGL of the kth scan initialization signal may be different from the initialization voltage VINT of the initialization voltage line VIL. In particular, since the difference voltage between the gate-on voltage VGL and the initialization voltage VINT is greater than the threshold voltage of the third transistor T3, the third transistor T3 may be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the initialization voltage VINT may be stably applied to the gate electrode of the first transistor T1 regardless of the threshold voltage of the third transistor T3.

[0082] The third transistor T3 may include a plurality of transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. This can prevent the voltage of the gate electrode of the first transistor T1 from leaking through the third transistor T3. The gate electrode of the first sub-transistor T31 may be connected to the k-th scan initialization line GILk, the first electrode may be connected to the gate electrode of the first transistor T1, and the second electrode may be connected to the first electrode of the second sub-transistor T32. The gate electrode of the second sub-transistor T32 may be connected to the k-th scan initialization line GILk, the first electrode may be connected to the second electrode of the first sub-transistor T31, and the second electrode may be connected to the initialization voltage line VIL.

[0083] The fourth transistor T4 is turned on by a k-th scan write signal of the k-th scan write line GWLk to connect the gate electrode and the second electrode of the first transistor T1, so that the first transistor T1 may operate as a diode during a period in which the fourth transistor T4 is turned on.

[0084] The fourth transistor T4 may include a plurality of transistors connected in series. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42. This can prevent the voltage of the gate electrode of the first transistor T1 from leaking through the fourth transistor T4. The gate electrode of the third sub-transistor T41 may be connected to the k-th scan write line GWLk, the first electrode may be connected to the second electrode of the first transistor T1, and the second electrode may be connected to the first electrode of the fourth sub-transistor T42. The gate electrode of the fourth sub-transistor T42 may be connected to the k-th scan write line GWLk, the first electrode may be connected to the second electrode of the third sub-transistor T41, and the second electrode may be connected to the gate electrode of the first transistor T1.

[0085] The fifth transistor T5 is turned on by a kth PWM light-emitting signal of the kth PWM light-emitting wiring PWELk to connect a first electrode of the first transistor T1 to the first power supply wiring VDL1. A gate electrode of the fifth transistor T5 may be connected to the kth PWM light-emitting wiring PWELk, a first electrode may be connected to the first power supply wiring VDL1, and a second electrode may be connected to the first electrode of the first transistor T1.

[0086] The sixth transistor T6 is turned on by a kth PWM light-emitting signal of the kth PWM light-emitting wiring PWELk to connect the second electrode of the first transistor T1 to the third node N3 of the third pixel driving unit PDU3. A gate electrode of the sixth transistor T6 may be connected to the kth PWM light-emitting wiring PWELk, a first electrode of the sixth transistor T6 may be connected to the second electrode of the first transistor T1, and a second electrode of the sixth transistor T6 may be connected to the third node N3 of the third pixel driving unit PDU3.

[0087] The seventh transistor T7 may be turned on by the kth scan control signal of the kth scan control line GCLk to supply the gate-off voltage VGH of the gate-off voltage line VGHL to the first node N1 connected to the kth sweep signal line SWPLk. Thus, during a period in which the initialization voltage VINT is applied to the gate electrode of the first transistor T1 and a period in which the PWM data voltage of the jth PWM data line DLj and the threshold voltage Vth1 of the first transistor T1 are programmed, the first capacitor PC1 may prevent a voltage change of the gate electrode of the first transistor T1 from being reflected in the kth sweep signal of the kth sweep signal line SWPLk. The gate electrode of the seventh transistor T7 may be connected to the kth scan control line GCLk, a first electrode may be connected to the gate-off voltage line VGHL, and a second electrode may be connected to the first node N1.

[0088] The first capacitor PC1 may be disposed between the gate electrode of the first transistor T1 and the first node N1, with one electrode of the first capacitor PC1 being coupled to the gate electrode of the first transistor T1 and the other electrode being coupled to the first node N1.

[0089] The first node N1 may be a junction of the k-th sweep signal wiring SWPLk, the second electrode of the seventh transistor T7, and the other electrode of the first capacitor PC1.

[0090] The second pixel driving unit PDU2 generates a driving current Ids to be applied to the first light emitting element REL in response to a first PAM data voltage of the first PAM data line RDL. The second pixel driving unit PDU2 may be a pulse amplitude modulation unit (PAM unit) that performs pulse amplitude modulation. The second pixel driving unit PDU2 may be a constant current generating unit that generates a constant driving current Ids in response to the first PAM data voltage.

[0091] In addition, the second pixel driving units PDU2 of the first sub-pixels RP may receive the same first PAM data voltage and generate the same driving current Ids regardless of the luminance of the first sub-pixels RP. Similarly, the second pixel driving units PDU2 of the second sub-pixels GP may receive the same second PAM data voltage and generate the same driving current Ids regardless of the luminance of the second sub-pixels GP. The second pixel driving units PDU2 of the third sub-pixels BP may receive the same third PAM data voltage and generate the same driving current Ids regardless of the luminance of the third sub-pixels BP.

[0092] The second pixel driving unit PDU2 may include eighth to fourteenth transistors T8 to T14 and a second capacitor PC2.

[0093] The eighth transistor T8 controls the driving current Ids flowing through the first light emitting element REL in response to the voltage applied to the gate electrode.

[0094] The ninth transistor T9 is turned on by a kth scan write signal of the kth scan write line GWLk to supply the first PAM data voltage of the first PAM data line RDL to the first electrode of the eighth transistor T8. The ninth transistor T9 may have a gate electrode connected to the kth scan write line GWLk, a first electrode connected to the first PAM data line RDL, and a second electrode connected to the first electrode of the eighth transistor T8.

[0095] The tenth transistor T10 is turned on by the kth scan initialization signal of the kth scan initialization line GILk and connects the initialization voltage line VIL to the gate electrode of the eighth transistor T8. Thus, during the period in which the tenth transistor T10 is turned on, the gate electrode of the eighth transistor T8 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. At this time, the gate-on voltage VGL of the kth scan initialization signal may be different from the initialization voltage VINT of the initialization voltage line VIL. In particular, since the difference voltage between the gate-on voltage VGL and the initialization voltage VINT is greater than the threshold voltage of the tenth transistor T10, the tenth transistor T10 may be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the eighth transistor T8. Therefore, when the tenth transistor T10 is turned on, the initialization voltage VINT may be stably applied to the gate electrode of the eighth transistor T8 regardless of the threshold voltage of the tenth transistor T10.

[0096] The tenth transistor T10 may include a plurality of transistors connected in series. For example, the tenth transistor T10 may include a fifth sub-transistor T101 and a sixth sub-transistor T102. This prevents the voltage of the gate electrode of the eighth transistor T8 from leaking through the tenth transistor T10. The gate electrode of the fifth sub-transistor T101 may be connected to the kth scan initialization line GILk, the first electrode may be connected to the gate electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the sixth sub-transistor T102. The gate electrode of the sixth sub-transistor T102 may be connected to the kth scan initialization line GILk, the first electrode may be connected to the second electrode of the fifth sub-transistor T101, and the second electrode may be connected to the initialization voltage line VIL.

[0097] The eleventh transistor T11 is turned on by a kth scan write signal of the kth scan write line GWLk to connect the gate electrode and the second electrode of the eighth transistor T8, so that the eighth transistor T8 can operate as a diode during the period in which the eleventh transistor T11 is turned on.

[0098] The eleventh transistor T11 may include a plurality of transistors connected in series. For example, the eleventh transistor T11 may include a seventh sub-transistor T111 and an eighth sub-transistor T112. This can prevent the voltage of the gate electrode of the eighth transistor T8 from leaking through the eleventh transistor T11. The gate electrode of the seventh sub-transistor T111 may be connected to the k-th scan write line GWLk, the first electrode may be connected to the second electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the eighth sub-transistor T112. The gate electrode of the eighth sub-transistor T112 may be connected to the k-th scan write line GWLk, the first electrode may be connected to the second electrode of the seventh sub-transistor T111, and the second electrode may be connected to the gate electrode of the eighth transistor T8.

[0099] The twelfth transistor T12 is turned on by the kth PWM light-emitting signal of the kth PWM light-emitting wiring PWELk to connect the first electrode of the eighth transistor T8 to the second power supply wiring VDL2. The gate electrode of the twelfth transistor T12 may be connected to the kth PWM light-emitting wiring PWELk, the first electrode may be connected to the first power supply wiring VDL1, and the second electrode may be connected to the first electrode of the eighth transistor T8.

[0100] The thirteenth transistor T13 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the first power line VDL1 to the second node N2. The thirteenth transistor T13 has a gate electrode connected to the kth scan control line GCLk, a first electrode connected to the second power line VDL2, and a second electrode connected to the second node N2.

[0101] The fourteenth transistor T14 is turned on by the k-th PWM light-emitting signal of the k-th PWM light-emitting wiring PWELk to connect the second power supply wiring VDL2 to the second node N2. Thus, when the fourteenth transistor T14 is turned on, the second power supply voltage VDD2 of the second power supply wiring VDL2 may be supplied to the second node N2. The fourteenth transistor T14 may have a gate electrode connected to the k-th PWM light-emitting wiring PWELk, a first electrode connected to the second power supply wiring VDL2, and a second electrode connected to the second node N2.

[0102] The second capacitor PC2 may be disposed between the gate electrode of the eighth transistor T8 and the second node N2. One electrode of the second capacitor PC2 may be coupled to the gate electrode of the eighth transistor T8, and the other electrode may be coupled to the second node N2.

[0103] The second node N2 may be a junction of the second electrode of the thirteenth transistor T13, the second electrode of the fourteenth transistor T14, and the other electrode of the second capacitor PC2.

[0104] The third pixel driving unit PDU3 adjusts the period during which the driving current Ids is applied to the first light emitting element REL according to the voltage of the third node N3.

[0105] The third pixel driving unit PDU3 may include fifteenth to twentieth transistors T15 to T20 and a third capacitor PC3.

[0106] The fifteenth transistor T15 is turned on or off according to the voltage of the third node N3. When the fifteenth transistor T15 is turned on, the driving current Ids of the eighth transistor T8 is supplied to the first light emitting element REL, and when the fifteenth transistor T15 is turned off, the driving current Ids of the eighth transistor T8 is not supplied to the first light emitting element REL. Therefore, the turn-on period of the fifteenth transistor T15 may be substantially the same as the light emitting period of the first light emitting element REL. The gate electrode of the fifteenth transistor T15 may be connected to the third node N3, the first electrode may be connected to the second electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the seventeenth transistor T17.

[0107] The sixteenth transistor T16 is turned on in response to the k-th scan control signal of the k-th scan control line GCLk to connect the initialization voltage line VIL to the third node N3, so that the third node N3 may be discharged to the initialization voltage VINT of the initialization voltage line VIL during the period in which the sixteenth transistor T16 is turned on.

[0108] The sixteenth transistor T16 may include a plurality of transistors connected in series. For example, the sixteenth transistor T16 may include a ninth sub-transistor T161 and a tenth sub-transistor T162. This prevents the voltage V_N3 of the third node N3 from leaking through the sixteenth transistor T16. The gate electrode of the ninth sub-transistor T161 may be connected to the kth scan control line GCLk, the first electrode may be connected to the third node N3, and the second electrode may be connected to the first electrode of the tenth sub-transistor T162. The gate electrode of the tenth sub-transistor T162 may be connected to the kth scan control line GCLk, the first electrode may be connected to the second electrode of the ninth sub-transistor T161, and the second electrode may be connected to the initialization voltage line VIL.

[0109] The 17th transistor T17 is turned on by a kth PAM light-emitting signal of the kth PAM light-emitting wiring PAELk to connect the second electrode of the 15th transistor T15 to the first electrode of the 19th transistor T19 and the first electrode of the 20th transistor T20. The gate electrode of the 17th transistor T17 may be connected to the kth PAM light-emitting wiring PAELk, the first electrode may be connected to the second electrode of the 15th transistor T15, and the second electrode may be connected to the first electrode of the 19th transistor T19 and the first electrode of the 20th transistor T20.

[0110] The eighteenth transistor T18 may include an eleventh sub-transistor T181 and a twelfth sub-transistor T182.

[0111] The eleventh sub transistor T181 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the initialization voltage line VIL to the first electrode of the first sub light emitting element REL1. Thus, during a period in which the eleventh sub transistor T181 is turned on, the first electrode of the first sub light emitting element REL1 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. A gate electrode of the eleventh sub transistor T181 may be connected to the kth scan control line GCLk, a first electrode of the eleventh sub light emitting element REL1 may be connected to the first electrode of the first sub light emitting element REL1, and a second electrode of the eleventh sub transistor T181 may be connected to the initialization voltage line VIL.

[0112] The twelfth sub-transistor T182 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the initialization voltage line VIL to the first electrode of the second sub-light-emitting element REL2. Thus, during a period in which the twelfth sub-transistor T182 is turned on, the first electrode of the second sub-light-emitting element REL2 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. The gate electrode of the twelfth sub-transistor T182 may be connected to the kth scan control line GCLk, a first electrode of the twelfth sub-transistor T182 may be connected to the first electrode of the second sub-light-emitting element REL2, and a second electrode of the twelfth sub-transistor T182 may be connected to the initialization voltage line VIL.

[0113] The 19th transistor T19 is turned on by the first emission control signal of the first emission control line RCL1 to connect a first electrode of the first sub light-emitting element REL1 to a second electrode of the 17th transistor T17. Thus, during a period in which the 19th transistor T19 is turned on, a driving current Ids may be supplied to the first sub light-emitting element REL1. A gate electrode of the 19th transistor T19 may be connected to the first emission control line RCL1, a first electrode of the 19th transistor T19 may be connected to a second electrode of the 17th transistor T17, and a second electrode of the 19th transistor T19 may be connected to a first electrode of the first sub light-emitting element REL1.

[0114] The twentieth transistor T20 is turned on by the second emission control signal of the second emission control line RCL2 to connect the first electrode of the second sub light-emitting element REL2 to the second electrode of the seventeenth transistor T17. Thus, during a period in which the twentieth transistor T20 is turned on, a driving current Ids may be supplied to the second sub light-emitting element REL2. The gate electrode of the twentieth transistor T20 may be connected to the second emission control line RCL2, a first electrode of the twentieth transistor T20 may be connected to the second electrode of the seventeenth transistor T17, and a second electrode of the twentieth transistor T20 may be connected to the first electrode of the second sub light-emitting element REL2.

[0115] Any one of the first electrode and the second electrode of each of the first through twentieth transistors T1 through T20 may be a source electrode, and the remaining one may be a drain electrode. The active layer of each of the first through twentieth transistors T1 through T20 may be formed of any one of polysilicon, amorphous silicon, and an oxide semiconductor. When the active layer of each of the first through twentieth transistors T1 through T20 is polysilicon, it may be formed by a low temperature polysilicon (LTPS) process.

[0116] 6, the first through twentieth transistors T1-T20 are mainly formed of P-type metal oxide semiconductor field effect transistors (MOSFETs), but the embodiments of the present specification are not limited thereto. For example, the first through twentieth transistors T1-T20 may be formed of N-type MOSFETs.

[0117] Alternatively, in order to block leakage current and improve the black expression capability of the first light emitting element REL, in the first sub-pixel RP, the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, and the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed as N-type MOSFETs. In this case, the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, and the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be turned on when a gate-off voltage VGH is applied to the gate electrode. Therefore, the gate electrodes of the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, and the gate electrodes of the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be connected to a kth control line to which a kth control signal is applied, instead of the kth scan write line GWLk. In addition, the active layers of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, and the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed of an oxide semiconductor, and the remaining transistors may be formed of polysilicon.

[0118] Alternatively, one of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, the active layer of the transistor formed of the N-type MOSFET among the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 may be formed of an oxide semiconductor, and the active layer of the transistor formed of the P-type MOSFET may be formed of polysilicon.

[0119] Alternatively, one of the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, the active layer of the transistor formed of the N-type MOSFET among the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 may be formed of an oxide semiconductor, and the active layer of the transistor formed of the P-type MOSFET may be formed of polysilicon.

[0120] Alternatively, one of the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, the active layer of the transistor formed of the N-type MOSFET among the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10 may be formed of an oxide semiconductor, and the active layer of the transistor formed of the P-type MOSFET may be formed of polysilicon.

[0121] Alternatively, one of the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, the active layer of the transistor formed of the N-type MOSFET among the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed of an oxide semiconductor, and the active layer of the transistor formed of the P-type MOSFET may be formed of polysilicon.

[0122] FIG. 7 is an equivalent circuit diagram illustrating a second sub-pixel according to an embodiment.

[0123] The embodiment of Fig. 7 differs from the embodiment of Fig. 6 in that the second sub-pixel GP includes one light-emitting element GEL and does not include a nineteenth transistor T19 and a twentieth transistor T20. In Fig. 7, the description overlapping with the embodiment of Fig. 6 will be omitted.

[0124] 7, the second light emitting element GEL emits a second light in response to a driving current Ids generated by the second pixel driving unit PDU2. The second light emitting element GEL may be disposed between the seventeenth transistor T17 and the third power wiring VSL. A first electrode of the second light emitting element GEL may be coupled to a second electrode of the seventeenth transistor T17, and a second electrode of the second light emitting element GEL may be coupled to the third power wiring VSL.

[0125] The first electrode of the second light emitting element GEL may be an anode electrode, and the second electrode may be a cathode electrode. The second light emitting element GEL may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the second light emitting element GEL may be, but is not limited to, a micro light emitting diode made of an inorganic semiconductor.

[0126] The seventeenth transistor T17 is turned on by a k-th PAM light-emitting signal of the k-th PAM light-emitting wiring PAELk to connect the second electrode of the fifteenth transistor T15 to the first electrode of the second light-emitting element EL2. The gate electrode of the seventeenth transistor T17 may be connected to the k-th PAM light-emitting wiring PAELk, the first electrode may be connected to the second electrode of the fifteenth transistor T15, and the second electrode may be connected to the first electrode of the second light-emitting element EL2.

[0127] The 18th transistor T18 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the initialization voltage line VIL to the first electrode of the second light emitting element EL2. Thus, during a period in which the 18th transistor T18 is turned on, the first electrode of the second light emitting element EL2 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. A gate electrode of the 18th sub-transistor T18 may be connected to the kth scan control line GCLk, a first electrode of the 18th sub-transistor T18 may be connected to the first electrode of the second light emitting element EL2, and a second electrode of the 18th sub-transistor T18 may be connected to the initialization voltage line VIL.

[0128] FIG. 8 is an equivalent circuit diagram illustrating a third sub-pixel according to an embodiment.

[0129] The embodiment of Fig. 8 differs from the embodiment of Fig. 6 in that the third sub-pixel BP includes one third light-emitting element BEL, and does not include a nineteenth transistor T19 and a twentieth transistor T20. In Fig. 8, the description overlapping with the embodiment of Fig. 6 will be omitted.

[0130] 8, the third light emitting element BEL emits a third light in response to the driving current Ids generated by the second pixel driving unit PDU2. The third light emitting element BEL may be disposed between the seventeenth transistor T17 and the third power line VSL. A first electrode of the third light emitting element BEL may be coupled to a second electrode of the seventeenth transistor T17, and a second electrode of the third light emitting element BEL may be coupled to the third power line VSL.

[0131] The first electrode of the third light emitting element BEL may be an anode electrode, and the second electrode may be a cathode electrode. The third light emitting element BEL may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the third light emitting element BEL may be, but is not limited to, a micro light emitting diode made of an inorganic semiconductor.

[0132] The 17th transistor T17 and the 18th transistor T18 are substantially the same as those described with reference to FIG. 7, except that they are connected to the third light-emitting element BEL instead of the second light-emitting element GEL, and therefore the description thereof will be omitted.

[0133] FIG. 9 is a diagram showing an example of the operation of the display device during the Nth to (N+2)th frame periods.

[0134] 9, each of the Nth to N+2th frame periods may include an active period ACT and a blank period VB. The active period ACT may include a data addressing period ADDR for supplying a PWM data voltage and a first / second / third PAM data voltage to each of the first to third sub-pixels RP, GP, and BP, and a number of emission periods (EP1, EP2, EP3, EP4, EP5, ..., EPn) during which the light emitting element EL of each of the sub-pixels RP, GP, and BP emits light. The blank period VB may be a period during which the sub-pixels RP, GP, and BP of the display panel 100 are inactive.

[0135] The address period ADDR and the first light emission period EP1 are shorter than each of the second to n-th light emission periods (EP2, EP3, EP4, EP5, ..., EPn). For example, the address period ADDR and the first light emission period EP1 may be approximately 5 horizontal periods, and each of the second to n-th light emission periods (EP2, EP3, EP4, EP5, ..., EPn) may be approximately 12 horizontal periods, but the embodiment of the present specification is not limited thereto. In addition, the active period ACT may include 25 light emission periods, but the number of light emission periods (EP1, EP2, EP3, EP4, EP5, ..., EPn) in the active period ACT is not limited thereto.

[0136] The sub-pixels RP, GP, and BP of the display panel 100 may sequentially receive the PWM data voltage and the first / second / third PAM data voltages for each row line during the address period ADDR. For example, the sub-pixels RP, GP, and BP arranged on the first row line to the sub-pixels RP, GP, and BP arranged on the n-th row line corresponding to the last row line may sequentially receive the PWM data voltage and the first / second / third PAM data voltages.

[0137] The sub-pixels RP, GP, and BP of the display panel 100 may emit light sequentially for each row during each of a plurality of emission periods (EP1, EP2, EP3, EP4, EP5, ..., EPn). For example, the sub-pixels RP, GP, and BP arranged in the first row may emit light sequentially to the sub-pixels RP, GP, and BP arranged in the last row.

[0138] The address period ADDR may overlap at least one of the emission periods (EP1, EP2, EP3, EP4, ..., EPn). For example, as shown in Fig. 9, the address period ADDR may overlap the first to third emission periods EP1, EP2, EP3. In this case, when the sub-pixels RP, GP, BP arranged on the pth row line (p is a positive integer) receive the PWM data voltage and the first / second / third PAM data voltages, the sub-pixels RP, GP, BP arranged on the qth row line (q is a positive integer smaller than p) may emit light.

[0139] Furthermore, each of the light emission periods (EP1, EP2, EP3, EP4, ..., EPn) may overlap with the adjacent light emission period. For example, the second light emission period EP2 may overlap with the first light emission period EP1 and the third light emission period EP3. In this case, the sub-pixels RP, GP, and BP arranged on the pth row line may emit light in the second light emission period EP2, while the sub-pixels RP, GP, and BP arranged on the qth row line may emit light in the first light emission period EP1.

[0140] FIG. 10 is a diagram showing another example of the operation of the display device during the Nth to N+2th frame periods.

[0141] 10 differs from the embodiment of FIG. 9 in that the sub-pixels RP, GP, and BP of the display panel 100 emit light simultaneously in each of a plurality of light-emitting periods (EP1, EP2, EP3, EP4, EP5, . . . , EPn).

[0142] 10, the address period ADDR does not overlap with the plurality of light emission periods (EP1, EP2, EP3, EP4, ..., EPn). The first light emission period EP1 may occur after the address period ADDR is completely finished.

[0143] The multiple light emission periods (EP1, EP2, EP3, EP4, ..., EPn) do not overlap with each other. In each of the multiple light emission periods (EP1, EP2, EP3, EP4, EP5, ..., EPn), the sub-pixels RP, GP, and BP arranged on all row lines can emit light simultaneously.

[0144] FIG. 11 is a waveform diagram showing the kth scan initialization signal, the kth scan write signal, the kth scan control signal, the kth PWM light-emitting signal, the kth PAM light-emitting signal, the kth sweep signal, the voltage of the third node, the light-emitting timing of the light-emitting element, the first light-emitting control signal, and the second light-emitting control signal applied to the first sub-pixel arranged on the kth row line during the Nth and N+1th frame periods according to one embodiment.

[0145] 11, the first sub-pixel RP arranged on the kth row line may be connected to the kth scan initialization line GILk, the kth scan write line GWLk, the kth scan control line GCLk, the kth PWM light-emitting line PWELk, the kth PAM light-emitting line PAELk, the kth sweep signal line SWPLk, the first light-emitting control line RCL1, and the second light-emitting control line RCL2. The kth scan initialization signal GIk refers to a signal applied to the kth scan initialization line GILk, the kth scan write signal GWk refers to a signal applied to the kth scan write line GWLk, the kth scan control signal GCk refers to a signal applied to the kth scan control line GCLk, and the kth PWM light-emitting signal PWEMk refers to a signal applied to the kth PWM light-emitting line PWELk. The kth PAM light-emitting signal PAEMk refers to a signal applied to the kth PAM light-emitting wiring PAELk, the kth sweep signal SWPk refers to a signal applied to the kth sweep signal wiring SWPLk, the first light-emitting control signal RCS1 refers to a signal applied to the first light-emitting control wiring RCL1, and the second light-emitting control signal RCS2 refers to a signal applied to the second light-emitting control wiring RCL2.

[0146] The scan initialization signals GIk to GIk+5, the scan write signals GWk to GWk+5, the scan control signals GCk to GCk+5, the PWM light emission signals PWEMk to PAEMk+5, the PAM light emission signals PAEMk to PAEMk+5, and the sweep signals SWPk to SWPk+5 may be shifted sequentially by one horizontal period. The kth scan write signal GWk may be a signal obtained by shifting the kth scan initialization signal GIk by one horizontal period, and the k+1th scan write signal GWk+1 may be a signal obtained by shifting the k+1th scan initialization signal GIk+1 by one horizontal period. In this case, since the k+1th scan initialization signal GIk+1 is a signal obtained by shifting the kth scan initialization signal GIk by one horizontal period, the kth scan write signal GWk and the k+1th scan initialization signal GIk+1 may be substantially the same.

[0147] The k-th scan initialization signal GIk is a signal for controlling the turn-on and turn-off of the third and tenth transistors T3, T10 of the sub-pixels RP, GP, and BP, respectively. The k-th scan write signal GWk is a signal for controlling the turn-on and turn-off of the second, fourth, ninth, and eleventh transistors T2, T4, T9, and T11 of the sub-pixels RP, GP, and BP, respectively. The k-th scan control signal GCk is a signal for controlling the turn-on and turn-off of the seventh, thirteenth, sixteenth, and eighteenth transistors T7, T13, T16, and T18 of the sub-pixels RP, GP, and BP, respectively. The k-th PWM light emission signal PWEMk is a signal for controlling the turn-on and turn-off of the fifth, sixth, twelfth, and fourteenth transistors T5, T6, T12, and T14. The k-th PAM light emission signal PAEMk is a signal for controlling the turn-on and turn-off of the seventeenth transistor T17. The first light-emitting control signal RCS1 is a signal for controlling the turn-on and turn-off of the nineteenth transistor T19. The second light-emitting control signal RCS2 is a signal for controlling the turn-on and turn-off of the twentieth transistor T20. The kth scan initialization signal, the kth scan write signal, the kth scan control signal, the kth PWM light-emitting signal, the kth PAM light-emitting signal, and the kth sweep signal may be generated with a period of one frame period.

[0148] The address period ADDR includes first to fourth periods t1 to t4. The first period t1 and the fourth period t4 are first initialization periods for initializing the first electrode of the light-emitting element EL and the voltage V_N3 of the third node N3. The second period t2 is a second initialization period for initializing the gate electrode of the first transistor T1 and the gate electrode of the eighth transistor T8. The third period t3 is a period for sampling the PWM data voltage Vdata of the jth PWM data line DLj and the threshold voltage Vth1 of the first transistor T1 at the gate electrode of the first transistor T1, and for sampling the first PAM data voltage Rdata of the first PAM data line RDL and the threshold voltage Vth8 of the eighth transistor T8 at the gate electrode of the eighth transistor T8.

[0149] The first light emission period EM1 includes a fifth period t5 and a sixth period t6. The first light emission period EM1 is a period in which the turn-on period of the fifteenth transistor T15 is controlled in response to the control current Ic and the driving current Ids is supplied to the light emitting element EL.

[0150] The second to n-th light emission periods EM2 to EMn each include seventh to ninth periods t7 to t9. The seventh period t7 is a third initialization period for initializing the third node N3, the eighth period t8 is substantially the same period as the fifth period t5, and the ninth period t9 is substantially the same period as the sixth period t6.

[0151] Adjacent light emission periods among the first to n-th light emission periods EM1 to EMn can be spaced apart by approximately several horizontal periods to several tens of horizontal periods.

[0152] The kth scan initialization signal GIk may have a gate-on voltage VGL during the second period t2 and a gate-off voltage VGH during the remaining period. That is, the kth scan initialization signal GIk may have a scan initialization pulse generated by the gate-on voltage VGL during the second period t2. The gate-off voltage VGH may be a voltage level higher than the gate-on voltage VGL.

[0153] The kth scan write signal GWk may have a gate-on voltage VGL during the third period t3 and a gate-off voltage VGH during the remaining period, i.e., the kth scan write signal GWk may have a scan write pulse generated by the gate-on voltage VGL during the third period t3.

[0154] The kth scan control signal GCk may have a gate-on voltage VGL during the first through fourth periods t1 to t4 and the seventh period t7, and a gate-off voltage VGH during the remaining periods. That is, the kth scan control signal GCk may have a scan control pulse generated by the gate-on voltage VGL during the first through fourth periods t1 to t4 and the seventh period t7.

[0155] The kth sweep signal SWPk may have a sweep pulse in the form of a triangular wave during the sixth period t6 and the ninth period t9, and may have a gate-off voltage VGH during the remaining periods. For example, the sweep pulse of the kth sweep signal SWPk may have a triangular wave pulse that linearly decreases from the gate-off voltage VGH to the gate-on voltage VGL during each of the sixth period t6 and the ninth period t9, and immediately increases from the gate-on voltage VGL to the gate-off voltage Voff at the end of the sixth period t6 and the end of the ninth period t9.

[0156] The kth PWM light-emitting signal PWEMk may have a gate-on voltage VGL during the fifth and sixth periods t5, t6 and the eighth and ninth periods t8, t9, and may have a gate-off voltage VGH during the remaining periods. That is, the kth PWM light-emitting signal PWEMk may include a PWM pulse generated by the gate-on voltage VGL during the fifth and sixth periods t5, t6 and the eighth and ninth periods t8, t9. The PWM pulse width of the kth PWM light-emitting signal PWEMk may be greater than the sweep pulse width of the kth sweep signal SWPk.

[0157] The kth PAM light-emitting signal PAEMk may have a gate-on voltage VGL during the sixth period t6 and the ninth period t9, and may have a gate-off voltage VGH during the remaining periods. That is, the kth PAM light-emitting signal PAEMk may include a PAM pulse generated by the gate-on voltage VGL during the sixth period t6 and the ninth period t9.

[0158] The first light-emitting control signal RCS1 may have a gate-on voltage VGL during the Nth frame period and a gate-off voltage Voff during the N+1th frame period. The second light-emitting control signal RCS2 may have a gate-off voltage Voff during the Nth frame period and a gate-on voltage VGL during the N+1th frame period. That is, the first light-emitting control signal RCS1 and the second light-emitting control signal RCS2 may have different voltages in one frame period.

[0159] 12 is a timing diagram showing the kth sweep signal, the voltage of the gate electrode of the first transistor, the turn-on timing of the first transistor, and the turn-on timing of the fifteenth transistor during the fifth and sixth periods according to an embodiment. FIGs. 13 to 16 are circuit diagrams showing the operation of the first sub-pixel during the first, second, third, fifth, and sixth periods in the Nth frame period of FIG. 11.

[0160] Hereinafter, the operation of the first sub-pixel RP according to an embodiment in the first to ninth periods t1 to t9 during the Nth frame period will be examined in detail with reference to FIGS.

[0161] During the Nth frame period, the nineteenth transistor T19 is turned on by the first emission control signal RCS1 having the gate-on voltage VGL, and the twentieth transistor T20 is turned off by the second emission control signal RCS2 having the gate-off voltage VGH.

[0162] First, during the first period t1, as shown in FIG. 13, the eleventh sub-transistor T181 and the twelfth sub-transistor T182 of the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on by the kth scan control signal GCk of the gate-on voltage VGL.

[0163] When the seventh transistor T7 is turned on, the gate-off voltage VGH of the gate-off voltage line VGHL is applied to the first node N1, and when the thirteenth transistor T13 is turned on, the first power supply voltage VDD1 of the first power supply line VDL1 is applied to the second node N2.

[0164] As the sixteenth transistor T16 is turned on, the third node N3 is initialized to the initialization voltage VINT of the initialization voltage line VIL, and the fifteenth transistor T15 is turned on by the initialization voltage VINT of the third node N3.

[0165] When the first sub-transistor T181 and the second sub-transistor T182 of the eighteenth transistor T18 are turned on, the first electrode of the first sub-light-emitting element REL1 and the first electrode of the second sub-light-emitting element REL2 are initialized to the initialization voltage VINT of the initialization voltage line VIL.

[0166] Secondly, during the second period t2, the first sub-transistor T181 and the second sub-transistor T182 of the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on by the k-th scan control signal GCk of the gate-on voltage VGL, as shown in Fig. 14. Also, during the second period t2, the third transistor T3 and the tenth transistor T10 are turned on by the k-th scan initialization signal Gik of the gate-on voltage VGL.

[0167] The seventh transistor T7, the thirteenth transistor T13, the fifteenth transistor T15, the sixteenth transistor T16, and the first sub-transistor T181 and the second sub-transistor T182 of the eighteenth transistor T18 are substantially the same as those described in the first period t1.

[0168] When the third transistor T3 is turned on, the gate electrode of the first transistor T1 is initialized to the initialization voltage VINT of the initialization voltage line VIL. When the tenth transistor T10 is turned on, the gate electrode of the eighth transistor T8 is initialized to the initialization voltage VINT of the initialization voltage line VIL.

[0169] At this time, the gate-off voltage VGH of the gate-off voltage line VGHL is applied to the first node N1, so that the first capacitor PC1 causes the voltage change amount of the gate electrode of the first transistor T1 to be reflected on the k-th sweep signal line SWPLk, thereby preventing the gate-off voltage VGH of the k-th sweep signal SWPk from fluctuating.

[0170] Thirdly, during the third period t3, the first sub-transistor T181 and the second sub-transistor T182 of the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on by the kth scan control signal GCk of the gate-on voltage VGL, as shown in Fig. 15. Also, during the third period t3, the second transistor T2, the fourth transistor T4, the ninth transistor T9, and the eleventh transistor T11 are turned on by the kth scan write signal GWk of the gate-on voltage VGL.

[0171] The seventh transistor T7, the thirteenth transistor T13, the fifteenth transistor T15, the sixteenth transistor T16, and the first sub-transistor T181 and the second sub-transistor T182 of the eighteenth transistor T18 are substantially the same as those described in the first period t1.

[0172] When the second transistor T2 is turned on, the PWM data voltage Vdata of the jth PWM data line DLj is applied to the first electrode of the first transistor T1. When the fourth transistor T4 is turned on, the gate electrode and the second electrode of the first transistor T1 are connected to each other, so that the first transistor T1 operates as a diode.

[0173] At this time, since the voltage between the gate electrode and the first electrode of the first transistor T1 (Vgs=VINT-Vdata) is greater than the threshold voltage Vth1, the first transistor T1 is turned on and forms a current path until the voltage Vgs between the gate electrode and the first electrode reaches the threshold voltage Vth1. As a result, the voltage of the gate electrode of the first transistor T1 can rise from "VINT" to "Vdata+Vth1". Since the first transistor T1 is formed of a P-type MOSFET, the threshold voltage Vth1 of the first transistor T1 is less than 0V.

[0174] In addition, since the gate-off voltage VGH of the gate-off voltage line VGHL is applied to the first node N1, the first capacitor PC1 causes the voltage change amount of the gate electrode of the first transistor T1 to be reflected on the k-th sweep signal line SWPLk, thereby preventing the gate-off voltage VGH of the k-th sweep signal SWPk from fluctuating.

[0175] When the ninth transistor T9 is turned on, the first PAM data voltage Rdata of the first PAM data line RDL is applied to the first electrode of the eighth transistor T8. When the ninth transistor T9 is turned on, the gate electrode and the second electrode of the eighth transistor T8 are connected to each other, so that the eighth transistor T8 operates as a diode.

[0176] At this time, since the voltage between the gate electrode and the first electrode of the eighth transistor T8 (Vgs=VINT-Rdata) is greater than the threshold voltage Vth8, the eighth transistor T8 forms a current path until the voltage Vgs between the gate electrode and the first electrode reaches the threshold voltage Vth8. As a result, the voltage of the gate electrode of the eighth transistor T8 can rise from "VINT" to "Rdata+Vth8".

[0177] Fourth, during the fourth period t4, the first sub-transistor T181 and the second sub-transistor T182 of the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on by the kth scan control signal GCk of the gate-on voltage VGL.

[0178] The seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the first sub-transistor T181 and the second sub-transistor T182 of the eighteenth transistor T18 are substantially the same as those described in the first period t1.

[0179] Fifth, during a fifth period t5, as shown in FIG. 16, the fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the fourteenth transistor T14 are turned on by the kth PWM light-emitting signal PWEMk of the gate-on voltage VGL.

[0180] When the fifth transistor T5 is turned on, the first power supply voltage VDD1 is applied to the first electrode of the first transistor T1, and when the sixth transistor T6 is turned on, the second electrode of the first transistor T1 is connected to the third node N3.

[0181] During the fifth period t5, the control current Ic flowing due to the voltage (Vdata+Vth1) of the gate electrode of the first transistor T1 does not depend on the threshold voltage Vth1 of the first transistor T1 as shown in Equation 1.

[0182]

number

[0183] In Equation 1, k″ is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vth1 is a threshold voltage of the first transistor T1, VDD1 is a first power supply voltage, and Vdata is a PWM data voltage. In Equation 1, Vgs is a voltage between the gate electrode and the first electrode of the first transistor T1.

[0184] In addition, when the twelfth transistor T12 is turned on, the first electrode of the eighth transistor T8 may be coupled to the second power line VDL2.

[0185] Furthermore, when the fourteenth transistor T14 is turned on, the second power supply voltage VDD2 of the second power supply wiring VDL2 is applied to the second node N2. When the second power supply voltage VDD2 of the second power supply wiring VDL2 fluctuates due to a voltage drop or the like, the voltage difference (ΔV2) between the first power supply voltage VDD1 and the second power supply voltage VDD2 may be reflected in the gate electrode of the eighth transistor T8 by the second capacitor PC2.

[0186] When the fourteenth transistor T14 is turned on, a driving current Ids that flows according to the gate voltage (Rdata+Vth8) of the eighth transistor T8 can be supplied to the fifteenth transistor T15. The driving current Ids does not depend on the threshold voltage Vth8 of the eighth transistor T8 as shown in Equation 2.

[0187]

number

[0188] In Equation 2, k' is a proportionality coefficient determined by the structure and physical characteristics of the eighth transistor T8, Vth8 is a threshold voltage of the eighth transistor T8, VDD2 is a second power supply voltage, and Rdata is a first PAM data voltage. In Equation 2, Vgs is a voltage between the gate electrode and the first electrode of the eighth transistor T8.

[0189] Sixth, during the sixth period t6, the fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the fourteenth transistor T14 are turned on by the kth PWM light-emitting signal PWEMk of the gate-on voltage VGL, as shown in Fig. 16. During the sixth period t6, the seventeenth transistor T17 is turned on by the kth PAM light-emitting signal PAEMk of the gate-on voltage VGL, as shown in Fig. 16. During the sixth period t6, the kth sweep signal SWPk linearly decreases from the gate-off voltage VGH to the gate-on voltage VGL.

[0190] The fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the fourteenth transistor T14 are substantially the same as those described in the fifth period t5.

[0191] During the N-th frame period, the 19th transistor T19 is turned on by the first light-emitting control signal RCS1 of the gate-on voltage VGL, so that when the 17th transistor T17 is turned on, the first electrode of the first sub light-emitting element REL1 may be connected to the second electrode of the 15th transistor T15.

[0192] During the sixth period t6, the kth sweep signal SWPk linearly decreases from the gate-off voltage VGH to the gate-on voltage VGL, and the voltage change amount (ΔV1) of the kth sweep signal SWPk is reflected to the gate electrode of the first transistor T1 by the first capacitor PC1, so that the voltage of the gate electrode of the first transistor T1 can be Vdata+Vth1-ΔV1. That is, during the sixth period t6, the voltage of the gate electrode of the first transistor T1 linearly decreases due to the voltage decrease of the kth sweep signal SWPk.

[0193] The period during which the control current Ic is applied to the third node N3 may vary depending on the magnitude of the PWM data voltage Vdata applied to the first transistor T1. As a result, the voltage V_N3 of the third node N3 varies depending on the magnitude of the PWM data voltage Vdata applied to the first transistor T1, so that the turn-on period of the fifteenth transistor T15 can be controlled. Therefore, by controlling the turn-on period of the fifteenth transistor T15, the period SEP during which the driving current Ids is applied to the first sub-light-emitting element REL1 during the sixth period t6 can be controlled.

[0194] First, as shown in FIG. 12, when the PWM data voltage Vdata of the gate electrode of the first transistor T1 is the PWM data voltage of the peak black gradation, the voltage VG_T1 of the gate electrode of the first transistor T1 is lower than the first power supply voltage VDD1, which is the voltage of the first electrode of the first transistor T1, during the sixth period t6 according to the voltage decrease of the k-th sweep signal SWPk. Therefore, the first transistor T1 may be turned on during the sixth period t6. As a result, the control current Ic of the first transistor T1 may flow to the third node N3 during the fifth period t5 and the sixth period t6, and the voltage V_N3 of the third node N3 may rise to the high level VH during the fifth period t5. Therefore, the fifteenth transistor T15 may be turned off during the sixth period t6. Therefore, the driving current Ids is not applied to the first sub light-emitting element REL1 during the sixth period t6, so that the first sub light-emitting element REL1 does not emit light during the sixth period t6.

[0195] 12, when the PWM data voltage Vdata of the gate electrode of the first transistor T1 is a gray-level PWM data voltage, the voltage VG_T1 of the gate electrode of the first transistor T1 may have a level higher than the first power supply voltage VDD1 during the first sub-period t61 and a level lower than the first power supply voltage VDD1 during the second sub-period t62 due to the voltage reduction of the k-th sweep signal SWPk. Thus, the first transistor T1 may be turned on during the second sub-period t62 of the sixth period t6. In this case, the control current Ic of the first transistor T1 flows to the third node N3 during the second sub-period t62, so that the voltage V_N3 of the third node N3 may have a high level VH during the second sub-period t62. Thus, the fifteenth transistor T15 may be turned off during the second sub-period t62. Therefore, the driving current Ids is applied to the first sub-light-emitting element REL1 during the first sub-period t61, and is not applied to the first sub-light-emitting element REL1 during the second sub-period t62. That is, the first sub-light-emitting element REL1 can emit light during the first sub-period t61, which is a part of the sixth period t6. The closer the first sub-pixel RP expresses a gray gradation to the peak black gradation, the shorter the emission period SET of the first sub-light-emitting element REL1. Also, the closer the first sub-pixel RP expresses a gray gradation to the peak white gradation, the longer the emission period SET of the first sub-light-emitting element REL1.

[0196] Also, as shown in FIG. 12, when the PWM data voltage Vdata of the gate electrode of the first transistor T1 is the PWM data voltage of the peak white gradation, the voltage VG_T1 of the gate electrode of the first transistor T1 is higher than the first power supply voltage VDD1 during the sixth period t6 despite the voltage reduction of the k-th sweep signal SWPk. As a result, the first transistor T1 can be turned off throughout the sixth period t6. In this case, the control current Ic of the first transistor T1 does not flow to the third node N3 throughout the sixth period t6, so that the voltage of the third node N3 can maintain the initialization voltage VINT. Therefore, the fifteenth transistor T15 can be turned on throughout the sixth period t6. Therefore, the driving current Ids is applied to the first sub-light-emitting element REL1 throughout the sixth period t6, and the first sub-light-emitting element REL1 can emit light throughout the sixth period t6.

[0197] Also, at the end of the sixth period t6, as the kth sweep signal SWPk rises from the gate-on voltage VGL to the gate-off voltage VGH, the voltage VG_T1 of the gate electrode of the first transistor T1 can rise to be substantially the same as that of the fifth period t5.

[0198] Meanwhile, when the digital video data converted into the PWM data voltage is 8 bits, the digital video data of the peak black gradation may be 0, and the digital video data of the peak white gradation may be 255. In addition, the digital video data in the black gradation area may be 0 to 63, the digital video data in the gray gradation area may be 64 to 191, and the digital video data in the white gradation area may be 192 to 255.

[0199] Also, the seventh period t7, the eighth period t8, and the ninth period t9 in each of the second to n-th light-emitting periods EP2 to EPn are substantially the same as the first period t1, the fifth period t5, and the sixth period t6 described above. That is, in each of the second to n-th light-emitting periods EP2 to EPn, after the third node N3 is initialized, the period during which the driving current Ids generated by the first PAM data voltage Rdata written to the gate electrode of the eighth transistor T8 based on the PWM data voltage Vdata written to the gate electrode of the first transistor T1 during the address period ADDR is applied to the first sub-light-emitting element REL1 can be adjusted.

[0200] FIG. 17 is an equivalent circuit diagram showing an operation of the first sub-pixel during a sixth period in the (N+1)th frame period of FIG.

[0201] 17, during the (N+1)th frame period, the 19th transistor T19 is turned off by the first light-emitting control signal RCS1 having the gate-off voltage VGH, and the 20th transistor T20 is turned on by the second light-emitting control signal RCS2 having the gate-on voltage VGL. Therefore, when the 17th transistor T17 is turned on, the first electrode of the second sub-light-emitting element REL2 may be connected to the second electrode of the 15th transistor T15. Therefore, during the sixth period t6, the driving current Ids is applied to the second sub-light-emitting element REL2, and the second sub-light-emitting element REL2 may emit light.

[0202] That is, the operation of the sixth period t6 of the first sub-pixel RP during the Nth frame period is substantially similar to the operation of the sixth period t6 of the first sub-pixel RP during the Nth frame period described with reference to FIG. 16, except that the second sub-light-emitting element REL2 emits light instead of the first sub-light-emitting element REL1, and therefore a description thereof will be omitted.

[0203] As described above, the light emitting period SET of the first sub light emitting element REL1 and the light emitting period of the second sub light emitting element REL2 can be adjusted by adjusting the PWM data voltage applied to the gate electrode of the first transistor T1. Therefore, by adjusting the magnitude of the driving current Ids, the gray scale to be expressed by the first sub-pixel RP can be adjusted by adjusting the period during which the driving current Ids is applied to the first sub light emitting element REL1 or the second sub light emitting element REL2 while keeping the driving current Ids constant.

[0204] Also, the first sub-pixel RP emits light through the first sub-light-emitting element REL1 during the Nth frame period, and emits light through the second sub-light-emitting element REL2 during the N+1th frame period. That is, the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2 of the first sub-pixel RP emit light during different periods. Therefore, the emission period SET of the first sub-light-emitting element REL1 and the emission period of the second sub-light-emitting element REL2 may be reduced to half of the emission period of the second light-emitting element GEL and the emission period of the third light-emitting element BEL, respectively. This can reduce the amount of heat generated by the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2, thereby lowering the temperature of the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2. Therefore, it is possible to reduce or prevent the emission luminance of the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2 from decreasing due to the heat generated by the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2.

[0205] FIG. 18 is an equivalent circuit diagram showing an operation of the second sub-pixel during a sixth period between the Nth frame period and the (N+1)th frame period in FIG.

[0206] 18, the second sub-pixel GP includes one second light-emitting element GEL, and when the seventeenth transistor T17 is turned on, a first electrode of the second light-emitting element GEL may be connected to a second electrode of the fifteenth transistor T15. Thus, during the sixth period t6, the driving current Ids is applied to the second light-emitting element GEL, and the second light-emitting element GEL may emit light.

[0207] In other words, the operation of the sixth period t6 of the second sub-pixel GP is substantially similar to the operation of the sixth period t6 of the first sub-pixel RP during the Nth frame period described with reference to FIG. 16, except that the second light-emitting element GEL emits light regardless of whether it is the Nth frame period or the N+1th frame period, and therefore a description thereof will be omitted.

[0208] In addition, the operation of the second sub-pixel GP during the first to fifth periods t1 to t5 may be substantially the same as the operation of the first sub-pixel RP during the first to fifth periods t1 to t5 described with reference to Figures 11 to 16, so a description thereof will be omitted.

[0209] On the other hand, since the operation of the third subpixel BP is substantially similar to that of the second subpixel GP, a description of the operation of the third subpixel BP during the first to sixth periods t1 to t6 in the Nth frame period and the (N+1)th frame period will be omitted.

[0210] 19 and 20 are layout diagrams showing a pixel according to an embodiment. FIG. 21 is an enlarged layout diagram showing a detail of region A of FIG. 19. FIG. 22 is an enlarged layout diagram showing a detail of region B of FIG. 19. FIG. 23 is an enlarged layout diagram showing a detail of region A of FIG. 20. FIG. 24 is an enlarged layout diagram showing a detail of region C of FIG. 19. FIG. 25 is an enlarged layout diagram showing a detail of region D of FIG. 19. FIG. 26 is an enlarged layout diagram showing a detail of region C of FIG. 20.

[0211] Figures 19, 21, 22, 24, and 25 show layouts of the bottom metal layer, active layer, first gate metal layer, second gate metal layer, first source metal layer, and second source metal layer of a pixel according to one embodiment. Figure 20 shows a layout of the third and fourth source metal layers in addition to the layout of Figure 19, and Figure 23 shows a layout of the third and fourth source metal layers in addition to the layout of Figure 21. Figure 26 shows a layout of the third and fourth source metal layers in addition to the layout of Figure 25.

[0212] 19 to 26, the initialization voltage line VIL, the kth scan initialization line GILk, the kth scan write line GWLk, the kth PWM light emission line PWELk, the first horizontal power supply line HVDL, the gate-off voltage line VGHL, the kth sweep signal line SWPLk, the kth scan control line GCLk, the kth PAM light emission line PAELk, the first light emission control line RCL1, and the second light emission control line RCL2 may extend in the first direction DR1. The initialization voltage line VIL, the kth scan initialization line GILk, the kth scan write line GWLk, the kth PWM light emission line PWELk, the first horizontal power supply line HVDL, the gate-off voltage line VGHL, the kth sweep signal line SWPLk, the kth scan control line GCLk, the kth PAM light emission line PAELk, the test signal line, and the third power supply line VSL may be spaced apart in the second direction DR2.

[0213] The j-th PWM data line DLj, the first vertical power line VVDL, and the first PAM data line RDL may extend in the second direction DR2. The second PAM data line GDL and the third PAM data line BDL shown in FIG. 1 may extend in the second direction DR2. The j-th PWM data line DLj, the first vertical power line VVDL, the first PAM data line RDL, the second PAM data line GDL, and the third PAM data line BDL may be arranged apart from each other in the first direction DR1.

[0214] First, the layout of the first sub-pixel RP will be described in detail with reference to FIGS.

[0215] 19 to 23, the first sub-pixel RP includes first to twentieth transistors T1 to T20, first to sixth capacitor electrodes CE1 to CE6, first to eighth gate connecting electrodes GCE1 to GCE8, first and second data connecting electrodes DCE1, DCE2, first to ninth source connecting electrodes CCE1 to CCE9, first to fifth connecting electrodes CNE1 to CNE5, a first anode pad electrode APD1, a second anode pad electrode APD2, a cathode pad electrode CPD, a first sub-light-emitting element REL1, and a second sub-light-emitting element REL2.

[0216] The first transistor T1 includes a first channel CH1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first channel CH1 may extend in a first direction DR1. The first channel CH1 may overlap the first gate electrode G1 in a third direction DR3. The first gate electrode G1 may be connected to the first source connecting electrode CCE1 through a first contact hole CT1. The first gate electrode G1 may be integrally formed with the first capacitor electrode CE1. The first gate electrode G1 may overlap the second capacitor electrode CE2 in the third direction DR3. The first source electrode S1 may be disposed on one side of the first channel CH1, and the first drain electrode D1 may be disposed on the other side of the first channel CH1. The first source electrode S1 may be connected to the second drain electrode D2 and the fifth drain electrode D5. The first drain electrode D1 may be connected to the third sub-source electrode S41 and the sixth source electrode S6. The first source electrode S1 and the first drain electrode D1 do not overlap the first gate electrode G1 in the third direction DR3. The first source electrode S1 and the first drain electrode D1 may overlap the second capacitor electrode CE2 in the third direction DR3.

[0217] The second transistor T2 includes a second channel CH2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second channel CH2 may overlap the second gate electrode G2 in the third direction DR3. The second gate electrode G2 may be formed integrally with the first gate connecting electrode GCE1. The second source electrode S2 may be disposed on one side of the second channel CH2, and the second drain electrode D2 may be disposed on the other side of the second channel CH2. The second source electrode S2 may be connected to the first data connecting electrode DCE1 through the first data contact hole DCT1. The second drain electrode D2 may be connected to the first source electrode S1. The second source electrode S2 and the second drain electrode D2 do not overlap the second gate electrode G2 in the third direction DR3. The second drain electrode D2 may extend in the second direction DR2.

[0218] The first sub-transistor T31 of the third transistor T3 includes a first sub-channel CH31, a first sub-gate electrode G31, a first sub-source electrode S31, and a first sub-drain electrode D31. The first sub-channel CH31 may overlap the first sub-gate electrode G31 in the third direction DR3. The first sub-gate electrode G31 may be formed integrally with the second gate connecting electrode GCE2. The first sub-source electrode S31 may be disposed on one side of the first sub-channel CH31, and the first sub-drain electrode D31 may be disposed on the other side of the first sub-channel CH31. The first sub-source electrode S31 may be connected to the fourth sub-drain electrode D42, and the first sub-drain electrode D31 may be connected to the second sub-source electrode S32. The first sub-source electrode S31 and the first sub-drain electrode D31 do not overlap the first sub-gate electrode G31. The first sub-source electrode S31 may overlap the k-th scan write line GWLk in the third direction DR3. The first sub-drain electrode D31 may overlap the initialization voltage line VIL in the third direction DR3.

[0219] The second sub-transistor T32 of the third transistor T3 includes a second sub-channel CH32, a second sub-gate electrode G32, a second sub-source electrode S32, and a second sub-drain electrode D32. The second sub-channel CH32 may overlap the second sub-gate electrode G32 in the third direction DR3. The second sub-gate electrode G32 may be integrally formed with the second gate connecting electrode GCE2. The second sub-source electrode S32 may be disposed on one side of the second sub-channel CH32, and the second sub-drain electrode D32 may be disposed on the other side of the second sub-channel CH32. The second sub-source electrode S32 may be connected to the first sub-drain electrode D31, and the second sub-drain electrode D32 may be connected to the initialization voltage line VIL through the first power contact hole VCT1. The second sub-source electrode S32 and the second sub-drain electrode D32 do not overlap the second sub-gate electrode G32. The second sub-source electrode S32 and the second sub-drain electrode D32 may overlap the initialization voltage line VIL in the third direction DR3.

[0220] The third sub-transistor T41 of the fourth transistor T4 includes a third sub-channel CH41, a third sub-gate electrode G41, a third sub-source electrode S41, and a third sub-drain electrode D41. The third sub-channel CH41 may overlap the third sub-gate electrode G41 in the third direction DR3. The third sub-gate electrode G41 may be formed integrally with the first gate connecting electrode GCE1. The third sub-source electrode S41 may be disposed on one side of the third sub-channel CH41, and the third sub-drain electrode D41 may be disposed on the other side of the third sub-channel CH41. The third sub-source electrode S41 may be connected to the first drain electrode D1, and the third sub-drain electrode D41 may be connected to the fourth sub-source electrode S42. The third sub-source electrode S41 and the third sub-drain electrode D41 may not overlap the third sub-gate electrode G41.

[0221] The fourth sub-transistor T42 of the fourth transistor T4 includes a fourth sub-channel CH42, a fourth sub-gate electrode G42, a fourth sub-source electrode S42, and a fourth sub-drain electrode D42. The fourth sub-channel CH42 may overlap with the fourth sub-gate electrode G42 in the third direction DR3. The fourth sub-gate electrode G42 may be formed integrally with the second gate connecting electrode GCE2. The fourth sub-source electrode S42 may be disposed on one side of the fourth sub-channel CH42, and the fourth sub-drain electrode D42 may be disposed on the other side of the fourth sub-channel CH42. The fourth sub-source electrode S42 may be connected to the third sub-drain electrode D41, and the fourth sub-drain electrode D42 may be connected to the first sub-source electrode S31. The fourth sub-source electrode S42 and the fourth sub-drain electrode D42 may not overlap with the fourth sub-gate electrode G42.

[0222] The fifth transistor T5 includes a fifth channel CH5, a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5. The fifth channel CH5 may overlap the fifth gate electrode G5 in the third direction DR3. The fifth gate electrode G5 may be formed integrally with the sixth gate connecting electrode GCE6. The fifth source electrode S5 may be disposed on one side of the fifth channel CH5, and the fifth drain electrode D5 may be disposed on the other side of the fifth channel CH5. The fifth source electrode S5 may be connected to the first horizontal power supply wiring HVDL through the second power supply contact hole VCT2. The fifth drain electrode D5 may be connected to the first source electrode S1. The fifth source electrode S5 and the fifth drain electrode D5 do not overlap the fifth gate electrode G5 in the third direction DR3. The fifth drain electrode D5 may overlap the extension portion EX of the second capacitor electrode CE2 in the third direction DR3.

[0223] The sixth transistor T6 includes a sixth channel CH6, a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6. The sixth channel CH6 may overlap the sixth gate electrode G6 in the third direction DR3. The sixth gate electrode G6 may be formed integrally with the sixth gate connecting electrode GCE6. The sixth source electrode S6 may be disposed on one side of the sixth channel CH6, and the sixth drain electrode D6 may be disposed on the other side of the sixth channel CH6. The sixth source electrode S6 may be connected to the first drain electrode D1. The sixth drain electrode D6 may be connected to the fourth source connecting electrode CCE4 through a tenth contact hole CT10. The sixth source electrode S6 and the sixth drain electrode D6 do not overlap the sixth gate electrode G6 in the third direction DR3. The sixth drain electrode D6 may overlap the second source connecting electrode CCE2 and the first horizontal power line HVDL in the third direction DR3.

[0224] The seventh transistor T7 includes a seventh channel CH7, a seventh gate electrode G7, a seventh source electrode S7, and a seventh drain electrode D7. The seventh channel CH7 may overlap the seventh gate electrode G7 in the third direction DR3. The seventh gate electrode G7 may be integrally formed with the third gate connecting electrode GCE3. The seventh gate electrode G7 may overlap the initialization voltage line VIL in the third direction DR3. The seventh source electrode S7 may be disposed on one side of the seventh channel CH7, and the seventh drain electrode D7 may be disposed on the other side of the seventh channel CH7. The seventh source electrode S7 may be connected to the gate-off voltage line VGHL via a seventh contact hole CT7. The seventh drain electrode D7 may be connected to the k-th sweep signal line SWPLk via a sixth contact hole CT6. The seventh source electrode S7 and the seventh drain electrode D7 may not overlap the seventh gate electrode G7 in the third direction DR3.

[0225] The eighth transistor T8 includes an eighth channel CH8, an eighth gate electrode G8, an eighth source electrode S8, and an eighth drain electrode D8. The eighth channel CH8 may overlap with the eighth gate electrode G8 in the third direction DR3. The eighth gate electrode G8 may extend in the second direction DR2. The eighth gate electrode G8 may be formed integrally with the third capacitor electrode CE3. The eighth source electrode S8 may be disposed on one side of the eighth channel CH8, and the eighth drain electrode D8 may be disposed on the other side of the eighth channel CH8. The eighth source electrode S8 may be connected to the ninth drain electrode D9 and the twelfth drain electrode D12. The eighth drain electrode D8 may be connected to the seventh sub-source electrode S111. The eighth source electrode S8 and the eighth drain electrode D8 may not overlap with the eighth gate electrode G8 in the third direction DR3.

[0226] The ninth transistor T9 includes a ninth channel CH9, a ninth gate electrode G9, a ninth source electrode S9, and a ninth drain electrode D9. The ninth channel CH9 may overlap with the ninth gate electrode G9 in the third direction DR3. The ninth gate electrode G9 may extend in the second direction DR2. The ninth gate electrode G9 may be formed integrally with the first gate connecting electrode GCE1. The ninth source electrode S9 may be disposed on one side of the ninth channel CH9, and the ninth drain electrode D9 may be disposed on the other side of the ninth channel CH9. The ninth source electrode S9 may be connected to the second data connecting electrode DCE2 via a third data contact hole DCT3. The ninth drain electrode D9 may be connected to the eighth source electrode D8. The ninth source electrode S9 and the ninth drain electrode D9 may not overlap with the ninth gate electrode G9 in the third direction DR3.

[0227] The fifth sub-transistor T101 of the tenth transistor T10 includes a fifth sub-channel CH101, a fifth sub-gate electrode G101, a fifth sub-source electrode S101, and a fifth sub-drain electrode D101. The fifth sub-channel CH101 may overlap the fifth sub-gate electrode G101 in the third direction DR3. The fifth sub-gate electrode G101 may be formed integrally with the second gate connection electrode GCE2. The fifth sub-source electrode S101 may be disposed on one side of the fifth sub-channel CH101, and the fifth sub-drain electrode D101 may be disposed on the other side of the fifth sub-channel CH101. The fifth sub-source electrode S101 may be connected to the eighth sub-drain electrode D112, and the fifth sub-drain electrode D101 may be connected to the sixth sub-source electrode S102. The fifth sub-source electrode S101 and the fifth sub-drain electrode D101 may not overlap the fifth sub-gate electrode G101. The fifth sub-source electrode S101 may overlap the k-th scan write line GWLk in the third direction DR3, and the fifth sub-drain electrode D101 may overlap the initialization voltage line VIL in the third direction DR3.

[0228] The sixth sub-transistor T102 of the tenth transistor T10 includes a sixth sub-channel CH102, a sixth sub-gate electrode G102, a sixth sub-source electrode S102, and a sixth sub-drain electrode D102. The sixth sub-channel CH102 may overlap with the sixth sub-gate electrode G102 in the third direction DR3. The sixth sub-gate electrode G102 may be formed integrally with the second gate connecting electrode GCE2. The sixth sub-source electrode S102 may be disposed on one side of the sixth sub-channel CH102, and the sixth sub-drain electrode D102 may be disposed on the other side of the sixth sub-channel CH102. The sixth sub-source electrode S102 may be connected to the fifth sub-drain electrode D101, and the sixth sub-drain electrode D102 may be connected to the initialization voltage line VIL through the first power contact hole VCT1. The sixth sub-source electrode S102 and the sixth sub-drain electrode D102 may not overlap with the sixth sub-gate electrode G102. The sixth sub-source electrode S102 and the sixth sub-drain electrode D102 may overlap the initialization voltage line VIL in the third direction DR3.

[0229] The seventh sub-transistor T111 of the eleventh transistor T11 includes a seventh sub-channel CH111, a seventh sub-gate electrode G111, a seventh sub-source electrode S111, and a seventh sub-drain electrode D111. The seventh sub-channel CH111 may overlap the seventh sub-gate electrode G111 in the third direction DR3. The seventh sub-gate electrode G111 may be formed integrally with the first gate connection electrode GCE1. The seventh sub-source electrode S111 may be disposed on one side of the seventh sub-channel CH111, and the seventh sub-drain electrode D111 may be disposed on the other side of the seventh sub-channel CH111. The seventh sub-source electrode S111 may be connected to the eighth drain electrode D8, and the seventh sub-drain electrode D111 may be connected to the eighth sub-source electrode S112. The seventh sub-source electrode S111 and the seventh sub-drain electrode D111 may not overlap the seventh sub-gate electrode G111.

[0230] The eighth sub-transistor T112 of the eleventh transistor T11 includes an eighth sub-channel CH112, an eighth sub-gate electrode G112, an eighth sub-source electrode S112, and an eighth sub-drain electrode D112. The eighth sub-channel CH112 may overlap with the eighth sub-gate electrode G112 in the third direction DR3. The eighth sub-gate electrode G112 may be formed integrally with the first gate connection electrode GCE1. The eighth sub-source electrode S112 may be disposed on one side of the eighth sub-channel CH112, and the eighth sub-drain electrode D112 may be disposed on the other side of the eighth sub-channel CH112. The eighth sub-source electrode S112 may be connected to the seventh sub-drain electrode D111, and the eighth sub-drain electrode D112 may be connected to the fifth sub-source electrode S101. The eighth sub-source electrode S112 and the eighth sub-drain electrode D112 may not overlap with the eighth sub-gate electrode G112.

[0231] The twelfth transistor T12 includes a twelfth channel CH12, a twelfth gate electrode G12, a twelfth source electrode S12, and a twelfth drain electrode D12. The twelfth channel CH12 may overlap the twelfth gate electrode G12 in the third direction DR3. The twelfth gate electrode G12 may be formed integrally with the sixth gate connecting electrode GCE6. The twelfth source electrode S12 may be disposed on one side of the twelfth channel CH12, and the twelfth drain electrode D12 may be disposed on the other side of the twelfth channel CH12. The twelfth source electrode S12 may be connected to the fifth source connecting electrode CCE5 via an eleventh contact hole CT11. The twelfth source electrode S12 and the twelfth drain electrode D12 may not overlap the twelfth gate electrode G12 in the third direction DR3.

[0232] The thirteenth transistor T13 includes a thirteenth channel CH13, a thirteenth gate electrode G13, a thirteenth source electrode S13, and a thirteenth drain electrode D13. The thirteenth channel CH13 may overlap the thirteenth gate electrode G13 in the third direction DR3. The thirteenth gate electrode G13 may be integrally formed with the third gate connecting electrode GCE3. The thirteenth source electrode S13 may be disposed on one side of the thirteenth channel CH13, and the thirteenth drain electrode D13 may be disposed on the other side of the thirteenth channel CH13. The thirteenth source electrode S13 may be connected to the first horizontal power supply line HVDL via a second power supply contact hole VCT2. The thirteenth drain electrode D13 may be connected to the second source connecting electrode CCE2 via a third contact hole CT3. The thirteenth source electrode S13 and the thirteenth drain electrode D13 may not overlap the thirteenth gate electrode G13 in the third direction DR3.

[0233] The fourteenth transistor T14 includes a fourteenth channel CH14, a fourteenth gate electrode G14, a fourteenth source electrode S14, and a fourteenth drain electrode D14. The fourteenth channel CH14 may overlap with the fourteenth gate electrode G14 in the third direction DR3. The fourteenth gate electrode G14 may be integrally formed with the sixth gate connecting electrode GCE6. The fourteenth source electrode S14 may be disposed on one side of the fourteenth channel CH14, and the fourteenth drain electrode D14 may be disposed on the other side of the fourteenth channel CH14. The fourteenth source electrode S14 may be connected to the fifth source connecting electrode CCE5 via an eleventh contact hole CT11. The fourteenth drain electrode D14 may be connected to the second source connecting electrode CCE2 via a fourth contact hole CT4. The fourteenth source electrode S14 and the fourteenth drain electrode D14 may not overlap with the fourteenth gate electrode G14 in the third direction DR3.

[0234] The fifteenth transistor T15 includes a fifteenth channel CH15, a fifteenth gate electrode G15, a fifteenth source electrode S15, and a fifteenth drain electrode D15. The fifteenth channel CH15 may overlap the fifteenth gate electrode G15 in the third direction DR3. The fifteenth gate electrode G15 may be formed integrally with the fifth capacitor electrode CE5. The fifteenth source electrode S15 may be disposed on one side of the fifteenth channel CH15, and the fifteenth drain electrode D15 may be disposed on the other side of the fifteenth channel CH15. The fifteenth source electrode S15 may be connected to the ninth drain electrode D9. The fifteenth drain electrode D15 may be connected to the seventeenth source electrode S17. The fifteenth source electrode S15 and the fifteenth drain electrode D15 may not overlap the fifteenth gate electrode G15 in the third direction DR3.

[0235] The ninth sub-transistor T161 of the sixteenth transistor T16 includes a ninth sub-channel CH161, a ninth sub-gate electrode G161, a ninth sub-source electrode S161, and a ninth sub-drain electrode D161. The ninth sub-channel CH161 may overlap the ninth sub-gate electrode G161 in the third direction DR3. The ninth sub-gate electrode G161 may be integrally formed with the third gate connecting electrode GCE3. The ninth sub-source electrode S161 may be disposed on one side of the ninth sub-channel CH161, and the ninth sub-drain electrode D161 may be disposed on the other side of the ninth sub-channel CH161. The ninth sub-source electrode S161 may be connected to the fourth source connecting electrode CCE4 through a tenth contact hole CT10, and the ninth sub-drain electrode D161 may be connected to the tenth sub-source electrode S162. The ninth sub-source electrode S161 and the ninth sub-drain electrode D161 may not overlap with the ninth sub-gate electrode G161.

[0236] The tenth sub-transistor T162 of the sixteenth transistor T16 includes a tenth sub-channel CH162, a tenth sub-gate electrode G162, a tenth sub-source electrode S162, and a tenth sub-drain electrode D162. The tenth sub-channel CH162 may overlap with the tenth sub-gate electrode G162 in the third direction DR3. The tenth sub-gate electrode G162 may be integrally formed with the third gate connecting electrode GCE3. The tenth sub-source electrode S162 may be disposed on one side of the tenth sub-channel CH162, and the tenth sub-drain electrode D162 may be disposed on the other side of the tenth sub-channel CH162. The tenth sub-source electrode S162 may be connected to the ninth sub-drain electrode D161, and the tenth sub-drain electrode D162 may be connected to the initialization voltage line VIL via a ninth contact hole CT9. This is because the tenth sub-source electrode S162 and the tenth sub-drain electrode D162 do not overlap with the tenth sub-gate electrode G162.

[0237] The 17th transistor T17 includes a 17th channel CH17, a 17th gate electrode G17, a 17th source electrode S17, and a 17th drain electrode D17. The 17th channel CH17 may overlap the 17th gate electrode G17 in the third direction DR3. The 17th gate electrode G17 may be integrally formed with the fifth gate connecting electrode GCE5. The 17th source electrode S17 may be disposed on one side of the 17th channel CH17, and the 17th drain electrode D17 may be disposed on the other side of the 17th channel CH17. The 17th source electrode S17 may be connected to the 15th drain electrode D15. The 17th drain electrode D17 may be connected to the seventh source connecting electrode CCE7 via a 16th contact hole CT16. The 17th source electrode S17 and the 17th drain electrode D17 may not overlap the 17th gate electrode G17 in the third direction DR3.

[0238] The eleventh sub-transistor T181 of the eighteenth transistor T18 includes an eleventh sub-channel CH181, an eleventh sub-gate electrode G181, an eleventh sub-source electrode S181, and an eleventh sub-drain electrode D181. The eleventh sub-channel CH181 may overlap with the eleventh sub-gate electrode G181 in the third direction DR3. The eleventh sub-gate electrode G181 may be integrally formed with the third gate connecting electrode GCE3. The eleventh sub-source electrode S181 may be disposed on one side of the eleventh sub-channel CH181, and the eleventh sub-drain electrode D181 may be disposed on the other side of the eleventh sub-channel CH181. The eleventh sub-source electrode S181 may be connected to the initialization voltage line VIL via a twenty-first contact hole CT21. The eleventh sub-drain electrode D181 may be connected to the eighth source connecting electrode CCE8 via a twenty-fifth contact hole CT25. The eleventh sub-source electrode S181 and the eleventh sub-drain electrode D181 may not overlap with the eleventh sub-gate electrode G181 in the third direction DR3.

[0239] The twelfth sub-transistor T182 of the eighteenth transistor T18 includes a twelfth sub-channel CH182, a twelfth sub-gate electrode G182, a twelfth sub-source electrode S182, and a twelfth sub-drain electrode D182. The twelfth sub-channel CH182 may overlap with the twelfth sub-gate electrode G182 in the third direction DR3. The twelfth sub-gate electrode G182 may be integrally formed with the third gate connecting electrode GCE3. The twelfth sub-source electrode S182 may be disposed on one side of the twelfth sub-channel CH182, and the twelfth sub-drain electrode D182 may be disposed on the other side of the twelfth sub-channel CH182. The twelfth sub-source electrode S182 may be connected to the initialization voltage line VIL via a 21st contact hole CT21. The twelfth sub-drain electrode D182 may be connected to the ninth source connecting electrode CCE9 via a 26th contact hole CT26. The twelfth sub-source electrode S182 and the twelfth sub-drain electrode D182 may not overlap with the twelfth sub-gate electrode G182 in the third direction DR3.

[0240] The 19th transistor T19 includes a 19th channel CH19, a 19th gate electrode G19, a 19th source electrode S19, and a 19th drain electrode D19. The 19th channel CH19 may overlap the 19th gate electrode G19 in the third direction DR3. The 19th gate electrode G19 may be integrally formed with the seventh gate connecting electrode GCE7. The 19th source electrode S19 may be disposed on one side of the 19th channel CH19, and the 19th drain electrode D19 may be disposed on the other side of the 19th channel CH19. The 19th source electrode S19 may be connected to the third source connecting electrode CCE3 via a 24th contact hole CT24. The 19th drain electrode D19 may be connected to the eighth source connecting electrode CCE8 via a 25th contact hole CT25. The 19th source electrode S19 and the 19th drain electrode D19 may not overlap the 19th gate electrode G19 in the third direction DR3.

[0241] The twentieth transistor T20 includes a twentieth channel CH20, a twentieth gate electrode G20, a twentieth source electrode S20, and a twentieth drain electrode D20. The twentieth channel CH20 may overlap the twentieth gate electrode G20 in the third direction DR3. The twentieth gate electrode G20 may be integrally formed with the eighth gate connecting electrode GCE8. The twentieth source electrode S20 may be disposed on one side of the twentieth channel CH20, and the twentieth drain electrode D20 may be disposed on the other side of the twentieth channel CH20. The twentieth source electrode S20 may be connected to the third source connecting electrode CCE3 via a 24th contact hole CT24. The twentieth drain electrode D20 may be connected to the ninth source connecting electrode CCE9 via a 26th contact hole CT26. The twentieth source electrode S20 and the twentieth drain electrode D20 may not overlap the twentieth gate electrode G20 in the third direction DR3.

[0242] The first capacitor electrode CE1 may be integrally formed with the first gate electrode G1. The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 in the third direction DR3. The first capacitor electrode CE1 may be one electrode of the first capacitor PC1, and the second capacitor electrode CE2 may be the other electrode of the first capacitor PC1.

[0243] The second capacitor electrode CE2 includes a hole exposing the first gate electrode G1, and the first source connecting electrode CCE1 may be connected to the first gate electrode G1 through the first contact hole CT1 in the hole.

[0244] The second capacitor electrode CE2 may include an extension EX extending in the second direction DR2. The extension EX of the second capacitor electrode CE2 may intersect with the k-th PWM light emitting wiring PWELk and the first horizontal power supply wiring HVDL. The extension EX of the second capacitor electrode CE2 may be coupled to the k-th sweep signal wiring SWPLk through a fifth contact hole CT5.

[0245] The third capacitor electrode CE3 may be formed integrally with the eighth gate electrode G8. The fourth capacitor electrode CE4 may overlap the third capacitor electrode CE3 in the third direction DR3. The third capacitor electrode CE3 may be one electrode of the second capacitor PC2, and the fourth capacitor electrode CE4 may be the other electrode of the second capacitor PC2.

[0246] The fourth capacitor electrode CE4 includes a hole exposing the eighth gate electrode G8, and the sixth source connecting electrode CCE6 may be connected to the eighth gate electrode G8 at the hole through a twelfth contact hole CT12.

[0247] The fifth capacitor electrode CE5 may be integrally formed with the fourth gate connecting electrode GCE4 and the fifteenth gate electrode G15. The sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR3. The fifth capacitor electrode CE5 may be one electrode of the third capacitor PC3, and the sixth capacitor electrode CE6 may be the other electrode of the third capacitor PC3. The sixth capacitor electrode CE6 may be connected to the initialization voltage line VIL via an eighteenth contact hole CT18.

[0248] The first gate connecting electrode GCE1 may be connected to the k-th scan write line GWLk through the first gate contact hole GCT1 and the third gate contact hole GCT3. The second gate connecting electrode GCE2 may be connected to the k-th scan initialization line GILk through the second gate contact hole GCT2. The third gate connecting electrode GCE3 may be connected to the k-th scan control line GCLk through the eighth contact hole CT8. The fourth gate connecting electrode GCE4 may be connected to the fourth source connecting electrode CCE4 through the seventeenth contact hole CT17. The fifth gate connecting electrode GCE5 may be connected to the k-th PAM light emission line PAELk through the nineteenth contact hole CT19. The sixth gate connecting electrode GCE6 may be connected to the k-th PWM light emission line PWELk through the fourteenth contact hole CT14. The seventh gate connecting electrode GCE7 may be connected to the first light emission control line RCL1 through the twenty-second contact hole CT22. The eighth gate connecting electrode GCE8 may be connected to the second emission control line RCL2 through a twenty-third contact hole CT23.

[0249] The first data connecting electrode DCE1 may be connected to the second source electrode S2 through the first data contact hole DCT1 and to the j-th PWM data line DLj through the second data contact hole DCT2. The second data connecting electrode DCE2 may be connected to the ninth source electrode S9 through the third data contact hole DCT3 and to the first PAM data line RDL through the fourth data contact hole DCT4.

[0250] The first source connecting electrode CCE1 may extend in a second direction DR2, may be connected to the first gate electrode G1 through a first contact hole CT1, and may be connected to the first sub-source electrode S31 and the fourth sub-drain electrode D42 through a second contact hole CT2.

[0251] The second source connecting electrode CCE2 may extend in the first direction DR1 and may be connected to the twelfth drain electrode D12 through a third contact hole CT3, to the fourteenth drain electrode D14 through a fourth contact hole CT4, and to the fourth capacitor electrode CE4 through a fifteenth contact hole CT15.

[0252] The third source connecting electrode CCE3 may be connected to the nineteenth source electrode S19 and the twentieth source electrode S20 through a twenty-fourth contact hole CT24, and may be connected to the first connecting electrode CNE1 through a twenty-seventh contact hole CT27.

[0253] The fourth source connecting electrode CCE4 may extend in the first direction DR1, may be connected to the sixth drain electrode D6 and the ninth sub-source electrode S161 through a tenth contact hole CT10, and may be connected to the fourth gate connecting electrode GCE4 through a seventeenth contact hole CT17.

[0254] The fifth source connecting electrode CCE5 may extend in the first direction DR1, may be connected to the twelfth source electrode S12 and the fourteenth source electrode S14 through an eleventh contact hole CT11, and may be connected to the fourth capacitor electrode CE4 through a fourth power contact hole VCT4.

[0255] The sixth source connecting electrode CCE6 may extend in the second direction DR2, may be connected to the third capacitor electrode CE3 through a twelfth contact hole CT12, and may be connected to the fifth sub-source electrode S101 and the eighth sub-drain electrode D112 through a thirteenth contact hole CT13.

[0256] The seventh source connecting electrode CCE7 may be connected to the seventeenth drain electrode D17 and the eighteenth drain electrode D18 through a sixteenth contact hole CT16. The seventh source connecting electrode CCE7 may be connected to the first connecting electrode CNE1 through a twentieth contact hole CT20.

[0257] The eighth source connecting electrode CCE8 may be connected to the eleventh sub-drain electrode D181 of the eleventh sub-transistor T181 of the eighteenth transistor T18 and the nineteenth drain electrode D19 of the nineteenth transistor T19 through a twenty-fifth contact hole CT25. The eighth source connecting electrode CCE8 may be connected to the second connecting electrode CNE2 through a twenty-eighth contact hole CT28.

[0258] The ninth source connecting electrode CCE9 may be connected to the twelfth sub-drain electrode D182 of the twelfth sub-transistor T182 of the eighteenth transistor T18 and the twentieth drain electrode D20 of the twentieth transistor T20 through a twenty-sixth contact hole CT26. The ninth source connecting electrode CCE9 may be connected to the third connecting electrode CNE3 through a twenty-ninth contact hole CT29.

[0259] The first connecting electrode CNE1 may extend in the second direction DR2, may be connected to the seventh source connecting electrode CCE7 through a twentieth contact hole CT20, and may be connected to the third source connecting electrode CCE3 through a twenty-seventh contact hole CT27.

[0260] The second connecting electrode CNE2 may be connected to the eighth source connecting electrode CCE8 through a twenty-eighth contact hole CT28, and may be connected to the fourth connecting electrode CNE4 through a thirtieth contact hole CT30.

[0261] The third connecting electrode CNE3 may be connected to the ninth source connecting electrode CCE9 through a twenty-ninth contact hole CT29, and may be connected to the fifth connecting electrode CNE5 through a thirty-first contact hole CT31.

[0262] The fourth connecting electrode CNE4 may be connected to the second connecting electrode CNE2 through a 30th contact hole CT30 and may be connected to the first anode pad electrode APD1 through a 32nd contact hole CT32.

[0263] The fifth connecting electrode CNE5 may be connected to the third connecting electrode CNE3 through a thirty-first contact hole CT31, and may be connected to the second anode pad electrode APD2 through a thirty-third contact hole CT33.

[0264] The first anode pad electrode APD1, the second anode pad electrode APD2, and the cathode pad electrode CPD may extend in the second direction DR2. The length of the first anode pad electrode APD1 in the second direction DR2 may be smaller than the length of the cathode pad electrode CPD in the second direction DR2. The length of the second anode pad electrode APD2 in the second direction DR2 may be smaller than the length of the cathode pad electrode CPD in the second direction DR2. The area of ​​the cathode pad electrode CPD may be larger than the area of ​​the first anode pad electrode APD1 or the area of ​​the second anode pad electrode APD2.

[0265] The first anode pad electrode APD1 and the second anode pad electrode APD2 may be arranged in a second direction DR2. The first anode pad electrode APD1 and the cathode pad electrode CPD may be arranged in a first direction DR1. The second anode pad electrode APD2 and the cathode pad electrode CPD may be arranged in the first direction DR1. The first anode pad electrode APD1 and the second anode pad electrode APD2 may be arranged on one side, for example, the left side, of the cathode pad electrode CPD.

[0266] The first anode pad electrode APD1 and a partial region of the cathode pad electrode CPD may overlap in the first direction DR1, and the second anode pad electrode APD2 and another partial region of the cathode pad electrode CPD may overlap in the first direction DR1.

[0267] The first anode pad electrode APD1 may be connected to the fourth connecting electrode CNE4 through a contact hole CT32. The second anode pad electrode APD2 may be connected to the fifth connecting electrode CNE5 through a contact hole CT33.

[0268] The second power connecting electrode VDCE may extend in a second direction DR2 and may be connected to the fifth source connecting electrode CCE5 through a fourth power contact hole VCT4.

[0269] The first light emitting sub-element REL1 may be disposed on the first anode pad electrode APD1 and the cathode pad electrode CPD, and a first electrode of the first light emitting sub-element REL1 may be connected to the first anode pad electrode APD1 and a second electrode of the first light emitting sub-element REL1 may be connected to the cathode pad electrode CPD.

[0270] The second light emitting sub-element REL2 may be disposed on the second anode pad electrode APD2 and the cathode pad electrode CPD, with a first electrode of the second light emitting sub-element REL2 being connected to the second anode pad electrode APD2 and a second electrode being connected to the cathode pad electrode CPD.

[0271] Secondly, the layout of the second sub-pixel GP will be described in detail with reference to FIGS. 19, 20, and 24 to 26. FIG.

[0272] 19, 20, and 24 to 26, the second sub-pixel GP includes first to eighteenth transistors T1 to T18, first to sixth capacitor electrodes CE1 to CE6, first to sixth gate connecting electrodes GCE1 to GCE6, first and second data connecting electrodes DCE1, DCE2, first to seventh source connecting electrodes CCE1 to CCE7, first and second connecting electrodes CNE1, CNE2, an anode pad electrode APD, a cathode pad electrode CPD, and a second light-emitting element GEL.

[0273] In the embodiment of the second sub-pixel GP in Figures 19, 20, and 24 to 26, the description will be omitted for the sake of brevity, and the description will focus on the differences from the embodiment of the first sub-pixel RP shown in Figures 19 to 23.

[0274] 19, 20, and 24 to 26, the 18th transistor T18 includes an 18th channel CH18, an 18th gate electrode G18, an 18th source electrode S18, and an 18th drain electrode D18. The 18th channel CH18 may overlap with the 18th gate electrode G18 in the third direction DR3. The 18th gate electrode G18 may be integrally formed with the third gate connecting electrode GCE3. The 18th source electrode S18 may be disposed on one side of the 18th channel CH18, and the 18th drain electrode D18 may be disposed on the other side of the 18th channel CH18. The 18th source electrode S18 may be connected to the initialization voltage line VIL via a ninth contact hole CT9. The 18th drain electrode D18 may be connected to the seventh source connecting electrode CCE7 via a sixteenth contact hole CT16. The eighteenth source electrode S18 and the eighteenth drain electrode D18 may not overlap the eighteenth gate electrode G18 in the third direction DR3.

[0275] The second connecting electrode CNE2' may be connected to the third source connecting electrode CCE3 through a 28th contact hole CT28'. The anode pad electrode APD may be disposed on the other side, for example, the right side, of the cathode pad electrode CPD. The anode pad electrode APD may be connected to the second connecting electrode CNE2' through a 29th contact hole CT29'. The area of ​​the cathode pad electrode CPD of the second subpixel GP may be smaller than the area of ​​the cathode pad electrode CPD of the first subpixel RP. For example, referring to FIGS. 23 and 26, the length of the cathode pad electrode CPD of the second subpixel GP in the second direction DR2 may be smaller than the length of the cathode pad electrode CPD of the first subpixel RP in the second direction DR2.

[0276] The second light emitting element GEL may be disposed on the anode pad electrode APD and the cathode pad electrode CPD, with a first electrode of the second light emitting element GEL being coupled to the anode pad electrode APD and a second electrode being coupled to the cathode pad electrode CPD.

[0277] It should be noted that the layout of the third sub-pixel BP is substantially similar to that of the second sub-pixel GP, and therefore a description thereof will be omitted.

[0278] Fig. 27 is a cross-sectional view showing an example of a display panel taken along line A-A' in Fig. 21. Fig. 28 is a cross-sectional view showing an example of a display panel taken along line B-B' in Figs. 21 and 24.

[0279] 27 and 28, a buffer film BF may be disposed on a substrate SUB. The substrate SUB may be made of an insulating material such as glass or polymer resin. For example, when the substrate SUB is made of polymer resin, it may include polyimide. The substrate SUB may be a flexible substrate capable of bending, folding, rolling, and the like.

[0280] The buffer film BF is made of a plurality of inorganic films alternately stacked. For example, the buffer film BF may be formed as a multi-layer film (stacked film) in which one or more inorganic films selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The buffer film BF may be omitted.

[0281] An active layer may be disposed on the buffer film BF. The active layer may include channels, source electrodes, and drain electrodes of the first to twentieth transistors T1 to T20. The active layer may include polycrystalline silicon, single crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

[0282] The channels of the first through twentieth transistors T1 to T20 may overlap with the gate electrodes in the third direction DR3. The source electrodes and drain electrodes of the first through twentieth transistors T1 to T20 do not overlap with the gate electrodes in the third direction DR3. The source electrodes and drain electrodes of the first through twentieth transistors T1 to T20 may be regions of silicon semiconductors or oxide semiconductors doped with ions or impurities to have conductivity.

[0283] A gate insulating film 130 may be disposed on the active layer. The gate insulating film 130 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0284] , A first gate metal layer may be disposed on the gate insulating film 130. The first gate metal layer includes the gate electrodes of the first to twentieth transistors T1 to T20, the first capacitor electrode CE1, the third capacitor electrode CE3, the fifth capacitor electrode CE5, and the first to sixth gate connecting electrodes GCE1 to GCE6. The gate electrodes of the first to twentieth transistors T1 to T20, the first capacitor electrode CE1, the third capacitor electrode CE3, the fifth capacitor electrode CE5, and the first to sixth gate connecting electrodes GCE1 to GCE6 may be formed of a single layer or multiple layers (stacked film) made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0285] A first interlayer insulating film 141 may be disposed on the first gate metal layer. The first interlayer insulating film 141 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0286] A second gate metal layer may be disposed on the first interlayer insulating film 141. The second gate metal layer may include a second capacitor electrode CE2, a fourth capacitor electrode CE4, and a sixth capacitor electrode CE6. The second gate metal layer may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0287] The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 in the third direction DR3, the fourth capacitor electrode CE4 may overlap the third capacitor electrode CE3 in the third direction DR3, and the sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR3. Since the first interlayer insulating film 141 has a predetermined dielectric constant, a first capacitor PC1 may be formed by the first capacitor electrode CE1, the second capacitor electrode CE2, and the first interlayer insulating film 141 disposed therebetween. A second capacitor PC2 may be formed by the third capacitor electrode CE3, the fourth capacitor electrode CE4, and the first interlayer insulating film 141 disposed therebetween. A third capacitor PC3 may be formed by the fifth capacitor electrode CE5, the sixth capacitor electrode CE6, and the first interlayer insulating film 141 disposed therebetween.

[0288] A second interlayer insulating film 142 may be disposed on the second gate metal layer. The second interlayer insulating film 142 may be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0289] A first source metal layer may be disposed on the second interlayer insulating film 142. The first source metal layer may include an initialization voltage line VIL, a kth scan initialization line GILk, a kth scan write line GWLk, a kth PWM light emission line PWELk, a first horizontal power supply line HVDL, a gate-off voltage line VGHL, a kth sweep signal line SWPLk, a kth scan control line GCLk, a kth PAM light emission line PAELk, a first light emission control line RCL1, a second light emission control line RCL2, and a third power supply line VSL. In addition, the first source metal layer may include first and second data connecting electrodes DCE1, DCE2 and first to ninth source connecting electrodes CCE1 to CCE9. The first source metal layer may be formed of a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0290] The kth scan write line GWLk may be connected to the first gate connecting electrode GCE1 through a first gate contact hole GCT1 and a third gate contact hole GCT3 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The kth scan initialization line GILk may be connected to the second gate connecting electrode GCE2 through a second gate contact hole GCT2 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The kth scan control line GCLk may be connected to the third gate connecting electrode GCE3 through an eighth contact hole CT8 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The kth PAM light emitting line PAELk may be connected to the fifth gate connecting electrode GCE5 through a nineteenth contact hole CT19 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The k-th PWM light emitting wiring PWELk may be connected to the sixth gate connecting electrode GCE6 through a fourteenth contact hole CT14 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142.

[0291] The initialization voltage line VIL may be connected to the second sub-drain electrode D32 and the sixth sub-drain electrode D102 through a first power contact hole VCT1 that penetrates the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The initialization voltage line VIL may be connected to the tenth sub-drain electrode D162 and the eighteenth drain electrode D18 through a ninth contact hole CT9 that penetrates the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The initialization voltage line VIL may be connected to the sixth capacitor electrode CE6 through an eighteenth contact hole CT18 that penetrates the second interlayer insulating film 142. The first horizontal power line HVDL may be connected to the fifth source electrode S5 and the thirteenth source electrode S13 through a second power contact hole VCT2 that penetrates the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The gate-off voltage wiring VGHL may be connected to the seventh source electrode S7 through a seventh contact hole CT7 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The test signal wiring may be connected to the nineteenth gate electrode G19 through a twenty-third contact hole CT23 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The third power supply wiring VSL may be connected to the nineteenth drain electrode D19 through a twenty-fourth contact hole CT24 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0292] The first data connecting electrode DCE1 may be connected to the second source electrode S2 through a first data contact hole DCT1 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The second data connecting electrode DCE2 may be connected to the ninth source electrode S9 through a third data contact hole DCT3 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0293] The first source connecting electrode CCE1 may be connected to the first gate electrode G1 via a first contact hole CT1 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142, and may be connected to the first sub-source electrode S31 and the fourth sub-drain electrode D42 via a second contact hole CT2 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0294] The second source connecting electrode CCE2 may be connected to the seventeenth drain electrode D17 via a third contact hole CT3 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142, connected to the fourteenth drain electrode D14 via a fourth contact hole CT4 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142, and connected to the fourth capacitor electrode CE4 via a fifteenth contact hole CT15 penetrating the second interlayer insulating film 142.

[0295] The third source connecting electrode CCE3 may be connected to the nineteenth source electrode S19 through a twenty-first contact hole CT21 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0296] The fourth source connecting electrode CCE4 may be connected to the sixth drain electrode D6 via a tenth contact hole CT10 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142, and may be connected to the fourth gate connecting electrode GCE4 via a seventeenth contact hole CT17 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142.

[0297] The fifth source connecting electrode CCE5 may be connected to the twelfth source electrode S12 and the fourteenth source electrode S14 through an eleventh contact hole CT11 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0298] The sixth source connecting electrode CCE6 may be connected to the eighth gate electrode G8 via a twelfth contact hole CT12 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142, and may be connected to the fifth sub-source electrode S101 and the eighth sub-drain electrode D112 via a thirteenth contact hole CT13 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0299] The seventh source connecting electrode CCE7 may be connected to the seventeenth drain electrode D17 and the eighteenth drain electrode D18 through a sixteenth contact hole CT16 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0300] The eighth source connecting electrode CCE8 may be connected to the eleventh sub-drain electrode D181 and the nineteenth drain electrode D19 through a twenty-fifth contact hole CT25 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0301] The ninth source connecting electrode CCE9 may be connected to the twelfth sub-drain electrode D182 and the twentieth drain electrode D20 through a twenty-sixth contact hole CT26 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0302] A first planarization layer 160 may be disposed on the first source metal layer. The first planarization layer 160 may be formed of an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0303] A first inorganic insulating layer 161 may be disposed on the first planarization layer 160. The first inorganic insulating layer 161 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0304] A second source metal layer may be disposed on the first inorganic insulating layer 161. The second source metal layer may include a jth PWM data line DLj, a first vertical power line VVDL, and a first PAM data line RDL. The second source metal layer may also include first to third connecting electrodes CNE1, CNE2, and CNE3 and a second power connecting electrode VDCE. The second source metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0305] The j-th PWM data line DLj may be connected to the first data connecting electrode DCE1 through a second data contact hole DCT2 penetrating the first planarization film 160 and the first inorganic insulating film 161. The first PAM data line RDL may be connected to the second data connecting electrode DCE2 through a fourth data contact hole DCT4 penetrating the first planarization film 160 and the first inorganic insulating film 161. The first vertical power line VVDL may be connected to the first horizontal power line HVDL through a third power contact hole VCT3 penetrating the first planarization film 160 and the first inorganic insulating film 161. The third power contact hole VCT3 may overlap the second power contact hole VCT2 in the third direction DR3. The area of ​​the third power contact hole VCT3 may be larger than the area of ​​the second power contact hole VCT2.

[0306] The first connecting electrode CNE1 may be connected to the seventh source connecting electrode CCE7 through a twentieth contact hole CT20 penetrating the first planarization film 160 and the first inorganic insulating film 161, and may be connected to the third source connecting electrode CCE3 through a twenty-seventh contact hole CT27 penetrating the first planarization film 160 and the first inorganic insulating film 161.

[0307] The second connecting electrode CNE2 may be connected to the eleventh sub-drain electrode D181 and the nineteenth drain electrode D19 through a twenty-fifth contact hole CT25 penetrating the first planarization layer 160 and the first inorganic insulating layer 161.

[0308] The third connecting electrode CNE3 may be connected to the twelfth sub-drain electrode D182 and the twentieth drain electrode D20 through a twenty-sixth contact hole CT26 penetrating the first planarization layer 160 and the first inorganic insulating layer 161.

[0309] The second power connecting electrode VDCE may be connected to the fifth source connecting electrode CCE5 through a fourth power contact hole VCT4 penetrating the first planarization layer 160 and the first inorganic insulating layer 161.

[0310] A second planarization layer 180 may be disposed on the second source metal layer. The second planarization layer 180 may be formed of an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0311] A second inorganic insulating layer 181 may be disposed on the second planarization layer 180. The second inorganic insulating layer 181 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0312] A third source metal layer may be disposed on the second inorganic insulating layer 181. The third source metal layer may include a first sub-power wiring VDL21, a fourth connecting electrode CNE4, and a fifth connecting electrode CNE5. The third source metal layer may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0313] The first sub-power wiring VDL21 may be connected to the second power connecting electrode VDCE through a fifth power contact hole VCT5 penetrating the second planarization film 180 and the second inorganic insulating film 181. The fourth connecting electrode CNE4 may be connected to the second connecting electrode CNE2 through a 28th contact hole CT28 penetrating the second planarization film 180 and the second inorganic insulating film 181. The fifth connecting electrode CNE5 may be connected to the third connecting electrode CNE3 through a 29th contact hole CT29 penetrating the second planarization film 180 and the second inorganic insulating film 181.

[0314] A third planarization film 190 may be disposed on the third source metal layer. The third planarization film 190 may be formed of an organic film such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The third planarization film 190 may be referred to as a fifth insulating film.

[0315] A third inorganic insulating layer 191 may be disposed on the third planarization layer 190. The third inorganic insulating layer 191 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating layer 141 may be referred to as a third insulating layer.

[0316] A fourth source metal layer may be disposed on the third inorganic insulating layer 191. The fourth source metal layer may include a first anode pad electrode APD1, a second anode pad electrode APD2, and a cathode pad electrode CPD. The first anode pad electrode APD1, the second anode pad electrode APD2, and the cathode pad electrode CPD may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0317] The first anode pad electrode APD1 may be connected to the fourth connecting electrode CNE4 via a 32nd contact hole CT32 penetrating the third planarization film 190 and the third inorganic insulating film 191. The second anode pad electrode APD2 may be connected to the fifth connecting electrode CNE5 via a 33rd contact hole CT33 penetrating the third planarization film 190 and the third inorganic insulating film 191.

[0318] Although not shown, the cathode pad electrode CPD may be connected to a cathode wiring of the fourth source metal layer. Since the third power supply voltage VSS is applied to the cathode wiring, the third power supply voltage VSS may be applied to the cathode pad electrode CPD.

[0319] A transparent metal layer may be disposed on the fourth source metal layer. The transparent metal layer may include pad electrodes. The pad electrodes may be disposed on the first anode pad electrode APD1, the second anode pad electrode APD2, and the cathode pad electrode CPD, respectively. The transparent metal layer may be formed of a transparent conductive material (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO) that can transmit light.

[0320] FIG. 28 illustrates a flip-chip type micro LED in which the first contact electrode CTE1 of each of the light emitting elements REL1, REL2, GEL, and BEL faces the anode pad electrode (APD1 / APD2 / APD) and the second contact electrode CTE2 faces the cathode pad electrode CPD. Each of the light emitting elements REL1, REL2, GEL, and BEL may be formed of an inorganic material such as GaN. The first sub-light emitting element REL1 may have a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3 of several μm to several hundred μm. For example, each of the light emitting elements REL1, REL2, GEL, and BEL may have a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3 of approximately 100 μm or less.

[0321] Each of the light emitting elements REL1, REL2, GEL, and BEL may be formed by growing on a semiconductor substrate such as a silicon wafer. Each of the light emitting elements REL1, REL2, GEL, and BEL may be directly transferred from the silicon wafer onto the anode pad electrodes (APD1 / APD2 / APD) and the cathode pad electrodes CPD of the substrate SUB. Alternatively, each of the light emitting elements REL1, REL2, GEL, and BEL may be transferred onto the anode pad electrodes (APD1 / APD2 / APD) and the cathode pad electrodes CPD of the substrate SUB by an electrostatic method using an electrostatic head, or by a stamp method using an elastic polymeric material such as PDMS (polydimethyl siloxane) or silicon as a transfer substrate.

[0322] Each of the light emitting elements REL1, REL2, GEL, and BEL may be a light emitting structure including a base substrate SSUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first contact electrode CTE1, and a second contact electrode CTE2.

[0323] The base substrate SPUB may be a sapphire substrate, although embodiments herein are not limited thereto.

[0324] The n-type semiconductor NSEM may be disposed on one surface of the base substrate SPUB. For example, the n-type semiconductor NSEM may be disposed on the lower surface of the base substrate SPUB. The n-type semiconductor NSEM may be made of GaN doped with an n-type conductive dopant such as Si, Ge, Se, Sn, or the like.

[0325] The active layer MQW may be disposed on a portion of one surface of the n-type semiconductor NSEM. The active layer MQW may include a material with a single or multiple quantum well structure. When the active layer MQW includes a material with a multiple quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer MQW may have a structure in which a semiconductor material with a large band gap energy and a semiconductor material with a small band gap energy are alternately stacked, and may include other group III to V semiconductor materials according to the wavelength band of the emitted light.

[0326] The p-type semiconductor PSEM may be disposed on one side of the active layer MQW. The p-type semiconductor PSEM may be made of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, Ba, or the like.

[0327] The first contact electrode CTE1 may be disposed on the p-type semiconductor PSEM, and the second contact electrode CTE2 may be disposed on another part of the one surface of the n-type semiconductor NSEM. The other part of the one surface of the n-type semiconductor NSEM on which the second contact electrode CTE2 is disposed may be disposed away from the part of the one surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

[0328] The first contact electrode CTE1 and the anode pad electrode (APD1 / APD2 / APD) may be bonded to each other via a conductive adhesive member such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). Alternatively, the first contact electrode CTE1 and the anode pad electrode (APD1 / APD2 / APD) may be bonded to each other by a soldering process.

[0329] The second contact electrode CTE2 and the cathode pad electrode CPD may be bonded to each other by a conductive adhesive member such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). Alternatively, the second contact electrode CTE2 and the cathode pad electrode CPD may be bonded to each other by a soldering process.

[0330] As described above, the first sub-pixel RP connects two light-emitting elements, i.e., the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2, to one pixel circuit, thereby shortening the emission period SET of the first sub-light-emitting element REL1 and the emission period SET of the second sub-light-emitting element REL2. This reduces the heat generation amount of the first sub-light-emitting element REL1 and the heat generation amount of the second sub-light-emitting element REL2, thereby lowering the temperature of the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2. Therefore, it is possible to reduce or prevent a decrease in the emission luminance of the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2 due to the heat generation of the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2.

[0331] FIG. 29 is an equivalent circuit diagram illustrating a first sub-pixel according to an embodiment.

[0332] The embodiment of Fig. 29 differs from the embodiment of Fig. 6 in that the 17th transistor T17 of the first sub-pixel RP includes the 13th sub-transistor T171 and the 14th sub-transistor T172, and the 19th transistor T19 and the 20th transistor T20 are omitted. In Fig. 30, the description overlapping with the embodiment of Fig. 6 will be omitted.

[0333] Referring to FIG. 29, the seventeenth transistor T17 may include a thirteenth sub-transistor T171 and a fourteenth sub-transistor T172.

[0334] The thirteenth sub-transistor T171 is turned on by the kth PAMA light-emitting signal of the kth PAMA light-emitting wiring PAALk to connect the second electrode of the fifteenth transistor T15 to the first electrode of the first sub-light-emitting element REL1. The gate electrode of the thirteenth sub-transistor T171 may be connected to the kth PAMA light-emitting wiring PAALk, the first electrode of the thirteenth sub-transistor T171 may be connected to the second electrode of the fifteenth transistor T15, and the second electrode of the thirteenth sub-transistor T171 may be connected to the first electrode of the first sub-light-emitting element REL1.

[0335] The 14th sub-transistor T172 is turned on by a kth PAMB light-emitting signal of the kth PAMB light-emitting wiring PABLk to connect the second electrode of the 15th transistor T15 to the first electrode of the second sub-light-emitting element REL2. A gate electrode of the 14th sub-transistor T172 may be connected to the kth PAMB light-emitting wiring PABLk, a first electrode of the 14th sub-transistor T172 may be connected to the second electrode of the 15th transistor T15, and a second electrode of the 14th sub-transistor T172 may be connected to the first electrode of the second sub-light-emitting element REL2.

[0336] Fig. 30 is an equivalent circuit diagram showing a second sub-pixel according to an embodiment. The embodiment of Fig. 30 differs from the embodiment of Fig. 29 in that the second sub-pixel GP includes one second light-emitting element GEL. In Fig. 30, descriptions overlapping with the embodiment of Fig. 29 will be omitted.

[0337] 30, the second light emitting element GEL emits a second light in response to the driving current Ids generated by the second pixel driving unit PDU2. The second light emitting element GEL may be disposed between the thirteenth sub-transistor T171 of the seventeenth transistor T17 and the third power supply wiring VSL, and between the fourteenth sub-transistor T172 of the seventeenth transistor T17 and the third power supply wiring VSL. A first electrode of the second light emitting element GEL may be coupled to a second electrode of the thirteenth sub-transistor T171 of the seventeenth transistor T17 and a second electrode of the fourteenth sub-transistor T172, and a second electrode of the second light emitting element GEL may be coupled to the third power supply wiring VSL.

[0338] The 18th transistor T18 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the initialization voltage line VIL to the first electrode of the second light emitting element EL2. Thus, during a period in which the 18th transistor T18 is turned on, the first electrode of the second light emitting element EL2 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. A gate electrode of the 18th sub-transistor T18 may be connected to the kth scan control line GCLk, a first electrode of the 18th sub-transistor T18 may be connected to the first electrode of the second light emitting element EL2, and a second electrode of the 18th sub-transistor T18 may be connected to the initialization voltage line VIL.

[0339] FIG. 31 is an equivalent circuit diagram illustrating a third sub-pixel according to an embodiment.

[0340] The embodiment of Fig. 31 differs from the embodiment of Fig. 29 in that the third sub-pixel BP includes one third light-emitting element BEL. In Fig. 31, the description overlapping with the embodiment of Fig. 29 will be omitted.

[0341] 31, the third light emitting element BEL emits a third light according to the driving current Ids generated by the third pixel driving unit PDU3. The third light emitting element BEL may be disposed between the thirteenth sub-transistor T171 of the seventeenth transistor T17 and the third power supply wiring VSL, and between the fourteenth sub-transistor T172 of the seventeenth transistor T17 and the third power supply wiring VSL. A first electrode of the third light emitting element BEL may be coupled to a second electrode of the thirteenth sub-transistor T171 of the seventeenth transistor T17 and a second electrode of the fourteenth sub-transistor T172, and a second electrode of the third light emitting element BEL may be coupled to the third power supply wiring VSL.

[0342] The eighteenth transistor T18 is substantially similar to the content described with reference to FIG. 30, except that it is connected to the third light emitting element BEL instead of the second light emitting element GEL, and therefore a description thereof will be omitted.

[0343] FIG. 32 is a waveform diagram showing a period during which the kth scan initialization signal, the kth scan write signal, the kth scan control signal, the kth PWM light-emitting signal, the kth PAMA light-emitting signal, the kth PAMB light-emitting signal, and the kth sweep signal are applied to the first sub-pixel arranged on the kth row line during the Nth frame period, as well as the voltage of the third node and the driving current applied to the light-emitting element, according to one embodiment.

[0344] The embodiment of FIG. 32 differs from the embodiment of FIG. 11 in that the kth PAM emission signal PAEMk is deleted and the kth PAMA emission signal PAAMk and the kth PAMB emission signal PAMBk are added.

[0345] Referring to FIG. 32, the kth PAMA light-emitting signal PAAMk refers to a signal applied to the kth PAMA light-emitting wiring PAALk, and the kth PAMB light-emitting signal PAMBk refers to a signal applied to the kth PAMB light-emitting wiring PABLk.

[0346] The kth PAMA light-emitting signal PAAMk is a signal for controlling the turn-on and turn-off of the thirteenth sub-transistor T171 of the seventeenth transistor T17. The kth PAMB light-emitting signal PAMBk is a signal for controlling the turn-on and turn-off of the fourteenth sub-transistor T172 of the seventeenth transistor T17. The kth PAMA light-emitting signal PAAMk and the kth PAMA light-emitting signal PAAMk may be generated at a cycle of one frame period.

[0347] The kth PAMA light emission signal PAAMk may have a gate-on voltage VGL during odd-numbered light emission periods EP1, EP3, ..., EPn-1 among the multiple light emission periods EP1 to EPn in one frame period, and may have a gate-off voltage VGH during the remaining periods. The kth PAMA light emission signal PAAMk may include a PAM pulse generated by the gate-on voltage VGL during a sixth period t6 or a ninth period t9 in each of the odd-numbered light emission periods (EP1, EP3, ..., EPn-1).

[0348] The kth PAMB light-emitting signal PAMBk may have a gate-on voltage VGL during even-numbered light-emitting periods (EP2, EP4, ..., EPn) among the multiple light-emitting periods EP1 to EPn in one frame period, and may have a gate-off voltage VGH during the remaining periods. The kth PAMB light-emitting signal PAMBk may include a PAM pulse generated by the gate-on voltage VGL during a sixth period t6 or a ninth period t9 in each of the even-numbered light-emitting periods (EP2, EP4, ..., EPn).

[0349] 29 and 32, the thirteenth sub-transistor T171 and the fourteenth sub-transistor T172 may be turned on during different light-emitting periods among a plurality of light-emitting periods EP1 to EPn in one frame period. Thus, the first sub-light-emitting element REL1 may receive the driving current Ids through the thirteenth sub-transistor T171 during odd-numbered light-emitting periods (EP1, EP3, ..., EPn-1) among the plurality of light-emitting periods EP1 to EPn in one frame period, and the second sub-light-emitting element REL2 may receive the driving current Ids through the fourteenth sub-transistor T172 during even-numbered light-emitting periods (EP2, EP4, ..., EPn).

[0350] 30 to 32, each of the second light emitting element GEL and the third light emitting element BEL can be supplied with the driving current Ids through the thirteenth sub-transistor T171 during odd-numbered light emitting periods (EP1, EP3, ..., EPn-1) among the plurality of light emitting periods EP1 to EPn in one frame period, and can be supplied with the driving current Ids through the fourteenth sub-transistor T172 during the even-numbered light emitting periods (EP2, EP4, ..., EPn). Thus, each of the second light emitting element GEL and the third light emitting element BEL can emit light throughout the plurality of light emitting periods EP1 to EPn in one frame period.

[0351] As shown in FIG. 29 to FIG. 32, the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2 of the first sub-pixel RP emit light in different periods. Therefore, the emission period of the first sub-light-emitting element REL1 and the emission period of the second sub-light-emitting element REL2 can be reduced to half of the emission period of the second light-emitting element GEL and the emission period of the third light-emitting element BEL, respectively. This can reduce the heat generation amount of the first sub-light-emitting element REL1 and the heat generation amount of the second sub-light-emitting element REL2, so that the temperature of the first sub-light-emitting element REL1 and the temperature of the second sub-light-emitting element REL2 can be lowered. Therefore, it is possible to reduce or prevent the emission luminance of the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2 from decreasing due to the heat generation of the first sub-light-emitting element REL1 and the second sub-light-emitting element REL2.

[0352] FIG. 33 is an exemplary diagram showing a PAMA light emitting signal output unit and a PAMB light emitting signal output unit according to an embodiment.

[0353] For ease of explanation, FIG. 33 illustrates the kth through k+6th PAMA stages PASTk to PASTk+6 of the PAMA light emission signal output unit 1151 and the kth through k+6th PAMB stages PBSTk to PBSTk+6 of the PAMB light emission signal output unit 1152.

[0354] In the following description, the term "previous stage" refers to a stage located before a reference stage. For example, the stage before the k+1th stage refers to the first through kth stages, and the stage before the k+2th stage refers to the first through k+1th stages.

[0355] 33, the light emission control signal driver 115 includes a PAMA light emission signal output unit 1151 and a PAMB light emission signal output unit 1152. The PAMA light emission signal output unit 1151 is disposed on one side of the display area DA, for example, on the left side, and the PAMB light emission signal output unit 1152 is disposed on the other side of the display area DA, for example, on the right side, but the embodiment of the present specification is not limited thereto. For example, the PAMA light emission signal output unit 1151 and the PAMB light emission signal output unit 1152 may both be disposed on one side of the display area DA or on both sides of the display area DA.

[0356] On one side, for example, on the left side, of the kth through k+6th PAMA stages PASTk through PASTk+6, PAMA clock wirings PACL1 through PACL6 to which PAMA clock signals whose phases are sequentially delayed are applied may be arranged. On one side, for example, on the right side, of the kth through k+6th PAMB stages PBSTk through PBSTk+6, PAMB clock wirings PBCL1 through PBCL6 to which PAMB clock signals whose phases are sequentially delayed are applied may be arranged.

[0357] FIG. 33 illustrates six PAMA clock wires PACL1 to PACL6 and six PAMB clock wires PBCL1 to PBCL6, but the numbers of PAMA clock wires PACL1 to PACL6 and PBMA clock wires PBCL1 to PBCL6 are not limited to this.

[0358] Each of the kth through k+6th PAMA stages PASTk through PASTk+6 may be connected to one of the six PAMA clock wires PACL1 through PACL6 and one of the kth through k+6th PAMA light emitting wires PAALk through PAALk+6. The kth through k+6th PAMA stages PASTk through PASTk+6 may be alternately connected to the six PAMA clock wires PACL1 through PACL6. For example, the kth PAMA stage PASTk may be connected to the first PAMA clock wire PACL1, the k+1st PAMA stage PASTk+1 may be connected to the second PAMA clock wire PACL2, the k+2th PAMA stage PASTk+2 may be connected to the third PAMA clock wire PACL3, and the k+3rd PAMA stage PASTk+3 may be connected to the fourth PAMA clock wire PACL4. In addition, the k+4th PAMA stage PASTk+4 may be connected to the fifth PAMA clock wire PACL5, the k+5th PAMA stage PASTk+5 may be connected to the sixth PAMA clock wire PACL6, and the k+7th PAMA stage PASTk+7 may be connected to the first PAMA clock wire PACL1. Similarly, the kth through k+6th PAMB stages PBSTk-PBSTk+6 may be connected to any one of the six PAMB clock wires PBCL1-PBCL6 and any one of the kth through k+6th PAMB light-emitting wires PABLk-PABLk+6.

[0359] FIG. 34 is a waveform diagram showing the PAMA clock signal and the PAMB clock signal.

[0360] 34, the first through sixth PAMA clock signals PACK1 through PACK6 refer to signals applied to the first through sixth PAMA clock lines PACL1 through PACL6, respectively. The first through sixth PAMB clock signals PBCK1 through PBCK6 refer to signals applied to the first through sixth PAMB clock lines PBCL1 through PBCL6, respectively.

[0361] The first through sixth PAMA clock signals PACK1 through PACK6 and the first through sixth PAMA clock lines PBCL1 through PBCL6 may be signals whose phases are sequentially delayed. For example, the second PAMA clock signal PACK2 may be delayed in phase by one horizontal period from the first PAMA clock signal PACK1, the third PAMA clock signal PACK3 may be delayed in phase by one horizontal period from the second PAMA clock signal PACK2, the fourth PAMA clock signal PACK4 may be delayed in phase by one horizontal period from the third PAMA clock signal PACK3, the fifth PAMA clock signal PACK5 may be delayed in phase by one horizontal period from the fourth PAMA clock signal PACK4, and the sixth PAMA clock signal PACK6 may be delayed in phase by one horizontal period from the fifth PAMA clock signal PACK5.

[0362] In addition, the first PAMB clock signal PBCK1 may be delayed in phase by one horizontal period from the sixth PAMB clock signal PBCK6, the second PAMB clock signal PBCK2 may be delayed in phase by one horizontal period from the first PAMB clock signal PBCK1, the third PAMB clock signal PBCK3 may be delayed in phase by one horizontal period from the second PAMB clock signal PBCK2, the fourth PAMB clock signal PBCK4 may be delayed in phase by one horizontal period from the third PAMB clock signal PBCK3, the fifth PAMB clock signal PBCK5 may be delayed in phase by one horizontal period from the fourth PAMB clock signal PBCK4, and the sixth PAMB clock signal PBCK6 may be delayed in phase by one horizontal period from the fifth PAMB clock signal PBCK5.

[0363] 33 and 34, each of the kth to k+6th PAMA stages PASTk to PASTk+6 may output a PAM pulse of the PAMA clock signal applied via the PAMA clock line connected thereto to the corresponding PAMA light-emitting line. For example, the kth PAMA stage PASTk may output a PAM pulse of the gate-on voltage VGL in the first PAMA clock signal PACK1 of the first PAMA clock line PACL1 to the kth PAMA light-emitting line PAALk. The k+1th PAMA stage PASTk+1 may output a PAM pulse of the gate-on voltage VGL in the second PAMA clock signal PACK2 of the second PAMA clock line PACL2 to the k+1th PAMA light-emitting line PAALk+1. The k+2th PAMA stage PASTk+2 may output a PAM pulse of the gate-on voltage VGL in the third PAMA clock signal PACK3 of the third PAMA clock line PACL3 to the k+2th PAMA light-emitting line PAALk+2. The k+3-th PAMA stage PASTk+3 may output a PAM pulse of the gate-on voltage VGL in the fourth PAMA clock signal PACK4 of the fourth PAMA clock line PACL4 to the k+3-th PAMA light-emitting line PAALk+3. Similarly, each of the k-th through k+6-th PAMB stages PBSTk to PBSTk+6 may output a PAM pulse of the PAMB clock signal applied via the PAMB clock line connected thereto to the corresponding PAMB light-emitting line.

[0364] Furthermore, the k+4th PAMA stage PASTk+4 may output a PAM pulse of the gate-on voltage VGL in the fifth PAMA clock signal PACK4 of the fifth PAMA clock line PACL5 to the k+4th PAMA light-emitting line PAALk+4. The k+5th PAMA stage PASTk+5 may output a PAM pulse of the gate-on voltage VGL in the sixth PAMA clock signal PACK6 of the sixth PAMA clock line PACL6 to the k+5th PAMA light-emitting line PAALk+5. The k+6th PAMA stage PASTk+6 may output a PAM pulse of the gate-on voltage VGL in the first PAMA clock signal PACK1 of the first PAMA clock line PACL11 to the k+6th PAMA light-emitting line PAALk+6.

[0365] FIG. 35 is a perspective view illustrating a tiled display including multiple displays according to one embodiment.

[0366] 35, the tiled display device TD may include a plurality of display devices 11, 12, 13, and 14, and a seam portion SM. For example, the tiled display device TD may include a first display device 11, a second display device 12, a third display device 13, and a fourth display device 14.

[0367] The multiple display devices 11, 12, 13, 14 may be arranged in a lattice pattern. The multiple display devices 11, 12, 13, 14 may be arranged in a matrix pattern with M (M is a positive integer) rows and N (N is a positive integer) columns. For example, the first display device 11 and the second display device 12 may be adjacent to each other in the first direction DR1. The first display device 11 and the third display device 13 may be adjacent to each other in the second direction DR2. The third display device 13 and the fourth display device 14 may be adjacent to each other in the first direction DR1. The second display device 12 and the fourth display device 14 may be adjacent to each other in the second direction DR2.

[0368] However, the number and arrangement of the multiple display devices 11, 12, 13, and 14 in the tiled display device TD are not limited to those shown in Fig. 35. The number and arrangement of the display devices 11, 12, 13, and 14 in the tiled display device TD can be determined by the respective sizes of the display device 10 and the tiled display device TD, and the shape of the tiled display device TD.

[0369] The display devices 11, 12, 13, and 14 may have the same size, but are not limited to this. For example, the display devices 11, 12, 13, and 14 may have different sizes.

[0370] Each of the multiple display devices 11, 12, 13, 14 may have a rectangular shape including a long side and a short side. The multiple display devices 11, 12, 13, 14 may be arranged with their long sides or short sides connected to each other. Some or all of the multiple display devices 11, 12, 13, 14 may be arranged on the periphery of the tiled display device TD and form one side of the tiled display device TD. At least one of the multiple display devices 11, 12, 13, 14 may be arranged at at least one corner of the tiled display device TD and may form two adjacent sides of the tiled display device TD. At least one of the multiple display devices 11, 12, 13, 14 may be surrounded by other display devices.

[0371] Each of the multiple display devices 11, 12, 13, and 14 may be substantially the same as the display device 100 described with reference to Fig. 1. Therefore, a description of each of the multiple display devices 11, 12, 13, and 14 will be omitted.

[0372] The seam portion SM may include a joining member or an adhesive member. In this case, the multiple display devices 11, 12, 13, and 14 may be connected to each other via the joining member or adhesive member of the seam portion SM. The seam portion SM may be disposed between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

[0373] FIG. 36 is an enlarged layout diagram showing the E region of FIG. 35 in detail.

[0374] 36, the seam portion SM may have a planar shape of a cross, a cross, or a summing sign in a central region of the tiled display device TD where the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14 are adjacent. The seam portion SM may be disposed between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

[0375] The first display device 11 may include first pixels PX1 arranged in a matrix in the first direction DR1 and the second direction DR2 to display an image. The second display device 12 may include second pixels PX2 arranged in a matrix in the first direction DR1 and the second direction DR2 to display an image. The third display device 13 may include third pixels PX3 arranged in a matrix in the first direction DR1 and the second direction DR2 to display an image. The fourth display device 14 may include fourth pixels PX4 arranged in a matrix in the first direction DR1 and the second direction DR2 to display an image.

[0376] The minimum distance between adjacent first pixels PX1 in the first direction DR1 may be defined as a first horizontal separation distance GH1, and the minimum distance between adjacent second pixels PX2 in the first direction DR1 may be defined as a second horizontal separation distance GH2. The first horizontal separation distance GH1 and the second horizontal separation distance GH2 may be substantially equal to each other.

[0377] A seam portion SM may be disposed between the first pixel PX1 and the second pixel PX2 adjacent to each other in the first direction DR1. The minimum distance GM12 between the first pixel PX1 and the second pixel PX2 adjacent to each other in the first direction DR1 may be the sum of the minimum distance GHS1 between the first pixel PX1 and the seam portion SM in the first direction DR1, the minimum distance GHS2 between the second pixel PX2 and the seam portion SM in the first direction DR1, and the width GSM1 of the seam portion SM in the first direction DR1.

[0378] The minimum distance GM12 between the first pixel PX1 and the second pixel PX2 adjacent to each other in the first direction DR1, the first horizontal separation distance GH1, and the second horizontal separation distance GH2 may be substantially the same. Therefore, the minimum distance GHS1 between the first pixel PX1 and the seam portion SM in the first direction DR1 may be smaller than the first horizontal separation distance GH1, and the minimum distance GHS2 between the second pixel PX2 and the seam portion SM in the first direction DR1 may be smaller than the second horizontal separation distance GH2. Also, the width GSM1 of the seam portion SM in the first direction DR1 may be smaller than the first horizontal separation distance GH1 or the second horizontal separation distance GH2.

[0379] The minimum distance between the third pixels PX3 adjacent to each other in the first direction DR1 may be defined as a third horizontal separation distance GH3, and the minimum distance between the fourth pixels PX4 adjacent to each other in the first direction DR1 may be defined as a fourth horizontal separation distance GH4. The third horizontal separation distance GH3 and the fourth horizontal separation distance GH4 may be substantially equal to each other.

[0380] A seam portion SM may be disposed between the third pixel PX3 and the fourth pixel PX4 adjacent to each other in the first direction DR1. The minimum distance GM34 between the third pixel PX3 and the fourth pixel PX4 adjacent to each other in the first direction DR1 may be the sum of the minimum distance GHS3 between the third pixel PX3 and the seam portion SM in the first direction DR1, the minimum distance GHS4 between the fourth pixel PX4 and the seam portion SM in the first direction DR1, and the width GSM1 of the seam portion SM in the first direction DR1.

[0381] The minimum distance GM34 between the third pixel PX3 and the fourth pixel PX4 adjacent to each other in the first direction DR1, the third horizontal separation distance GH3, and the fourth horizontal separation distance GH4 may be substantially the same. Therefore, the minimum distance GHS3 between the third pixel PX3 and the seam portion SM in the first direction DR1 may be smaller than the third horizontal separation distance GH3, and the minimum distance GHS4 between the fourth pixel PX4 and the seam portion SM in the first direction DR1 may be smaller than the fourth horizontal separation distance GH4. Also, the width GSM1 of the seam portion SM in the first direction DR1 may be smaller than the third horizontal separation distance GH3 or the fourth horizontal separation distance GH4.

[0382] The minimum distance between adjacent first pixels PX1 in the second direction DR2 may be defined as a first vertical separation distance GV1, and the minimum distance between adjacent third pixels PX3 in the second direction DR2 may be defined as a third vertical separation distance GV3. The first vertical separation distance GV1 and the third vertical separation distance GV3 may be substantially equal to each other.

[0383] A seam portion SM may be disposed between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2. The minimum distance GM13 between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2 may be the sum of the minimum distance GVS1 between the first pixel PX1 and the seam portion SM in the second direction DR2, the minimum distance GVS3 between the third pixel PX3 and the seam portion SM in the second direction DR2, and the width GSM2 of the seam portion SM in the second direction DR2.

[0384] The minimum distance GM13 between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2, the first vertical separation distance GV1, and the third vertical separation distance GV3 may be substantially the same. Therefore, the minimum distance GVS1 between the first pixel PX1 and the seam portion SM in the second direction DR2 may be smaller than the first vertical separation distance GV1, and the minimum distance GVS3 between the third pixel PX3 and the seam portion SM in the second direction DR2 may be smaller than the third vertical separation distance GV3. Also, the width GSM2 of the seam portion SM in the second direction DR2 may be smaller than the first vertical separation distance GV1 or the third vertical separation distance GV3.

[0385] The minimum distance between adjacent second pixels PX2 in the second direction DR2 may be defined as a second vertical separation distance GV2, and the minimum distance between adjacent fourth pixels PX4 in the second direction DR2 may be defined as a fourth vertical separation distance GV4. The second vertical separation distance GV2 and the fourth vertical separation distance GV4 may be substantially equal to each other.

[0386] A seam portion SM may be disposed between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR2. The minimum distance GM24 between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR2 may be the sum of the minimum distance GVS2 between the second pixel PX2 and the seam portion SM in the second direction DR2, the minimum distance GVS4 between the fourth pixel PX4 and the seam portion SM in the second direction DR2, and the distance GSM4 of the seam portion SM in the second direction DR2.

[0387] The minimum distance GM24 between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR2, the second vertical separation distance GV2, and the fourth vertical separation distance GV4 may be substantially the same. Therefore, the minimum distance GVS2 between the second pixel PX2 and the seam portion SM in the second direction DR2 may be smaller than the second vertical separation distance GV2, and the minimum distance GVS4 between the fourth pixel PX4 and the seam portion SM in the second direction DR2 may be smaller than the fourth vertical separation distance GV4. Also, the width GSM2 of the seam portion SM in the second direction DR2 may be smaller than the second vertical separation distance GV2 or the fourth vertical separation distance GV4.

[0388] As shown in FIG. 36, in order to prevent seam portions SM from being visible between images displayed by multiple display devices 11, 12, 13, and 14, the minimum distance between pixels of adjacent display devices may be substantially the same as the minimum distance between pixels of each of the display devices.

[0389] FIG. 37 is a cross-sectional view showing an example of a tiled display device taken along the line EE' in FIG.

[0390] 37, the first display device 11 includes a first display module DPM1 and a first front cover COV1, and the second display device 12 includes a second display module DPM2 and a second front cover COV2.

[0391] Each of the first display module DPM1 and the second display module DPM2 includes a substrate SUB, a thin film transistor layer TFTL, and a light emitting element layer EML. The thin film transistor layer TFTL and the light emitting element layer EML have already been described in detail with reference to Figures 27 and 28. In Figure 37, the description overlapping with the embodiment of Figures 27 and 28 will be omitted.

[0392] The substrate SUB may include a first surface 41 on which the thin film transistor layer TFTL is disposed, a second surface 42 opposite to the first surface, and a first side surface 43 disposed between the first surface 41 and the second surface 42. The first surface 41 may be a front or top surface of the substrate SUB, and the second surface 42 may be a back or bottom surface of the substrate SUB.

[0393] In addition, the substrate SUB may further include chamfered surfaces 44 disposed between the first surface 41 and the first side surface 43 and between the second surface 42 and the first side surface 43. The thin film transistor layer TFTL and the light emitting element layer EML do not have to be disposed on the chamfered surfaces 44. The chamfered surfaces 44 can prevent the substrate SUB of the first display device 10 and the substrate of the second display device 10 from colliding with each other and being damaged.

[0394] The chamfered surface 44 may also be disposed between the first surface 41 and each of the other side surfaces except the first side surface 43, and between the second surface 42 and each of the other side surfaces except the first side surface 43. For example, when the first display device 11 and the second display device 12 have a rectangular planar shape as shown in Fig. 35, the chamfered surface 44 may be disposed between the first surface 41 and each of the second side surface, the third side surface, and the fourth side surface, and between the second surface 42 and each of the second side surface, the third side surface, and the fourth side surface.

[0395] The first front cover COV1 may be arranged on the chamfered surface 44 of the substrate SUB. That is, the first front cover COV1 may protrude from the substrate SUB in the first direction DR1 and the second direction DR2. Thus, the distance GSUB between the substrate SUB of the first display device 11 and the substrate SUB of the second display device 12 may be greater than the distance GCOV between the first front cover COV1 and the second front cover COV2.

[0396] Each of the first front cover COV1 and the second front cover COV2 may include an adhesive member 51, a light transmittance adjusting layer 52 arranged on the adhesive member 51, and an anti-glare layer (53) arranged on the light transmittance adjusting layer 52.

[0397] The adhesive member 51 of the first front cover COV1 serves to bond the light emitting element layer EML of the first display module DPM1 to the first front cover COV1. The adhesive member 51 of the second front cover COV2 serves to bond the light emitting element layer EML of the second display module DPM2 to the second front cover COV2. The adhesive member 51 may be a transparent adhesive member that can transmit light. For example, the adhesive member 51 may be an optically clear adhesive film or an optically clear resin.

[0398] The anti-glare layer 53 may be designed to diffusely reflect external light so as to prevent the external light from being reflected directly and reducing the visibility of the image, thereby increasing the contrast ratio of the images displayed by the first display device 10 and the second display device 20.

[0399] The light transmittance adjusting layer 52 can be designed to reduce the transmittance of external light or light reflected by the first display module DPM1 and the second display module DPM2, thereby preventing the gap GSUB between the substrate SUB of the first display module DPM1 and the substrate SUB of the second display module DPM2 from being visible from the outside.

[0400] The anti-glare layer 53 may be realized as a polarizer, and the light transmittance adjusting layer 52 may be realized as a phase retardation layer, but the embodiments of the present specification are not limited thereto.

[0401] Note that an example of a tiled display device TD cut along F-F', G-G', and H-H' in Figure 36 is substantially similar to the example of a tiled display device TD cut along E-E' described in relation to Figure 37, so a description thereof will be omitted.

[0402] FIG. 38 is an enlarged layout diagram showing the details of the F region in FIG.

[0403] FIG. 38 shows the pad PAD arranged on the upper side of the first display device 10 and the second sub-pixel GP of the first pixel PX1.

[0404] 38, pads PAD may be arranged on an upper edge of the first display device 10. When the PWM data lines DL of the first display device 10 extend in the second direction DR2, the pads PAD may be arranged on the upper and lower edges of the first display device 10. Alternatively, when the PWM data lines DL of the first display device 10 extend in the first direction DR1, the pads PAD may be arranged on the left and right edges of the first display device 10.

[0405] Each of the pads PAD may be connected to a PWM data line DL. Also, each of the pads PAD may be connected to a side line SSL. The side line SSL may be disposed on one side and the bottom surface (or rear surface) of the substrate SUB. The side line SSL may be connected to a connection line (CCL in FIG. 37) on the bottom surface of the substrate SUB.

[0406] Fig. 39 is a cross-sectional view showing an example of a tiled display device cut along II' in Fig. 38. In Fig. 39, explanations that overlap with the embodiment in Figs. 27 and 28 will be omitted.

[0407] 39, the pad PAD may be disposed on the first insulating film 161. The pad PAD may be exposed and not covered by the second insulating film 181 and the third insulating film 191. Although the pad PAD is illustrated as being included in the second data metal layer, the embodiment of the present specification is not limited thereto. For example, the pad PAD may be included in the third data metal layer. The pad PAD may be connected to the PWM data line DL via a first side pad contact hole SCT1 penetrating the first planarization film 160 and the first insulating film 161.

[0408] The interconnect wiring CCL may be disposed on the lower surface of the substrate SUB. The interconnect wiring CCL may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0409] The third planarization film 170 may be disposed on a portion of the connecting wiring CCL. The third planarization film 170 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0410] The fourth insulating film 171 may be disposed on the third planarization film 170. The fourth insulating film 171 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0411] The side wiring SSL may be disposed on the lower surface edge, the side surface, and the upper surface edge of the substrate SUB. One end of the side wiring SSL may be coupled to the connecting wiring CCL. One end of the side wiring SSL may contact the side surface and the lower surface of the connecting wiring CCL. The other end of the side wiring SSL may be coupled to the pad part PAD. The other end of the side wiring SSL may be coupled to the pad part PAD via a second side pad contact hole SCT2 penetrating the second insulating film 181 and the third insulating film 191.

[0412] The side wiring SSL may be arranged on the side of the substrate SUB, the side of the buffer film BF, the side of the gate insulating film 130, the side of the first interlayer insulating film 141, the side of the second interlayer insulating film 142, the side of the first insulating film 161, the side of the second insulating film 181, and the side of the third insulating film 191.

[0413] The flexible film FPCB may be disposed on a lower surface of the fourth insulating film 171. The flexible film FPCB may be connected to the connecting line CCL through a back contact hole BCT penetrating the third planarization film 170 and the third insulating film 171 by using a conductive adhesive material CAM. A source driving circuit SIC for supplying a data voltage to the PWM data line DL may be disposed on the lower surface of the flexible film FPCB. The conductive adhesive material CAM may be an anisotropic conductive film or an anisotropic conductive paste.

[0414] 38 and 39, in the first display device 11, the source driving circuit SIC of the flexible film FPCB arranged under (below) the substrate SUB can be connected to the PWM data wiring DL via the connection wiring CCL, the side wiring SSL, and the pad PAD. That is, since the source driving circuit SIC is arranged on the substrate SUB, the non-display area NDA can be eliminated, and the pixels PX can be formed even on the periphery of the substrate SUB.

[0415] FIG. 40 is a block diagram illustrating a tiled display device according to one embodiment.

[0416] For convenience of explanation, FIG. 40 shows a first display device 11 and a host system HOST.

[0417] Referring to FIG. 40, a tiled display device TD according to one embodiment may include a host system HOST, a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, a speaker 240, a user input unit 250, a HDD 260, a network communication unit 270, a UI generation unit 280 and a control unit 290.

[0418] The host system HOST may be realized as one of a television system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a mobile phone system, or a tablet.

[0419] A user's command may be input to the host system HOST in various forms. For example, the host system HOST may receive a command by touch input from the user. Alternatively, the host system HOST may receive a command by keyboard input or button input from a remote controller.

[0420] The host system HOST may receive an input of original video data corresponding to an original image from the outside. The host system HOST may divide the original video data as many times as the number of display devices (a number corresponding to the number of display devices). For example, the host system HOST may divide the original video data into first video data corresponding to a first image, second video data corresponding to a second image, third video data corresponding to a third image, and fourth video data corresponding to a fourth image, corresponding to the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14. The host system HOST may transmit the first video data to the first display device 11, the second video data to the second display device 12, the third video data to the third display device 13, and the fourth video data to the fourth display device 14.

[0421] The first display device 11 can display a first image according to the first video data, the second display device 12 can display a second image according to the second video data, the third display device 13 can display a third image according to the third video data, and the fourth display device 14 can display a fourth image according to the fourth video data. Therefore, the user can view the original image in which the first to fourth images displayed on the first to fourth display devices 11, 12, 13, and 14 are combined.

[0422] The first display device 11 may include a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, a speaker 240, a user input unit 250, a HDD 260, a network communication unit 270, a UI generation unit 280, and a control unit 290.

[0423] The broadcast tuning unit 210 may tune to a predetermined channel frequency under the control of the control unit 290, and receive a broadcast signal of the corresponding channel via an antenna. The broadcast tuning unit 210 may include a channel detection module and an RF demodulation module.

[0424] The broadcast signal demodulated by the broadcast tuning unit 210 is processed by a signal processing unit 220 and output to a display unit 230 and a speaker 240. Here, the signal processing unit 220 may include a demultiplexer 221, a video decoder 222, a video processing unit 223, an audio decoder 224, and an additional data processing unit 225.

[0425] The demultiplexer 221 separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal, and additional data are respectively restored by a video decoder 222, an audio decoder 224, and an additional data processor 225. At this time, the video decoder 222, the audio decoder 224, and the additional data processor 225 restore the signals to a decoding format corresponding to the encoding format used when the broadcast signal was transmitted.

[0426] In addition, the decoded video signal is converted by the video processor 223 to have a vertical frequency, resolution, aspect ratio, etc. suitable for the output standard of the display unit 230, and the decoded audio signal is output to the speaker 240.

[0427] The display unit 230 includes a display panel 100 on which an image is displayed, and a panel driver that controls driving of the display panel 100. A detailed block diagram of the display panel 100 and the panel driver has been described above in detail with reference to FIG.

[0428] The user input unit 250 can receive signals transmitted by the host system HOST. The user input unit 250 can be provided so that a user can select and input data for commands related to communication with other display devices as well as data related to channel selection, UI (User Interface) menu selection and operation transmitted by the host system HOST.

[0429] The storage unit 260 stores various software programs including an OS program, recorded broadcast programs, videos, photos, and other data, and may be implemented as a storage medium such as a hard disk or a non-volatile memory.

[0430] The network communication unit 270 is for short-range communication with the host system HOST and other display devices, and can be realized as a communication module including an antenna pattern capable of realizing mobile communication, data communication, Bluetooth (registered trademark), RF, Ethernet, etc.

[0431] The network communication unit 270 can also transmit and receive wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network constructed in accordance with a technical standard or communication method for mobile communication (e.g., Global System for Mobile communication (GSM), Code Division Multi Access (CDMA), Code Division Multi Access 2000 (CDMA2000), Enhanced Voice-Data Optimized or Enhanced Voice-Data Only (EV-DO), Wideband CDMA (WCDMA (registered trademark)), High Speed ​​Downlink Packet Access (HSDPA), High Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), Long Term Evolution-Advanced (LTE-A), 5G, etc.) via an antenna pattern described below.

[0432] The network communication unit 270 can also transmit and receive wireless signals through a communication network using wireless Internet technology via an antenna pattern described below. Examples of wireless Internet technology include WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, DLNA (Digital Living Network Alliance), WiBro (Wireless Broadband), WiMAX (World Interoperability for Microwave Access), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), and LTE-A (Long Term Evolution-Advanced), and the antenna pattern transmits and receives data using at least one wireless Internet technology including Internet technologies not listed above.

[0433] The UI generating unit 280 generates a UI menu for communication with the host system HOST and other display devices, and can be realized by an algorithm code and an OSD IC. The UI menu for communication with the host system HOST and other display devices can be a menu for specifying a partner digital TV with which communication is desired and for selecting a desired function.

[0434] The control unit 290 is responsible for overall control of the first display device 11 and communication control between the host system HOST and the second through fourth display devices 12, 13, and 14, and can be realized by an MCU (Micro Controller Unit) in which the relevant algorithm code for control is stored and the stored algorithm code is executed.

[0435] The control unit 290 controls the transmission of corresponding control commands and data to the host system HOST and the second through fourth display devices 12, 13, and 14 via the network communication unit 270 in response to the input and selection of the user input unit 250. Of course, when a predetermined control command and data is input from the host system HOST and the second through fourth display devices 12, 13, and 14, the control unit 290 performs an operation according to the corresponding control command.

[0436] Note that the block diagram of the second display device 12, the block diagram of the third display device 13, and the block diagram of the fourth display device 14 are substantially similar to the block diagram of the first display device 11 described with reference to Figure 4, so descriptions thereof will be omitted.

[0437] Although the embodiment of the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiment is illustrative in all respects and is not limiting. [Explanation of symbols]

[0438] 10 Display device 100 Display Panel 110 Scan drive unit 200 Source drive unit 300 Timing control section 400 Power supply section

Claims

1. a first sub-pixel and a second sub-pixel that emit different light from each other; The first sub-pixel is a first anode pad electrode and a second anode pad electrode spaced apart from each other on a plane; a first cathode pad electrode disposed apart from the first anode pad electrode and the second anode pad electrode on a plane; and a first light emitting element including a first sub light emitting element disposed on the first anode pad electrode and the cathode pad electrode, and a second sub light emitting element disposed on the second anode pad electrode and the cathode pad electrode; an area of ​​the first cathode pad electrode is larger than an area of ​​the first anode pad electrode or an area of ​​the second anode pad electrode; The first and second sub light emitting elements emit light during different periods, The first sub-light-emitting element and the second sub-light-emitting element emit the same light.

2. The display device of claim 1 , wherein a length in one direction of the first cathode pad electrode is greater than a length in one direction of the first anode pad electrode or a length in one direction of the second anode pad electrode.

3. The second sub-pixel is A third anode pad electrode; a second cathode pad electrode disposed apart from the third anode pad electrode; and The display device of claim 1 , further comprising: a second light emitting element disposed on the third anode pad electrode and the second cathode pad electrode.

4. The display device according to claim 3 , wherein an area of ​​the first cathode pad electrode is larger than an area of ​​the second cathode pad electrode.

5. The display device according to claim 3 , wherein a length in one direction of the first cathode pad electrode is greater than a length in one direction of the second cathode pad electrode.

6. a third sub-pixel emitting light different from the first sub-pixel and the second sub-pixel; The third sub-pixel is A fourth anode pad electrode; a third cathode pad electrode disposed apart from the third anode pad electrode on a plane; and The display device according to claim 1 , further comprising a third light emitting element disposed on the fourth anode pad electrode and the third cathode pad electrode.

7. The display device according to claim 6 , wherein an area of ​​the first cathode pad electrode is larger than an area of ​​the third cathode pad electrode.

8. The display device of claim 7 , wherein a length in one direction of the first cathode pad electrode is greater than a length in one direction of the third cathode pad electrode.

9. The display device of claim 8 , wherein the first and second sub light emitting elements emit a first light, the second light emitting element emits a second light, and the third light emitting element emits a third light.

10. The display device of claim 6 , wherein the first light is red light, the second light is green light, and the third light is blue light.

11. a first data line to which a first data voltage is applied; a second data line to which a second data voltage is applied; a first light emission control wiring to which a first light emission control signal is applied; a second light emission control wiring to which a second light emission control signal is applied; and a first sub-pixel connected to the first data wiring, the second data wiring, the first light-emitting control wiring, and the second light-emitting control wiring; The first sub-pixel is a first light-emitting element including a first sub-light-emitting element and a second sub-light-emitting element for emitting a first light; a first pixel driver that generates a control current in response to the first data voltage of the first data line; a second pixel driver that generates a first driving current to be applied to the first sub light emitting element or the second sub light emitting element in response to the second data voltage of the second data line; and a third pixel driver configured to control a period for applying the first driving current to the first sub light emitting element or the second sub light emitting element in response to a control current of the first pixel driver; The third pixel driving unit is a first transistor that supplies the first driving current to the first light emitting element in response to the first light emitting control signal; and a second transistor configured to supply the first driving current to the second light emitting element in response to the second light emitting control signal; the first light emission control signal has a gate-on voltage during an N-th frame period and a gate-off voltage during an N+1-th frame period; The second light emission control signal has the gate-off voltage during an N-th frame period and has the gate-on voltage during the N+1-th frame period.

12. a first initialization signal wiring to which a first initialization signal is applied; and An initialization voltage wiring to which an initialization voltage is applied is further provided; The first sub-pixel is a third transistor that supplies the initialization voltage to the first electrode of the first sub light-emitting element in response to the first initialization signal; and The display device of claim 11 , further comprising a fourth transistor supplying the initialization voltage to the first electrode of the second light emitting element in response to the first initialization signal.

13. A light emission signal wiring to which a light emission signal is applied; and a second sub-pixel connected to the light emitting signal line and the first initialization signal line, The second sub-pixel is a second light-emitting element that emits a second light; a fifth transistor that supplies a second driving current to the second light-emitting element in response to the first light-emitting signal; and The display device of claim 12 , further comprising a sixth transistor configured to supply the initialization voltage to the first electrode of the second light emitting element in response to the first initialization signal.

14. The display device of claim 13 , wherein the first light is red light, and the second light is green light or blue light.

15. a first data line to which a first data voltage is applied; a second data line to which a second data voltage is applied; a first light emission signal wiring to which a first light emission signal is applied; a second light emission signal wiring to which a second light emission signal is applied; and a first sub-pixel connected to the first data wiring, the second data wiring, the first light-emitting signal wiring, and the second light-emitting signal wiring; The first sub-pixel is a first light-emitting element including a first sub-light-emitting element and a second sub-light-emitting element for emitting a first light; a first pixel driver that generates a control current in response to the first data voltage of the first data line; a second pixel driving unit that generates a driving current to be applied to the first sub light emitting element or the second sub light emitting element in response to the second data voltage of the second data line; and a third pixel driver configured to control a period for applying the first driving current to the first sub light emitting element or the second sub light emitting element in response to a control current of the first pixel driver; The third pixel driving unit is a first transistor that supplies a first driving current to the first sub light-emitting element in response to the first light-emitting signal; and a second transistor configured to supply the first driving current to the second light emitting element in response to the second light emitting signal; One frame period includes a plurality of light emission periods, The first transistor and the second transistor are turned on during different light emission periods among the plurality of light emission periods.

16. the first transistor is turned on during odd-numbered light emission periods among the plurality of light emission periods, The display device of claim 15 , wherein the second transistor is turned on during even-numbered light-emitting periods among the plurality of light-emitting periods.

17. During odd-numbered light emission periods among the plurality of light emission periods, the first light emission signal has a gate-on voltage and the second light emission signal has a gate-off voltage, The display device of claim 15 , wherein the second light-emitting signal has the gate-on voltage and the first light-emitting signal has the gate-off voltage during even-numbered light-emitting periods of the plurality of light-emitting periods.

18. a first initialization signal wiring to which a first initialization signal is applied; and An initialization voltage wiring to which an initialization voltage is applied is further provided; The first sub-pixel is a third transistor that supplies the initialization voltage to the first electrode of the first sub light-emitting element in response to the first initialization signal; and The display device of claim 15, further comprising a fourth transistor supplying the initialization voltage to the first electrode of the second light emitting element in response to the first initialization signal.

19. a second sub-pixel connected to the first light-emitting signal line and the second light-emitting signal line, The second sub-pixel is a second light-emitting element that emits a second light; a fifth transistor that supplies a second driving current to the second light-emitting element in response to the first light-emitting signal; and The display device according to claim 18 , further comprising a sixth transistor configured to supply the second driving current to the second light emitting element in response to the second light emitting signal.

20. a first initialization signal wiring to which a first initialization signal is applied; and An initialization voltage wiring to which an initialization voltage is applied is further provided; The second sub-pixel is The display device of claim 19 , further comprising a seventh transistor supplying the initialization voltage to the first electrode of the second light emitting element in response to the first initialization signal.

21. The display device of claim 19 , wherein the first light is red light, and the second light is green light or blue light.

Images