Thin film transistor array substrate and its manufacturing method

Abstract

A thin film transistor array substrate according to one embodiment includes a substrate, a semiconductor layer on the substrate, and a gate electrode on the semiconductor layer, the semiconductor layer including a channel region, conductive regions located on both sides of the channel region, and an edge portion, the edge portion being located at an edge of the conductive region, and the edge portion being doped with a higher concentration of carbon than the channel region and the conductive region.

Description

[Technical field]

[0001] The present disclosure relates to a thin film transistor array substrate and a manufacturing method thereof. [Background technology]

[0002] A semiconductor device such as a display device includes a thin film transistor array substrate on which a plurality of thin film transistors for switching functions or driving electronic elements are formed. For example, the display device may include a plurality of thin film transistors located in a display area capable of displaying an image and a plurality of thin film transistors located in a circuit in a peripheral area.

[0003] The thin film transistor includes a semiconductor layer and a gate electrode of an active layer formed on a substrate, with a gate insulating layer located between the semiconductor layer and the gate electrode.

[0004] The semiconductor layer may include various semiconductor materials such as amorphous silicon, polycrystalline silicon, and oxide semiconductor, and may be doped with impurities for electrical properties.

[0005] The smaller the variation between transistors having the same function among a plurality of transistors included in a semiconductor device, the more uniform the characteristics can be. Summary of the Invention [Problem to be solved by the invention]

[0006] The embodiments provide a thin film transistor array substrate including thin film transistors and a manufacturing method thereof that can prevent unwanted diffusion of dopants or impurities, thereby minimizing undesirable variations in the characteristics of a plurality of thin film transistors and making the performance of the thin film transistors sufficiently constant and uniform. [Means for solving the problem]

[0007] A thin film transistor array substrate according to an embodiment includes a substrate, a semiconductor layer on the substrate, and a gate electrode on the semiconductor layer, the semiconductor layer including a channel region, conductive regions located on both sides of the channel region, and an edge portion, the edge portion being located at an edge of the conductive region, and the edge portion being doped with a higher concentration of carbon than the channel region and the conductive region.

[0008] The edge portion may include a vertical portion that extends in a first direction perpendicular to a surface of the substrate and contacts a side surface of the conductive region.

[0009] The edge portion may further include a horizontal portion extending in a second direction different from the first direction and contacting an upper surface of the conductive region.

[0010] The vertical portion and the horizontal portion may be connected to each other at a ridge.

[0011] A side of the horizontal portion may contact a side of the channel region.

[0012] The width of the horizontal portion in the first direction may be smaller than the length of the vertical portion in the first direction, and the length of the horizontal portion in the second direction may be larger than the width of the vertical portion in the second direction.

[0013] The semiconductor device may further include an insulating layer located on the gate electrode, and an electrode located on the insulating layer, the electrode contacting and electrically connecting with an upper surface of the horizontal portion of the edge portion through an opening formed in the insulating layer.

[0014] The semiconductor device may further include an insulating layer located between the semiconductor layer and the gate electrode, a lower portion of the insulating layer being doped with carbon and including an additional horizontal portion in contact with the horizontal portion.

[0015] The semiconductor layer may further include a bottom portion located at a lower portion and doped with a higher concentration of carbon than the channel region and the conductive region.

[0016] The edge and bottom may together cover the bottom, side and top surfaces of the semiconductor layer, and the entire top surface of the semiconductor layer except for the top surface of the channel region.

[0017] The edge may be conductive.

[0018] The semiconductor layer may include polycrystalline silicon.

[0019] A method for manufacturing a thin film transistor array substrate according to an embodiment includes the steps of forming a semiconductor layer on a substrate, forming a first mask pattern on the semiconductor layer to expose an edge of the semiconductor layer, primarily doping the semiconductor layer with carbon using the first mask pattern as a mask, removing the first mask pattern to dope the exposed semiconductor layer with impurities, and forming a first insulating layer on the semiconductor layer.

[0020] The method may further include forming a second mask pattern on the first insulating layer, and secondly doping the semiconductor layer with carbon using the second mask pattern as a mask.

[0021] The method may further include removing the first insulating layer, forming a second insulating layer on the semiconductor layer, and forming a gate electrode on the second insulating layer.

[0022] The method may further include forming a gate electrode on the first insulating layer, and secondarily doping the semiconductor layer with carbon using the gate electrode as a mask.

[0023] The method may further include forming a second insulating layer on the gate electrode, forming an opening in the second insulating layer and the first insulating layer, and forming an electrode connected to the semiconductor layer through the opening.

[0024] The method may further include injecting carbon into a lower portion of the semiconductor layer to form a carbon-doped bottom portion at a lower portion of the semiconductor layer.

[0025] A method for manufacturing a thin film transistor array substrate according to an embodiment includes the steps of: depositing amorphous silicon on a substrate to form a first semiconductor layer; injecting carbon from below (a lower portion) of the substrate to perform primary carbon doping on a lower portion of the first semiconductor layer (primary carbon doping) to form a lower doped layer; depositing amorphous silicon on the first semiconductor layer to form an additional semiconductor layer; forming a first mask pattern exposing an edge of the second semiconductor layer on a second semiconductor layer including the lower doped layer, the first semiconductor layer, and the additional semiconductor layer; performing primary carbon doping on the second semiconductor layer (primary carbon doping) using the first mask pattern as a mask; removing the first mask pattern to dope impurities into the exposed second semiconductor layer; and forming a first insulating layer on the second semiconductor layer.

[0026] The method may further include forming a second mask pattern on the first insulating layer, and performing a second carbon doping on the semiconductor layer using the second mask pattern as a mask.

[0027] According to an embodiment, a thin film transistor array substrate includes a channel region, a first region doped with a first material, and a second region doped with a second material, the first region contacting the channel region and positioned on both ends of the channel region, and the second region overlapping the first region and contacting the channel region.

[0028] The first material may include boron.

[0029] The second material may include carbon. Effect of the Invention

[0030] According to the embodiment, it is possible to prevent diffusion of dopants or impurities in a thin film transistor or a thin film transistor array, minimize undesirable variations in the characteristics of a plurality of thin film transistors, and make the performance of the thin film transistors sufficiently constant and uniform. [Brief description of the drawings]

[0031] [Figure 1] FIG. 2 is a cross-sectional view of a thin film transistor array substrate according to an embodiment; [Diagram 2] FIG. 2 is a plan view of a thin film transistor according to an embodiment; [Diagram 3] 1 is a cross-sectional view illustrating a process of a method for manufacturing a thin film transistor array substrate according to an embodiment; [Figure 4] FIG. 4 is a cross-sectional view of a step subsequent to the step shown in FIG. [Diagram 5] 5 is a cross-sectional view of a step after the process shown in FIG. [Figure 6] 6 is a cross-sectional view of a thin film transistor array substrate according to an embodiment at a step after the process shown in FIG. 5; [Figure 7] FIG. 6 is a cross-sectional view of a step after the step shown in FIG. 5, as a process of a method for manufacturing a thin film transistor array substrate according to an embodiment; [Figure 8] 8 is a cross-sectional view of a step after the process shown in FIG. [Figure 9] 9 is a cross-sectional view of a thin film transistor array substrate according to an embodiment at a step after the process shown in FIG. 8; [Figure 10] 1 is a cross-sectional view illustrating a process of a method for manufacturing a thin film transistor array substrate according to an embodiment; [Figure 11] 11 is a cross-sectional view of a step after the process shown in FIG. [Figure 12] 12 is a cross-sectional view of a step after the step shown in FIG. 11 ; [Figure 13] 13 is a cross-sectional view of a step after the process shown in FIG. 12; [Figure 14]FIG. 14 is a cross-sectional view of a thin film transistor array substrate according to an embodiment at a step after the process shown in FIG. 13; [Figure 15] FIG. 14 is a cross-sectional view of a thin film transistor array substrate according to an embodiment at a step after the step shown in FIG. 13 as a process of a method for manufacturing a thin film transistor array substrate according to an embodiment; [Figure 16] FIG. 2 is a plan view of a thin film transistor according to an embodiment; [Figure 17] 1 is a cross-sectional view illustrating a process of a method for manufacturing a thin film transistor array substrate according to an embodiment; [Figure 18] 1 is a schematic plan view of a display device according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] A thin film transistor array substrate according to an embodiment includes a substrate, a semiconductor layer on the substrate, and a gate electrode on the semiconductor layer, the semiconductor layer including a channel region, conductive regions located on both sides of the channel region, and an edge portion, the edge portion being located at an edge of the conductive region, and the edge portion being doped with a higher concentration of carbon than the channel region and the conductive region.

[0033] A method for manufacturing a thin film transistor array substrate according to an embodiment includes the steps of forming a semiconductor layer on a substrate, forming a first mask pattern on the semiconductor layer to expose an edge of the semiconductor layer, primarily doping the semiconductor layer with carbon using the first mask pattern as a mask, removing the first mask pattern to dope the exposed semiconductor layer with impurities, and forming a first insulating layer on the semiconductor layer.

[0034] A method for manufacturing a thin film transistor array substrate according to an embodiment includes the steps of: depositing amorphous silicon on a substrate to form a first semiconductor layer; injecting carbon from below the substrate to perform primary carbon doping on a lower portion of the first semiconductor layer (by doping with carbon primarily) to form a lower doped layer; depositing amorphous silicon on the first semiconductor layer to form an additional semiconductor layer; forming a first mask pattern on a second semiconductor layer including the lower doped layer, the first semiconductor layer, and the additional semiconductor layer to expose an edge of the second semiconductor layer; performing primary carbon doping on the second semiconductor layer using the first mask pattern as a mask (doping with carbon primarily); removing the first mask pattern to dope impurities into the exposed second semiconductor layer; and forming a first insulating layer on the second semiconductor layer.

[0035] According to an embodiment, a thin film transistor array substrate includes a channel region, a first region doped with a first material, and a second region doped with a second material, the first region contacting the channel region and positioned on both ends of the channel region, and the second region overlapping the first region and contacting the channel region.

[0036] <Embodiments of the invention> DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention. The present invention may be embodied in several different forms, and is not limited to the embodiments described herein.

[0037] In order to clearly describe the present invention, parts that are not relevant to the description will be omitted, and the same reference numerals will be used throughout the specification to refer to the same or similar components.

[0038] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, thicknesses are enlarged to clearly show multiple layers and regions. In the drawings, thicknesses of some layers and regions are exaggerated for convenience of explanation.

[0039] In addition, when a part such as a layer, film, region, or plate is said to be "on" or "above" another part, this includes not only when it is "directly above" (just above) the other part, but also when there is another part between them. Conversely, when a part is said to be "directly above" (just above) another part, it means that there is no other part in between. In addition, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" the opposite direction of gravity.

[0040] In addition, throughout the specification, when a part is said to "comprise" a certain element, this means that it may further include other elements, rather than excluding other elements, unless specifically stated to the contrary.

[0041] Additionally, throughout the specification, "on a plane" means when the target part is viewed from above, and "on a cross section" means when the target part is cut vertically and viewed from the side.

[0042] A thin film transistor and a thin film transistor array substrate according to an embodiment will be described with reference to FIG. 1 and FIG.

[0043] FIG. 1 is a cross-sectional view of a thin film transistor array substrate according to an embodiment, and FIG. 2 is a plan view of a thin film transistor according to an embodiment.

[0044] 1, a thin film transistor array substrate according to an embodiment may be referred to as a transistor substrate and includes a substrate 110, a buffer layer 120, a semiconductor layer 130, a gate electrode 154, a first electrode 173, a second electrode 175, a first insulating layer 140, and a second insulating layer 160. The substrate 110 may include an insulating material. The buffer layer 120 may be an insulating layer and may be located on the substrate 110.

[0045] A semiconductor layer 130 is located above the buffer layer 120 .

[0046] The semiconductor layer 130 includes a channel region 134 capable of forming a channel when the thin film transistor is on, conductive regions 133d, 135d located on either side of the channel region 134, and edges 133, 135.

[0047] With respect to one channel region 134 as a reference, the first conductive region 133d located on one side may be a source region and the second conductive region 135d located on the other side may be a drain region, or vice versa.

[0048] The edges 133, 135 have a higher concentration of doped carbon (C) than the remaining portions of the semiconductor layer 130, i.e., the channel region 134 and the conductive regions 133d, 135d. In some embodiments, the channel region 134 and the conductive regions 133d, 135d may be substantially undoped with carbon, and only the edges 133, 135 may be doped with carbon.

[0049] The doping dose of carbon doped in the edges 133 and 135 is approximately 1*e 11 / cm 2 ~1*e 13 / cm 2 It can be, but is not limited to this.

[0050] The conductive regions 133d, 135d and the edges 133, 135 are all conductive and may have a higher carrier concentration than the channel region 134. Therefore, the edges 133, 135 may be defined as being included in the conductive regions 133d, 135d.

[0051] The first edge 133 located on one side based on one channel region 134 may be located at the edge of the first conductive region 133d, and the second edge 135 located on the other side may be located at the edge of the second conductive region 135d.

[0052] The first edge portion 133 may include a first vertical portion 133a extending in a direction perpendicular to the surface of the substrate 110, i.e., in the z direction, and contacting a side surface of the first conductive region 133d, and a first horizontal portion 133b extending in a y direction perpendicular to the z direction and contacting an upper surface of the first conductive region 133d. The first conductive region 133d may be located between the first vertical portion 133a and the channel region 134, and between the first horizontal portion 133b and the substrate 110.

[0053] The first vertical portion 133a and the first horizontal portion 133b may be connected to each other at a ridge. One side of the first horizontal portion 133b may contact one side of the channel region .

[0054] The first vertical portion 133a and the first horizontal portion 133b connected to each other may have a generally inverted L-shape on the yz cross section.

[0055] The length of the first horizontal portion 133b in the y direction may be greater than the width of the first vertical portion 133a in the y direction. The width of the first horizontal portion 133b in the z direction may be less than the length of the first vertical portion 133a in the z direction. For example, the thickness of the first horizontal portion 133b in the z direction may be, but is not limited to, approximately 1 angstrom to 50 angstroms. The width of the first vertical portion 133a in the y direction may be, but is not limited to, approximately 1 angstrom to 100 angstroms.

[0056] The second edge portion 135 may include a second vertical portion 135a extending in a direction perpendicular to the surface of the substrate 110, i.e., in the z direction, and contacting a side surface of the second conductive region 135d, and a second horizontal portion 135b extending in the y direction and contacting an upper surface of the second conductive region 135d.

[0057] The second vertical portion 135a and the second horizontal portion 135b may be connected to each other at a ridge. The second horizontal portion 135b and the first horizontal portion 133b may contact two opposite sides of the channel region 134.

[0058] The second vertical portion 135a and the second horizontal portion 135b connected to each other may have a generally inverted L-shape on the yz cross section.

[0059] The length of the second horizontal portion 135b in the y direction may be greater than the width of the second vertical portion 135a in the y direction. The width of the second horizontal portion 135b in the z direction may be less than the length of the second vertical portion 135a in the z direction. For example, the thickness of the second horizontal portion 135b in the z direction may be, but is not limited to, approximately 1 angstrom to 50 angstroms. The width of the second vertical portion 135a in the y direction may be, but is not limited to, approximately 1 angstrom to 100 angstroms.

[0060] 1 and 2, the edges 133, 135 may include two opposing side surfaces of the semiconductor layer 130, and may include two opposing ends of the top surface of the semiconductor layer 130 located on two opposing sides of the channel region 134. The edges 133, 135 may include outer peripheries of the semiconductor layer 130 located on both opposing sides of the channel region 134 of the semiconductor layer 130.

[0061] The semiconductor layer 130 may include a semiconductor material such as polycrystalline silicon, and the semiconductor layer 130 is doped with impurities other than carbon as a whole.

[0062] The semiconductor layer 130 can be a P-type semiconductor or an N-type semiconductor.

[0063] In the case of a P-type semiconductor, the dopant, i.e., the impurity, doped into the semiconductor layer 130 may include Group 13 elements such as boron (Boron, B), aluminum (Al), and indium (In). In the case of an N-type semiconductor, the impurity doped into the semiconductor layer 130 may include Group 15 elements such as phosphorus (P), arsenic (As), and antimony (Sb). In this description, the semiconductor layer 130 doped with boron as the main impurity will be mainly described. In addition, in this description, the impurity doped into the semiconductor layer 130 means an impurity other than carbon.

[0064] The amount of impurities implanted into the semiconductor layer 130 is approximately 1*10 11 / cm 2 ~1*10 13 / cm 2 It can be, but is not limited to this.

[0065] The thickness of the semiconductor layer 130 in the z direction may be approximately 400 angstroms to 500 angstroms, but is not limited thereto.

[0066] A first insulating layer 140 may be located on the semiconductor layer 130. The first insulating layer 140 is also called a gate insulating layer.

[0067] A gate electrode 154 may be located on the first insulating layer 140. The gate electrode 154 may overlap the channel region 134 of the semiconductor layer 130 in the z-direction.

[0068] The gate electrode 154 may not overlap the conductive regions 133d, 135d in the z-direction. The gate electrode 154 may not overlap the edges 133, 135 in the z-direction.

[0069] The semiconductor layer 130 and the gate electrode 154 together may form a thin film transistor. According to an embodiment, a thin film transistor array substrate includes a plurality of such thin film transistors.

[0070] A second insulating layer 160 may be located on the gate electrode 154 .

[0071] At least one of the buffer layer 120, the first insulating layer 140 and the second insulating layer 160 may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and / or an organic insulating material such as polyimide, an acrylic-based polymer, or a siloxane-based polymer.

[0072] A first electrode 173 and a second electrode 175 may be located on the second insulating layer 160 .

[0073] The first electrode 173 can contact and be electrically connected to the upper surface of the first horizontal portion 133b of the first edge portion 133 of the thin film transistor through the opening 163 formed in the second insulating layer 160 and the first insulating layer 140.

[0074] The second electrode 175 can contact and be electrically connected to the upper surface of the second horizontal portion 135b of the second edge portion 135 of the thin film transistor through the opening 165 formed in the second insulating layer 160 and the first insulating layer 140.

[0075] At least one of the gate electrode 154, the first electrode 173, and the second electrode 175 may include at least one of metals such as copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof. Each of the gate electrode 154, the first electrode 173, and the second electrode 175 may be composed of a single layer or multiple layers.

[0076] According to the present embodiment, in the semiconductor layer 130 of the thin film transistor, the edges 133 and 135 doped with carbon are located like walls at the edges of the side and top surfaces except the channel region 134, so that impurities such as boron doped in the semiconductor layer 130 are prevented from diffusing to other layers outside the semiconductor layer 130 or other thin film transistors. The carbon doped in the edges 133 and 135 affects the remaining dangling bonds in the semiconductor layer 130, and can prevent the diffusion of impurities. This can prevent the problem of the impurity diffusion from increasing the variation in characteristics such as the on / off ratio, threshold voltage, and leakage current in a plurality of thin film transistors.

[0077] When a semiconductor device including a thin film transistor array substrate requires high resolution, high speed driving or variable frequency driving, a short channel thin film transistor with a shorter channel length (Wa) is required, as shown in Figure 2. For example, the channel length (Wa) and channel width (Wb) of the short channel thin film transistor may be about 1.5 micrometers to 2.0 micrometers, respectively.

[0078] Thus, as the channel length (Wa) of the thin film transistor becomes shorter, there is a risk that impurities such as boron doped in the semiconductor layer will diffuse to the outside of the semiconductor layer 130, causing a large variation in the characteristics of the thin film transistor, but according to this embodiment, it is possible to prevent and control the variation in the characteristics of the thin film transistor by blocking the diffusion of the impurities to the outside of the semiconductor layer 130. This makes it possible to easily realize high-speed driving and variable frequency driving of the semiconductor device, and also improve the characteristics of a high-resolution display device in which thin film transistors are densely arranged.

[0079] A method for manufacturing a thin film transistor array substrate according to one embodiment will be described with reference to FIGS. 3 to 6 together with the above-mentioned FIGS.

[0080] FIG. 3 is a cross-sectional view at one step of a method for manufacturing a thin film transistor array substrate according to one embodiment, FIG. 4 is a cross-sectional view at a step after the step shown in FIG. 3, FIG. 5 is a cross-sectional view at a step after the step shown in FIG. 4, and FIG. 6 is a cross-sectional view at a step after the step shown in FIG. 5, which are cross-sectional views of a thin film transistor array substrate according to one embodiment.

[0081] First, referring to FIG. 3, a buffer layer 120 is formed on a substrate 110 by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).

[0082] Then, a semiconductor material layer is deposited on the buffer layer 120, a mask pattern 50 is formed thereon, and the semiconductor material layer is etched or patterned using the mask pattern 50 as a mask, thereby forming the semiconductor layer 130.

[0083] When the semiconductor layer 130 includes polycrystalline silicon, an amorphous silicon layer may be formed by first depositing amorphous silicon (a-Si) on the buffer layer 120, and the amorphous silicon layer may be crystallized to form the polycrystalline silicon semiconductor layer 130. The crystallization method may include, but is not limited to, an annealing process using a heat source such as an excimer laser.

[0084] The mask pattern 50 may include photoresist.

[0085] 4, a portion of the side of the mask pattern 50 is removed. The method for removing the portion of the mask pattern 50 is to use oxygen gas (O 2 ) may be used. At this time, a portion of the upper part of the mask pattern 50 may also be removed, and the thickness of the mask pattern 50 in the z direction may be reduced. That is, the mask pattern 50 may be entirely etched, and the widths in the x, y, and z directions may be reduced.

[0086] As a result, as shown in FIG. 4, the edge portion of the semiconductor layer 130 is not covered by the mask pattern 50 and is exposed.

[0087] Next, a first carbon injection is performed from above the substrate 110 (carbon is injected first). As a result, the edge of the semiconductor layer 130 that is exposed and not covered by the mask pattern 50 is doped with carbon, forming the first vertical portion 133a and the second vertical portion 135a described above. The portion of the semiconductor layer 130 that overlaps with the mask pattern 50 may be hardly doped with carbon because the mask pattern 50 acts as a mask to block the carbon.

[0088] During carbon doping, the carbon acceleration voltage may be about 10 keV to 40 keV, but is not limited thereto.

[0089] 5, the mask pattern 50 is removed and the entire semiconductor layer 130 exposed is doped with impurities such as boron from above. Thus, the entire semiconductor layer 130 including the first vertical portion 133a and the second vertical portion 135a is doped with the impurities such as boron. At this time, when doping the impurities such as boron, the acceleration voltage of boron may be about 1 keV to 10 keV, but is not limited thereto.

[0090] 6, an insulating material is deposited on the semiconductor layer 130 to form a first insulating layer 140, and a conductive material such as a metal is deposited thereon and patterned to form a gate electrode 154. The gate electrode 154 overlaps a region of the semiconductor layer 130 that will become a channel region, but does not overlap a portion of the periphery of the semiconductor layer 130.

[0091] Then, impurities such as boron are implanted from above the substrate 110 using the gate electrode 154 as a mask, forming conductive regions 133d and 135d on both sides of the channel region 134.

[0092] Next, a second carbon implantation is performed from above the substrate 110 using the gate electrode 154 as a mask (secondary carbon implantation). Then, the carbon doping is blocked in the region of the semiconductor layer 130 overlapping with the gate electrode 154, and carbon is doped into the upper surface of the edge portion of the semiconductor layer 130 that does not overlap with the gate electrode 154 in the z direction, thereby forming the first horizontal portion 133b and the second horizontal portion 135b described above.

[0093] The depth of the second carbon doping may be smaller than the depth of the first carbon doping. That is, the thickness in the z direction of the first horizontal portion 133b and the second horizontal portion 135b is smaller than the length in the z direction of the first vertical portion 133a and the second vertical portion 135a. This allows the concentration or time of the second carbon doping to be smaller than the concentration or time of the first carbon doping.

[0094] Depending on the amount of doping of the second carbon, a part of the upper portion of the semiconductor layer 130 may be formed into the first horizontal portion 133b and the second horizontal portion 135b. In addition, a part of the lower portion of the first insulating layer 140 in contact with the upper surfaces of the first horizontal portion 133b and the second horizontal portion 135b may be doped with carbon to form the first additional horizontal portion 133c and the second additional horizontal portion 135c as shown in FIG. 6. The first additional horizontal portion 133c may be in contact with the first horizontal portion 133b and may be formed continuously with the first horizontal portion 133b in the z direction, and the second additional horizontal portion 135c may be in contact with the second horizontal portion 135b and may be formed continuously with the second horizontal portion 135b in the z direction. The first additional horizontal portion 133c and the second additional horizontal portion 135c may not overlap the gate electrode 154 in the z direction.

[0095] The first additional horizontal portion 133c and the second additional horizontal portion 135c may be insulating as parts included in the first insulating layer 140.

[0096] However, the amount of the secondary carbon doping may be adjusted so that the first additional horizontal portion 133c and the second additional horizontal portion 135c are not formed, in which case only the edge portions 133 and 135 may be formed in the carbon-doped semiconductor layer 130 as shown in FIG.

[0097] In this way, the thin film transistor array substrate according to the embodiment can be completed.

[0098] 1, an insulating material is deposited on the gate electrode 154 to form the second insulating layer 160. The first insulating layer 140 and the second insulating layer 160 are then patterned to form openings 163 and 165. A conductive material such as a metal is then deposited on the second insulating layer 160 and patterned to form the first electrode 173 and the second electrode 175.

[0099] With reference to the above-mentioned drawings, particularly with reference to FIGS. 3 to 5 as well as FIGS. 7 to 9, a method for manufacturing a thin film transistor array substrate according to an embodiment will be described.

[0100] FIG. 7 is a cross-sectional view of a step after the process shown in FIG. 5 as one process of a method for manufacturing a thin film transistor array substrate according to one embodiment, FIG. 8 is a cross-sectional view of a step after the process shown in FIG. 7, and FIG. 9 is a cross-sectional view of a step after the process shown in FIG. 8, both of which are cross-sectional views of a thin film transistor array substrate according to one embodiment.

[0101] The manufacturing method of the thin film transistor array substrate according to this embodiment is almost the same as the manufacturing method according to the embodiment shown in FIGS. 3 to 6 described above, but there are cases where the steps after the process step shown in FIG. 5 are different.

[0102] As described above, according to the embodiment shown in FIGS. 3 to 5, the entire semiconductor layer 130 including the first vertical portion 133a and the second vertical portion 135a is doped with impurities such as boron, and then an insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON) or the like is laminated on the semiconductor layer 130 to form the protective layer 180 as shown in FIG. 7.

[0103] The thickness of the protective layer 180 in the z direction may be, but is not limited to, approximately 200 angstroms to 1000 angstroms.

[0104] Then, a mask pattern 60 is formed on the protective layer 180. The mask pattern 60 overlaps a region that will become a channel region in the semiconductor layer 130, but does not overlap a portion of the periphery of the semiconductor layer 130.

[0105] The mask pattern 60 may include, but is not limited to, metals, organic materials such as photoresist, and the like.

[0106] Then, impurities such as boron are implanted from above the substrate 110 using the mask pattern 60 as a mask to form conductive regions 133d and 135d on both sides of the channel region 134.

[0107] Next, using the mask pattern 60 as a mask, a second carbon doping is performed from above the substrate 110 (carbon is doped for the second time) (the first carbon doping is the same as in FIG. 4). This second carbon doping can be performed under the same conditions as the second carbon doping described above. Then, carbon doping is blocked in the area of ​​the semiconductor layer 130 overlapping with the mask pattern 60, and the upper surface of the edge part of the semiconductor layer 130 that does not overlap with the mask pattern 60 in the z direction is doped, forming the first horizontal portion 133b and the second horizontal portion 135b described above.

[0108] Here, the depth of the secondary carbon doping can be controlled by adjusting the thickness in the z direction of the protective layer 180. In addition, the protective layer 180 can reduce damage to the upper part of the semiconductor layer 130 during the secondary carbon doping.

[0109] Depending on the amount of doping of the second carbon, a part of the upper portion of the semiconductor layer 130 may be formed into the first horizontal portion 133b and the second horizontal portion 135b, and in addition, a part of the lower portion of the protective layer 180 in contact with the upper surfaces of the first horizontal portion 133b and the second horizontal portion 135b may also be doped with carbon to form the first additional horizontal portion 133c and the second additional horizontal portion 135c as shown in FIG. 7. The first additional horizontal portion 133c may be in contact with the first horizontal portion 133b and may be continuously formed in the z direction, and the second additional horizontal portion 135c may be in contact with the second horizontal portion 135b and may be continuously formed in the z direction. The first additional horizontal portion 133c and the second additional horizontal portion 135c may not overlap the mask pattern 60 in the z direction.

[0110] 8, the mask pattern 60 and the protective layer 180 are removed using an etching process, etc. Then, the first additional horizontal portion 133c and the second additional horizontal portion 135c may also be removed, thereby forming the edges 133 and 135 as shown in FIG.

[0111] Referring now to FIG. 9, an insulating material is deposited on the semiconductor layer 130 to form a first insulating layer 140, and a conductive material such as a metal is deposited thereon and patterned to form a gate electrode 154.

[0112] In this way, the thin film transistor array substrate according to the embodiment can be completed.

[0113] 1, an insulating material is deposited on the gate electrode 154 to form the second insulating layer 160. The first insulating layer 140 and the second insulating layer 160 are then patterned to form openings 163 and 165. A conductive material such as a metal is then deposited on the second insulating layer 160 and patterned to form the first electrode 173 and the second electrode 175.

[0114] A method for manufacturing a thin film transistor array substrate according to an embodiment will be described with reference to FIGS. 10 to 14 as well as FIGS. 3 to 6 described above.

[0115] 10 is a cross-sectional view at a step in a manufacturing method for a thin film transistor array substrate according to one embodiment, FIG. 11 is a cross-sectional view at a step after the step shown in FIG. 10, FIG. 12 is a cross-sectional view at a step after the step shown in FIG. 11, FIG. 13 is a cross-sectional view at a step after the step shown in FIG. 12, FIG. 14 is a cross-sectional view at a step after the step shown in FIG. 13, a cross-sectional view of a thin film transistor array substrate according to one embodiment, and FIG. 15 is a cross-sectional view at a step after the step shown in FIG. 13 as a step in a manufacturing method for a thin film transistor array substrate according to one embodiment, a cross-sectional view of a thin film transistor array substrate according to one embodiment.

[0116] First, referring to FIG. 10, a buffer layer 120 is formed on a substrate 110 by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).

[0117] Then, a semiconductor material layer such as amorphous silicon (a-Si) is deposited on the buffer layer 120 to form a semiconductor layer 130a.

[0118] 11, carbon is injected from below the substrate 110 to primarily dope at least a portion of the lower portion of the semiconductor layer 130a with carbon, thereby forming a doped layer 131a in the lower portion of the semiconductor layer 130a. Only a portion of the lower portion of the semiconductor layer 130a may become the doped layer 131a, or, unlike that shown in FIG. 11, the entire semiconductor layer 130a may be doped with carbon to become the doped layer 131a.

[0119] 12, an additional semiconductor layer 130b is formed by stacking the same semiconductor material, such as amorphous silicon, on the upper portion of the semiconductor layer 130a. There may be no substantial boundary between the semiconductor layer 130a and the additional semiconductor layer 130b, and the semiconductor layer 130a and the additional semiconductor layer 130b may together form substantially one semiconductor layer (i.e., referred to as a combined semiconductor layer).

[0120] The semiconductor layer 130a, the additional semiconductor layer 130b, and the doping layer 131a are then crystallized to form a polycrystalline silicon semiconductor layer. The crystallization method may include, but is not limited to, an annealing process using a heat source such as an excimer laser.

[0121] Next, referring to FIG. 13, similar to that described above with respect to FIG. 3, a mask pattern is formed on the semiconductor layer crystallized in FIG. 12, and then the semiconductor layer 130a, the additional semiconductor layer 130b, and the doping layer 131a are etched to form a semiconductor layer 130 including a patterned semiconductor layer 130a, the additional semiconductor layer 130b, and a bottom portion 131 as shown in FIG. 13.

[0122] The subsequent processes may be the same as the processes according to the embodiment shown and described in Figures 4 to 6 or the processes according to the embodiment shown and described in Figures 7 to 9. Such subsequent processes may include at least two carbon doping processes for the edge and upper regions of the semiconductor layer 130, as described above.

[0123] Through this process, a first additional horizontal portion 133c and a second additional horizontal portion 135c may be formed on the bottom of the first insulating layer 140 as shown in Figures 6 and 14 described above, or a thin film transistor and a thin film transistor array substrate may be completed in which the first additional horizontal portion 133c and the second additional horizontal portion 135c are not formed as shown in Figures 9 and 15.

[0124] The thin film transistor included in the thin film transistor array substrate according to the embodiment shown in Fig. 14 has almost the same structure as the thin film transistor according to the embodiment shown in Fig. 6, but the semiconductor layer 130 is located at the interface with the buffer layer 120 and further includes a bottom portion 131 doped with carbon. The bottom portion 131 is also called an intermediate region.

[0125] The concentration of carbon doped into the bottom portion 131 is higher than the concentration of carbon in the channel region 134 and the conductive regions 133d, 135d of the semiconductor layer 130. In some embodiments, the channel region 134 and the conductive regions 133d, 135d may be substantially free of carbon doping, and only the edges 133, 135 and the bottom portion 131 may be doped with carbon.

[0126] The bottom portion 131 may be formed to a certain thickness from the lowermost surface of the semiconductor layer 130 and may contact the entire lower surfaces of the channel region 134 and the first and second vertical portions 133a and 135a of the edge portion 133 of the semiconductor layer 130. That is, the bottom portion 131 may be formed over the entire bottom surface of the semiconductor layer 130 to which it belongs.

[0127] The thin film transistor included in the thin film transistor array substrate according to the embodiment shown in FIG. 15 has a structure almost the same as that of the thin film transistor according to the embodiment shown in FIG. 1 or FIG. 9 described above, but the semiconductor layer 130 is located at the interface with the buffer layer 120 and further includes a carbon-doped bottom portion 131.

[0128] The features of the base 131 shown in FIG. 15 may be the same as those described above for the base 131 shown in FIG.

[0129] 14 and 15, the carbon-doped bottom portion 131 and edges 133, 135 together enclose the bottom and side surfaces of the semiconductor layer 130, and the entire top surface of the semiconductor layer 130, except for the top surface of the channel region 134, like a bowl. This effectively blocks impurities such as boron in the semiconductor layer 130 from undesirably diffusing into other layers outside the semiconductor layer 130 or into other thin film transistors.

[0130] 16 and 17 as well as FIGS. 1 to 6 described above, a thin film transistor and a thin film transistor array substrate, and a method for manufacturing the thin film transistor array substrate according to an embodiment will be described.

[0131] FIG. 16 is a plan view of a thin film transistor according to an embodiment, and FIG. 17 is a cross-sectional view of a process in a method for manufacturing a thin film transistor array substrate according to an embodiment.

[0132] 16, the thin film transistor and the thin film transistor array substrate including the same according to this embodiment are substantially the same as the embodiment shown in FIGS. 1 and 2, but the semiconductor layer 130 may further include a lateral edge 136 located at an edge of the channel region 134 where the first and second conductive regions 133d, 135d are not adjacent. For example, as shown in FIG. 16, when the first and second conductive regions 133d, 135d are located on both sides of the channel region 134 in the y direction, the lateral edges 136 may be located at edges extending in the y direction and facing each other in the x direction with respect to the center of the channel region 134.

[0133] The lateral edge 136 may have a higher concentration of doped carbon compared to the channel region 134. The concentration of doped carbon at the lateral edge 136 may be lower than the concentration of doped carbon at the edges 133, 135. The carrier concentration at the lateral edge 136 may be lower than the carrier concentration of the conductive regions 133d, 135d.

[0134] The gate electrode 154 located above the lateral edge 136 may overlap the lateral edge 136 in the z-direction.

[0135] The manufacturing method of the thin film transistor array substrate including the thin film transistor according to the embodiment shown in FIG. 16 is almost the same as the manufacturing method according to the embodiment shown in FIG. 3 to FIG. 6 described above, but when removing a part of the side of the mask pattern 50 in the process shown in FIG. 4, the edge portions of the side surfaces of the semiconductor layer 130 on all four sides (four directions) may be exposed without being covered by the mask pattern 50. That is, not only the edge portions of both sides of the periphery of the semiconductor layer 130 facing in the y direction as shown in FIG. 4, but also the edge portions of both sides of the semiconductor layer 130 facing in the x direction as shown in FIG. 17 may be exposed without being covered by the mask pattern 50. Here, the edge portions of the side surfaces of the semiconductor layer 130 on all four sides (four directions) exposed without being covered by the mask pattern 50 may form a closed figure such as a rectangle.

[0136] Subsequently, when a first carbon injection is performed from above the substrate 110 (carbon is injected primarily), the exposed edge of the semiconductor layer 130 is doped with carbon, and not only the first vertical portion 133a and the second vertical portion 135a shown in Fig. 4 but also the lateral edge portion 136 shown in Fig. 17 can be formed. The first vertical portion 133a, the second vertical portion 135 and the pair of lateral edge portions 136 can be connected to each other to have a planar shape forming a closed figure.

[0137] The subsequent steps may be the same as those shown in FIGS.

[0138] Depending on the embodiment, the first horizontal portion 133b and the second horizontal portion 135b may be omitted in the various embodiments described above. In this case, the second carbon doping process for forming the first horizontal portion 133b and the second horizontal portion 135b may be omitted in the manufacturing method of the thin film transistor array substrate.

[0139] FIG. 18 is a schematic plan view of a display device according to an embodiment.

[0140] 18, a display device as a semiconductor device according to an embodiment may include a display area (DA) including a plurality of pixels (PX) that are units for displaying an image, and a peripheral area (PA) surrounding the display area (DA). A driving circuit (DR) for driving the pixels (PX) may be located in the peripheral area (PA).

[0141] A display device according to an embodiment can include the thin film transistor array substrate described in this description. The pixel (PX) and the driving circuit (DR) can include a plurality of thin film transistors as in this embodiment.

[0142] When a display device requires high resolution, high speed driving or variable frequency driving, a short channel thin film transistor with a shorter channel length may be required, but according to the present embodiment, impurities doped in a semiconductor layer such as boron are prevented from diffusing into other layers or other thin film transistors. Therefore, in a high resolution display device, the variation in characteristics of a plurality of thin film transistors can be improved, and display characteristics can be improved, and high speed driving and variable frequency driving can be easily realized.

[0143] Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims also belong to the scope of the present invention. [Industrial Applicability]

[0144] The present invention relates to a thin film transistor array substrate and a manufacturing method thereof.

Claims

1. substrate, a semiconductor layer on the substrate; and a gate electrode on the semiconductor layer; The semiconductor layer is a channel region, a conductive region directly connected to one end of the channel region, and an edge; the edge is located at an edge of the conductive region; A transistor substrate, wherein the edge portion has a higher carbon concentration than each of the channel region and the conductive region.

2. the edge portion includes a first member in contact with a first side of the conductive region; The transistor substrate of claim 1 , wherein the conductive region is located between the first member and the channel region.

3. the edge further includes a second member in contact with a second side of the conductive region; The transistor substrate of claim 2 , wherein the conductive region is located between the second member and the substrate.

4. The transistor substrate according to claim 3 , wherein the first member and the second member are directly connected to each other.

5. The transistor substrate of claim 4 , wherein the second member contacts the channel region.

6. a first dimension of the second member in a direction perpendicular to the substrate is smaller than a first dimension of the first member in the direction perpendicular to the substrate; The transistor substrate of claim 3 , wherein a second dimension of the second member in a direction parallel to the substrate is greater than a second dimension of the first member in the direction parallel to the substrate.

7. an insulating layer located on the gate electrode and having an opening; and an electrode located partially on the insulating layer and partially within the opening; The transistor substrate of claim 3 , wherein the electrode contacts the second member at the edge.

8. further comprising an insulating layer located between the semiconductor layer and the gate electrode; The transistor substrate according to claim 3 , wherein the insulating layer includes a portion that is doped with carbon and that is in contact with the second member.

9. the semiconductor layer further includes an intermediate region located between the channel region and the substrate; The transistor substrate of claim 1 , wherein the carbon concentration of the intermediate region is higher than a carbon concentration of the channel region and a carbon concentration of the conductive region.

10. the channel region, the edge region, and the intermediate region together encase the conductive region; The transistor substrate according to claim 9 , wherein the intermediate region contacts an entire surface of the channel region.

11. The transistor substrate of claim 1 , wherein the edge is electrically conductive.

12. The transistor substrate of claim 1 , wherein the semiconductor layer comprises polycrystalline silicon.

13. forming a semiconductor layer on a substrate; forming a first mask pattern on the semiconductor layer to expose an edge of the semiconductor layer; performing a first carbon doping on the semiconductor layer partially covered by the first mask pattern; removing the first mask pattern and doping the exposed semiconductor layer with impurities; and A method for manufacturing a transistor substrate, comprising the step of forming a first insulating layer on the semiconductor layer.

14. forming a second mask pattern on the first insulating layer; and The method of claim 13, further comprising the step of performing a second carbon doping on the semiconductor layer partially covered by the second mask pattern.

15. removing the first insulating layer; forming a second insulating layer on the semiconductor layer; and The method for manufacturing a transistor substrate according to claim 14 , further comprising forming a gate electrode on the second insulating layer.

16. forming a gate electrode on the first insulating layer; and The method of claim 13, further comprising the step of performing a second carbon doping on the semiconductor layer partially covered by the gate electrode.

17. forming a second insulating layer on the gate electrode; and forming an opening in the second insulating layer and the first insulating layer; The method for manufacturing a transistor substrate according to claim 16 , further comprising the step of forming an electrode that connects to the semiconductor layer through the opening.

18. The method for manufacturing a transistor substrate according to claim 13, further comprising the step of implanting carbon into the semiconductor layer through the substrate to form a portion containing carbon in the semiconductor layer.

19. forming a first semiconductor layer by depositing amorphous silicon on a substrate; performing a first carbon implantation into the first semiconductor layer through the substrate to form a carbon-containing portion in the first semiconductor layer; forming a second semiconductor layer including amorphous silicon on the first semiconductor layer including the portion including the carbon; forming a first mask pattern on a combined semiconductor layer including the first semiconductor layer and the second semiconductor layer; performing a second carbon doping on the bonded semiconductor layer partially covered by the first mask pattern; removing the first mask pattern and doping the combined semiconductor layer with an impurity; and A method for manufacturing a transistor substrate, comprising forming a first insulating layer on the bonded semiconductor layer.

20. forming a second mask pattern on the first insulating layer; and 20. The method of claim 19, further comprising the step of performing a third carbon doping on the bonded semiconductor layer partially covered by the second mask pattern.

21. Channel area, a first region contacting one end of the channel region and doped with a first material; a second region doped with a second material different from the first material; The second region overlaps the first region and contacts the one end of the channel region.

22. 22. The transistor substrate of claim 21, wherein the first material comprises boron.

23. The transistor substrate of claim 22 , wherein the second material comprises carbon.

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