CMOS SRAM cell with trench structure.

Abstract

The present invention relates to a CMOS SRAM cell having a trench structure, and more particularly, to a CMOS SRAM cell having a trench structure vertical MOSFET with a gate, source and drain having a vertical structure, and current flow occurs in an active region between a trench gate electrode and vertical source and drain regions, thereby providing various advantages in density, operating frequency, noise margin, current handling capacity, power dissipation, and manufacturing process compared to an existing CMOS SRAM cell having a planar structure.

Description

[Technical field]

[0001] The present invention relates to a CMOS SRAM cell having a trench structure, and more particularly, to a CMOS SRAM cell having a trench structure vertical MOSFET with a gate, source and drain having a vertical structure, and current flow occurs in an active region between a trench gate electrode and vertical source and drain regions, thereby providing various advantages in density, operating frequency, noise margin, current handling capacity, power dissipation, and manufacturing process compared to an existing CMOS SRAM cell having a planar structure. [Background technology]

[0002] The SRAM cell structure is composed of two inverters and two pass gates, and the outputs of these inverters are cross-coupled to each other to form a flip-flop structure.

[0003] To store information, an SRAM cell requires four transistors that form two inverters, and two transistors that select a specific cell from the outside.

[0004] Such SRAM cells are different from DRAM cells (Dynamic Random Access Memory cells) in that as long as power is applied, they can store static data without a refresh operation due to the feedback effect of the flip-flops, hence they are called static RAM.

[0005] Such SRAM unit cells are roughly classified into two types. One is a high load resistor SRAM cell that uses a high resistor as a load device, and the other is a CMOS SRAM cell that uses a PMOS transistor as a load device.

[0006] The CMOS SRAM cells are further broadly classified into two types. One is a thin film transistor SRAM cell that uses a thin film transistor (TFT) stacked on a semiconductor substrate as a load element, and the other is a bulk CMOS SRAM cell that uses a bulk transistor formed on a semiconductor substrate as a load element.

[0007] The bulk SRAM cell exhibits high cell stability compared to the thin film transistor SRAM cell and the high resistance SRAM cell, i.e., good low voltage characteristics and low stand-by current.

[0008] This is because the thin film transistors are generally fabricated using a polysilicon film as a body layer, whereas all the transistors constituting the bulk CMOS SRAM cell are formed on a single crystal silicon substrate.

[0009] However, the bulk CMOS SRAM cells exhibit low integration density compared to thin film transistor SRAM cells.

[0010] Although the thin film transistor SRAM cell exhibits a higher density than the bulk CMOS SRAM cell, the density of the thin film transistor SRAM cell is still lower than that of the DRAM cell.

[0011] Therefore, in order to realize a highly integrated SRAM device with high reliability, it is required to design a compact cell having a three-dimensional structure.

[0012] Korean Patent Publication No. 10-0530305 discloses an SRAM cell structure using a vertical MOSFET. Although such a conventional SRAM cell structure allows the formation of a multi-gate FET, the pull-down transistor or pull-up transistor constituting the SRAM cell is merely arranged using the multi-gate FET, so that there is a drawback in that there is a limit to improving the integration level. Summary of the Invention [Problem to be solved by the invention]

[0013] The present invention has been made to solve the above-mentioned problems of the prior art, and its object is to provide a CMOS SRAM cell having a trench structure, which has various advantages in density, operating frequency, noise margin, current handling capacity, power dissipation, and manufacturing process, compared with a CMOS SRAM cell having a planar structure, by manufacturing a CMOS SRAM cell using a vertical MOSFET having a trench structure with a gate, source, and drain having a vertical structure, and allowing current to flow in an active region between the trench gate electrode and the vertical source and drain regions. [Means for solving the problem]

[0014] In order to achieve the above object, the present invention provides a CMOS SRAM cell comprising: a semiconductor substrate having a first polarity; a plurality of diffusion regions having a second polarity opposite to that of the semiconductor substrate and a first polarity equal to that of the semiconductor substrate, the diffusion regions being formed at a distance from a surface of the semiconductor substrate in a vertical structure having a constant cross section and a constant depth; a plurality of electrodes formed in upper layers of the diffusion regions and functioning as source electrodes, drain electrodes or substrate electrodes of MOSFETs by applying respective signal voltages; a plurality of trenches formed at a distance from the surface of the semiconductor substrate in a constant cross section and a constant depth; an insulating layer formed on a surface of each trench from the surface of the semiconductor substrate; a conductive material filled in the inner trench of the insulating layer; and a MOSFET formed in an upper portion of the trench filled with the conductive material, the MOSFET having a gate electrode to which each signal voltage is applied.

[0015] In addition, the present invention provides a semiconductor device for manufacturing a complementary MOSFET complementary to a MOSFET having one polarity, the device comprising: a well region of a second polarity formed in a semiconductor substrate of a first polarity; a number of diffusion regions formed at intervals from a surface of the well region in a vertical structure having a certain cross section and a certain depth, the diffusion regions having a first polarity opposite to that of the well region and a second polarity equal to that of the well region; a number of electrodes formed in upper layers of the diffusion regions and operating as source electrodes, drain electrodes or well region electrodes of the complementary MOSFET by applying respective signal voltages; a number of trenches formed at intervals from the surface of the well region in a certain cross section and a certain depth; an insulating layer formed from the surface of the well region on a surface of each trench; a conductive material filled in the inner trench of the insulating layer; and a MOSFET having gate electrodes of the complementary MOSFET formed on an upper portion of the trench filled with the conductive material, the gate electrodes being applied with respective signal voltages.

[0016] In this case, the plurality of diffusion regions or the trench gate electrodes of the MOSFETs having the first or second polarity are connected to each other by a conductive material. Effect of the Invention

[0017] According to the present invention, the current flow occurs in a vertical channel formed by the trench gate electrode and the source and drain of the vertical structure, and by utilizing the vertical volume of silicon, it is possible to increase the current processing capacity without consuming surface area, and also to improve the speed and integration density.

[0018] In addition, according to the present invention, multiple gate electrodes can be used through the trench structure, and by adjusting the vertical size and spacing of the gate electrodes and the vertical source and drain diffusion regions, the current and charge handling capacity can be significantly increased, thereby enabling the fabrication of smaller, more highly integrated and faster SRAM cells.

[0019] In addition, according to the present invention, signal processing is easier than with conventional planar structure SRAM cells, and leakage current can be reduced by avoiding short channel effects, thereby not only reducing standby power consumption but also improving operating speed due to improved noise margin. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a plan view showing a CMOS SRMA cell having a trench structure according to the present invention. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA of the present invention shown in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line BB of the present invention shown in FIG. [Figure 4] 2 is a cross-sectional view taken along line CC of FIG. 1. [Diagram 5] 1 is a circuit diagram of a CMOS SRMA cell having a trench structure according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a CMOS SRAM cell having a trench structure according to the present invention will be described in detail with reference to the accompanying drawings.

[0022] FIG. 1 is a plan view showing a CMOS SRAM cell having a trench structure according to the present invention, FIG. 2 is a cross-sectional view taken along line AA of the present invention shown in FIG. 1, FIG. 3 is a cross-sectional view taken along line BB of the present invention shown in FIG. 1, FIG. 4 is a cross-sectional view taken along line CC of the present invention shown in FIG. 1, and FIG. 5 is a circuit diagram of a CMOS SRAM cell having a trench structure according to the present invention.

[0023] The present invention relates to a CMOS SRAM cell 100 (hereinafter, referred to as "SRAM cell 100") having a trench structure, which has various advantages in density, operating frequency, noise margin, current handling capacity, power dissipation, and manufacturing process, as compared with a conventional CMOS SRAM cell having a planar structure, by manufacturing a CMOS SRAM cell using a vertical MOSFET having a trench structure with a gate, source, and drain having a vertical structure, and by making a current flow occur in an active region between a trench gate electrode 99 and a vertical source and drain region. As shown in FIG. 1, the SRAM cell 100 includes a semiconductor substrate 10 having either N-type or P-type polarity (hereinafter, referred to as "first polarity"), a well region 20 formed in the semiconductor substrate 10 and having a polarity different from that of the semiconductor substrate 10 (hereinafter, referred to as "second polarity"), and a 6-transistor SRAM cell 100 made of a vertical MOSFET having a trench structure including a number of trench gates 99, sources, and drains.

[0024] That is, the SRAM cell 100 according to the present invention may include a semiconductor substrate 10 of a first polarity, and a number of diffusion regions and trench electrodes 99 formed in the semiconductor substrate 10, and the diffusion regions may be formed in a vertical structure having a certain depth and a certain cross section from the surface of the semiconductor substrate 10. Hereinafter, a description will be given on the basis that the first polarity is N-type, i.e., an N-type semiconductor substrate 10.

[0025] In this case, the diffusion regions may be formed to have a second polarity, i.e., P type, opposite to the N type semiconductor substrate 10, or the same first polarity, i.e., N type, spaced apart from each other by a certain distance, and have an impurity concentration of 10 17 ~10 20 cm -3 and can be relatively highly doped.

[0026] A number of trenches 99 having a certain cross section and a certain depth are formed at a certain distance apart in a semiconductor substrate 10 of a first polarity, i.e., an N-type semiconductor substrate 10, and a well region 20 of a second polarity, i.e., a P-type well region 20. Diffusion regions of the first polarity or second polarity are formed in the semiconductor substrate 10 and the well region 20. A number of electrodes for applying each signal voltage to the source electrode or drain electrode of the MOSFET are formed in the upper layer of the diffusion region.

[0027] An insulating layer 98 such as an oxide film having a thickness of about 1 μm or less may be formed on the inner surface of each trench 99 formed in the semiconductor substrate 10, and the inner trench 99 of the insulating layer 98 is filled with a conductive material such as polysilicon, and a number of electrodes are formed thereon to act as gate electrodes of MOSFETs and apply each signal voltage.

[0028] The P-type well region 20 is for making a complementary MOSFET that is complementary to the MOSFET formed in the semiconductor substrate 10, and is formed to have a second polarity. In the P-type well region 20 having the second polarity, source and drain diffusion regions having a first polarity are formed, so that a MOSFET having the opposite polarity to the MOSFET formed in the semiconductor substrate 10 can be formed.

[0029] At this time, as shown in FIG. 1, a first polarity for applying a constant voltage, i.e., an N-type diffusion region 102, is formed in the N-type semiconductor substrate 10, and a second polarity for applying a constant voltage, i.e., a P-type diffusion region 101, is formed in the P-type well region 20.

[0030] More specifically, the SRAM cell 100 includes two N-type pass-gate transistors 91 and 94, two back-to-back CMOS inverters, and a contact region 97 that connects a diffusion region and a polysilicon region with a conductive material such as metal.

[0031] As shown in FIG. 5, there are provided a bit line 88 and an inverting bit line 89 which act as a path for data to move between the outside and the SRAM cell 100 and supply a voltage to the drain terminal, and a word line 90 which acts as a switch between the bit line 88 and the SRAM cell 100 and supplies a voltage to the gate terminal, whereby the bit line 88 and the inverting bit line 89 are connected to an inverter in the SRAM cell 100 via the pass gate transistors 91 and 94 by the word line 90.

[0032] In addition, the output of a left inverter, i.e., one side inverter, including an N-type pull-down transistor 92 and a P-type pull-up transistor 93 is connected to the input of a right inverter, i.e., the other side inverter, including an N-type pull-down transistor 95 and a P-type pull-up transistor 96.

[0033] More specifically, as shown in FIG. 2, an N-type pass gate transistor 91 and an N-type pull-down transistor 95 may be formed in a trench gate 99 structure in a P-type well region 20 of a second polarity formed in the semiconductor substrate 10, and a P-type pull-up transistor 96 may be formed in a trench gate 99 structure in the semiconductor substrate 10 of a first polarity.

[0034] At this time, the width W of each of the transistors 91, 95, 96 is proportional to the depths Wn and Wp of the n+ and p+ diffusion regions, as shown in FIGS.

[0035] Also, as shown in Figures 1, 3 and 4, an n+ diffusion region of a first polarity or a p+ diffusion region of a second polarity is formed in the N-type semiconductor substrate 10, and an n+ diffusion region of a first polarity or a p+ diffusion region of a second polarity is similarly formed in the P-type well region 20.

[0036] A contact region 97 for connection to a conductive material is formed on the diffusion region and the polysilicon.

[0037] As shown in FIG. 4, a p+ diffusion region having a depth Wp is formed in the N-type semiconductor substrate 10, and a P-type pull-up transistor 93 having a channel length Lp is formed in a trench gate 99 structure between the p+ diffusion regions.

[0038] In other words, the SRAM cell 100 of the present invention can realize an SRAM cell 100 structure having a larger ratio of channel width W to channel length L than that of a planar structure SRAM cell by replacing the planar polysilicon gate of an existing planar structure SRAM cell with a trench structure gate 99.

[0039] Also, as can be seen from FIGS. 3 and 4, the channel width W and channel length L of an N-channel MOSFET and a P-channel MOSFET are defined as the depth of the source and drain diffusion regions and the distance between the source and drain diffusion regions, respectively. For gate electrodes having the same trench depth, the channel widths of P-type and N-type transistors are determined by the depths of the p+ and n+ diffusion regions, Wp and Wn.

[0040] The channel width W of the six transistors 91, 92, 93, 94, 95, 96 can be optimized by adjusting the gate electrode 99 and the diffusion depths Wp, Wn, thereby enabling high frequency and high performance devices to be realized.

[0041] As can be seen from FIG. 1, all of the transistors 91, 92, 93, 94, 95, and 96 have gate electrodes 99 of minimum size, which not only minimizes the surface area of ​​the entire SRAM cell 100, but also makes it easier to fabricate trench gate electrodes 99 and diffusion regions with a large aspect ratio of surface area to depth.

[0042] The channel width W of the P-type pull-up transistor 93 is equal to twice the depth Wp of the diffusion region plus the spacing Lp of the gate electrodes, which is similar to the structure of a Tri-Gate Bulk FinFET.

[0043] As described above, the six transistors 91, 92, 93, 94, 95, and 96 having an increased channel width W to channel length L ratio, i.e., aspect ratio, of the surface area to depth, can exhibit increased noise margin and increased operation speed, as well as reduced standby power consumption.

[0044] In other words, by effectively controlling the short channel effects in the channel formed between the two gate electrodes, the leakage current in the channel can be reduced, thereby reducing standby power dissipation.

[0045] In addition, transistors 91, 92, 93, 94, 95, and 96 having a minimum size gate electrode and an increased aspect ratio of surface area to depth not only enable a high-performance, compact SRAM cell 100 to be fabricated without significantly increasing the masking steps, but also allow the channel including a pair of trench gate electrodes to have a greater alignment tolerance than existing planar structure cells.

[0046] The above-mentioned embodiment has been described as the most preferred example of the present invention, however, the present invention is not limited to the above embodiment. Various modifications are possible without departing from the technical concept of the present invention, such as applying the SRAM cell 100 of the present invention to application processors, CPUs and GPUs (Graphic Processing Units) that require high integration, high frequency operation and low power consumption, or applying the trench structure of the present invention to various existing planar structure elements such as CMOS digital and analog devices, image sensors, signal processing devices, memory devices and power devices. [Industrial Applicability]

[0047] The present invention relates to a CMOS SRAM cell having a trench structure, and more particularly, to a CMOS SRAM cell having a trench structure vertical MOSFET with a gate, source and drain having a vertical structure, and current flow occurs in an active region between a trench gate electrode and vertical source and drain regions, thereby providing various advantages in density, operating frequency, noise margin, current handling capacity, power dissipation, and manufacturing process compared to an existing CMOS SRAM cell having a planar structure.

Claims

1. In a CMOS SRAM cell, a first polarity semiconductor substrate having one polarity; a plurality of diffusion regions spaced apart from a surface of the semiconductor substrate in a vertical configuration having a cross section and a depth, the diffusion regions having a second polarity opposite to the semiconductor substrate and a first polarity equal to the semiconductor substrate; a number of electrodes formed in an upper layer of the diffusion region, the electrodes operating as source electrodes, drain electrodes or substrate electrodes of a MOSFET when a signal voltage is applied thereto; a plurality of trenches formed at a surface of the semiconductor substrate and spaced apart from one another with a constant cross section and a constant depth; an insulating layer formed on a surface of the semiconductor substrate and on a surface of each trench; a conductive material filling the inner trench of the insulating layer; a MOSFET formed in an upper portion of the trench filled with the conductive material, the MOSFET having a gate electrode to which each signal voltage is applied, the MOSFET having a gate electrode formed in an upper portion of the trench filled with the conductive material, the MOSFET having a gate electrode to which each signal voltage is applied,

2. To make a complementary MOSFET that is complementary to the MOSFET having one polarity as claimed in claim 1, a well region of a second polarity formed in a semiconductor substrate of a first polarity; a plurality of diffusion regions spaced apart from a surface of the well region in a vertical structure having a constant cross section and a constant depth, the diffusion regions having a first polarity opposite to the well region and a second polarity identical to the well region; a number of electrodes formed in an upper layer of the diffusion region, the electrodes operating as source electrodes, drain electrodes or well region electrodes of a complementary MOSFET when a signal voltage is applied thereto; a number of trenches formed at intervals from a surface of the well region and having a constant cross section and a constant depth; an insulating layer formed on a surface of each trench from a surface of the well region; a conductive material filling the inner trench of the insulating layer; a MOSFET having complementary MOSFET gate electrodes formed in the upper portion of the trench filled with the conductive material and to which respective signal voltages are applied, said MOSFET gate electrodes being complementary to said MOSFET gate electrodes.

3. 3. The CMOS SRAM cell having a trench structure as claimed in claim 1 or 2, wherein the plurality of diffusion regions or trench gate electrodes of the MOSFETs having the first or second polarity are connected to each other by a conductive material.

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