Quantum computing device having an interposer, and its manufacturing method and operation method, quantum computing device having tantalum nitride and its manufacturing method

Abstract

A quantum computing device (30) is disclosed comprising a patterned layer comprising a conductive material and forming a plurality of qubits (34), the patterned layer adjacent to and parallel to a substrate layer such that the substrate layer and the patterned layer form a layer stack (31). The quantum computing device further comprises an interposer comprising a rigid connection element (37) mechanically connected to the layer stack, where the connection element is substantially planar and disposed in a plane non-parallel to the plane in which the substrate layer is formed, the connection element comprising a conductive element (38), preferably a transmission line, formed on or within the connection element for providing an electrical connection to the patterned layer.

Description

[Technical field]

[0001]

[0001] The present disclosure relates generally to the field of quantum computing. More specifically, but not by way of limitation, the present disclosure relates to quantum computing devices utilizing interposers. Additionally, the present disclosure relates to quantum computing devices comprising tantalum nitride. [Background technology]

[0002] Quantum computing uses properties of quantum states, such as superposition, interference, and entanglement, to perform computational tasks by executing quantum algorithms. In some quantum computing architectures, these quantum algorithms are executed on quantum processors that comprise superconducting qubits.

[0003]

[0003] A qubit, or quantum bit, is a two-state (or two-level) quantum mechanical system and is one of the simplest quantum systems that exhibits the properties of a quantum state. A general quantum state of a qubit can be represented by a linear superposition of its two orthonormal basis states: |0〉 and |1〉.

[0004]

[0004] There are various superconducting qubit implementations into specific physical systems. Three superconducting qubit archetypes are the phase qubit, the charge qubit, and the flux qubit, but many hybrids exist. For any qubit implementation, the basis states will be mapped to different states of the physical system, typically to the quantized energy levels of the physical system, or to a quantum superposition of them.

[0005]

[0005] There are other quantum computing architectures, for example with spin qubits. These are called spin qubit quantum computers. Their functioning is based on controlling the spin of charge carriers in semiconductor devices. The charge carriers can be electrons and electron holes.

[0006]

[0006] Superconducting qubits and spin qubits are examples of promising technologies within the field of quantum computing. However, building large-scale quantum computers poses several technical challenges. For example, a practical quantum computer needs to be physically scalable, i.e., both the number and the quality of qubits in a quantum processor must be scaled up significantly to achieve useful quantum computing in the future.

[0007]

[0007] The most fundamental challenge facing the task of scaling quantum computers is the fragility of qubits. To perform a calculation successfully, all qubits must be kept in a quantum coherent state. Quantum coherence refers to the ability of a quantum state to maintain its entanglement and superposition in the face of thermalization effects and interactions. Any environmental interference in a quantum system usually results in what is known as decoherence, i.e., loss of quantum coherence. Decoherence is irreversible and results in loss of information because the qubits "collapse" or fall out of superposition, thus resulting in the loss of the desired quantum state. These environmental interferences, known as noise, include vibrations, radiation, electromagnetic waves, or very slight fluctuations in temperature.

[0008]

[0008] A significant bottleneck to scaling up the number of qubits in quantum processors is caused by the spatial issues associated with current two-dimensional quantum processor architectures.

[0009] First, lateral wire bonds cause space shortages at the chip edges because chip edges scale linearly while the area for placement of chip elements scales quadratically. Thus, as more qubits are implemented in a quantum processor, the surface area occupied by chip elements grows faster than the perimeter of the chip, leading to a situation where there is not enough space at the edge of the chip to accommodate wire bonds to all the qubits.

[0010] Second, the need to route waveguides to the edge of the chip leads to on-chip routing problems as chip features grow exponentially.

[0011] Third, the up-chain fan-out of wires and other components also creates space problems.

[0012]

[0012] A partial solution to the first two of the above bottlenecks is represented by the prior art document EP 3 427 310 B1, which allows each interconnect to be placed close to its associated qubit, eliminating the need for routing to the edge of the chip and allowing for a repeatable and tileable layout. This solution alone is not sufficient, as it does not provide suitable techniques for continuing the waveguides in a scalable way without incurring fan-out problems.

[0013]

[0013] In the exemplary case of a particular design choice for superconducting qubits, each qubit requires access to microwave drive, magnetic flux bias, and input / output feedlines, so on average about 2.5 transmission lines per qubit are required. The input / output feedlines can be shared between qubits in some cases. The transmission lines are usually routed towards the edge of the chip, where the signals continue through wire bonds to connectors located on the printed circuit board. In the case of a small number of qubits, this is still a feasible option. However, when scaling up the number of qubits on the chip, this leads to spatial issues at the chip edge due to connector size and on-chip routing difficulties.

[0014]

[0014] In the case of spin qubits, a large plurality of low frequency gates are required, so the space issue becomes even more pressing when scaling up the number of spin qubits on a chip than it is for superconducting qubits.

[0015]

[0015] A second bottleneck in creating quantum processors with high qubit counts arises from the fact that the probability that all qubits are functioning on a particular chip (in other words, the chip yield) decreases exponentially with the number of qubits.

[0016]

[0016] Another technical challenge in building a practical quantum computer is that to achieve useful quantum computation, the qubits need to be of significant quality to avoid errors. One measure of high quality qubits is a long decoherence time, i.e., the time it takes for a qubit to lose its quantum coherent state. Time-consuming tasks (longer than the decoherence time of the qubits required to perform the task) can be difficult to perform using certain quantum algorithms, because maintaining a state of superposition of qubits for a long enough duration will eventually result in those qubits collapsing due to decoherence. For this reason, ways to increase the decoherence time are currently a major topic of research. Summary of the Invention

[0017]

[0017] To address the above-mentioned shortcomings of the prior art, according to a first aspect of the present disclosure, a quantum computing device is proposed. The quantum computing device comprises a substrate layer, a pattern layer adjacent and parallel to the substrate layer such that the substrate layer and the pattern layer form a layer stack, where the pattern layer comprises a conductive material and forms at least a part of a quantum computing circuit component, a substantially rigid connection element mechanically connected to the layer stack and arranged in a non-parallel plane, i.e. arranged in a plane that is not parallel to the plane in which the substrate layer is formed, and an interposer comprising a conductive element formed on or in the connection element for providing an electrical connection to the pattern layer. The substantially rigid connection element is preferably arranged in a plane substantially orthogonal to the plane in which the substrate layer of the layer stack is formed. The conductive element is preferably a transmission line formed on or in the connection element. The quantum computing device preferably comprises a plurality of computing circuit components and a plurality of interposers comprising a plurality of connection elements.

[0018] In one embodiment, the connecting element is substantially planar, and preferably the connecting element is substantially rectangular or square in shape.

[0019] In one embodiment, the interposer is electrically connected to the patterned layer, and the electrical connection is made galvanically, inductively, and / or capacitively between the connection elements and the patterned layer.

[0020]

[0020] In one embodiment, the substrate layer is made of or includes sapphire, silicon, BeO, AlN, quartz, and / or other dielectric materials, and / or the pattern layer is made of or includes a superconducting material such as Al, Nb, NbN, NbTiN, tantalum, or preferably tantalum nitride, or a combination of these materials.

[0021] In one embodiment, the patterned layer is formed at least in part by atomic layer deposition, evaporation, molecular beam epitaxy, and / or sputtering.

[0022] In one embodiment, the connection elements are at least partially made from the same material used for the substrate layers, and the complete interposer may also be at least partially made from this material.

[0023] In one embodiment, the quantum computing circuitry comprises a qubit, a photonic quantum circuit, and / or chip elements associated with the qubit or photonic quantum circuit, preferably control electronics, readout circuitry, amplifiers, filters, and / or transducers. The qubit preferably comprises a superconducting qubit, a spin qubit, a trapped ion qubit, or a neutral atom qubit. The quantum computing circuitry may comprise multiple qubits, a photonic quantum circuit, and associated chip elements.

[0024]

[0024] In one embodiment, the connection element further comprises a functional element, which is a circuit component that receives input from and / or sends output to the quantum computing circuit component, and preferably the functional element comprises a low pass filter, an attenuator, a DC-block, an IR filter, a directional coupler, a circulator, and / or an amplifier.

[0025]

[0025] In one embodiment, the connection element may have at least one of the following functions: microwave drive, magnetic flux bias, feedline input / output, pump for an amplifier or circulator, parametric amplifier, circulator, directional coupler, or routing line.

[0026] In one embodiment, inputs to and / or outputs from the quantum computing circuitry are routed at least in part through connection elements.

[0027] In one embodiment, the interposer is directly connected to the patterned layer, or the interposer is indirectly connected to the patterned layer, preferably through vias.

[0028]

[0028] In one embodiment, the connection element and the layer stack each have a connection surface having a connection profile for mechanically and / or electrically coupling the connection element to the layer stack, preferably the connection surface of the layer stack is the outermost layer of the layer stack, more preferably the connection surface of the layer stack is a patterned layer, preferably the connection profile comprises a coupling structure, preferably a recess, protrusion, coupling pin, preferably the coupling structure is self-aligning.

[0029] In one embodiment, the connection profile formed on the connection surface is created using a lithography process, deep reactive etching, and / or photoablation.

[0030]

[0030] In one embodiment, the quantum computing device further comprises a connectable circuit component, where the connection element is an intermediate link between the layer stack, preferably the quantum computing circuit component, and the connectable circuit component, and preferably the connectable circuit component comprises a connectorized circuit, more preferably a printed circuit board or an array of waveguides.

[0031]

[0031] In one embodiment, the connectable circuit component comprises at least a second layer stack formed by a second substrate layer and a second patterned layer adjacent and parallel to the second substrate layer, where the second patterned layer forms at least one second quantum computing circuit component.

[0032]

[0032] In one embodiment, the second layer stack is substantially parallel to the layer stack and is angled, preferably substantially perpendicular, to the connection element, and preferably the second layer stack is arranged in substantially the same plane as the layer stack, and the layer stack and the second layer stack are electrically connected via routing lines in the interposer, or the second layer stack is arranged in a plane different from the plane in which the layer stack is arranged, and the connection element reaches from the plane in which the layer stack is arranged to the plane in which the second layer stack is arranged.

[0033]

[0033] In one embodiment, the connectable circuit components comprise qubits and / or other chip elements, preferably control electronics, readout circuitry, or transducers, and preferably the second quantum computing circuit comprises qubits and / or other chip elements, preferably control electronics, readout circuitry, or transducers.

[0034]

[0034] In one embodiment, the interposer comprises an array of connection elements that are substantially parallel to each other and angled, preferably substantially orthogonal, with respect to the layer stack, each connection element of the array being connected to a pattern layer, and preferably the connection elements being spaced at specific intervals related to the spacing of the qubits on the horizontal plane.

[0035] In one embodiment, the layer stack comprises a plurality of patterned layers, each patterned layer comprising quantum computing circuitry.

[0036] In one embodiment, the layers in the layer stack and / or the layers in the connection element are connected through through silicon vias, preferably the layer stack and / or the connection element comprises through vias and / or blind vias.

[0037]

[0037] In one embodiment, a second interposer is mechanically connected to the layer stack at an opposite end of the layer stack from where the interposer is mechanically connected to the layer stack, and preferably input feed lines of the patterned layer are provided through the interposer and output feed lines of the patterned layer are provided through the second interposer.

[0038] In one embodiment, multiple interposers are mechanically and electrically connected to the connecting surfaces of the layer stack, and / or multiple layer stacks alternate with the interposers.

[0039] According to a second aspect of the present disclosure, a method of performing a quantum computing operation using a quantum computing device according to the first aspect of the present disclosure is disclosed.

[0040]

[0040] According to a third aspect of the present disclosure, a method of manufacturing a quantum computing device is disclosed, the method comprising: providing a substrate; depositing a pattern layer on top of and parallel to the substrate layer such that the substrate layer and the pattern layer form a layer stack, where the pattern layer comprises a conductive material and forms at least a part of one quantum computing circuit component; mechanically connecting a substantially rigid connection element included in an interposer to the layer stack, the connection element being disposed in a non-parallel plane, preferably substantially orthogonal to the plane in which the substrate layer is formed; forming a conductive element on or in the connection element, preferably a transmission line, to provide an electrical connection to the pattern layer; and electrically coupling the conductive element to the pattern layer.

[0041] According to a fourth aspect of the present disclosure, a quantum computing device is disclosed comprising: a substrate layer; a patterned layer adjacent and parallel to the substrate layer such that the substrate layer and the patterned layer form a layer stack, where the patterned layer comprises a conductive material and forms at least one quantum computing circuit component, where the conductive material comprises tantalum nitride.

[0042]

[0042] In one embodiment, the substrate layer is made of sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material, and / or the quantum computing circuit component comprises a qubit, preferably a superconducting qubit or a spin qubit.

[0043] According to a fifth aspect of the present disclosure, a method of fabricating a quantum computing device is disclosed, comprising: providing a substrate layer; and depositing a patterned layer on top of the substrate layer using atomic layer deposition and / or sputtering with tantalum nitride, the patterned layer comprising tantalum nitride and forming at least one quantum computing circuit component, preferably a qubit, more preferably a superconducting qubit or a spin qubit, wherein preferably the substrate layer is made of sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material.

[0044] According to a sixth aspect of the present disclosure, a quantum computing device is disclosed. The quantum computing device includes a substrate layer and a patterned layer adjacent to and parallel to the substrate layer such that the substrate layer and the patterned layer form a layer stack. The patterned layer may include a conductive material, and the layer stack may form a plurality of qubits.

[0045]

[0045] The quantum computing device further comprises an interposer comprising a connection element mechanically connected to the layer stack, where the connection element is substantially planar and may be disposed in a plane non-parallel to the plane in which the substrate layer is formed. The connection element may comprise a conductive element formed on or within the connection element, preferably a transmission line, for providing an electrical connection to the patterned layer. The connection element may be rigid.

[0046] In one embodiment, the connecting element may be substantially rectangular or square in shape.

[0047] In one embodiment, the interposer is electrically connected to the patterned layer galvanically, inductively, or capacitively.

[0048]

[0048] In one embodiment, the substrate layer is made of sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material, and / or the pattern layer is made of a superconducting material such as Al, Nb, NbN, NbTiN, tantalum, preferably tantalum nitride.

[0049] In one embodiment, the patterned layer is formed by atomic layer deposition, evaporation, molecular beam epitaxy, and / or sputtering.

[0050] In one embodiment, the interposer, and preferably the connection elements, are made from the same material as that used for the substrate layers.

[0051]

[0051] In one embodiment, the connection element comprises a connection substrate layer, or a connection substrate layer and a connection pattern layer adjacent to and parallel to the connection substrate layer, wherein the connection pattern layer comprises a conductive material.

[0052]

[0052] The connection substrate layer can be made of sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material. The connection pattern layer can be made of a superconducting material such as Al, Nb, NbN, NbTiN, tantalum, preferably tantalum. The connection pattern layer can be coated with a conductive layer.

[0053] In an embodiment, the qubits may comprise superconducting qubits, spin qubits, trapped ions, or neutral atoms. Additionally or alternatively, the patterned layer may further form a quantum computing circuit, where the quantum computing circuit comprises a photonic quantum circuit and / or other chip elements, preferably control electronics, readout circuitry, amplifiers, filters, and / or transducers.

[0054]

[0054] In one embodiment, the connection element may further comprise a functional element, which is a circuit component that obtains input from a qubit and / or sends output to a qubit, and / or which modifies input / output signals from the quantum computing circuit component, preferably the functional element comprises a low pass filter, an attenuator, a DC-block, an IR filter, a directional coupler, a routing line, a circulator, and / or an amplifier.

[0055] In one embodiment, the connection pattern layer may form a functional element.

[0056] A connection element may have at least one of the following functions: microwave drive, flux bias, feedline input / output, pump for an amplifier or circulator, parametric amplifier, circulator, directional coupler, or routing line.

[0057] In one embodiment, routing to and / or from a qubit is at least partially via a connection element.

[0058] In one embodiment, the interposer is directly connected to the patterned layer, or the interposer is indirectly connected to the patterned layer, preferably through vias.

[0059]

[0059] In one embodiment, the connection element and the layer stack each have a connection surface having a connection profile for mechanically and / or electrically coupling the connection element to the layer stack, preferably the connection surface of the layer stack is the outermost layer of the layer stack, more preferably the connection surface of the layer stack is a patterned layer, preferably the connection profile comprises a coupling structure, preferably a recess, protrusion, coupling pin, preferably the coupling structure is self-aligning.

[0060] In one embodiment, the connection profile formed on the connection surface is created through lithography, deep reactive etching, and / or photoablation.

[0061]

[0061] In one embodiment, the quantum computing device may further comprise a connectable circuit component, where the connection element is an intermediate link between the layer stack, preferably the qubits, and the connectable circuit component, and preferably the connectable circuit component comprises a connectorized circuit, more preferably a printed circuit board or an array of waveguides.

[0062]

[0062] In one embodiment, the connectable circuit component comprises at least a second layer stack formed by a second substrate layer and a second patterned layer adjacent and parallel to the second substrate layer, where the second patterned layer forms at least one quantum computing circuit component.

[0063]

[0063] In one embodiment, the second layer stack is substantially parallel to the layer stack and at an angle to the connection element, preferably substantially perpendicular. Preferably, the second layer stack is arranged in substantially the same plane as the layer stack. The layer stack and the second layer stack can be electrically connected via routing lines in the interposer. The second layer stack can also be arranged in a different plane than the plane in which the layer stack is arranged, in which case the connection element can reach from the plane in which the layer stack is arranged to the plane in which the second layer stack is arranged.

[0064]

[0064] In one embodiment, the connectable circuit components comprise qubits and / or other chip elements, preferably control electronics, readout circuitry, or transducers, and preferably the second quantum computing circuit comprises qubits and / or other chip elements, preferably control electronics, readout circuitry, or transducers.

[0065]

[0065] In one embodiment, the interposer comprises an array of connection elements that are substantially parallel to each other and angled, preferably substantially orthogonal, with each connection element of the array connected to a pattern layer, and preferably the connection elements are spaced at specific intervals related to the spacing of the qubits on the horizontal plane.

[0066]

[0066] In one embodiment, the interposer comprises at least one spacer element. Preferably, the connection elements are aligned by the at least one spacer element. The spacer element may be mechanically connected to the connection elements and / or the layer stack, preferably through a through silicon via. The at least one spacer element may be arranged in a plane non-parallel to the substrate plane of the layer stack, preferably substantially orthogonal to the substrate plane of the layer stack, more preferably the spacer element is arranged in a plane parallel to one or more connection elements. Preferably, the interposer comprises a plurality of spacers, more preferably the plurality of spacers may alternate with the connection elements, not necessarily one to one.

[0067]

[0067] In one embodiment, at least one spacer comprises a spacer substrate layer or a spacer substrate layer and a spacer pattern layer adjacent and parallel to the spacer substrate layer, where the spacer pattern layer comprises a conductive material. The spacer substrate layer may be made of sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material. Preferably, the spacer pattern layer is made of a superconducting material such as Al, Nb, NbN, NbTiN, tantalum, preferably tantalum nitride. The spacer pattern layer may be further coated with a conductive layer.

[0068] In one embodiment, at least one spacer comprises a functional spacer element. Preferably, the functional spacer element comprises a shield and / or at least one spacer may comprise a waveguide with a connectable circuit component, such as a PCB.

[0069] In one embodiment, the layer stack comprises a plurality of patterned layers deposited on one or more substrate layers, each patterned layer comprising a quantum circuit component, preferably a qubit.

[0070] In one embodiment, the layers in the layer stack and / or the layers in the connection element are connected through through silicon vias. Preferably, the layer stack and / or the connection element comprises through vias and / or blind vias.

[0071] In one embodiment, a second interposer is mechanically connected to the layer stack at an opposite end of the layer stack to where the interposer is mechanically connected to the layer stack. Preferably, input feed lines of the patterned layer are provided through the interposer and / or output feed lines of the patterned layer are provided through the second interposer.

[0072] In one embodiment, multiple interposers are mechanically and electrically connected to the connecting surfaces of the layer stack, and / or multiple layer stacks alternate with interposers.

[0073] In a seventh aspect, a method is disclosed of performing a quantum computing operation according to the sixth aspect of the present invention using a quantum computing apparatus according to the sixth aspect.

[0074]

[0074] In an eighth aspect, a method of manufacturing a quantum computing device is disclosed. The method comprises providing a substrate, depositing a pattern layer on top of and parallel to the substrate layer such that the substrate layer and the pattern layer form a layer stack, where the pattern layer comprises a conductive material and the layer stack forms a plurality of qubits, mechanically connecting a connection element included in an interposer to the layer stack, the connection element being disposed in a non-parallel plane, preferably substantially orthogonal, to the plane in which the substrate layer is formed, forming a conductive element on or in the connection element, preferably a transmission line, to provide an electrical connection to the pattern layer, and electrically coupling the conductive element to the pattern layer. The connection element may be rigid and / or substantially planar.

[0075]

[0075] Embodiments will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which: [Brief description of the drawings]

[0076] [Figure 1] FIG. 1 illustrates, in schematic form, a portion of a quantum computing device comprising a layer stack on which an interposer is disposed, according to one embodiment. [Diagram 2]

[0077] FIG. 2 illustrates, in accordance with one embodiment, a perspective view of a portion of a quantum computing device comprising a layer stack on which is disposed an interposer comprising an array of connection elements. [Diagram 3]

[0078] FIG. 3 illustrates generally a perspective view of how one or more quantum computing circuit components, preferably qubits, may be electrically connected to connection elements in a portion of a quantum computing device, according to one embodiment. [Figure 4]

[0079] FIG. 4 illustrates a schematic of a portion of a quantum computing device comprising a connection element comprising a transmission line and one or more functional elements, according to one embodiment. [Diagram 5]

[0080] FIG. 5 illustrates, in accordance with one embodiment, a perspective view of a portion of a quantum computing device comprising a layer stack on which is disposed an interposer comprising an array of connection elements having transmission lines and one or more functional elements. [Figure 6]

[0081] FIG. 6 illustrates, in schematic form, a perspective view of a portion of a quantum computing device comprising two layer stacks with an interposer formed between them. [Figure 7]

[0082] FIG. 7 illustrates, in schematic form, a portion of a quantum computing device comprising a layer stack with two interposers disposed on either side of the layer stack, according to one embodiment. [Figure 8]

[0083] FIG. 8 shows a schematic representation of a portion of a quantum computing device with mechanical and electrical connections between connection elements and layer stacks. [Figure 9]

[0084] FIG. 9 illustrates generally a portion of a quantum computing device that includes a modular structure having multiple planes that include one or more quantum computing circuit components, preferably qubits. [Figure 10]

[0085] FIG. 10 illustrates generally a portion of a quantum computing device that includes an interposer connecting two layer stacks that include one or more quantum computing circuit components, preferably qubits. [Figure 11]

[0086] FIG. 11 illustrates generally a portion of a quantum computing device comprising an interposer comprising an array of connection elements that connect multiple modules in a modular structure, each module comprising one or more quantum computing circuit components, preferably qubits. [Figure 12]

[0087] FIG. 12 illustrates generally an interposer disposed on a layer stack comprising quantum computing circuitry, preferably qubits, where the interposer comprises connecting elements and spacer elements. [Figure 13A]

[0088] FIG. 13A shows a spacer connected to the top of a vertical connecting element. [Figure 13B]FIG. 13B shows a spacer connected on top of another spacer. [Figure 14]

[0089] FIG. 14 shows a schematic of a connection profile between a connection element and a layer stack comprising a qubit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0077]

[0090] These diagrams are intended for illustrative purposes only and do not serve as a limitation on the scope or protection defined by the claims.

[0078]

[0091] In the following, certain embodiments are described in more detail, but it should be understood that these embodiments cannot be construed as limiting the scope of protection of the present disclosure.

[0079]

[0092] FIG. 1 illustrates, in schematic form, a portion of a quantum computing device 10 comprising a layer stack 14 having an interposer 16 disposed thereon, according to one embodiment.

[0080]

[0093] The layer stack 14 may comprise one or more substrate layers 11 and one or more patterned layers 12, where each of the patterned layers 12 comprises a conductive material, and where each of the patterned layers 12 and / or the layer stack 14 forms (part of) at least one quantum computing circuit component, preferably one or more qubits. The transmission lines of the individual qubit planes of the stack may be connected through signal vias in the (vertically) adjacent horizontal plane that optionally contains the qubits. Instead of qubits, other quantum computing circuit components may be connected in this manner.

[0081]

[0094] The one or more connecting substrate layers 11 may be made of, for example, sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material. Each of the substrate layers 11 may differ in thickness and / or material. The one or more patterned layers 12 may be made of a superconducting material such as Al, Nb, NbN, NbTiN, tantalum, preferably tantalum nitride. The patterned layers are formed by atomic layer deposition, evaporation, molecular beam epitaxy, and / or sputtering. Layer stack spacing elements may also be present between different layers of the layer stack in which the quantum computing circuitry is formed. Adjacent layers may be directly adjacent or there may be different layers between them.

[0082]

[0095] The quantum computing circuitry may be qubits, preferably superconducting qubits, spin qubits, trapped ions, or neutral atoms; photonic quantum computing circuitry; and / or other chip elements, preferably control electronics, amplifiers, filters, or transducers, that may be used to control the function of the qubits of quantum computing device 10.

[0083]

[0096] The layers of layer stack 14 are formed on top of one another in a substantially parallel manner. Thus, layer stack 14 of quantum computing device 10, e.g., quantum processor, may comprise, for example, one or more qubit planes comprised of a 2D (or 3D cavity) substrate layer 11 and one or more adjacent patterned layers 12 containing qubits, possibly with one or more additional layers between the substrate plane and the patterned layers.

[0084]

[0097] While layer stack 14 may comprise substrate layer 11 and one or more adjacent pattern layers 12, layer stack may also comprise multiple substrate layers. For example, layer stack 14 may comprise multiple horizontal chip layers, which may or may not be operatively connected to one another. The horizontal chip layers need not be in direct contact with one another at all locations along the chip layers, but may be spaced apart.

[0085]

[0098] An interposer 16 comprising one or more connection elements 15 may be mechanically connected to the layer stack 14. The interposer 16 provides electrical connections from one or more quantum computing circuit components, preferably qubits, formed on the one or more patterned layers 12 to different portions of the quantum computing device. The interposer may be electrically connected to the layer stack 14 (and preferably the one or more patterned layers 12 formed therein) in a variety of ways, for example, galvanically, inductively, and / or capacitively.

[0086]

[0099] The one or more connection elements 15 may be arranged in a plane substantially perpendicular to the plane in which the substrate layers of the layer stack 14 (comprising the quantum computing circuitry, preferably qubits) are formed. In general, the one or more connection elements 15 may be arranged in a plane that is non-parallel to the plane in which the substrate layers are formed. A conductive element may be formed on or in the connection element, preferably a transmission line, to provide an electrical connection to one or more of the patterned layers 12. The connection element is thus arranged to provide an electrical connection to one or more quantum computing circuitry, preferably qubits, formed on one or more of the patterned layers 12. This electrical connection may be made directly or indirectly, for example, by forming a quantum computing circuitry on an outer layer of the layer stack facing the connection element and forming an electrical connection directly on the outer layer of the layer stack, or by forming quantum computing circuitry in different layers of the layer stack and electrically connecting them through vias. These connection elements may be formed substantially parallel to each other, thus forming an array.

[0087]

[0100] The connection elements 15 may be formed from one or more substrate layers and one or more pattern layers formed thereon. The connection elements 15 may differ from each other within the interposer 16. The thickness of the connection elements 15 may be, for example, between 200 μm and 1 mm. The connection elements 15 may include, for example, different types of vias connecting different pattern layers within the connection elements 15.

[0088]

[0101] When the quantum computing circuitry, preferably qubits, are formed in an array in a layer stack, the connection element may have a width at least equal to the width of a row of the quantum computing circuitry array. In this way, a single connection element may electrically connect to all quantum computing circuitry in a particular row. The number of rows of the quantum computing circuitry array may be equal to the number of connection elements. In this way, each row of the quantum computing circuitry array may be connected to a corresponding connection element. It is also possible, for example, for more than one connection element to be connected to a quantum computing circuitry in a particular row, or for example, for more than one row to be connected to a single connection element.

[0089]

[0102] The connection elements 15 may be rigid and not easily bendable due to the way in which they are formed. Each connection element may comprise a connection substrate layer or a connection substrate layer and a connection pattern layer adjacent and parallel to the connection substrate layer, where the connection pattern layer comprises a conductive material. Preferably, the connection substrate layer is made of sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material. The connection pattern layer is preferably made of a superconducting material such as Al, Nb, NbN, NbTiN, tantalum, more preferably tantalum nitride.

[0090]

[0103] The connection elements can be substantially planar, for example, the connection elements can be substantially rectangular or square in shape. Other shapes are also possible, for example, the connection elements can have a footprint on the layer stack 14 with curved sections. The connection elements can also be curved along their length. When multiple connection elements are disposed on the layer stack 14, it is not necessary for all connection elements to be disposed parallel to one another on the layer stack 14, they can, for example, be in planes that intersect one another.

[0091]

[0104] The outermost layer 13 of the layer stack 14 may serve as a connection surface with one or more of the connection elements 15 of the interposer 16, having a connection profile for mechanically and electrically coupling the connection elements 15 of the interposer 16 to the layer stack. Preferably, the outermost layer 13 of the layer stack 14 is a patterned layer 12.

[0092]

[0105] Preferably, the one or more connection elements 15 may be made of the same material as the material of the substrate layers in the layer stack, the advantage being to have a similar thermal shrinkage for both the connection elements 15 of the processor and the layer stack 14.

[0093]

[0106] The connection elements 15 are spaced apart to form an array. Because every quantum computing circuit component has, for example, a transmission line connected to it, splitting the connection elements 15 on the connection plane allows the transmission line to be routed therefrom vertically through the connection elements 15, for example, rather than horizontally through the layer stack 14.

[0094]

[0107] To space the connection elements 15 of the interposer 16, the interposer 16 may further comprise one or more spacer elements. In this way, the connection elements forming the array of connection elements of the interposer 16 may be aligned by at least one spacer element. For example, a spacer element may be disposed between each pair of connection elements 15 forming the array of connection elements, i.e., the spacer elements and the connection elements may alternate. It is also possible that multiple connection elements are formed between two consecutive spacer elements, or multiple spacer elements are formed between two consecutive connection elements.

[0095]

[0108] Each spacer element may be formed as a substantially planar structure having a substantially square or rectangular shape. In particular, each spacer element may have substantially the same width and height as the connecting elements as defined above, but the connecting elements may also have, for example, a greater height than the spacer elements. The planar structure of each spacer element may be formed in a plane that is not perpendicular to the top surface of the layer stack 14, and may preferably be formed perpendicular to the top surface of the layer stack 14. Furthermore, each spacer element may be formed parallel to the connecting elements 15 in the array.

[0096]

[0109] FIG. 12 illustrates a schematic representation of a quantum computing device 120 having an interposer disposed on a layer stack 121 comprising quantum computing circuitry, preferably qubits, where the interposer comprises a connection element 121 and a spacer element 122. The connection element 121 may have a height greater than the spacer element 122 so that the connection element 121 may be connected to another connection substrate, such as, for example, a flexible cable or a PCB. The connection element 121 may also have a height similar to the spacer element 122 or a height less than the spacer element 210. The connection elements and spacer elements may have various heights. The spacer elements may alternate with vertical connection elements, not necessarily one-to-one alternation, and may have various spacer element dimensions and numbers in one stack. The spacer elements and connection elements are glued and / or soldered to one another overlapping such that recesses in the spacer elements cover transmission lines, such as coplanar waveguides, that may be formed in the connection elements, thus shielding the signal. The spacer may include a particular connection profile, for example with a finger-like structure, to form one ground together with the ground of the substrate layer of the layer stack in which the qubits are formed.

[0097]

[0110] The spacer element may be substantially rigid and may be mechanically connected to the connection element and / or the layer stack, for example via adhesive or soldering. Preferably, the electrical connection is made through through vias. The spacer may be in electrical connection with, for example, the ground of the layer stack in which the qubit is formed.

[0098]

[0111] Each spacer element may comprise a spacer substrate layer. Additionally, each spacer element may comprise a spacer pattern layer adjacent and parallel to the spacer substrate layer. The spacer pattern layer may comprise a conductive material.

[0099]

[0112] Preferably, the spacer substrate layer is made of or comprises sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material. Preferably, the spacer pattern layer is made of or comprises a superconducting material such as Al, Nb, NbN, NbTiN, tantalum, preferably tantalum nitride. A conductive layer can be formed on the superconducting layer of the connecting elements and / or spacer elements in the interposer. Preferably, each spacer element comprises the same material as the connecting elements of the interposer.

[0100]

[0113] The spacer elements need not be in functional contact with the qubits formed in the layer stack.The spacer substrate layer may also be patterned using a laser.

[0101]

[0114] The dimensions of the spacer elements included in the interposer 16 may be the same, e.g., the width of all spacer elements may be the same, such that the connection elements are equally spaced across the array. It is also possible for the dimensions of the spacer elements included in the interposer 16 to differ. For example, the width of a first spacer element disposed between a first pair of connection elements may be different from the width of a second spacer element formed between a second pair of connection elements of the interposer 16.

[0102]

[0115] Thus, each spacer element may ensure that connecting elements 15 are spaced apart the correct distance and / or may provide structural stability to connecting elements 15 and interposer 16 .

[0103]

[0116] The spacer element may comprise a functional spacer element. The functional spacer element is, for example, a shield. Also, a transmission line, for example a waveguide, may be formed in the spacer element. The functional spacer element is formed in or on the spacer element.

[0104]

[0117] The shield may shield the transmission lines on adjacent connection elements of the interposer. The shield may be formed within a pattern layer of the spacer element and thus may be formed of a superconducting material, optionally with a conductive coating.

[0105]

[0118] The waveguide can be a waveguide for the transmission of electromagnetic radiation of higher frequencies, for example sub-millimeter waves, also called terahertz radiation, with wavelengths between 1 millimeter and 100 micrometers, i.e. microwaves and far infrared. The exact frequency of the waveguide is determined by the dimensions of the recess.

[0106]

[0119] 13A and 13B respectively show a spacer 130 connected to the top of a vertical connection element 131 or a spacer 140A connected to the top of another spacer 140B. The configuration of FIG. 13A shows an enlargement of one of the transmission lines 134 and is suitable for transmission with frequencies in the order of GHz. The signal is trapped in a cache or gap or vacuum 132 formed by hatched / patterned pockets in the spacer 130 covered by superconducting and conducting material, thereby shielding the signal from "jumping" to the other transmission line. Reference number 133 indicates a gap between the transmission line (such as a coplanar waveguide) and ground. A coplanar waveguide is shown in this figure, but other waveguides are possible. FIG. 13B shows two spacer elements 140A, 140B forming a waveguide suitable for transmission with frequencies in the order of THz. Again, the signal is trapped by an electrical cache in the gap / vacuum 141.

[0107]

[0120] Therefore, with this spacer design, the interposer is suitable for reading a wider range of frequencies.

[0108]

[0121] The spacer and the connecting element may be glued and / or soldered to overlap one another such that the recess covers the coplanar waveguide located above the connecting element in the pattern layer, shielding the signal.

[0109]

[0122] The spacer elements may have the same connection structure / profile as shown in Figure 14 and may be in electrical contact with the grounds of the layer stack forming the qubit. The spacer elements may include fingers to form one ground with the ground of the substrate layer.

[0110]

[0123] Interposer 16, and particularly connecting elements 15, can be more easily made longer than heights typically used for layer stack 14, allowing more freedom in the integration of in-line functional elements.

[0111]

[0124] Thus, an interposer may comprise a plurality of connection elements arranged in an array formed along an array of qubits or other quantum circuit components in, for example, stacked layers. The connection elements provide electrical connections to and / or from the qubits or other quantum circuit components. Because the connection elements may be substantially planar structures, they may be easily manufactured and individualized to the needs of a particular row of qubits or other quantum circuit components. Furthermore, the space between the connection elements may be more easily utilized, for example by spacer elements having a specific design, for example to shield transmission lines that may be present in the (individualized) connection elements.

[0112]

[0125] The quantum computing device may further comprise control hardware, preferably one or more of an on-chip control element, a magnetic amplifier, an amplifier, a filter, a circulator, wiring, and a dilution refrigerator.

[0113]

[0126] FIG. 2 illustrates, in schematic form, a perspective view of a portion of a quantum computing device 20 comprising a layer stack 21 on which is disposed an interposer 23 comprising an array of connection elements 22, according to one embodiment.

[0114]

[0127] Conductive elements may be patterned in and / or on the connecting elements 22. For example, one or more transmission lines 24 may be formed in and / or on the connecting elements 22. The transmission lines 24 provide electrical connection to the layer stack, and in particular, the transmission lines 24 may provide electrical connection to patterned layers in the layer stack.

[0115]

[0128] The transmission line 24 can be, for example, a patterned strip made of a conductive material. For example, normal conductors or superconductors can be used as required by the quantum computing circuitry or device. Exemplary materials are indium, aluminum, gold, and tin, which can be deposited on the surface of the substrate. The formation of the material can be done via evaporation, electroplating, and / or sputtering. The patterning can be done by using patterning techniques such as, for example, wet etching, dry etching, stripping, laser writing, milling, and / or screen printing.

[0116]

[0129] FIG. 3 illustrates generally a perspective view of how one or more quantum computing circuit components 32 may be electrically connected to a portion of a connection element 37 of a quantum computing device 30, according to one embodiment.

[0117]

[0130] As an example, the computation circuitry 32 is shown as a schematic diagram of a superconducting qubit having a qubit 34 with a transmission line 33, e.g., a feedline. In the case of a superconducting qubit, on average about 2.5 transmission lines per qubit may be required, since each qubit requires, e.g., microwave drive, flux bias, and access to input / output feedlines. One or more quantum computation circuitry components, e.g., qubits, may be formed in a two-dimensional array with equal spacing between components, or the spacing may vary between different components. Although the quantum computation circuitry components are shown in the figures as layers at the top of the layer stack 31, these components may be formed anywhere in the layer stack 31 and on or in various layers within the layer stack 31. For example, not all components need be formed in the same patterned layer of the layer stack 31, but rather they may be formed in or on different patterned layers of the layer stack 31. The layers in the layer stack 31 may be connected to each other via through silicon vias.

[0118]

[0131] An interposer containing an array of connection elements 37, each of which may have its own function (e.g., microwave drive, magnetic flux bias, and / or input / output feedlines), makes it possible to have transmission line connectors above the qubit plane rather than next to it, which further helps reduce the degree of on-chip routing.

[0119]

[0132] In the case of spin qubits, a large number of low frequency gates are required. In this case, the bulk of the gate quantity per qubit is electrostatic gates. The interposer according to the present embodiment facilitates the scaling up of the number of spin qubits on a chip by incorporating the transmission lines of these electrostatic gates into the interposer connection elements 37.

[0120]

[0133] Thus, in general, challenges posed by large qubit counts, such as the difficulty of on-chip routing of transmission lines and spatial issues at the edges of the horizontal qubit plane due to wire bonding to the printed circuit board, can be overcome by using an interposer having connection elements for connecting quantum computing circuit components, e.g., qubits. Vertical interposers also limit the upchain fan-out of waveguides due to the possibility of incorporating macro-sized functional elements in the vertical elements of the vertical interposer.

[0121]

[0134] For example, the wiring footprint 35A, i.e., the area occupied by a qubit and associated wiring for that qubit in a particular layer, may be limited at least in part to the three-dimensional volume between the wiring footprint 35A and its projection 35B in a plane parallel to the layer stack 31.

[0122]

[0135] The connection elements 37 in the interposer may have, for example, one of the following functions: microwave drive (M), flux bias (F), feedline input / output (I / O), pump for an amplifier or circulator, parametric amplifier, circulator, directional coupler, or routing line. It is also possible to combine multiple functions within one vertical element of a vertical interposer.

[0123]

[0136] FIG. 4 illustrates generally a portion of a quantum computing device 40 including a connection element 46 that includes one or more functional elements 42A-D, according to one embodiment.

[0124]

[0137] Functional elements 42A-D are circuit components that obtain inputs from and / or send outputs to quantum computing circuit components in layer stack 41. In other words, functional elements are circuit components formed in a quantum computing device to modify input / output signals from quantum computing circuit components, preferably qubits. Functional elements 42A-D may include, for example, low pass filters, attenuators, DC-blocks, IR filters, directional couplers, circulators, and / or amplifiers.

[0125]

[0138] Transmission lines 43A, 45A may connect functional elements 42B, 42D to layer stack 41. Further transmission lines 43B, 45C then connect functional elements 42B, 42C to different parts of quantum computing device 40 via interfaces of connection element 46 opposite the interfaces connected to layer stack 41. Transmission line 45B may also electrically connect different functional elements 42C, 42D within connection element 46.

[0126]

[0139] This allows these functional elements to be above the qubit plane instead of next to it, which also helps reduce the amount of routing within the qubit plane.

[0127]

[0140] Thus, the vertical interposer may also limit the upchain fan-out of the waveguides for the qubits in the qubit plane. This is due to the possibility of incorporating macro-sized functional elements in the vertical elements of the vertical interposer. Also, due to the ability to 3D mold each vertical element into a complex shape and pattern superconducting films on them, the vertical interposer will also perform some microwave hygiene functions, such as subdividing large cavity volumes into smaller ones (pushing spurious modes to higher frequencies) and equalizing grounds across multiple horizontal elements.

[0128]

[0141] FIG. 5 illustrates, in schematic form, a perspective view of a portion of a quantum computing device 50 comprising a layer stack 51 on which an interposer comprising an array of connection elements 53 having one or more functional elements 54 is disposed, according to one embodiment.

[0129]

[0142] Within the array of connection elements 53 in the interposer, there is a well-defined spacing (also referred to as pitch) between each vertical element that is related to the spacing of quantum computing circuit components, e.g., qubits 52, contained on or within the layer stack 51. For example, a 1 mm inter-qubit spacing may be observed in a patterned layer of the layer stack 51, and then vertical elements 53 may be formed at specific locations, e.g., to make mechanical and / or electrical connections at that location for each quantum computing circuit component. As previously mentioned, interposer spacer elements may be disposed between the connection elements 53 of the array.

[0130]

[0143] Again, the functional elements 54 and transmission lines 55 may be formed in one or more of the connection elements 53 of the interposer, and the connection elements 53 within the interposer may differ in terms of their built and / or function.

[0131]

[0144] FIG. 6 shows diagrammatically a perspective view of a portion of a quantum computing device 60 comprising two layer stacks 61A-B with an interposer formed between them.

[0132]

[0145] The transmission lines may be connected to an interface of the vertical interposer opposite the interface connected to the horizontal plane containing the qubits, possibly continuing the signal path to other components of the quantum computer. In this embodiment, the interposer is disposed between two layer stacks 61A-B, possibly containing qubits or other chip elements such as control electronics or transducers. The layer stacks 61A-B may be the same or different in terms of the amount of layers, the number of substrate layers and the materials contained therein, the number of pattern layers and the materials contained therein. The layer stacks 61A-B have connection surfaces 62A, 62B, respectively, which are the outermost layers of the layer stacks 61A, 61B, facing the opposing layer stacks 61B, 61A.

[0133]

[0146] In this manner, the quantum computing circuit components 63A, 63B in different layer stacks 61A, 61B may be electrically connected to each other via one or more connection elements 64, for example via transmission lines 65 and / or functional elements (not shown).

[0134]

[0147] Instead of a second layer stack, the interposer may connect the layer stack 61A to another connectable circuit component, where the connection element is an intermediate link between the layer stack 61A, preferably the quantum computing circuit component 63A, and the connectable circuit component.

[0135]

[0148] For example, the connectable circuitry may comprise a circuit with connectors, preferably a printed circuit board. The connectable circuitry may comprise other chip elements, such as control electronics, (flexible) cabling, and / or transducers.

[0136]

[0149] As previously mentioned, the connectable circuit components may comprise a second substrate layer and a second patterned layer adjacent and parallel to the second substrate layer such that the second substrate layer and the second patterned layer form a second layer stack 61B, where the second patterned layer forms at least one second quantum computing circuit component 63B. The second layer stack 61B may be substantially parallel to the layer stack 61A and at an angle, preferably substantially orthogonal, to the connection element 64.

[0137]

[0150] Thus, the second layer stack 61B can be arranged in a plane different from the plane in which the layer stack 61A is arranged, and the connection element reaches from the plane in which the layer stack 61A is arranged to the plane in which the second layer stack 61B is arranged.

[0138]

[0151] Incorporating an interposer in this way may facilitate several novel quantum processor unit (QPU) architectures. Thus, one such option is a stacked planar architecture. Here, several horizontal planes, e.g., layer stacks 61A, 61B, possibly including quantum computing circuitry components such as qubits or other chip elements, may be used in combination with one or several interposers. This type of QPU architecture facilitates scaling up the number of qubits in a QPU by expanding in three dimensions, rather than just in two dimensions. Thus, this allows for an increase in the number of qubits in the same area footprint.

[0139]

[0152] One possibility for quantum computing devices, such as quantum processors, employing stacked architectures may be to mount several qubit planes containing signal vias on top of each other. An interposer may then be connected to one or both interfaces of the outermost planes in the stack that are non-parallel, and preferably orthogonal, to the outermost planes in the stack. The transmission lines of the individual qubit planes may then be connected to vertical interposers at the bottom and / or top of the stack, possibly through signal vias in adjacent horizontal planes that also contain qubits. Instead of qubits, other quantum computing circuit components may be connected in this way.

[0140]

[0153] FIG. 7 illustrates diagrammatically a portion of a quantum computing device 70 comprising a layer stack 74 with two interposers 76A, 76B disposed on either side of the layer stack 74, according to one embodiment.

[0141]

[0154] The layer stack 74 may comprise one or more substrate layers 71 and one or more patterned layers 72, where each of the patterned layers 72 may comprise a conductive material and may form at least one quantum computing circuit component.

[0142]

[0155] The layers of the layer stack 74 are formed on top of each other so as to be substantially parallel. Interposers 76A, 76B with one or more connection elements 75A, 75B may be mechanically connected to the layer stack 74 on both the top surface 73A and the bottom surface 73B of the stack. The interposers 76A, 76B need not be identical. The number of connection elements 75A, 75B may vary, as may the construction and function of the connection elements 75A, 75B.

[0143]

[0156] Connecting the interposers 76A, 76B at both the bottom and top of the stack facilitates a useful way of connecting quantum computing circuitry (e.g., qubits), e.g., having all the input feedlines at one end of the stack and all the output feedlines at the other end. Thus, a second interposer 76B can be mechanically connected to the layer stack at an opposite end of the layer stack to where the first interposer 76A is mechanically connected to the layer stack. Thus, the input feedlines of the patterned layers in the layer stack 74 can be provided, for example, through the first interposer 76A, and the output feedlines of the patterned layer 74 can be provided, for example, through the second interposer 76B.

[0144]

[0157] Another possible way to use a stacked architecture is to use an alternating stack of vertical interposers and, potentially, one or more planes containing qubits. Thus, for example, multiple layer stacks could alternate with interposers. This could create a 3D lattice of quantum computing circuitry, e.g., a 3D lattice of qubits.

[0145]

[0158] By connecting two planes containing qubits together through an interposer in this way, thus creating a 3D lattice, the degree of interconnectivity can be increased from that of the current 2D qubit plane layout. This feature is beneficial for several possible applications. It brings more computational power for certain quantum algorithms. Another possible application is error correction. Working with a 3D qubit lattice offers the opportunity to work with a class of new 3D error correcting codes, where the degree of interconnectivity is higher than the degree of four currently used for 2D surface codes.

[0146]

[0159] FIG. 8 shows diagrammatically a portion of a quantum computing device 80 comprising mechanical connections 85A, 85B and an electrical connection 83 between a connection element 84 and an outermost layer 81 of a layer stack.

[0147]

[0160] The outermost layer 81 of the layer stack, e.g., the surface of the connection elements 84 in the interposer facing the qubit plane, and the outermost layer 81 itself, may have a particular profile such that the interposer may be coupled (electrically and mechanically) to the outermost layer 81 of the layer stack, e.g., by using self-aligning structures. The outermost layer 81 may be a patterned layer having a pattern 82 of conductive material formed thereon or therein. For example, the pattern 82 formed on or in the outermost layer 81 may form part of a quantum computing circuit component, such as a qubit.

[0148]

[0161] The geometry of the profile of the outermost layer 81 may include structures such as one or more recesses 85A. The geometry of the surface of one or more connection elements 84 in the interposer facing the outermost layer 81 may include protrusions 85B, e.g., pins, that may mate with the recesses 85A in the outermost layer 81. Such connections may be self-aligning structures and may be incorporated to make the connection structure between the interposer and the layer stack compound more robust after fabrication.

[0149]

[0162] Electrical connection between connection element 84 and the outermost layer 81 of the layer stack can be made using, for example, conductive bumps 83 or other conductive connection elements made, for example, of indium. Indium has the advantage of not becoming brittle even at cryogenic temperatures and is therefore a good material choice, for example, when dealing with superconducting qubits as quantum computing circuit components integrated into the layer stack.

[0150]

[0163] Conductive bumps 83 may be formed at specific locations on the outermost layer 81, for example, via soldering, electroplating, lamination, and / or ball grid array stenciling, and may function, for example, to route signals to or from quantum computing circuitry, for example, to or from waveguides, and / or to connect, for example, quantum computing circuitry in the layer stack to functional elements in the connection element 84. The conductive bumps 83 may be formed to be in contact with the ground line 86C or the transmission line 86A. The transmission line 86A and the ground line 86C may be separated by the etched-away section 86B of the connection element 84. In this exemplary embodiment, on the outermost layer 81, the transmission line and the ground are separated by the etched-away pattern 82.

[0151]

[0164] The profile on both the surface of the outermost layer 81 and the surface of one or more connection elements 84 in the interposer, i.e., on one or both of the connection surfaces, can be created through the techniques of lithography, deep reactive etching, and / or photoablation. The mechanical and electrical geometry of the profile can be created using one of these techniques.

[0152]

[0165] Thus, the connection element 84 and the layer stack may each have a connection surface with a connection profile for mechanically and / or electrically coupling the connection element 84 to the layer stack. Preferably, the connection surface of the layer stack is the outermost layer of the layer stack, more preferably, the connection surface of the layer stack is a patterned layer. Furthermore, certain adhesives and solder materials, such as epoxies or stycast, may be used to further strengthen the mechanical connection between the layer stack and the connection element 84.

[0153]

[0166] The connection profile may comprise a coupling structure, preferably a recess, a protrusion, a coupling pin, more preferably the coupling structure may be self-aligning. The recess may be formed in the outermost layer 81 and the subsequent layers below it, depending on the requirements of the connection.

[0154]

[0167] The connection profile of the (vertical) connection elements 84 thus comprises protrusions (also called fingers or pins) on which a superconducting and / or conductive material is deposited. These protrusions may contact the outer layer of the layer stack containing the qubits. The protrusions associated with the transmission lines contact this plane directly or by contact with through-and-through VIAs. The protrusions associated with the ground lines may form one uniform ground by connecting to a grounded part of the outer layer of the layer stack. To ensure contact even in cryogenic conditions and to allow for tolerances of misalignment during assembly, the tips of the protrusions may be covered with a nodule of indium.

[0155]

[0168] FIG. 14 shows a schematic connection profile 150 between a connection element and a layer stack comprising qubits. The connection profile of the connection element comprises protrusions (fingers / pins) 151 on which a superconducting and / or conductive material is deposited. The protrusions are in contact with the outer layer of the layer stack 154, preferably containing the qubits. The fingers 151 associated with the transmission lines 153 either directly contact this plane or by contact with through-and-through VIAs 155. The fingers associated with the ground lines may form one uniform ground by connecting to a grounded part of the outer layer of the layer stack. To ensure contact even in cryogenic conditions and to allow for tolerances of misalignment during assembly, the tips of the fingers 151 may be covered with blobs 152 of indium (or other material that is soft and thermally conductive in cryogenic conditions).

[0156]

[0169] FIG. 9 illustrates generally a portion of a quantum computing device 90 that includes a modular structure 91 having multiple modules 92 that include one or more quantum computing circuit components.

[0157]

[0170] Each module 92 may comprise a layer stack having one or more substrate layers and one or more patterned layers. The patterned layers may form one or more quantum computing circuit components. For example, one module 92 may comprise a qubit plane having an array of qubits.

[0158]

[0171] FIG. 10 illustrates diagrammatically a portion of a quantum computing device 100 comprising an interposer having a connection element 103 connecting two layer stacks 101A, 101B comprising one or more quantum computing circuit components.

[0159]

[0172] The two layer stacks 101A, 101B may, for example, each be included in different modules of a modular structure. Conductive elements such as conductive bumps 102A, 102B may be used to electrically connect the layer stacks 101A, 101B to a connection element 103 of an interposer. In this way, the connection element, and thus the interposer, may, for example, be connected to multiple qubit planes in different modules of the modular structure. For example, the qubit planes may be staggered relative to the interposer. These multiple qubit planes may be coupled to each other through one or more routing lines 104 in the connection element 103 of the interposer. This allows for a modular quantum processor.

[0160]

[0173] This modular quantum processor structure allows for an increase in the number of qubits while maintaining the yield of a decoupled chip between modules. This is because the probability P QPU But the following formula:

[0161]

number

[0162] where m is the number of modules in the quantum processor structure, and P q is the average individual qubit yield, and n iis the number of qubits in module i. Thus, for a quantum processor structure composed of a single module with many qubits, the probability that all qubits in the quantum processor structure are functional approaches zero. If instead the quantum processor structure is made up of many smaller modules, one can select modules where all qubits on the module are functional before assembling the modules into the structure. Thus, after this intermediate selection step,

[0163]

number

[0164] Thus, the yield of quantum processor structures can be increased.

[0165]

[0174] FIG. 11 illustrates generally a portion of a quantum computing device 110 comprising an interposer comprising an array of connection elements 113 connecting multiple modules 112 in a modular structure 111, each module 112 comprising one or more quantum computing circuit components.

[0166]

[0175] Again, the layer stacks are all disposed in substantially the same plane and may be electrically connected via routing lines 115 in the connection elements 113. Other transmission lines 114 or functional elements (not shown) may also be present in one or more of the connection elements.

[0167]

[0176] The modular structure 111 may also have multiple interposers, each with an array of connection elements 113 that cover only a portion of the modular structure 111, at least in terms of connectivity, but together cover the entire modular structure 111. Another option is for each module 112 to have its own interposer. Each of these interposers may have connection elements that only extend to that particular module.

[0168]

[0177] A module 112 in the modular structure 111, or indeed any layer stack, may also comprise multiple interposers, all of which are mechanically and electrically connected to the same connection side of the layer stack.

[0169]

[0178] In general, to achieve maximum utility of the large qubit plane (or other quantum computing circuitry), an intermediate choice can be applied.

[0170]

[0179] A first method of intermediate selection may involve fabricating a large qubit plane. After this plane is fabricated, the functionality of each qubit is evaluated, for example, by optical microscopy or probe station measurements. Then, as large an area of ​​the chip as possible is selected that contains qubits that are free of qubit defects. Within this area, the transmission lines are rerouted. Finally, the area free of qubit defects is cut out of the wafer.

[0171]

[0180] The second method of intermediate selection may also involve fabricating a large qubit plane. After the plane is fabricated, the functionality of each qubit is evaluated, for example, by optical microscopy or probe station measurements. The portion of the qubit plane where the qubit failure occurred is then cut out from the plane. The remaining elements are then connected to each other by air bridges or non-parallel, preferably orthogonal, interposers.

[0172]

[0181] For example, in the case of both spin qubits and superconducting qubits, it is particularly beneficial to use tantalum nitride for the patterned layer of one or more qubit planes. Superconducting qubits made of tantalum have already achieved long decoherence times, which are a measure of good qubit quality. For some superconducting elements, alloying the metal for the patterned layer with nitrogen results in a higher superconducting transition temperature (Tc) for the patterned layer, as in the case of niobium. The use of tantalum nitride results in long decoherence times, generally longer than when using tantalum. To fabricate such patterned layers of tantalum nitride, atomic layer deposition and / or sputtering can be used to deposit tantalum nitride on a substrate layer.

[0173]

[0182] In general, a quantum computing device can be fabricated that includes a substrate layer and a pattern layer adjacent and parallel to the substrate layer, such that the substrate layer and the pattern layer form a layer stack. The pattern layer can include or be fabricated from a conductive material and can form at least one quantum computing circuit component. In this case, the conductive material can include or be tantalum nitride. For example, the quantum computing circuit component can include tantalum nitride. In this way, a longer decoherence time can be achieved.

[0174]

[0183] Superconducting tantalum qubits have already achieved very long decoherence times. The reason for this could be the absence (or reduction) of undesirable material defects at the interface, such as two-level systems (TLS), which destroy the coherence. Tantalum also has one stable oxide (Ta 2 O 5) at 2000 K. This effect also occurs with aluminum. Annealing tantalum with nitrogen can be even more beneficial, since nitrogen forms stronger bonds with tantalum than oxygen and can therefore (strongly) reduce the oxide layer. As a rule of thumb, the thinner the oxide layer, the better.

[0175]

[0184] In addition, for other superconducting materials, annealing the metal of the patterned layer with nitrogen can increase the critical temperature of the metal. The critical temperature is the temperature at which the superconducting effect occurs, so a higher critical temperature of the metal is usually preferred. The same can be achieved with tantalum nitride.

[0176]

[0185] Tantalum nitride can be deposited by ALD, reactive magnetron sputtering, and PLD, among other methods. Due to the nitrogen bonds to the tantalum atoms, the surface of the TaN film has a reduced oxide compared to tantalum films, thus reducing the amount of defects exhibited by metal-air interfaces (TLS) at cryogenic temperatures and low power excitations typical of superconducting qubit operation. The substrate layer can be made of sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material. The quantum computing circuitry can comprise qubits, preferably superconducting qubits or spin qubits. For example, part or the entire patterned layer can be made of TaN. Preferably, the Josephson junctions can be part of the patterned layer that is not made of TaN.

[0177]

[0186] In general, a method of fabricating a quantum computing device may include providing a substrate layer and depositing a patterned layer on top of the substrate layer using atomic layer deposition and / or sputtering with tantalum nitride. In this manner, the patterned layer may comprise or be made of tantalum nitride. The patterned layer may be fabricated to form at least one quantum computing circuit component, preferably a qubit, more preferably a superconducting qubit or a spin qubit. The substrate layer may be fabricated from sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material.

[0178]

[0187] Quantum computing devices comprising tantalum nitride as described above may be used to perform quantum computing operations.

[0179]

[0188] Both horizontal and vertical elements can be fabricated via conventional microfabrication techniques, for example as described below. Typically, the substrate can be cleaned and prepared to receive metallization, for example by sputtering, evaporation, ALD, or MBE. A lithographic pattern can then be defined, for example by optical or e-beam techniques. Etching can be performed, for example, by dry etching, wet etching, or a combination thereof. VIAs can be realized by DRIE or laser ablation, and the coating can be realized conformally by ALD. The elements can be separated from the starting substrate by a dicing blade or laser ablation.

[0180]

[0189] After the horizontal and vertical elements are individually fabricated, they can then be prepared for 3D assembly, which may involve additional metal deposition (gold and indium) and subsequent patterning. Finally, alignment of the horizontal and vertical elements is performed, for example prior to thermocompression bonding.

[0181]

[0190] Two or more of the above embodiments may be combined in any suitable manner.

Claims

1. 1. A quantum computing device, comprising: a substrate layer; a patterned layer adjacent to and parallel to the substrate layer such that the substrate layer and the patterned layer form a layer stack, wherein the patterned layer comprises a conductive material, and the layer stack forms a plurality of qubits; an interposer comprising rigid connection elements mechanically connected to the layer stack, wherein the connection elements are substantially planar and disposed in a plane non-parallel to the plane in which the substrate layer is formed, the connection elements comprising conductive elements formed on or within the connection elements, preferably transmission lines, for providing electrical connection to the patterned layer; A quantum computing device comprising:

2. The quantum computing device of claim 1 , wherein the connecting elements are substantially rectangular or square in shape.

3. The quantum computing device of claim 1 or 2, wherein the interposer is electrically connected to the patterned layer galvanically, inductively, or capacitively.

4. 2. The quantum computing device of claim 1, wherein the substrate layer is made of sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material, and / or the patterned layer is made of a superconducting material such as Al, Nb, NbN, NbTiN, tantalum, preferably tantalum nitride.

5. The quantum computing device of claim 1 , wherein the patterned layer is formed by atomic layer deposition, evaporation, molecular beam epitaxy, and / or sputtering.

6. The quantum computing device of claim 1 , wherein the interposer, preferably the connection elements, are made from the same material as that used for the substrate layer.

7. the connecting element comprises a connecting substrate layer or a connecting substrate layer and a connecting pattern layer adjacent to and parallel to the connecting substrate layer, the connecting pattern layer comprising a conductive material; Preferably, said connection substrate layer is made of sapphire, silicon, BeO, AlN, quartz and / or any other dielectric material, and / or preferably, said connection pattern layer is made of a superconducting material such as Al, Nb, NbN, NbTiN, tantalum, preferably tantalum, Preferably, the connection pattern layer is coated with a conductive layer. The quantum computing device of claim 1 .

8. the qubit comprises a superconducting qubit, a spin qubit, a trapped ion, or a neutral atom; and / or the patterned layer further forms a quantum computing circuit, the quantum computing circuit comprising a photonic quantum circuit and / or other chip elements, preferably control electronics, readout circuits, amplifiers, filters, and / or transducers. The quantum computing device of claim 1 .

9. 2. The quantum computing device of claim 1, wherein the connection elements further comprise functional elements, which are circuit components that obtain input from and / or send output to the qubits, and / or which modify the input / output signals from the quantum computing circuit components, preferably functional elements comprising low-pass filters, attenuators, DC-blocks, IR filters, directional couplers, routing lines, circulators, and / or amplifiers.

10. The quantum computing device according to claim 9 dependent on claim 7, wherein the connection pattern layer forms the functional element.

11. 10. The quantum computing device of claim 1, wherein the connection element has at least one of the following functions: microwave drive, magnetic flux bias, feedline input / output, pump for the amplifier or circulator, parametric amplifier, circulator, directional coupler, or routing line.

12. The quantum computing device of claim 1 , wherein routing to and / or from the qubits occurs at least in part through the connection elements.

13. The quantum computing device of claim 1 , wherein the interposer is directly connected to the patterned layer, or the interposer is indirectly connected to the patterned layer, preferably through vias.

14. 2. The quantum computing device of claim 1, wherein the connection element and the layer stack each have a connection surface having a connection profile for mechanically and / or electrically coupling the connection element to the layer stack, preferably the connection surface of the layer stack is an outermost layer of the layer stack, more preferably the connection surface of the layer stack is the patterned layer, preferably the connection profile comprises a coupling structure, preferably a recess, a protrusion, a coupling pin, preferably the coupling structure is self-aligning.

15. 15. The quantum computing device of claim 14, wherein the connection profile formed on the connection surface is created through lithography, deep reactive etching, and / or photoablation.

16. 10. The quantum computing device of claim 1, further comprising a connectable circuit component, wherein the connection element is an intermediate link between the layer stack, preferably the qubit, and the connectable circuit component, and preferably the connectable circuit component comprises a connectorized circuit, more preferably a printed circuit board or an array of waveguides.

17. 17. The quantum computing device of claim 16, wherein the connectable circuit component comprises at least a second layer stack formed by a second substrate layer and a second patterned layer adjacent to and parallel to the second substrate layer, the second patterned layer forming at least one quantum computing circuit component.

18. the second layer stack is substantially parallel to the layer stack and at an angle to the connecting element, preferably substantially perpendicular, and preferably the second layer stack is disposed in substantially the same plane as the layer stack, and the layer stack and the second layer stack are electrically connected via routing lines in the interposer; or the second layer stack is arranged in a plane different from the plane on which the layer stack is arranged, and the connecting element extends from the plane on which the layer stack is arranged to the plane on which the second layer stack is arranged.

18. The quantum computing device of claim 17.

19. 19. A quantum computing device according to any one of claims 16 to 18, wherein the connectable circuit components comprise qubits and / or other chip elements, preferably control electronics, readout circuitry or transducers, and preferably the second quantum computing circuit comprises qubits and / or other chip elements, preferably control electronics, readout circuitry or transducers.

20. 2. The quantum computing device of claim 1, wherein the interposer comprises an array of connection elements that are substantially parallel to one another and angled, preferably substantially orthogonal, with respect to the layer stack, each connection element of the array being connected to the patterned layer, and preferably the connection elements being spaced apart at specific intervals related to the spacing of the qubits on the horizontal plane.

21. the interposer comprises at least one spacer element; Preferably, said connecting elements are aligned by said at least one spacer element; the spacer elements are preferably mechanically connected to the connecting elements and / or the layer stack through through silicon vias, the at least one spacer element is arranged in a plane non-parallel to the substrate plane of the layer stack, preferably in a plane substantially perpendicular to the substrate plane of the layer stack, more preferably the spacer element is arranged in a plane parallel to the one or more connecting elements, Preferably, the interposer comprises a plurality of spacers, more preferably the plurality of spacers alternate with the connecting elements.

21. The quantum computing device of claim 20.

22. the at least one spacer comprises a spacer substrate layer, or a spacer substrate layer and a spacer pattern layer adjacent to and parallel to the spacer substrate layer, the spacer pattern layer comprising a conductive material; Preferably, said spacer substrate layer is made of sapphire, silicon, BeO, AlN, quartz and / or any other dielectric material, and / or preferably said spacer pattern layer is made of a superconducting material such as Al, Nb, NbN, NbTiN, tantalum, preferably tantalum nitride, Preferably, the spacer pattern layer is coated with a conductive layer.

22. The quantum computing device of claim 21.

23. 23. The quantum computing device of claim 21 or 22, wherein the at least one spacer comprises a functional spacer element, preferably the functional spacer element comprises a shield and / or the at least one spacer comprises a waveguide with the connectable circuit component, e.g. a PCB.

24. 10. The quantum computing device of claim 1, wherein the layer stack comprises a plurality of patterned layers deposited on one or more substrate layers, each patterned layer comprising a quantum circuit component, preferably a qubit.

25. 2. The quantum computing device of claim 1, wherein the layers in the layer stack and / or the layers in the connection element are connected through through-silicon vias, and preferably the layer stack and / or the connection element comprise through-silicon vias and / or blind vias.

26. 2. The quantum computing device of claim 1, wherein a second interposer is mechanically connected to the layer stack at an end of the layer stack opposite to where the interposer is mechanically connected to the layer stack, and preferably the input feed lines of the patterned layer are provided through the interposer and the output feed lines of the patterned layer are provided through the second interposer.

27. 10. The quantum computing device of claim 1, wherein a plurality of interposers are mechanically and electrically connected to connection surfaces of the layer stack, and / or a plurality of layer stacks alternate with interposers.

28. A method of performing quantum computing operations using the quantum computing device of claim 1.

29. 1. A method of manufacturing a quantum computing device, comprising: providing a substrate; depositing the patterned layer on top of and parallel to the substrate layer such that the substrate layer and the patterned layer form a layer stack, wherein the patterned layer comprises a conductive material and the layer stack forms a plurality of qubits; mechanically connecting a rigid connection element included in an interposer to the layer stack, wherein the connection element is substantially planar and disposed in a plane non-parallel to the plane in which the substrate layers are formed; forming conductive elements on or within said connection elements, preferably transmission lines, to provide electrical connections to said patterned layer; electrically coupling the conductive elements to the patterned layer; A method for providing the above.

30. 1. A quantum computing device, comprising: a substrate layer; a patterned layer adjacent to and parallel to the substrate layer such that the substrate layer and the patterned layer form a layer stack, wherein the patterned layer comprises a conductive material, and the layer stack forms at least one quantum computing circuit component, preferably a ground plane, a resonator, a waveguide, and / or a qubit capacitor; Equipped with wherein the conductive material comprises tantalum nitride. Quantum computing device.

31. 26. The quantum computing device of claim 25, wherein the substrate layer is made of sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material, and / or the quantum computing circuitry comprises a qubit, preferably a superconducting qubit or a spin qubit.

32. 1. A method of manufacturing a quantum computing device, comprising: providing a substrate layer; depositing the patterned layer on top of the substrate layer using atomic layer deposition and / or sputtering with tantalum nitride, such that the patterned layer comprises tantalum nitride and forms at least one quantum computing circuit component, preferably a qubit, more preferably a superconducting qubit or a spin qubit, wherein preferably the substrate layer is made of sapphire, silicon, BeO, AlN, quartz, and / or any other dielectric material; A method for providing the above.

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