Cache-based memory access tracking

Abstract

An apparatus for executing a software program comprising: a processing unit, a plurality of memory components each connected to the processing unit and mapped to at least one range of memory addresses of a plurality of memory address ranges of the processing unit, and at least one memory tracking circuit connected to the processing unit and to the at least one memory component, the memory tracking circuit configured to: update at least one statistical counter of a plurality of statistical counters in response to receiving a memory access command from the processing unit at each iteration of the plurality of iterations, and provide one or more of the plurality of statistical counters to a memory management component for purposes of mapping an application memory of the software program to the at least one memory component.

Description

[Technical field]

[0001] The present disclosure relates to computerized devices, and more particularly, but not exclusively, to computerized devices having two or more memory components. [Background technology]

[0002] For simplicity, hereinafter the term "system" will be used to mean a computerized system, and these terms will be used interchangeably.

[0003] There are a myriad of metrics for measuring the performance of a computerized system, for example, throughput, i.e., the amount of tasks executed within a identified time interval, and latency, i.e., the amount of time a task is delayed before being executed. Improving the performance of a system, for example, by increasing the throughput of the system, and additionally or alternatively, by reducing the latency of the system, depends, among other factors, on the amount of computer resources available in the system and how well the various components of the system work together. For example, reducing the latency when accessing memory, and additionally or alternatively, increasing the throughput of memory accesses, can improve the performance of the system.

[0004] Memory components with relatively higher performance access characteristics, e.g., memory components with low latency or high throughput, e.g., static RAM (SRAM), are typically more expensive than memory components with lower performance access characteristics, e.g., dynamic RAM (DRAM). To balance the cost and performance of a system, it is common to design the memory of a system using two or more types of memory components. Some common system designs organize memory components in multiple tiers of memory, with smaller and faster tiers shadowing larger and slower tiers and acting as caches to the larger tiers. In some designs, there is a hierarchy of tiers, where only the largest tier is available for use by a software program, i.e., addressable using the software program's application memory address, and the other tiers in the hierarchy act as hierarchical caches.

[0005] Some other system designs make all layers of memory addressable using the software program's application memory address. In such systems, the performance of the system is affected by the distribution of the software program's application memory among multiple layers of memory, i.e., among one or more memory components of the system. When the software program's application memory comprises multiple application memory areas, performance can be improved when frequently accessed application memory areas are stored in one or more high performance memory components, while lower performance memory components are used to store less frequently accessed application memory areas.

[0006] The term non-uniform memory access (NUMA) refers to a computerized system having two or more memory components, where some characteristics of memory access from a processing unit to the memory components, e.g., latency, and additionally or alternatively, throughput, depend on the topology of the system, e.g., the location of the memory components relative to the processing units. In a manner similar to the systems described above, in a system with NUMA, the performance of the system may be affected by the distribution of a software program's application memory among one or more memory components. Summary of the Invention [Means for solving the problem]

[0007] The present disclosure includes a description of an apparatus and method for tracking memory access and managing memory. In some embodiments described herein, one or more memory tracking circuits are used to update at least one statistical counter of a plurality of statistical counters in response to receiving a memory access command from a processing unit. Furthermore, in such embodiments, the one or more memory tracking circuits are configured to provide one or more of the plurality of statistical counters to a memory management component for purposes of mapping an application memory of a software program to a plurality of memory components connected to the processing unit. Using one or more memory tracking circuits to update the at least one statistical counter reduces the amount of processing overhead required from the processing unit to track memory access and to manage the allocation of the application memory of the software program to the plurality of memory components, enhancing the performance of the apparatus.

[0008] These and other objects are achieved by the features of the independent claims. Further implementations are evident from the dependent claims, the description and the figures.

[0009] According to a first aspect, an apparatus for executing a software program comprises a processing unit, at least one memory component each connected to the processing unit and mapped to at least one range of memory addresses of a plurality of memory address ranges of the processing unit, and at least one memory tracking circuit connected to the processing unit and to the at least one memory component, wherein the at least one memory tracking circuit is configured to: update at least one statistical counter of a plurality of statistical counters in response to receiving a memory access command from the processing unit in each iteration of the plurality of iterations, and provide one or more of the plurality of statistical counters to a memory management component for purposes of mapping an application memory of the software program to the at least one memory component.

[0010] According to a second aspect, a method for managing memory in an apparatus for executing one or more software programs includes, in each iteration of a plurality of iterations, updating at least one statistical counter of a plurality of statistical counters in response to receiving a memory access command from the processing unit by at least one memory tracking circuit connected to the processing unit and to at least one memory component connected to the processing unit, each of the at least one memory component being mapped to at least one range of memory addresses of a plurality of memory address ranges of the processing unit, and providing one or more of the plurality of statistical counters to the memory management component for purposes of mapping application memory of the software programs to the at least one memory component.

[0011] According to a third aspect, a software program product for memory management comprises a non-transitory computer-readable storage medium and program instructions for receiving, in each management iteration of one or more management iterations, one or more of a plurality of statistical counters from at least one memory tracking circuit connected to a processing unit and to at least one memory component connected to the processing unit for purposes of mapping an application memory of the software program to the at least one memory component, each of the at least one memory component being mapped to at least one range of memory addresses of a plurality of memory address ranges of the processing unit. According to the third aspect, the program instructions are executed by at least one computerized processor from the non-transitory computer-readable storage medium.

[0012] According to a fourth aspect, a method for a memory management component includes, in each management iteration of one or more management iterations, receiving one or more of a plurality of statistical counters from a processing unit and from at least one memory tracking circuit connected to the at least one memory component connected to the processing unit, for purposes of mapping an application memory of a software program to the at least one memory component, wherein each of the at least one memory component is mapped to at least one range of memory addresses among a plurality of memory address ranges of the processing unit.

[0013] According to a fifth aspect, a memory tracking circuit comprising a plurality of statistical counters comprises a high access counter, a low access counter, and a plurality of range access counters. According to the fifth aspect, when the memory tracking circuit is connected to a processing unit and to at least one memory component each connected to the processing unit and mapped to at least one range of memory addresses of a plurality of memory address ranges of the processing unit, and when each of the plurality of range access counters is associated with one of the plurality of memory address ranges, the memory tracking circuit is configured to: in response to receiving a memory access command from the processing unit, identify a memory address in the memory access command, identify a memory address range of the plurality of memory address ranges, the memory address range comprising a memory address, increment a respective range access counter associated with the memory address range, increment the high access counter when the respective range access counter exceeds a high access threshold, and provide one or more of the plurality of statistical counters to a memory management component for purposes of mapping an application memory of a software program to the at least one memory component, in each iteration of the plurality of iterations.

[0014] In one implementation of the first and second aspects, the plurality of statistical counters comprises at least one watermark counter selected from the group consisting of a high access counter and a low access counter, and at least one of a plurality of range access counters each associated with one of a plurality of memory address ranges. Using the at least one watermark counter in addition to the plurality of range access counters reduces the amount of access to the plurality of range access counters and allows for a reduction in the amount of computing resources required for memory management compared to a method of accessing all of the plurality of range access counters. In some cases, at least one other of the plurality of statistical counters is implemented in at least one memory tracking circuit. Implementing the statistical counter in the memory tracking circuit reduces the amount of computing resources required to track one or more memory accesses compared to a method of implementing the statistical counter in a page table of an operating system executed by a processing unit executing a software program. In some cases, at least one other of the plurality of statistical counters is implemented in a cache memory component connected to one or more of the at least one memory component. In some cases, at least one other of the plurality of statistical counters is implemented in one of the at least one memory component.

[0015] In another implementation of the first and second aspects, updating the at least one statistical counter includes identifying a memory address in the memory access command, identifying a memory address range of a plurality of memory address ranges, the memory address range comprising the memory address, incrementing a respective range access counter, and incrementing the high access counter when the respective range access counter exceeds a high access threshold. Incrementing the high access counter when the respective range access counter associated with the memory address range exceeds a high access threshold reduces the amount of access to the plurality of range access counters and allows reducing the amount of computing resources required for memory management compared to accessing all of the plurality of range access counters. In some cases, providing the one or more statistical counters to the memory management component includes providing at least one watermark counter and providing at least one range access counter of the plurality of range access counters in response to a request from the memory management component. In some cases, the memory management component is configured to perform another analysis comprising the at least one watermark counter and send a request to at least one memory tracking circuit to provide at least one range access counter according to another result of the another analysis. Providing one or more statistical counters from the at least one memory tracking circuit to the memory management component in two or more steps and pursuant to performing the separate analysis includes mitigating an amount of accesses to the plurality of range access counters, reducing an amount of computing resources required for memory management compared to a method of accessing all of the plurality of range access counters, and reducing processing time, processing complexity, and an amount of accesses to the at least one memory tracking circuit. In some cases, the memory management component is further configured to set at least one of a low access threshold and a high access threshold within the at least one memory tracking circuit.In some cases, the memory management component sets at least one of the low access threshold and the high access threshold in the at least one memory tracking circuit according to yet another result of the yet another analysis comprising one or more statistical counters. Setting the low access threshold and, additionally or alternatively, the high access threshold increases the accuracy of the high access counter and the low access counter and increases the accuracy of the memory mapping calculated according to the one or more statistical counters.

[0016] In a further implementation of the first and second aspects, the at least one memory tracking circuit is configured to update at least one statistical counter while the processing unit executes the software program and to provide one or more of the plurality of statistical counters. Updating the at least one statistical counter while the processing unit executes the software program and providing the one or more statistical counters enables run-time modification of memory mapping of the software program's application memory while the software program is executed, enhancing system performance.

[0017] In a further implementation of the first and second aspects, the at least one memory tracking circuit comprises a plurality of local tracking circuits. In some cases, each of the plurality of local tracking circuits is connected to the processing unit and to one or more memory components of the at least one memory component, and each of the plurality of local tracking circuits updates at least one statistical counter in response to receiving a memory access command when at least one memory address range of the plurality of memory address ranges associated with the one or more memory components connected to the local tracking circuit comprises a local memory address that is the memory address in the memory address command. Using a plurality of local tracking circuits enhances the usability of the methods described herein in systems in which at least one memory component is topologically distant from each other.

[0018] In a further implementation of the first and second aspects, the application memory of the software program comprises a plurality of application memory areas each stored in one of the at least one memory components, and the mapping of the application memory by the memory management component includes performing an analysis comprising one or more statistical counters, and moving at least one of the plurality of application memory areas from one of the at least one memory components to another of the at least one memory components in response to a result of the analysis. In some cases, the memory mapping component maps the application memory while the processing unit executes the software program. Moving the application memory area from one memory component to another while the processing unit executes the software program reduces an overall amount of latency of memory accesses performed while executing the software program, and additionally or alternatively increases an overall bandwidth of the memory accesses, enabling an increase in performance of the device executing the software program. Performing the analysis comprising one or more statistical counters increases the accuracy of the results of the analysis, and moving at least one application memory area according to the results of the analysis increases the performance of the device executing the software program compared to other methods of selecting memory areas that do not comprise one or more statistical counters that are collected while the processing unit executes the software program, such as methods using static analysis of the software program.

[0019] In a further implementation of the first and second aspects, the at least one memory tracking circuit is further configured to perform a plurality of iterations including updating at least one statistical counter in each management iteration of the one or more management iterations, provide the one or more statistical counters to the memory management component, and reset one or more others of the plurality of statistical counters.

[0020] In a further implementation of the first and second aspects, the memory management component comprises a software object executed by the processing unit. In some cases, the memory management component comprises a memory management circuit connected to at least one memory tracking circuit and at least one memory component. Using the memory management circuit reduces the amount of computing resources of the processing unit required for memory management and reduces the impact of memory management on the performance of the device running the software program.

[0021] In a further implementation of the first and second aspects, the processing unit is configured to execute an operating system. In some cases, the operating system addresses at least one memory component using a plurality of operating system memory pages, each having a page size of an identified set of page sizes, and at least one identified memory address range of the plurality of memory address ranges has a range size that is not equal to any page size of the set of page sizes. Tracking memory address ranges that have a range size that is not equal to any page size of the set of page sizes of the operating system increases the accuracy of the analysis of one or more statistical counters, and thus increases the performance of the device executing the software program.

[0022] In one implementation of the fourth aspect, the plurality of statistical counters comprises a high access counter, a low access counter, and at least one of a plurality of range access counters each associated with one of a plurality of memory address ranges. In some cases, the step of receiving one or more statistical counters comprises a step of receiving at least one of the high access counter and the low access counter. In some cases, the method further comprises a step of performing an analysis comprising at least one of the low access counter and the high access counter, and a step of sending a request to at least one memory tracking circuit to provide at least one range access counter according to a result of the other analysis.

[0023] Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims.

[0024] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the implementation relates. Although methods and materials similar or equivalent to those described herein may be used in the practice or testing of the implementation, exemplary methods and / or materials are described below. In case of conflict, the present patent specification, including definitions, will control. Moreover, the materials, methods, and examples are illustrative only and are not necessarily intended to be limiting.

[0025] Some embodiments are described herein, by way of example only, with reference to the accompanying drawings. Referring now to the drawings in detail, it is stressed that the details shown are by way of example and for purposes of illustrative description of the embodiments. In this regard, the description taken together with the drawings will make apparent to those skilled in the art how the embodiments may be practiced.

[0026] In the drawings: [Brief description of the drawings]

[0027] [Figure 1] 1 is a schematic block diagram of an exemplary apparatus according to some embodiments. [Diagram 2] 1 is a schematic block diagram of another exemplary apparatus according to some embodiments. [Diagram 3] 1 is a schematic block diagram of an exemplary address mapping in accordance with some embodiments. [Figure 4] 1 is a flowchart that generally illustrates an optional flow of operations for managing memory, in accordance with some embodiments. [Diagram 5] 1 is a flowchart that generally illustrates an optional flow of operations for updating statistical counters, according to some embodiments. [Figure 6] 1 is a flowchart that generally illustrates an optional flow of operations for memory management, in accordance with some embodiments. [Figure 7] FIG. 2 is a sequence diagram of an optional flow of operations according to some embodiments. [Figure 8] 1 is a schematic block diagram of an exemplary memory mapping according to some embodiments. [Figure 9] 1 is a schematic block diagram of another example memory mapping according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The term "processing unit" as used herein refers to any type of programmable or non-programmable circuitry configured to perform the operations described below. A processing unit may comprise hardware as well as software. For example, a processing unit may comprise one or more processors and a temporary or non-transitory memory that carries a program that, when executed by the one or more processors, causes the processing unit to perform the respective operations.

[0029] Furthermore, as used herein, the term "physical address" refers to an address used by a processing unit in a memory access request to access a memory component. Furthermore, as used herein, the term "application address" refers to an address used in an application. The application address may be a virtual address, in which case the application address needs to be translated into a physical address in order to access one or more memory components. As used herein, the term "memory mapping" refers to mapping an application memory address of a software program to a physical address in a memory access request sent by a processing unit. Such mapping may be used to translate the application address into a physical address that identifies a location in a memory component where application data or instructions are stored.

[0030] Furthermore, as used herein, the terms "memory access request" and "memory access command" are both used to mean a request to access a memory component for the purposes of reading from, and additionally or alternatively, writing to, the memory component, and the terms are used interchangeably. Memory access requests may be generated when executing computer instructions of a software program that comprises memory access computer instructions.

[0031] Additionally, as used herein, the terms "memory address range" and "memory address range" are both used and are used interchangeably to mean a range of memory addresses.

[0032] In order to allocate each of a plurality of application memory areas to one or more memory components connected to a processing unit such that system performance is improved, some systems track accesses to the one or more memory components. Some existing tracking methods maintain access counters in a page table used to map application addresses to physical addresses. Such methods require updating the counters in the page table each time memory is accessed. Furthermore, analysis of the multiple counters in the page table requires merging counters of multiple virtual pages mapped to a common physical page. Some methods further require sorting the multiple counters to classify page table entries, for example, to identify page table entries that describe high-access application memory areas. Such methods require computing resources of the processing unit, thereby reducing system performance.

[0033] In some other methods of tracking memory accesses, the processing unit maintains multiple counters stored in one or more of the memory components. In systems implementing such methods, each memory access request from the processing unit requires two accesses from the processing unit to the memory, one to update the counters and another to access the data in the memory, reducing the effective throughput of the memory (i.e., accesses to application memory areas).

[0034] In order to reduce the amount of computing resources of a processing unit used to track multiple memory accesses, the present disclosure proposes, in some embodiments described herein, to use one or more memory management circuits connected to the processing unit and to one or more memory components to update at least one of multiple statistical counters in response to receiving a memory access command from the processing unit. In some cases, the statistical counter is indicative of the multiple memory access commands. For example, when the processing unit has multiple memory address ranges and each of the one or more memory components is mapped to one or more of the multiple memory address ranges, the statistical counter may be a range access counter associated with the memory address range that indicates the amount of time the memory address range is accessed in the multiple memory access commands. In some cases, the statistical counter indicates the amount of range access counters that meet an identified criterion. For example, the statistical counter may be a watermark counter that indicates the amount of range access counters that exceed a high access threshold, the high access threshold indicating the amount of accesses to the memory address range that is considered high. Alternatively, the watermark counter may indicate the amount of range access counters that are below a low access threshold, the low access threshold indicating another amount of accesses to the memory address range that is considered low. In some cases, the statistical counter indicates an amount of memory access commands received from the processing unit. In some cases, the one or more processing circuits receive the memory access commands in each of the multiple iterations and update at least one statistical counter of the multiple statistical counters in each of the multiple iterations. Updating the at least one statistical counter using the one or more processing circuits reduces an amount of resources used to track multiple memory accesses by the processing unit, e.g., reduces an amount of memory accesses performed by the processing unit, and additionally or alternatively reduces an amount of processor cycles of the processing unit used to calculate memory mapping.Reducing the amount of computing resources used by the processing unit increases the performance of the system when executing a software program, for example by increasing throughput and, additionally or alternatively, reducing latency when executing one or more tasks of the software program.

[0035] In some cases, at least one of the multiple statistical counters is implemented within one or more memory tracking circuits to further reduce the amount of accesses to one or more memory components, thus increasing the performance of the system.

[0036] Further, in some embodiments, the present disclosure proposes that one or more memory tracking circuits provide one or more of a plurality of statistical counters to a memory management component for the purpose of mapping an application memory of a software program to one or more memory components. In some cases, the memory management component performs an analysis of the one or more statistical counters for the purpose of mapping the application memory. In some cases, the memory management component comprises a software object executed by the processing unit. In some cases, the memory management component comprises other circuits, possibly connected to the one or more memory tracking circuits and the one or more memory components. Providing one or more of the statistical counters to the memory management component allows for improving system performance by moving one or more application memory areas of a plurality of application memory areas of a software program from one of the one or more memory components to another of the one or more memory components. For example, a range access counter for a range of memory addresses that exceeds a high access threshold may indicate that the range of memory addresses is accessed frequently, and the application memory area of ​​the plurality of application memory areas referenced by that range of memory addresses should be stored in a memory component that has relatively higher performance access characteristics, e.g., low latency, and additionally or alternatively high throughput. Similarly, a different range access counter for a different range of memory addresses below a low access threshold may indicate that the different range of memory addresses is accessed rarely, and that the different application memory areas of the plurality of application memory areas referenced by the different range of memory addresses should be stored in a different memory component having relatively lower performance access characteristics, e.g., higher latency, and additionally or alternatively lower throughput, than the memory component having the relatively higher performance access characteristics.In some cases, the memory mapping component maps application memory while the processing unit executes the software program, and in some cases moves one or more application memory areas while the processing unit executes the software program.

[0037] In some embodiments described herein, the at least one memory component is a plurality of memory components comprising at least two memory components. In some cases, the one or more memory tracking circuits comprise a plurality of local tracking circuits, such that each local tracking circuit of the plurality of local tracking circuits is connected to one or more of the plurality of memory components. In some cases, each local tracking circuit is connected to a subset of the plurality of memory components, such that the local tracking circuit is not connected to at least one of the plurality of memory components. In some cases, each local tracking circuit updates at least one statistical counter according to the one or more memory components connected thereto, i.e., in response to receiving a memory access command, when at least one memory address range of the plurality of memory address ranges associated with the one or more memory components connected to the local tracking circuit comprises a local memory address in the memory address command. When the processing unit is connected to the at least one memory component via a host memory controller, the local tracking circuit connected to the at least one memory component is optionally further connected to the host memory controller.

[0038] In some cases, when the one or more memory tracking circuits provide the one or more statistical counters to the memory management component, the one or more statistical counters comprise one or more watermark counters. In some cases, the memory management component performs another analysis of the one or more watermark counters, and according to the results of the another analysis, the memory management component sends a request to the one or more memory tracking circuits to provide at least one range access counter in some cases. For example, the memory management component may request at least one range access counter only when the results of the another analysis indicate that the high watermark counter exceeds an identified threshold. In this example, the memory area may not need to be moved as long as the amount of ranges subject to high access is below the threshold. This requires less computing resources compared to some other methods that require reading all multiple range access counters to identify that the memory area does not need to be moved. In another example, the memory management component may request one or more range access counters until it receives an amount of range access counters that exceeds a high watermark threshold equal to the high watermark counter. In this example, identifying all memory areas that experience high access rates can be accomplished without reading all multiple memory counters, requiring fewer computing resources than some other methods that do not use watermark counters.

[0039] When the processing unit executes an operating system, the operating system may address multiple memory components using multiple operating system memory pages. It is customary not to use any page size for the multiple operating system memory pages, i.e., each of the multiple operating system memory pages has one page size of the identified set of page sizes. When memory access tracking is performed using the operating system's page table, the granularity of the memory access tracking is according to the respective page size of each of the multiple operating system memory pages. In some embodiments described herein, at least one identified memory address range of the multiple memory address ranges has a range size that is not equal to any page size of the set of page sizes. Tracking multiple memory access commands according to multiple memory address ranges using one or more memory tracking circuits allows tracking multiple memory access commands at a granularity different from the operating system's page size and increasing the accuracy of memory mapping calculated according to multiple statistical counters compared to memory mapping calculated when tracking is according to the operating system page size, thus increasing the accuracy of allocation of multiple application memory areas to one or more memory components and increasing the performance of the system.

[0040] Before describing at least one embodiment in detail, it should be understood that the embodiments are not necessarily limited in their application to the details of construction and arrangement of components and / or methods set forth in the following description and / or illustrated in the drawings and / or examples. Implementations described herein are capable of other embodiments or of being practiced or carried out in various ways.

[0041] The embodiments may be systems, methods, and / or computer program products. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the embodiments.

[0042] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), static random access memories (SRAMs), portable compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, and any suitable combination of the above. A computer-readable storage medium as used herein should not be interpreted as being a transitory signal in itself, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a wave guide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electric signal transmitted through a wire.

[0043] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to the respective computing / processing device or to an external computer or storage device via a network, e.g., the Internet, a local area network, a wide area network, and / or a wireless network. The network may comprise copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage to a computer-readable storage medium in the respective computing / processing device.

[0044] The computer readable program instructions for carrying out the operations of the embodiments may be either source code or object code, natively compiled or just-in-time (JIT) compiled, written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, Java, object-oriented Fortran, interpreted programming languages ​​such as JavaScript, Python, and traditional procedural programming languages ​​such as the "C" programming language, Fortran, or similar programming languages. The computer readable program instructions may run entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be made to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer readable program instructions by utilizing state information of the computer readable program instructions to individualize the electronic circuitry to perform aspects of the embodiments.

[0045] Aspects of the embodiments are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to the embodiments. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0046] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions executing via the processor of the computer or other programmable data processing apparatus create means for performing the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions may also be stored in a computer readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions that perform aspects of the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0047] Computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be executed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device perform the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0048] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, comprising one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may be performed out of the order noted in the figures. For example, depending on the functionality involved, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in reverse order. It should also be noted that each block of the block diagrams and / or flowchart diagrams, as well as combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that executes the specified functions or operations, or a combination of dedicated hardware and computer instructions.

[0049] Reference is now made to Figure 1, which illustrates a schematic block diagram of an exemplary apparatus 100 according to some embodiments. In such an embodiment, a processing unit 101 is coupled to at least one memory component 120.

[0050] For brevity, hereafter, the term "memory component 120" is used to mean "at least one memory component 120," and these terms are used interchangeably. In some cases, memory component 120 comprises one memory component, e.g., memory component 120C. In some cases, memory component 120 comprises two or more memory components, e.g., memory component 120A, memory component 120B, and memory component 120C. The memory components may be random access memory (RAM) components, e.g., SRAM components or DRAM components. Other examples of memory components include read-only memory (ROM) components, electrically erasable programmable ROM (EEPROM), and non-volatile RAM (NVRAM). In some cases, one or more of memory components 120 are electrically coupled to processing unit 101. In some cases, one or more of memory components 120 are connected to processing unit 101 via a host memory controller (not shown).

[0051] In some cases, one or more of the memory components 120 are cache memory components of the processing unit 101. In some cases, one or more of the memory components 120 are connected to another cache memory component (not shown) that is further connected to the processing unit 101.

[0052] In some cases, one or more memory tracking circuits 130 are connected to the processing unit 101 and the memory component 120 .

[0053] Reference is now also made to FIG. 2, which illustrates a schematic block diagram of another exemplary apparatus 200 according to some embodiments. In such an embodiment, the one or more memory tracking circuits 130 comprise a plurality of local tracking circuits 201, for example comprising a local tracking circuit 201A and a local tracking circuit 201B. In some cases, each of the plurality of local tracking circuits 201 is connected to one or more of the memory components 120. In some cases, each of the plurality of local tracking circuits is connected to a subset of the memory components 120, such that each of the plurality of local tracking circuits 201 is not connected to at least one of the memory components 120. In this example, the local tracking circuit 201A is connected to the memory components 120A and 120B, and is not connected to the memory components 120C. Furthermore, in this example, the local tracking circuit 201B is connected to the memory components 120C, and is not connected to the memory components 120A and 120B. In some cases, each of the plurality of local tracking circuits 201 is connected to exactly one of the memory components 120.

[0054] Referring again now to Figure 1, in some cases, each of memory components 120 is mapped to at least one range of memory addresses among multiple memory address ranges of processing unit 101.

[0055] Reference is now also made to Figure 3, which illustrates a schematic block diagram of an exemplary address mapping 300 according to some embodiments. In this example, memory component 120A is mapped to memory address range 301A, memory address range 301B, and memory address range 301C of a plurality of memory address ranges 301. Thus, when processing unit 101 accesses a memory address in one of memory address range 301A, memory address range 301B, and memory address range 301C, processing unit 101 accesses the memory component.

[0056] Similarly, memory component 120B is mapped to memory address range 301D of multiple memory address ranges 301, and memory component 120C is mapped to memory address range 301E of multiple memory address ranges 301 and memory address range 301F.

[0057] In some cases, processing unit 101 executes an operating system that uses multiple operating system memory pages to address memory component 120. In some cases, each of the multiple operating system memory pages has a page size that is one page size of an identified set of page sizes. In some cases, at least one of the multiple memory address ranges 301 has a size that is not a member of the identified set of page sizes.

[0058] 1. In some cases, one or more memory tracking circuits 130 are coupled to memory management component 110. In some cases, memory management component 110 comprises a software object executed by processing unit 101. In some cases, memory management component 110 comprises a memory management circuit further coupled to processing unit 101 and memory component 120.

[0059] To track memory access commands and manage memory, any of the following methods may be implemented by system 100 or system 200 according to some embodiments.

[0060] Reference is now also made to FIG. 4, which shows a flow chart that generally illustrates an optional flow of operations 400 for managing memory, according to some embodiments. In such an embodiment, at 401, one or more memory tracking circuits 130 receive a memory access command from a processing unit 101, the memory access command comprising a memory address. In some cases, the memory address is in one of a plurality of memory address ranges 301. For example, when the memory address is within the range of memory addresses 301E, the memory address is a local memory address of memory component 120C. In this example, the range of memory addresses 301E comprises the local memory address of memory component 120C, the memory address in the memory access command. In some cases, processing unit 101 sends the memory access command when executing a software program, possibly for the purpose of accessing the application memory of the software program.

[0061] At 410, the one or more memory tracking circuits 130 optionally update at least one statistical counter of the multiple statistical counters. In some cases, the multiple statistical counters comprise multiple range access counters each associated with one of the multiple memory address ranges 301. In some cases, the multiple statistical counters comprise one or more watermark counters each associated with a frequency of access to the memory component. The watermark counter may indicate an amount of memory access ranges accessed at a frequency associated with the watermark counter. The watermark counter may be a high access counter indicating an amount of range access counters of the multiple range access counters that exceed a high access threshold, indicating frequent access to the respective memory component associated with the range access counter that exceeds the high access threshold. For example, a range access counter of the range of memory addresses 301F that exceeds a high access threshold may indicate frequent access to the memory component 120C associated with the range of memory addresses 301F. Another example of a watermark counter is a low access counter indicating an amount of range access counters of the multiple range access counters that exceed a low access threshold. There may be three or more watermark counters each associated with one of the multiple access frequencies to the memory component. Each watermark counter of the three or more watermark counters may be associated with an access threshold indicating an access frequency associated therewith, i.e., an amount of range access counters of the plurality of range access counters that exceed the threshold associated with the watermark counter.

[0062] In some cases, at least one of the plurality of statistical counters is implemented within one or more memory tracking circuits 130. In some cases, at least one other of the plurality of statistical counters is implemented within one of the memory components 120. In some cases, the one memory component that implements the at least one other statistical counter is a cache memory component of the processing unit 101. In some cases, at least one other of the plurality of statistical counters is implemented within another cache memory component connected to one or more of the memory components 120.

[0063] Reference is now also made to FIG. 5, which illustrates a flow chart that generally illustrates an optional flow of operations 500 for updating statistical counters, according to some embodiments. In such an embodiment, at 501, one or more memory tracking circuits 130 identify a memory address in a memory access command received at 401. At 502, one or more memory tracking circuits 130 optionally identify a memory address range of a plurality of memory address ranges 301, the memory address range comprising a memory address. For example, the memory command may comprise a memory address in a range of memory addresses 301F. In this example, one or more memory tracking circuits 130 identify the range of memory addresses 301F. Optionally, at 510, one or more memory tracking circuits 130 increment a respective range access counter of a plurality of range access counters associated with the range of memory addresses 301F. When the one or more memory tracking circuits 130 comprise multiple local tracking circuits 201, each local tracking circuit of the multiple local tracking circuits 201 updates at least one statistical counter when at least one memory address range of the multiple memory address ranges 301 associated with one or more memory components connected to the local tracking circuit comprises the memory address of a memory access command. For example, when the local tracking circuit 201B identifies that the memory address of the memory access command is within the range 301F of memory addresses associated with the memory component 120C connected to the local tracking circuit 201B, the local tracking circuit 201B may update one or more statistical counters.

[0064] At 520, the one or more memory tracking circuits 130 optionally determine whether a respective range access counter associated with the range of memory addresses 301F exceeds a low access threshold, and in accordance with a determination that a respective range access counter associated with the range of memory addresses 301F exceeds the low access threshold, at 521, the one or more memory tracking circuits 130 optionally decrement a low access counter. At 530, the one or more memory tracking circuits 130 optionally determine whether a respective range access counter associated with the range of memory addresses 301F exceeds a high access threshold, and in accordance with a determination that a respective range access counter associated with the range of memory addresses 301F exceeds the high access threshold, at 531, the one or more memory tracking circuits 130 optionally increment a high access counter. When the one or more watermark counters comprise three or more watermark counters, the one or more tracking circuits 130 optionally determine, for each of the three or more watermark counters, whether a respective range access counter associated with the range of memory addresses 301F exceeds a threshold associated with the watermark counter, and pursuant to a determination that a respective range access counter associated with the range of memory addresses 301F exceeds a threshold associated with the watermark counter, the one or more memory tracking circuits 130 optionally increment the watermark counter.

[0065] Reference is now made again to Figure 4. In some cases, the one or more memory tracking circuits 130 perform 401 and 410 while the processing unit 101 executes the software program. In some cases, the one or more memory tracking circuits 130 repeat 401 and 410 in each of multiple iterations.

[0066] At 420, the one or more memory tracking circuits 130 provide one or more of a plurality of statistical counters to the memory management component 110, possibly for purposes of mapping the application memory of the software program to the memory component 120. In some cases, the one or more memory tracking circuits 130 provide the one or more statistical counters while the processing unit 101 executes the software program. In some cases, the memory mapping component 110 maps the application memory to the memory component 120 while the processing unit 101 executes the software program.

[0067] Reference is now also made to Figure 6, which illustrates an optional flow of operations 600 for memory management, according to some embodiments. In such an embodiment, at 601, the memory management component 110 performs an analysis of one or more statistical counters. The following is an exemplary, but not required, way to perform the analysis.

[0068] Reference is now also made to FIG. 7, which illustrates a sequence diagram of an optional flow of operations 700 according to some embodiments. In such an embodiment, at 701, one or more memory tracking circuits 130 provide one or more watermark counters to the memory management component 110. In some cases, the one or more memory tracking circuits 130 provide a subset of the one or more watermark counters, e.g., only one of the one or more watermark counters, at 701. In some cases, the one or more watermark counters include a high access counter. In some cases, the one or more watermark counters include a low access counter. In 702, the one or more memory tracking circuits 130 perform another analysis comprising the one or more watermark counters. According to the results of the another analysis, at 710, the memory management component 110 sends a request to the one or more memory tracking circuits 130 to provide at least one range access counter of the plurality of range access counters, at 710. For example, when the results of the separate analysis indicate that the watermark counter exceeds the frequency threshold, the memory mapping component may request at least one range access counter to identify which of the multiple memory address ranges are frequently accessed. On the other hand, when the results of the separate analysis indicate that the watermark counter does not exceed the frequency threshold, the memory mapping component 110 may decline to perform the separate analysis and decline to change the mapping of the application memory of the software program. The separate analysis may use one of the one or more watermark counters, for example, when only one watermark counter is implemented. The separate analysis may use two or more of the one or more watermark counters. When the one or more watermark counters comprise at least one of a low access counter and a high access counter, the separate analysis may optionally comprise at least one of a low access counter and a high access counter.

[0069] In response to receiving a request from the memory management component 110, at 711, the one or more memory tracking circuits 130 optionally send at least one range access counter to the memory management component 110. In some cases, 710 and 711 are repeated in multiple read iterations. In some cases, at 711, the one or more memory tracking circuits 130 send one range access counter to the memory management component 110, causing the memory management component 110 to access the one or more range access counters one by one. In some cases, in each execution of 711, the one or more memory tracking circuits 130 send a subset of the multiple range access counters to the memory management component 110. In some cases, the management component 110 refuses to execute 710 pursuant to identifying a stop condition, e.g., receiving an amount of range access counters that exceeds a threshold equal to the value of the watermark counter provided in 701.

[0070] Reference is now also made to Figure 6. The memory management component 110 performs one or more memory management tasks, such as mapping application memory of the software program, possibly according to the results of the analysis performed in 601. Another example of a memory management task is to configure one or more memory tracking circuits 130.

[0071] Reference is now also made to FIG. 8, which illustrates a schematic block diagram of an exemplary memory mapping 800 according to some embodiments. In some cases, the application memory of a software program comprises multiple application memory areas 801, including, for example, memory application area 801A, memory application area 801B, and memory application area 801C. In some cases, each of the multiple memory application areas is stored in one of the memory components 120. For example, application memory area 801A may be stored in memory component 120A, application memory area 801B may be stored in memory component 120B, and application memory area 801C may be stored in memory component 120C.

[0072] Reference is now made again to Figure 6. At 610, in response to the analysis performed at 601 (e.g., using method 700), memory management component 110 may move one or more of the plurality of application memory areas 801 from one of memory components 120 to another of memory components 120.

[0073] Reference is now also made to FIG. 9, which illustrates a schematic block diagram of another exemplary memory mapping 900 according to some embodiments. In this example, for example, when memory component 120C has higher performance access characteristics than memory component 120A and the results of the analysis indicate high frequency access to application memory area 801A, the results of the analysis may be for memory management component 110 to move application memory area 801A from memory component 120A to memory component 120C. In some cases, memory management component 110 updates the mapping between application memory and one or more of the plurality of memory address ranges 301, for example, in a page table of an operating system executed by processing unit 101.

[0074] Reference is now made again to FIG. 7. At 721, memory management component 110 optionally sets one or more watermark thresholds in one or more memory tracking circuits 130, e.g., a high watermark threshold or a low watermark threshold. Optionally, at 720, memory management component 110 performs yet another analysis of one or more statistical counters and performs 721 according to yet another result of the yet another analysis. For example, when a memory component with high performance access characteristics is underused, memory management component 110 may lower the high watermark threshold. Similarly, when a memory component with high performance access characteristics is overworked, memory management component 110 may raise the high watermark threshold.

[0075] Reference is now made again to FIG. 4. At 430, the one or more memory tracking circuits 130 may possibly reset one or more other counters of the plurality of statistical counters. For example, the one or more memory tracking circuits 130 may reset the statistical counters after providing the statistical counters to the memory management component 110 at 420. Resetting the counters may be setting the counters to 0. Resetting the counters may be setting the counters to an initial value. For example, the low access counter may start with a value equal to the amount of memory components in the memory component 120 and be decremented at 521 for each range access counter that exceeds the low watermark threshold.

[0076] In some cases, the one or more memory tracking circuits 130 repeat performing multiple iterations including 401 and 410, providing one or more statistical counters at 420, and resetting one or more other counters in each of multiple management iterations.

[0077] The description of various embodiments has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will become apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over techniques found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0078] It is expected that many related memory tracking circuits will become developed during the life of the patent extending from this application, and the scope of the term memory tracking circuit is intended to include a priori all such new technologies.

[0079] As used herein, the term "about" refers to ±10%.

[0080] The terms "comprises," "comprising," "includes," "including," "having," and their cognates mean "including but not limited to." This term encompasses the terms "consisting of" and "consisting essentially of."

[0081] The phrase "consisting essentially of" means that the composition or method may include additional components and / or steps, but only if the additional components and / or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

[0082] As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" can include a plurality of compounds, including mixtures thereof.

[0083] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments and / or to exclude the incorporation of features from other embodiments.

[0084] The term "optionally" is used herein to mean "provided in some embodiments and not provided in other embodiments." Any particular embodiment may include multiple "optional" features, unless such features are inconsistent.

[0085] Throughout this application, various embodiments may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be interpreted as an inflexible limitation of the scope of the embodiments. Thus, the description of a range should be considered as specifically disclosing all possible subranges as well as individual numerical values ​​within that range. For example, the description of a range such as 1 to 6 should be considered as specifically disclosing subranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, and the individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

[0086] Whenever a numerical range is given herein, it is intended to include any of the preceding numbers (fractional or integer) within the given range. The phrases "ranging / ranges between" a first indicated number and a second indicated number, and "ranging / ranges from" a first indicated number and "to" a second indicated number are used interchangeably herein and are intended to include the first and second indicated numbers and all fractional and integer numbers therebetween.

[0087] It should be appreciated that some features of an embodiment that are described in the context of separate embodiments for clarity may also be provided in combination in a single embodiment. Conversely, various features of an embodiment that are described in the context of a single embodiment for brevity may also be provided separately or in any suitable subcombination, or as suitable in any other described embodiment. Some features described in the context of various embodiments should not be considered essential features of those embodiments, unless the embodiment is inoperable without those elements.

[0088] While the embodiments have been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications, and variations will become apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the spirit and broad scope of the appended claims.

[0089] It is the intention of the applicant that all publications, patents, and patent applications mentioned herein be incorporated herein by reference in their entirety as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated herein by reference. Furthermore, citation or identification of any reference in this application should not be construed as an admission that such reference is available as prior art to the present invention. To the extent that section headings are used, they should not necessarily be construed as limiting. Additionally, any priority documents of this application are incorporated herein by reference in their entirety. [Explanation of symbols]

[0090] 100, 200 Equipment, systems 101 Processing Unit 110 Memory management components, memory mapping components, management components 120, 120A, 120B, 120C Memory components 130 Memory tracking circuit, tracking circuit 201, 201A, 201B Local tracking circuit 300 Address Mapping 301 Memory Address Range 301A, 301B, 301C, 301D, 301E, 301F Memory Address Ranges 800, 900 memory mapping 801 Application Memory Area 801A, 801B, 801C Memory Application Area, Application Memory Area

Claims

1. 1. An apparatus for executing a software program, comprising: A processing unit; at least one memory component, each connected to the processing unit and mapped to at least one range of memory addresses of a plurality of memory address ranges of the processing unit; at least one memory tracking circuit coupled to the processing unit and to the at least one memory component; wherein the at least one memory tracking circuit comprises: updating at least one statistical counter of a plurality of statistical counters in response to receiving a memory access command from the processing unit at each iteration of the plurality of iterations; providing one or more of said plurality of statistical counters to a memory management component for purposes of mapping application memory of said software program to said at least one memory component; An apparatus configured to:

2. The plurality of statistical counters are at least one watermark counter selected from the group consisting of a high access counter and a low access counter; and a plurality of range access counters each associated with one of the plurality of memory address ranges; The apparatus of claim 1 , further comprising at least one of:

3. 3. The apparatus of claim 1 or 2, wherein at least one other of the plurality of statistical counters is implemented within the at least one memory tracking circuit.

4. 4. The apparatus of claim 1, wherein at least one and others of the plurality of statistical counters are implemented within a cache memory component connected to one or more of the at least one memory component.

5. 5. The apparatus of claim 1, wherein at least one further of the plurality of statistical counters is implemented within one of the at least one memory component.

6. the at least one memory trace circuit comprises a plurality of local trace circuits; each of the plurality of local tracking circuits is connected to the processing unit and to one or more memory components of the at least one memory component; 6. The apparatus of claim 1, wherein each local tracing circuit of the plurality of local tracing circuits updates the at least one statistical counter in response to receiving the memory access command when at least one memory address range of the plurality of memory address ranges associated with the one or more memory components connected to the local tracing circuit comprises a local memory address that is a memory address in the memory address command.

7. the application memory of the software program comprises a plurality of application memory areas, each stored in one of the at least one memory component; The mapping of the application memory by the memory management component comprises: performing an analysis comprising said one or more statistical counters; responsive to a result of said analyzing, migrating at least one application memory area of ​​said plurality of application memory areas from one of said at least one memory component to another of said at least one memory component; 7. The apparatus according to claim 1 , comprising:

8. The apparatus of claim 7 , wherein the memory mapping component maps the application memory while the processing unit executes the software program.

9. said at least one memory tracking circuit comprising: In each control iteration of the one or more control iterations, performing said multiple iterations, including updating said at least one statistical counter; providing said one or more statistical counters to said memory management component; resetting one or more others of said plurality of statistical counters; The apparatus of claim 1 , further configured to:

10. updating the at least one statistical counter identifying a memory address in the memory access command; identifying a memory address range of the plurality of memory address ranges, the memory address range comprising the memory address; incrementing the respective range access counter associated with the memory address range; incrementing said high access counter when said respective range access counter exceeds a high access threshold; 10. The apparatus according to claim 2, comprising:

11. providing the one or more statistical counters to the memory management component, providing said at least one watermark counter; providing at least one range access counter of the plurality of range access counters in response to a request from the memory management component; Including, said memory management component comprising: performing another analysis comprising said at least one watermark counter; and sending a request to the at least one memory tracking circuit to provide the at least one range access counter according to another result of the another analysis; The apparatus of claim 10 configured to:

12. 12. The apparatus of claim 10 or 11, wherein the memory management component is further configured to set at least one of the low access threshold and the high access threshold within the at least one memory tracking circuit.

13. 13. The apparatus of claim 12, wherein the memory management component sets at least one of the low access threshold and the high access threshold within the at least one memory tracking circuit according to a further result of a further analysis comprising the one or more statistical counters.

14. 14. The apparatus of claim 1, wherein the at least one memory tracking circuit is configured to update the at least one statistical counter while the processing unit executes the software program and to provide the one or more of the plurality of statistical counters.

15. The apparatus of claim 1 , wherein the memory management component comprises a software object executed by the processing unit.

16. 15. The apparatus of claim 1, wherein the memory management component comprises a memory management circuit connected to the at least one memory tracking circuit and the at least one memory component.

17. the processing unit is configured to execute an operating system; the operating system addresses the at least one memory component using a plurality of operating system memory pages, each having a page size of an identified set of page sizes; 17. The apparatus of claim 1, wherein at least one identified memory address range of the plurality of memory address ranges has a range size that is not equal to any page size of the set of page sizes.

18. 1. A method for managing memory in an apparatus for executing one or more software programs, comprising: updating, in each iteration of the plurality of iterations, by at least one memory tracking circuit coupled to a processing unit and to at least one memory component coupled to the processing unit, at least one statistical counter of a plurality of statistical counters in response to receiving a memory access command from the processing unit, wherein each of the at least one memory component is mapped to at least one range of memory addresses of a plurality of memory address ranges of the processing unit; providing one or more of said plurality of statistical counters to a memory management component for purposes of mapping application memory of a software program to said at least one memory component; A method comprising:

19. 1. A method for a memory management component, comprising: receiving, in each management iteration of the one or more management iterations, from at least one memory tracking circuit connected to the processing unit and to at least one memory component connected to the processing unit, one or more of a plurality of statistical counters for purposes of mapping application memory of a software program to the at least one memory component, each of the at least one memory component being mapped to at least one range of memory addresses of a plurality of memory address ranges of the processing unit; A method comprising:

20. the plurality of statistical counters comprises at least one of a high access counter, a low access counter, and a plurality of range access counters each associated with one of the plurality of memory address ranges; receiving the one or more statistical counters includes receiving at least one of the high access counter and the low access counter; The method further comprising: performing an analysis comprising at least one of the low access counter and the high access counter; sending a request to said at least one memory tracking circuit to provide said at least one range access counter according to the results of the other analysis; 20. The method of claim 19, further comprising:

21. 1. A software program product for memory management, comprising: a non-transitory computer readable storage medium; program instructions for receiving, in each management iteration of one or more management iterations, from a processing unit and from at least one memory tracking circuit connected to at least one memory component connected to said processing unit, one or more of a plurality of statistical counters for purposes of mapping application memory of a software program to said at least one memory component, each of said at least one memory component being mapped to at least one range of memory addresses of a plurality of memory address ranges of said processing unit; Equipped with A software program product, wherein the program instructions are executed by at least one computerized processor from the non-transitory computer-readable storage medium.

22. 1. A memory tracking circuit comprising a plurality of statistical counters, the plurality of statistical counters comprising: High access counter and Low access counter and Multiple range access counters and Equipped with when the memory tracking circuitry is connected to a processing unit and to at least one memory component each connected to the processing unit and mapped to at least one range of memory addresses among a plurality of memory address ranges of the processing unit, and when each of the plurality of range access counters is associated with one of the plurality of memory address ranges; in response to receiving a memory access command from the processing unit in each of the plurality of iterations, identifying a memory address in the memory access command; identifying a memory address range of the plurality of memory address ranges, the memory address range comprising the memory address; incrementing the respective range access counter associated with the memory address range; incrementing the high access counter when the respective range access counter exceeds a high access threshold; providing one or more of said plurality of statistical counters to a memory management component for purposes of mapping application memory of said software program to said at least one memory component; A memory tracking circuit configured to:

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