Display device

Abstract

A display device is provided, which includes: (1) a plurality of subpixels each including a first electrode and a second electrode spaced apart from each other, and a light-emitting element disposed on the first electrode and the second electrode and electrically connected to the first electrode and the second electrode, (2) a bank layer surrounding an area in which the light-emitting element of the subpixel is disposed, (3) a thermal control layer disposed so as to cover the light-emitting element and disposed in an area surrounded by the bank layer, (4) an upper bank layer disposed on the bank layer, and (5) a color control layer disposed on the thermal control layer and disposed in an area surrounded by the upper bank layer, the thermal control layer including (i) a resin layer, and (ii) phase transition particles dispersed in the resin layer, the phase transition particles including a core portion containing a phase transition material and a first shell surrounding the core portion.

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] Display devices have become increasingly important with the development of multimedia, and various types of display devices, such as organic light emitting displays (OLEDs) and liquid crystal displays (LCDs), are being used.

[0003] A self-luminous display device including light-emitting elements is an example of a device that displays an image on a display device. Self-luminous display devices include organic light-emitting display devices that use organic materials as light-emitting elements, inorganic light-emitting display devices that use inorganic materials as light-emitting elements, and the like. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of effectively controlling heat generated by a light emitting element.

[0005] The object of the present invention is not limited to the above-mentioned objects, and other technical objects not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] A display device according to one embodiment for solving the above problem includes: (1) a plurality of sub-pixels including a first electrode and a second electrode spaced apart from each other, and a light-emitting element disposed on the first electrode and the second electrode and electrically connected to the first electrode and the second electrode; (2) a bank layer surrounding an area in which the light-emitting element of the sub-pixel is disposed; (3) a thermal control layer disposed so as to cover the light-emitting element and disposed in an area surrounded by the bank layer; (4) an upper bank layer disposed on the bank layer; and (5) a color control layer disposed on the thermal control layer and disposed in an area surrounded by the upper bank layer, the thermal control layer including (i) a resin layer and (ii) a core portion including a phase transition material and a first shell surrounding the core portion, and phase transition particles dispersed in the resin layer.

[0007] The core portion may include at least one of dodecane, docosane, and an aluminum-silicon alloy, and the first shell may include at least one of polystyrene, polymethyl methacrylate, aluminum oxide, and polymethyl methacrylate-silica.

[0008] The phase change particle may further include a second shell surrounding the core and comprising a thermally conductive material, the first shell surrounding the second shell.

[0009] The second shell may include at least one of graphite, carbon black, and a conductive polymer.

[0010] The phase change particles may have a diameter of 1 μm or less.

[0011] The resin layer of the thermal control layer may include any one of an epoxy resin, an acrylic resin, a cardo resin, and an imide resin.

[0012] The thermal control layer may further include a scatterer.

[0013] The color control layer may have a thickness greater than a thickness of the thermal control layer.

[0014] The color control layer may have a thickness in the range of 8 μm to 10 μm, and the thermal control layer may have a thickness in the range of about 2 μm.

[0015] The semiconductor device may include a first insulating layer disposed on the first electrode and the second electrode, a second insulating layer disposed on the light-emitting element and the bank layer, and a third insulating layer disposed on the second insulating layer and the bank layer, and the bank layer may be disposed on the first insulating layer.

[0016] The height of the upper surface of the thermal control layer may be the same as or lower than the height of the upper surface of the third insulating layer disposed on the bank layer.

[0017] The height of the upper surface of the thermal control layer may be higher than the height of the upper surface of the third insulating layer disposed on the bank layer.

[0018] The thermal control layer may have a side surface that is partially in contact with the upper bank layer.

[0019] The thermal control layer may be partially disposed on the bank layer, and the color control layer and the upper bank layer may be disposed on the thermal control layer.

[0020] The color control layer may include (1) a first wavelength conversion layer disposed in a first subpixel and including first wavelength conversion particles, (2) a second wavelength conversion layer disposed in a second subpixel and including second wavelength conversion particles, and (3) a light-transmitting layer disposed in a third subpixel and including a scatterer, and the thermal control layer may be disposed between the first wavelength conversion layer, the second wavelength conversion layer, and the light-transmitting layer and the light-emitting element.

[0021] The light emitting device may include a first linking electrode in contact with the light emitting element and disposed on the first electrode, and a second linking electrode in contact with the light emitting element and disposed on the second electrode.

[0022] A display device according to one embodiment for solving the above problem includes: (1) a plurality of sub-pixels including a first electrode and a second electrode spaced apart from each other, and a light-emitting element disposed on the first electrode and the second electrode and electrically connected to the first electrode and the second electrode; (2) a bank layer surrounding an area in which the light-emitting element of the sub-pixel is disposed; (3) an upper bank layer disposed on the bank layer; and (4) a color control layer disposed on the light-emitting element and disposed in an area surrounded by the upper bank layer, the color control layer including: (i) a first wavelength conversion layer disposed in the first sub-pixel and including first wavelength conversion particles; (ii) a second wavelength conversion layer disposed in the second sub-pixel and including second wavelength conversion particles; and (iii) a light-transmitting layer disposed in the third sub-pixel and including a scatterer, the first wavelength conversion layer, the second wavelength conversion layer, and the light-transmitting layer including phase transition particles, the phase transition particles including a core portion including a phase transition material and a first shell surrounding the core portion.

[0023] The core portion may include at least one of dodecane, docosane, and an aluminum-silicon alloy, and the first shell may include at least one of polystyrene, polymethyl methacrylate, aluminum oxide, and polymethyl methacrylate-silica.

[0024] The phase change particle may further include a second shell surrounding the core and comprising a thermally conductive material, the first shell surrounding the second shell.

[0025] The phase change particles may have a diameter of 1 μm or less.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effect of the Invention

[0027] According to an embodiment, the display device may include a thermal control layer disposed between the light emitting element and the color control layer. The thermal control layer may include a phase transition material and may effectively control heat generated by the light emitting element.

[0028] Therefore, the display device can reduce thermal deformation of the color control layer due to heat generated by the light emitting device, thereby improving the product quality and lifespan of the display device.

[0029] The effects of the embodiments are not limited to the above-mentioned examples, and more diverse effects are included in the present specification. [Brief description of the drawings]

[0030] [Figure 1] 1 is a schematic plan view of a display device according to an embodiment; [Diagram 2] 1 is a plan view illustrating an arrangement of a number of wirings included in a display device according to an embodiment; [Diagram 3] 1 is an equivalent circuit diagram of a sub-pixel of a display device according to an embodiment. [Figure 4] 1 is an equivalent circuit diagram of a sub-pixel of a display device according to an embodiment. [Diagram 5] 1 is a plan view of one pixel of a display device according to an embodiment. [Figure 6] 6 is a cross-sectional view taken along line N1-N1' in FIG. 5. [Figure 7] 6 is a cross-sectional view taken along line N2-N2' in FIG. 5. [Figure 8] 6 is a cross-sectional view taken along line N3-N3' in FIG. 5. [Figure 9] 2 is a cross-sectional view showing a color control layer and a thermal control layer disposed in one pixel of a display device according to an embodiment. [Figure 10] 10 is a cross-sectional view showing a first wavelength conversion layer and a thermal control layer of the first sub-pixel of FIG. 9. [Figure 11] 1 is a schematic diagram illustrating phase change particles included in a thermal control layer of a display device according to an embodiment. [Figure 12] 11 is a schematic diagram illustrating phase change particles included in a thermal control layer of a display device according to another embodiment. [Figure 13] 1 is a schematic diagram of a light-emitting device according to one embodiment. [Figure 14]FIG. 11 is a cross-sectional view showing a wavelength conversion layer and a thermal control layer of a subpixel of a display device according to another embodiment. [Figure 15] FIG. 11 is a cross-sectional view showing a color control layer and a thermal control layer disposed in one pixel according to another embodiment. [Figure 16] FIG. 11 is a cross-sectional view showing a color control layer and a thermal control layer disposed in one pixel according to another embodiment. [Figure 17] FIG. 11 is a cross-sectional view showing a wavelength conversion layer and a thermal control layer of a subpixel of a display device according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The advantages and features of the present invention, as well as the methods for achieving the same, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be realized in various different forms. The present embodiments are provided merely to complete the disclosure of the present invention and to fully inform those skilled in the art of the invention of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0032] When an element or layer is referred to as "on" another element or layer, this includes all cases where it is directly on top of or has other layers or elements intervening. Similarly, when it is referred to as "below," "left," and "right," this includes all cases where it is directly adjacent to another element or has other layers or materials intervening. Like reference numbers refer to like elements throughout the specification.

[0033] Although the terms "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that the first component referred to below may be the second component within the technical concept of the present invention.

[0034] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0035] FIG. 1 is a schematic plan view of a display device according to an embodiment.

[0036] 1, a display device 10 displays moving images or still images. The display device 10 refers to any electronic device that provides a display screen. For example, the display device 10 may include a television, a notebook computer, a monitor, a billboard, the Internet of Things, a mobile phone, a smartphone, a tablet PC (Personal Computer), an electronic watch, a smart watch, a watch phone, a head mounted display, a mobile communication terminal, an electronic organizer, an electronic book, a PMP (Portable Multimedia Player), a navigation system, a game console, a digital camera, a camcorder, and the like that provide a display screen.

[0037] The display device 10 includes a display panel that provides a display screen. Examples of the display panel include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, a field emission display panel, etc. In the following, an inorganic light emitting diode display panel is used as an example of the display panel, but the present invention is not limited thereto and may be applied to other display panels as long as the same technical concept can be applied.

[0038] The shape of the display device 10 may be modified in various ways. For example, the display device 10 may have a shape such as a rectangle with a long width, a rectangle with a long height, a square, a rectangle with rounded corners (apexes), other polygons, a circle, etc. The shape of the display area DPA of the display device 10 may also be similar to the general shape of the display device 10. FIG. 1 illustrates a display device 10 having a rectangular shape with a long length in the second direction DR2.

[0039] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA is an area where a screen is displayed, and the non-display area NDA is an area where a screen is not displayed. The display area DPA may be referred to as an active area, and the non-display area NDA may be referred to as a non-active area. The display area DPA generally occupies the center of the display device 10.

[0040] The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a row and column direction. The shape of each pixel PX may be, but is not limited to, a rectangular or square shape in a plan view, and may be a rhombus shape with each side tilted in one direction. The pixels PX may be arranged in a stripe or island shape. Each pixel PX may include one or more light-emitting elements that emit light in a specific wavelength band, thereby displaying a specific color.

[0041] A non-display area NDA may be arranged around the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may have a rectangular shape, and the non-display area NDA may be arranged adjacent to the four sides of the display area DPA. The non-display area NDA may form a bezel of the display device 10. In each non-display area NDA, wiring or a circuit driver included in the display device 10 may be arranged, or an external device may be mounted.

[0042] FIG. 2 is a plan view showing an arrangement of a plurality of wirings included in a display device according to an embodiment.

[0043] Referring to FIG. 2, the display device 10 may include a plurality of wirings. The display device 10 may include a plurality of scan lines (SL; SL1, SL2, SL3), a plurality of data lines (DTL; DTL1, DTL2, DTL3), an initialization voltage wiring VIL, and a plurality of voltage wirings (VL; VL1, VL2, VL3, VL4). Although not shown in the drawing, other wirings may be further disposed in the display device 10. The plurality of wirings may include a wiring made of a first conductive layer and extending in a first direction DR1, and a wiring made of a third conductive layer and extending in a second direction DR2. However, the extension direction of each wiring is not limited thereto.

[0044] The first scan line SL1 and the second scan line SL2 may be arranged to extend in a first direction DR1. The first scan line SL1 and the second scan line SL2 may be arranged adjacent to each other and spaced apart from the other first scan line SL1 and second scan line SL2 in the second direction DR2. The first scan line SL1 and the second scan line SL2 may be connected to a scan wiring pad WPD_SC connected to a scan driver (not shown). The first scan line SL1 and the second scan line SL2 may be arranged to extend from a pad area PDA arranged in the non-display area NDA to a display area DPA.

[0045] The third scan lines SL3 may be arranged to extend in the second direction DR2 and spaced apart from other third scan lines SL3 in the first direction DR1. One third scan line SL3 may be connected to one or more first scan lines SL1 or one or more second scan lines SL2. The plurality of scan lines SL may have a mesh structure over the entire display area DPA, but is not limited thereto.

[0046] The data lines DTL may be arranged to extend in a first direction DR1. The data lines DTL include a first data line DTL1, a second data line DTL2, and a third data line DTL3, and each of the first to third data lines DTL1, DTL2, and DTL3 forms a pair and is arranged adjacent to each other. Each of the data lines DTL1, DTL2, and DTL3 may be arranged to extend from a pad area PDA arranged in a non-display area NDA to a display area DPA. However, without being limited thereto, the multiple data lines DTL may be arranged at equal intervals between a first voltage line VL1 and a second voltage line VL2 described later.

[0047] The initialization voltage wiring VIL may be arranged to extend in the first direction DR1. The initialization voltage wiring VIL may be arranged between the data line DTL and the first voltage wiring VL1. The initialization voltage wiring VIL may be arranged to extend from the pad area PDA arranged in the non-display area NDA to the display area DPA.

[0048] The first voltage wiring VL1 and the second voltage wiring VL2 are arranged to extend in the first direction DR1, and the third voltage wiring VL3 and the fourth voltage wiring VL4 are arranged to extend in the second direction DR2. The first voltage wiring VL1 and the second voltage wiring VL2 may be arranged alternately in the second direction DR2, and the third voltage wiring VL3 and the fourth voltage wiring VL4 may be arranged alternately in the first direction DR1. The first voltage wiring VL1 and the second voltage wiring VL2 are arranged to extend in the first direction DR1 and cross the display area DPA, and the third voltage wiring VL3 and the fourth voltage wiring VL4 may each have a part of wiring arranged in the display area DPA and the other wiring arranged in the non-display area NDA located on both sides of the first direction DR1 of the display area DPA. The multiple voltage wirings VL may have a mesh structure over the entire surface of the display area DPA. However, this is not limited thereto.

[0049] The first scan line SL1, the second scan line SL2, the data line DTL, the initialization voltage line VIL, the first voltage line VL1, and the second voltage line VL2 may be electrically connected to at least one wiring pad WPD. Each wiring pad WPD may be disposed in a non-display area NDA. In one embodiment, each wiring pad WPD may be disposed in a pad area PDA located on the other side of the display area DPA in the first direction DR1, i.e., the lower side. The first scan line SL1 and the second scan line SL2 are connected to a scan wiring pad WPD_SC disposed in the pad area PDA, and the data lines DTL are connected to different data wiring pads WPD_DT. The initialization voltage line VIL is connected to an initialization wiring pad WPD_Vint, the first voltage line VL1 is connected to a first voltage wiring pad WPD_VL1, and the second voltage line VL2 is connected to a second voltage wiring pad WPD_VL2. An external device may be mounted on the wiring pad WPD. An external device may be mounted on the wiring pads WPD by anisotropic conductive film, ultrasonic bonding, etc. In the drawings, the wiring pads WPD are illustrated as being arranged in a pad area PDA arranged below the display area DPA, but are not limited thereto. Some of the wiring pads WPD may be arranged in one of the areas above, on the left or right side of the display area DPA.

[0050] Each pixel PX or sub-pixel (SPXn, n is an integer from 1 to 3) of the display device 10 includes a pixel driving circuit. The above-mentioned wiring may pass through or around each pixel PX and apply a driving signal to each pixel driving circuit. The pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors in each pixel driving circuit may be variously modified. According to an embodiment, each sub-pixel SPXn of the display device 10 may have a 3T1C structure in which the pixel driving circuit includes three transistors and one capacitor. Hereinafter, the pixel driving circuit will be described using a 3T1C structure as an example, but the present invention is not limited thereto, and various other modified structures such as a 2T1C structure, a 7T1C structure, and a 6T1C structure may also be applied.

[0051] 3 and 4 are equivalent circuit diagrams of one sub-pixel of a display device according to an embodiment.

[0052] Referring to FIG. 3, each sub-pixel SPXn of the display device 10 according to the embodiment includes three transistors T1, T2, T3 and one storage capacitor Cst in addition to a light emitting diode EL.

[0053] The light emitting diode EL emits light in response to a current supplied through the first transistor T1. The light emitting diode EL includes a first electrode, a second electrode, and at least one light emitting element disposed therebetween. The light emitting element can emit light of a specific wavelength band in response to an electrical signal transmitted from the first electrode and the second electrode.

[0054] One end of the light emitting diode EL is connected to the source electrode of the first transistor T1, and the other end is connected to a second voltage line VL2 to which a low potential voltage (hereinafter, a second power supply voltage) lower than the high potential voltage (hereinafter, a first power supply voltage) of the first voltage line VL1 is supplied.

[0055] The first transistor T1 adjusts a current flowing from a first voltage line VL1 to which a first power supply voltage is supplied to the light emitting diode EL according to a voltage difference between the gate electrode and the source electrode. As an example, the first transistor T1 may be a driving transistor for driving the light emitting diode EL. The gate electrode of the first transistor T1 may be connected to a source electrode of the second transistor T2, the source electrode may be connected to a first electrode of the light emitting diode EL, and the drain electrode may be connected to the first voltage line VL1 to which the first power supply voltage is applied.

[0056] The second transistor T2 is turned on by a scan signal of the scan line SL to connect the data line DTL to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the scan line SL, the source electrode may be connected to the gate electrode of the first transistor T1, and the drain electrode may be connected to the data line DTL.

[0057] The third transistor T3 is turned on by a scan signal of the scan line SL to connect the initialization voltage line VIL to one end of the light emitting diode EL. The gate electrode of the third transistor T3 is connected to the scan line SL, the drain electrode is connected to the initialization voltage line VIL, and the source electrode is connected to one end of the light emitting diode EL or the source electrode of the first transistor T1.

[0058] In one embodiment, the source electrode and the drain electrode of each of the transistors T1, T2, and T3 are not limited to the above, and may be the opposite. Each of the transistors T1, T2, and T3 may be formed of a thin film transistor. Although FIG. 3 mainly describes the case where each of the transistors T1, T2, and T3 is formed of an N-type metal oxide semiconductor field effect transistor (MOSFET), the present invention is not limited thereto. That is, each of the transistors T1, T2, and T3 may be formed of a P-type MOSFET, or some of the transistors may be formed of an N-type MOSFET and the other part of the transistors may be formed of a P-type MOSFET.

[0059] The storage capacitor Cst is formed between the gate electrode and the source electrode of the first transistor T1, and stores a difference voltage between the gate voltage and the source voltage of the first transistor T1.

[0060] 3, the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3 may be connected to the same scan line SL3, and the second transistor T2 and the third transistor T3 may be turned on by a scan signal applied from the same scan line, but are not limited thereto.

[0061] 4, the gate electrodes of the second transistor T2 and the third transistor T3 may be connected to different scan lines SL1 and SL2. For example, the gate electrode of the second transistor T2 may be electrically connected to the first scan line SL1, and the gate electrode of the third transistor T3 may be electrically connected to the second scan line SL2. The second transistor T2 and the third transistor T3 may be simultaneously turned on by scan signals applied from different scan lines.

[0062] The structure of one pixel PX of the display device 10 according to an embodiment will be described in detail below with further reference to other drawings.

[0063] FIG. 5 is a plan view of one pixel of a display device according to an embodiment.

[0064] Figure 5 shows the planar arrangement of electrodes (RME: RME1, RME2), partitions BP1, BP2 and a bank layer BNL, multiple light-emitting elements (ED: ED1, ED2), and connecting electrodes (CNE: CNE1, CNE2, CNE3) arranged in one pixel PX of the display device 10.

[0065] Referring to FIG. 5, each pixel PX of the display device 10 may include a plurality of subpixels SPXn. For example, one pixel PX may include a first subpixel SPX1, a second subpixel SPX2, and a third subpixel SPX3. The first subpixel SPX1 may emit light of a first color, the second subpixel SPX2 may emit light of a second color, and the third subpixel SPX3 may emit light of a third color. As an example, the first color may be blue, the second color may be green, and the third color may be red. However, the present invention is not limited thereto, and each subpixel SPXn may emit light of the same color. In an embodiment, each subpixel SPXn may emit blue light. In the drawings, a case in which one pixel PX includes three subpixels SPXn is illustrated, but the present invention is not limited thereto, and the pixel PX may include a greater number of subpixels SPXn.

[0066] Each sub-pixel SPXn of the display device 10 may include a light-emitting area EMA and a non-light-emitting area. The light-emitting area EMA may be an area in which the light-emitting element ED is arranged and in which light of a specific wavelength band is emitted. The non-light-emitting area may be an area in which the light-emitting element ED is not arranged and light emitted from the light-emitting element ED does not reach, and thus no light is emitted.

[0067] The light emitting region EMA may include a region in which the light emitting element ED is arranged and a region adjacent to the light emitting element ED where light emitted from the light emitting element ED is output. For example, the light emitting region EMA may also include a region in which the light emitted from the light emitting element ED is reflected or refracted by another member and output. A plurality of light emitting elements ED are arranged in each sub-pixel SPXn, and the region in which they are arranged and the region adjacent thereto may form a light emitting region.

[0068] In the drawings, the light emitting regions EMA of the sub-pixels SPXn are illustrated as having a uniform area, but are not limited thereto. In some embodiments, the light emitting regions EMA of the sub-pixels SPXn may have different areas depending on the color or wavelength band of light emitted from the light emitting element ED disposed in the corresponding sub-pixel.

[0069] Each sub-pixel SPXn may further include sub-regions SA1 and SA2 arranged in a non-light-emitting region. The sub-regions SA1 and SA2 may include a first sub-region SA1 arranged on one side of the light-emitting region EMA in the first direction DR1, and a second sub-region SA2 arranged on the other side of the light-emitting region EMA in the first direction DR1, which is a lower side. The light-emitting region EMA and the sub-regions SA1 and SA2 are alternately arranged in the first direction DR1 according to the arrangement of the pixels PX and the sub-pixels SPXn, and the first sub-region SA1 or the second sub-region SA2 may be arranged between the different light-emitting regions EMA spaced apart in the first direction DR1. For example, the plurality of light-emitting regions EMA may be repeatedly arranged in the first direction DR1 with the first sub-region SA1 or the second sub-region SA2 interposed therebetween. The plurality of light-emitting regions EMA, the first sub-region SA1, and the second sub-region SA2 may be repeatedly arranged in the second direction DR2. The first sub-region SA1 and the second sub-region SA2 may be regions divided by the arrangement of the wiring connection electrode EP and the electrode RME described later, but are not limited thereto, and the light emitting region EMA and the sub-regions SA1 and SA2 in the plurality of pixels PX may have an arrangement different from that shown in FIG.

[0070] The first sub-region SA1 and the second sub-region SA2 may be regions shared by the sub-pixels SPXn adjacent to each other in the first direction DR1. For example, the second sub-region SA2 shown in FIG. 5 may be shared by the sub-pixels SPXn shown in the drawings and the sub-pixels SPXn adjacent to each other in the first direction DR1 not shown in the drawings. The sub-pixels SPXn shown in the drawings may be sub-pixels in which the first sub-region SA1 is disposed above the light-emitting region EMA, and the sub-pixels SPXn adjacent to each other in the first direction DR1 may be sub-pixels in which the second sub-region SA2 is disposed above the light-emitting region EMA.

[0071] Since the light-emitting element ED is not arranged in the sub-regions SA1 and SA2, light is not emitted therefrom, but a part of the electrode RME arranged in each sub-pixel SPXn may be arranged therein. The electrodes RME arranged in different sub-pixels SPXn may be arranged to be separated from each other by separation parts ROP1 and ROP2 of the sub-regions SA1 and SA2.

[0072] The display device 10 may include a plurality of electrodes RME1, RME2, barrier ribs BP1, BP2, a bank layer BNL, a light emitting element ED, and connecting electrodes CNE1, CNE2, and CNE3.

[0073] A plurality of partitions BP1 and BP2 may be disposed in the light emitting area EMA of each sub-pixel SPXn. The partitions BP1 and BP2 may extend generally in a first direction DR1 and be spaced apart from each other in a second direction DR2.

[0074] For example, the partitions BP1 and BP2 may include a first partition BP1 and a second partition BP2 spaced apart from each other in the second direction DR2 in the light-emitting region EMA of each sub-pixel SPXn. The first partition BP1 may be disposed at the center of the light-emitting region EMA, and the second partition BP2 may be disposed spaced apart from the first partition BP1. The first partition BP1 and the second partition BP2 may be alternately disposed along the second direction DR2 and may be disposed in an island pattern in the display region DPA. A plurality of light-emitting elements ED may be disposed between the first partition BP1 and the second partition BP2.

[0075] The second partition BP2 has a larger width measured in the second direction DR2 than the first partition BP1. The first partition BP1 is disposed in the light emitting region EMA of each sub-pixel SPXn, whereas the second partition BP2 may be disposed across the light emitting regions EMA of two sub-pixels SPXn adjacent to each other in the second direction DR2. The second partition BP2 is disposed across the boundary between the sub-pixels SPXn adjacent to each other in the second direction DR2, and may overlap with a bank layer BNL, which will be described later. However, without being limited thereto, the first partition BP1 and the second partition BP2 may have the same width.

[0076] The partitions BP1 and BP2 may have the same length in the first direction DR1 and may be greater than the length in the first direction DR1 of the light-emitting region EMA surrounded by the bank layer BNL. The partitions BP1 and BP2 may overlap with a portion of the bank layer BNL extending in the second direction DR2. However, this is not limited thereto, and the partitions BP1 and BP2 may be integrated with the bank layer BNL or separated from the portion of the bank layer BNL extending in the second direction DR2. In this case, the length in the first direction DR1 of the partitions BP1 and BP2 may be the same as or smaller than the length in the first direction DR1 of the light-emitting region EMA surrounded by the bank layer BNL.

[0077] In the drawings, one first barrier rib BP1 and two second barrier ribs BP2 are partially arranged for each sub-pixel SPXn, but the present invention is not limited thereto. The number and shape of the barrier ribs BP1 and BP2 may vary depending on the number or arrangement of the electrodes RME.

[0078] The electrodes RME1, RME2 are arranged for each sub-pixel SPXn in a shape extending in one direction. The electrodes RME1, RME2 extend in the first direction DR1 and are arranged in the light-emitting region EMA and sub-regions SA1, SA2 of the sub-pixel SPXn, and may be arranged spaced apart from each other in the second direction DR2. The electrodes RME1, RME2 may be electrically connected to the light-emitting element ED described below. However, the present invention is not limited to this, and the electrode RME may not be electrically connected to the light-emitting element ED.

[0079] The display device 10 may include a first electrode RME1 disposed at the center of each subpixel SPXn, and a second electrode RME2 disposed across different subpixels SPXn. The first electrode RME1 and the second electrode RME2 may have shapes generally extending in a first direction DR1, and the shapes of the portions disposed in the light-emitting region EMA may differ from each other. The first electrode RME1 may be disposed adjacent to the center of the subpixel SPXn, and may be disposed across the light-emitting region EMA and the subregions SA1 and SA2. The second electrode RME2 may be spaced apart from the first electrode RME1 in the second direction DR2 in the light-emitting region EMA, and may be disposed across a plurality of subpixels SPXn. The first electrode RME1 and the second electrode RME2 may have shapes generally extending in the first direction DR1, and the length of extension in the first direction DR1 and the shapes of the portions disposed in the light-emitting region EMA may differ from each other.

[0080] The first electrode RME1 may be disposed at the center of the sub-pixel SPXn, and a portion disposed in the light-emitting region EMA may be disposed on the first partition BP1. The first electrode RME1 may extend from the first sub-region SA1 in the first direction DR1 to the second sub-region SA2. The first electrode RME1 may have a shape in which the width measured in the second direction DR2 varies depending on the position, and at least a portion overlapping with the first partition BP1 in the light-emitting region EMA may be wider than the first partition BP1.

[0081] The second electrode RME2 may include a portion extending in the first direction DR1 and a portion branched at the light emitting region EMA. In one embodiment, the second electrode RME2 may include an electrode stem RM_S extending in the first direction DR1, and electrode branch portions RM_B1 and RM_B2 branching from the electrode stem RM_S, bending in the second direction DR2, and then extending again in the first direction DR1. The electrode stem RM_S may be arranged to overlap with the portion of the bank layer BNL extending in the first direction DR1, and may be arranged on one side of the sub-region SA in the second direction DR2. The electrode branch portions RM_B1 and RM_B2 branch at the electrode stem RM_S arranged at the portion of the bank layer BNL extending in the first direction DR1, and are bent to both sides of each other in the second direction DR2. The electrode branch portions RM_B1 and RM_B2 may be arranged across the light emitting region EMA in the first direction DR1, and be bent again to be connected to the electrode stem RM_S. For example, the electrode branch portions RM_B1 and RM_B2 of the second electrode RME2 may branch off above the light emitting area EMA of any one of the sub-pixels SPXn and be connected to each other again below the light emitting area EMA.

[0082] The second electrode RME2 may include a first electrode branch portion RM_B1 disposed on the left side of the first electrode RME1 and a second electrode branch portion RM_B2 disposed on the right side of the first electrode RME1. The electrode branches RM_B1 and RM_B2 included in one second electrode RME2 are respectively disposed in the light emitting regions EMA of the sub-pixels SPXn adjacent to each other in the second direction DR2, and different electrode branches RM_B1 and RM_B2 of the second electrode RME2 may be disposed in one sub-pixel SPXn. Based on the first electrode RME1, the first electrode branch portion RM_B1 of the second electrode RME2 may be disposed on the left side thereof, and the second electrode branch portion RM_B2 of the other second electrode RME2 may be disposed on the right side of the first electrode RME1.

[0083] Each of the electrode branches RM_B1, RM_B2 of the second electrode RME2 may overlap one side of the second partition BP2. The first electrode branch RM_B1 may partially overlap the second partition BP2 disposed on the left side of the first partition BP1, and the second electrode branch RM_B2 may partially overlap the second partition BP2 disposed on the right side of the first partition BP1. Both sides of the first electrode RME1 may face, at a distance, different electrode branches RM_B1, RM_B2 of the different second electrode RME2, and the distance between the first electrode RME1 and each of the electrode branches RM_B1, RM_B2 may be smaller than the distance between the different partitions BP1, BP2.

[0084] The width of the first electrode RME1 measured in the second direction DR2 may be greater than the widths of the electrode trunk RM_S and the electrode branch portions RM_B1, RM_B2 of the second electrode RME2. The first electrode RME1 has a width greater than the first barrier rib BP1 and overlaps both sides, whereas the second electrode RME2 has a relatively small width such that the electrode branch portions RM_B1, RM_B2 overlap only one side of the second barrier rib BP2.

[0085] Of the first electrode RME1 and the second electrode RME2, the first electrode RME1 is arranged to extend to the first separation portion ROP1 of the first sub-region SA1 and the second separation portion ROP2 of the second sub-region SA2, whereas the second electrode RME2 may not be separated from the sub-regions SA1 and SA2. One second electrode RME2 may include a plurality of electrode trunk portions RM_S and electrode branch portions RM_B1 and RM_B2, and may have a shape extending in the first direction DR1 and branching in the vicinity of the light-emitting region EMA of each sub-pixel SPXn. The first electrode RME1 may be arranged between the separation portions ROP1 and ROP2 arranged in different sub-regions SA1 and SA2 of each sub-pixel SPXn, and may be arranged across the light-emitting region EMA.

[0086] The display device 10 may include a wiring connection electrode EP disposed in a first sub-region SA1 among a plurality of sub-regions SA1 and SA2 of each sub-pixel SPXn and disposed between first electrodes RME1 of different sub-pixels SPXn. The wiring connection electrode EP may not be disposed in a second sub-region SA of the sub-pixel SPXn, and the first electrodes RME1 of other sub-pixels SPXn adjacent in the first direction DR1 may be spaced apart from each other. In the pixel PX illustrated in FIG. 5 among the plurality of sub-pixels SPXn, the first sub-region SA1 in which the wiring connection electrode EP is disposed may be disposed above the light-emitting region EMA, and the second sub-region SA2 may be disposed below the light-emitting region EMA. On the other hand, in the pixel PX adjacent in the first direction DR1 to the pixel PX in FIG. 5, the first sub-region SA1 in which the wiring connection electrode EP is disposed may be disposed below the light-emitting region EMA, and the second sub-region SA2 may be disposed above the light-emitting region EMA.

[0087] The first electrode RME1 may be separated from the line connecting electrode EP in the first sub-region SA1 with a first separation portion ROP1 therebetween. Two first separation portions ROP1 may be arranged in the first sub-region SA1, and the line connecting electrode EP may be separated from the first electrode RME1 arranged in the corresponding sub-pixel SPXn with a lower first separation portion ROP1 therebetween, and separated from the first electrode RME1 arranged in the other sub-pixel SPXn with an upper first separation portion ROP1 therebetween. One second separation portion ROP2 may be arranged in the second sub-region SA2, and different first electrodes RME1 may be separated from each other in the first direction DR1.

[0088] In the drawings, a case where one first electrode RME1 and a different second electrode RME2 are arranged for each sub-pixel SPXn is illustrated, but the present invention is not limited thereto. For example, the display device 10 may have a larger number of electrodes RME arranged for one sub-pixel SPXn, or the arrangement and shape of the electrodes RME may be changed.

[0089] The bank layer BNL may be arranged to surround the multiple subpixels SPXn, the light-emitting region EMA, and the subregions SA1 and SA2. The bank layer BNL may be arranged between the subpixels SPXn adjacent in the first direction DR1 and the second direction DR2, and may also be arranged between the light-emitting region EMA and the subregions SA1 and SA2. The subpixels SPXn, the light-emitting region EMA, and the subregions SA1 and SA2 of the display device 10 may be regions divided by the arrangement of the bank layer BNL. The intervals between the multiple subpixels SPXn, the light-emitting region EMA, and the subregions SA1 and SA2 may vary depending on the width of the bank layer BNL.

[0090] The light emitting element ED may be disposed in the light emitting area EMA. The light emitting element ED may be disposed between the partition walls BP1 and BP2 and may be spaced apart from each other in the first direction DR1 or the second direction DR2. In one embodiment, the light emitting elements ED may have a shape extending in one direction and both ends may be disposed on different electrodes RME. The length of the light emitting element ED may be longer than the distance between the electrodes RME spaced apart in the second direction DR2. The light emitting elements ED may generally be arranged such that the extension direction is perpendicular to the first direction DR1 in which the electrodes RME extend. However, the present invention is not limited thereto, and the light emitting elements ED may be arranged such that the extension direction is in the second direction DR2 or in a direction obliquely inclined thereto.

[0091] The light emitting element ED may include a first light emitting element ED1 having both ends disposed on one of the first electrode RME1 and the second electrode RME2, and a second light emitting element ED2 having both ends disposed on the first electrode RME1 and the other second electrode RME2. Based on the first subpixel SPX1, the first light emitting element ED1 may be disposed on the first electrode RME1 and the second electrode branch portion RM_B2 of the second electrode RME2, and the second light emitting element ED2 may be disposed on the first electrode RME1 and the first electrode branch portion RM_B1 of the other second electrode RME2. The first light emitting element ED1 may be disposed on the right side of the first electrode RME1, and the second light emitting element ED2 may be disposed on the left side of the first electrode RME1. The first light emitting element ED1 and the second light emitting element ED are disposed on the first electrode RME1 and the second electrode RME2, respectively, and the second electrodes RME2 on which they are disposed may be different from each other.

[0092] The connecting electrodes (CNE; CNE1, CNE2, CNE3) may be disposed on the electrode RME and the partition walls BP1, BP2. The connecting electrodes CNE may each have a shape extending in one direction and be disposed apart from each other. Each connecting electrode CNE may contact the light emitting element ED and be electrically connected to the conductive layer thereunder.

[0093] The connecting electrode CNE may include a first connecting electrode CNE1, a second connecting electrode CNE2, and a third connecting electrode CNE3 arranged in each sub-pixel SPXn.

[0094] The first connecting electrode CNE1 may have a shape extending in a first direction DR1 and be disposed on the first electrode RME1. The first connecting electrode CNE1 may be disposed to overlap the first barrier rib BP1 and the first electrode RME1, and may extend in the first direction DR1 from the light emitting region EMA to a first sub-region SA1 located above the light emitting region EMA. The first connecting electrode CNE1 may be in contact with the first electrode RME1 through a first contact hole CT1 formed on the first electrode RME1 in the first sub-region SA1.

[0095] The second connecting electrode CNE2 may be spaced apart from the first connecting electrode CNE1 in the second direction DR2, may have a shape extending in the first direction DR1, and may be disposed on the second electrode RME2. The second connecting electrode CNE2 may be disposed on the second electrode branch portion RM_B2 of the second electrode RME2 disposed on the left side of the first electrode RME1. The second connecting electrode CNE2 may be disposed to overlap the second barrier rib BP2 and the second electrode branch portion RM_B2 of the second electrode RME2, and may extend in the second direction DR2 from the light emitting region EMA to the first sub-region SA1 located above the light emitting region EMA. The second connecting electrode CNE2 may be in contact with the second electrode RME2 through a second contact hole CT2 formed on the second electrode RME2 in the first sub-region SA1.

[0096] The third connecting electrode CNE3 may include extensions CN_E1 and CN_E2 extending in the first direction DR1, and a first connecting portion CN_B1 connecting the extensions CN_E1 and CN_E2. The first extension portion CN_E1 may face the first connecting electrode CNE1 in the light emitting region EMA and be disposed on the second electrode RME2. With reference to the first subpixel SPX1, the first extension portion CN_E1 may be disposed on the second electrode branch portion RM_B2 of the second electrode RME2. The second extension portion CN_E2 may face the second connecting electrode CNE2 in the light emitting region EMA and be disposed on the first electrode RME1. The first connecting portion CN_B1 may extend in the second direction DR2 on the bank layer BNL disposed below the light emitting region EMA to connect the first extension portion CN_E1 and the second extension portion CN_E2. The third connecting electrode CNE3 is disposed on the light emitting region EMA and the bank layer BNL, and may not be directly connected to the electrode RME. The second electrode RME2 arranged at the bottom of the first extension portion CN_E1 is electrically connected to the second voltage wiring VL2, and the second power supply voltage applied to the second electrode RME2 does not need to be transmitted to the third connecting electrode CNE3.

[0097] As described below, the light emitting elements ED may be separated from each other at both ends in the extension direction and may be connected in series to each other via a connecting electrode CNE that contacts both ends. The display device 10 may include a greater number of light emitting elements ED for each sub-pixel SPXn and configure these to be connected in series, thereby increasing the amount of light emitted per unit area.

[0098] The display device 10 may further include insulating layers PAS1, PAS2, and PAS3 disposed between the electrodes RME1 and RME2, the light-emitting element ED, and the connecting electrodes CNE1, CNE2, and CNE3. The electrodes RME1 and RME2, the light-emitting element ED, and the connecting electrodes CNE1, CNE2, and CNE3 are disposed to overlap each other, but may only partially contact each other due to the insulating layers PAS1, PAS2, and PAS3 disposed therebetween.

[0099] Fig. 6 is a cross-sectional view taken along line N1-N1' in Fig. 5. Fig. 7 is a cross-sectional view taken along line N2-N2' in Fig. 5. Fig. 8 is a cross-sectional view taken along line N3-N3' in Fig. 5.

[0100] Fig. 6 shows a cross section across both ends of a light-emitting element (ED; ED1, ED2) arranged on different electrodes (RME: RME1, RME2). Fig. 7 and Fig. 8 show cross sections across electrode contact holes CTD, CTS, CTA and contact holes CT1, CT2.

[0101] 5 to 8, the display device 10 may include a first substrate SUB, a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers disposed thereon, and may also include a plurality of electrodes RME, a light emitting element ED, and a connecting electrode CNE.

[0102] The first substrate SUB may be an insulating substrate. The first substrate SUB may be made of an insulating material such as glass, quartz, or polymer resin. The first substrate SUB may be a rigid substrate, but may also be a flexible substrate capable of bending, folding, rolling, etc. The first substrate SUB includes a display area DPA and a non-display area NDA surrounding the display area DPA, and the display area DPA may include a light-emitting area EMA and sub-areas SA1 and SA2 which are parts of the non-light-emitting area.

[0103] The first conductive layer may include a lower metal layer BML, a first voltage wiring VL1, and a second voltage wiring VL2. The lower metal layer BML is disposed to overlap with the active layer ACT1 of the first transistor T1. The lower metal layer BML may function to prevent light from being incident on the first active layer ACT1 of the first transistor, or may be electrically connected to the first active layer ACT1 to stabilize the electrical characteristics of the first transistor T1. However, the lower metal layer BML may be omitted.

[0104] The first voltage wiring VL1 may be applied with a high potential voltage (or a first power supply voltage) transmitted to the first electrode RME1, and the second voltage wiring VL2 may be applied with a low potential voltage (or a second power supply voltage) transmitted to the second electrode RME2. The first voltage wiring VL1 may be electrically connected to the first transistor T1 via a conductive pattern of the second conductive layer (e.g., a third conductive pattern CDP3). The second voltage wiring VL2 may be electrically connected to the second electrode RME2 via a conductive pattern of the third conductive layer (e.g., a second conductive pattern CDP2).

[0105] In the drawings, the first voltage line VL1 and the second voltage line VL2 are disposed on the first conductive layer, but are not limited thereto. In some embodiments, the first voltage line VL1 and the second voltage line VL2 may be disposed on a third conductive layer and directly electrically connected to the first transistor T1 and the second electrode RME2, respectively.

[0106] A buffer layer BL may be disposed on the first conductive layer and the first substrate SUB. The buffer layer BL is formed on the first substrate SUB to protect the transistors of the pixels PX from moisture that may penetrate through the first substrate SUB, which is susceptible to moisture, and can perform a surface planarization function.

[0107] The semiconductor layer is disposed on the buffer layer BL. The semiconductor layer may include a first active layer ACT1 of the first transistor T1 and a second active layer ACT2 of the second transistor T2. The first active layer ACT1 and the second active layer ACT2 may be disposed to partially overlap a first gate electrode G1 and a second gate electrode G2 of a second conductive layer, respectively, which will be described later.

[0108] The semiconductor layer may include polycrystalline silicon, single crystal silicon, an oxide semiconductor, etc. In an exemplary embodiment, the semiconductor layer may include polycrystalline silicon or an oxide semiconductor. The oxide semiconductor may include indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0109] The drawing illustrates an example in which one first transistor T1 and one second transistor T2 are arranged in the sub-pixel SPXn of the display device 10, but this is not limited to this and the display device 10 may include a greater number of transistors.

[0110] The first gate insulating layer GI is disposed on the semiconductor layer. The first gate insulating layer GI can function as a gate insulating film for each of the transistors T1 and T2. In the drawings, the first gate insulating layer GI is patterned together with the gate electrodes G1 and G2 of the second conductive layer and is partially disposed between the second conductive layer and the active layers ACT1 and ACT2 of the semiconductor layer, but is not limited thereto. In some embodiments, the first gate insulating layer GI can cover the semiconductor layer and be disposed entirely on the buffer layer BL.

[0111] The second conductive layer is disposed on the first gate insulating layer GI. The second conductive layer may include a first gate electrode G1 of the first transistor T1 and a second gate electrode G2 of the second transistor T2. The first gate electrode G1 may be disposed to overlap a channel region of the first active layer ACT1 in a third direction DR3 that is a thickness direction, and the second gate electrode G2 may be disposed to overlap a channel region of the second active layer ACT2 in the third direction DR3 that is a thickness direction. Although not shown in the drawings, the second conductive layer may further include one electrode of a storage capacitor.

[0112] The first interlayer insulating layer IL1 is disposed on the second conductive layer. The first interlayer insulating layer IL1 functions as an insulating film between the second conductive layer and another layer disposed thereon, and can protect the second conductive layer.

[0113] The third conductive layer is disposed on the first interlayer insulating layer IL1. The third conductive layer may include a plurality of conductive patterns CDP1, CDP2, CDP3 and source electrodes S1, S2 and drain electrodes D1, D2 of the transistors T1, T2. Parts of the conductive patterns CDP1, CDP2, CDP3 may electrically connect conductive layers or semiconductor layers of different layers to each other and serve as source / drain electrodes of the transistors T1, T2.

[0114] The first conductive pattern CDP1 may contact the first active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1. The first conductive pattern CDP1 may contact the lower metal layer BML through a contact hole penetrating the first interlayer insulating layer IL1 and the buffer layer BL. The first conductive pattern CDP1 may serve as a first source electrode S1 of the first transistor T1. The first conductive pattern CDP1 may be electrically connected to the first electrode RME1 or the first connecting electrode CNE1. The first transistor T1 may transfer a first power supply voltage applied from the first voltage wiring VL1 to the first electrode RME1 or the first connecting electrode CNE1.

[0115] The second conductive pattern CDP2 may be in contact with the second voltage wiring VL2 through a contact hole penetrating the first interlayer insulating layer IL1 and the buffer layer BL. The second voltage wiring VL2 may transmit a second power supply voltage to the second connecting electrode CNE2 through the second conductive pattern CDP2.

[0116] The third conductive pattern CDP3 may contact the first voltage wiring VL1 through a contact hole penetrating the first interlayer insulating layer IL1 and the buffer layer BL. The third conductive pattern CDP3 may also contact the first active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1. The third conductive pattern CDP3 may electrically connect the first voltage wiring VL1 to the first transistor T1 and serve as the first drain electrode D1 of the first transistor T1.

[0117] The second source electrode S2 and the second drain electrode D2 may be in contact with the second active layer ACT2 of the second transistor T2 via contact holes that penetrate the first interlayer insulating layer IL1, respectively.

[0118] The first protective layer PV1 is disposed on the third conductive layer. The first protective layer PV1 can act as an insulating film between other layers of the third conductive layer and protect the third conductive layer.

[0119] The above-mentioned buffer layer BL, first gate insulating layer GI, first interlayer insulating layer IL1, and first protective layer PV1 are made of a plurality of inorganic layers alternately stacked. For example, the buffer layer BL, first gate insulating layer GI, first interlayer insulating layer IL1, and first protective layer PV1 are made of silicon oxide (Silicon Oxide, SiO x ), Silicon Nitride (SiN x ), Silicon Oxynitride (SiO x N y) may be laminated as a bilayer or a multilayer in which these are alternately laminated. However, without being limited thereto, the buffer layer BL, the first gate insulating layer GI, the first interlayer insulating layer IL1, and the first protective layer PV1 may be formed of a single inorganic layer including the insulating material described above. In addition, in some embodiments, the first interlayer insulating layer IL1 may be made of an organic insulating material such as polyimide (PI).

[0120] The via layer VIA is disposed on the third conductive layer in the display area DPA. The via layer VIA may include an organic insulating material, such as polyimide (PI), to compensate for the step caused by the lower conductive layer and to form a flat upper surface. However, in some embodiments, the via layer VIA may be omitted.

[0121] The display device 10 is a display element layer disposed on a via layer VIA, and may include partitions BP1, BP2, electrodes RME1, RME2, a bank layer BNL, light emitting elements ED1, ED2, and connecting electrodes CNE1, CNE2, and CNE3. The display device 10 may also include insulating layers PAS1, PAS2, and PAS3.

[0122] The barrier ribs BP1 and BP2 may be disposed on the via layer VIA. For example, the barrier ribs BP1 and BP2 may be disposed directly on the via layer VIA and may have a structure in which at least a portion of the barrier ribs BP1 and BP2 protrude from the upper surface of the via layer VIA. As described above, the first barrier ribs BP1 and the second barrier ribs BP2 may be disposed apart from each other, and the first barrier ribs BP1 may be disposed between the second barrier ribs BP2. The barrier ribs BP1 and BP2 may have a side surface that is inclined or curved to have a certain curvature, and light emitted from the light emitting elements ED1 and ED2 may be reflected by the electrodes RME1 and RME2 disposed on the barrier ribs BP1 and BP2 and emitted toward the upper portion of the via layer VIA. Unlike the example of the drawing, the barrier ribs BP1 and BP2 may have a curved shape, for example, a semicircular or semielliptical shape, so that the outer surface in the cross-sectional view has a certain curvature. The barrier ribs BP1 and BP2 may include an organic insulating material such as polyimide (PI), but are not limited thereto.

[0123] The electrodes RME1, RME2 may be disposed on the partition walls BP1, BP2 and the via layer VIA. For example, each of the electrodes RME1, RME2 may be disposed at least partially on the inclined side surfaces of the partition walls BP1, BP2. The first electrode RME1 may be disposed so as to cover the first partition wall BP1, and the second electrode RME2 may be disposed so that the electrode branch portions RM_B1, RM_B2 cover the side surfaces of the second partition wall BP2. The width of the first electrode RME1 may be larger than that of the first partition wall BP1, and the width of the electrode branch portions RM_B1, RM_B2 of the second electrode RME2 may be smaller than that of the second partition wall BP2. The distance between the electrodes RME spaced apart from each other in the second direction DR2 may be narrower than the distance between the partition walls BP1, BP2. At least a portion of each of the electrodes RME may be disposed directly on the via layer VIA, and they may be disposed on the same plane.

[0124] The light-emitting element ED disposed between the partitions BP1 and BP2 emits light toward both ends, and the emitted light is directed toward the electrode RME disposed on the partitions BP1 and BP2. Each electrode RME may have a structure in which a portion disposed on the partitions BP1 and BP2 reflects the light emitted from the light-emitting element ED. The electrode RME is disposed to cover at least one side surface of the partitions BP1 and BP2, and can reflect the light emitted from the light-emitting element ED.

[0125] The first electrode RME1 and the second electrode RME2 may directly contact the third conductive layer through electrode contact holes CTD, CTS arranged in the portion overlapping with the bank layer BNL. For example, the first electrode contact hole CTD is formed in the portion overlapping with the first electrode RME1 and the bank layer BNL, and the second electrode contact hole CTS is formed in the portion overlapping with the second electrode RME2 and the bank layer BNL. The first electrode RME1 may contact the first conductive pattern CDP1 through the first electrode contact hole CTD penetrating the via layer VIA and the first protective layer PV1, and may be electrically connected to the first transistor T1. The second electrode RME2 may contact the second conductive pattern CDP2 through the second electrode contact hole CTS penetrating the via layer VIA and the first protective layer PV1, and may be electrically connected to the second voltage wiring VL2.

[0126] The wiring connection electrode EP may be disposed in the first sub-region SA1 and may be in direct contact with the third conductive layer through the third electrode contact hole CTA. For example, the wiring connection electrode EP may be in contact with the third conductive pattern CDP3 through the third electrode contact hole CTA penetrating the via layer VIA and the first protective layer PV1. The wiring connection electrode EP may be electrically connected to the first voltage wiring VL1 through the third conductive pattern CDP3.

[0127] In the manufacturing process of the display device 10, the first electrode RME1 is formed in a state of being connected to the wiring connecting electrode EP, and an electrical signal applied to arrange the light emitting element ED may be applied to the first electrode RME1 from the first voltage wiring VL1 via the wiring connecting electrode EP. In the process of arranging the light emitting element ED, signals are applied to the first voltage wiring VL1 and the second voltage wiring VL2, which may be transmitted to the first electrode RME1 and the second electrode RME2, respectively.

[0128] In an embodiment, the first electrode contact hole CTD and the second electrode contact hole CTS may be disposed relative to the third electrode contact hole CTA. The first electrode contact hole CTD may be disposed in the first sub-region SA1 and the second sub-region SA2, respectively, and the second electrode contact hole CTS may be formed to overlap the bank layer BNL disposed on one side of each of the sub-regions SA1 and SA2 in the second direction DR2. On the other hand, the third electrode contact hole CTA may be disposed only in the first sub-region SA1. This is because the second electrode contact hole CTS and the third electrode contact hole CTA expose the upper surfaces of the voltage wirings VL1 and VL2 different from each other, and the positions of the electrode contact holes may be determined accordingly. Even in the case of the separation parts ROP1 and ROP2 in which the electrode RME is separated, the first separation part ROP1 may be disposed in the first sub-region SA1 and formed on the upper side and the lower side of the wiring connecting electrode EP, respectively. On the other hand, the second isolation part ROP2 may be disposed in the second sub-region SA2 and disposed between the first electrodes RME1. Two first isolation parts ROP1 may be formed in the first sub-region SA1, and one second isolation part ROP2 may be formed in the second sub-region SA2.

[0129] The electrode RME may include a conductive material with high reflectivity. For example, the electrode RME may include a metal such as silver (Ag), copper (Cu), aluminum (Al), or an alloy including aluminum (Al), nickel (Ni), lanthanum (La), or a metal layer including titanium (Ti), molybdenum (Mo), and niobium (Nb) and the alloy may be laminated. In some embodiments, the electrode RME may be a bilayer or multilayer structure including an alloy including aluminum (Al) and at least one metal layer including titanium (Ti), molybdenum (Mo), and niobium (Nb).

[0130] Without being limited thereto, each electrode RME may further include a transparent conductive material. For example, each electrode RME may include materials such as ITO, IZO, ITZO, etc. In some embodiments, each electrode RME may have a structure in which a transparent conductive material and a metal layer having high reflectivity are laminated in one or more layers, or may be formed as a single layer including these. For example, each electrode RME may have a laminate structure such as ITO / Ag / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO. The electrode RME is electrically connected to the light emitting element ED and may reflect a portion of light emitted from the light emitting element ED toward the upper direction of the first substrate SUB.

[0131] The first insulating layer PAS1 may be disposed over the entire display area DPA and on the via layer VIA and the electrode RME. The first insulating layer PAS1 protects the electrode RME and at the same time insulates different electrodes RME from each other. The first insulating layer PAS1 is disposed to cover the electrode RME before the bank layer BNL is formed, thereby preventing the electrode RME from being damaged in the process of forming the bank layer BNL. The first insulating layer PAS1 can also prevent the light-emitting element ED disposed thereon from being damaged by direct contact with other members.

[0132] In an exemplary embodiment, the first insulating layer PAS1 may have a step formed between the electrodes RME spaced apart in the second direction DR2 such that a portion of the upper surface is recessed. The light emitting element ED may be disposed on the upper surface of the first insulating layer PAS1 where the step is formed, and a space may be formed between the light emitting element ED and the first insulating layer PAS1.

[0133] According to an embodiment, the first insulating layer PAS1 may include isolation openings and contact holes CT1, CT2 formed corresponding to the isolation portions ROP1, ROP2. The first insulating layer PAS1 may be disposed entirely on the via layer VIA, and may partially expose the underlying layer in the portions where the isolation openings and the contact holes CT1, CT2 are formed.

[0134] The separation openings formed in the first insulating layer PAS1 corresponding to the separation parts ROP1, ROP2 of the sub-regions SA1, SA2 may expose the via layer VIA disposed thereunder. In the separation openings of the first insulating layer PAS1, a process of separating the first electrodes RME1 connected to each other is performed. The first electrodes RME1 extending in the first direction DR1 may be formed in a state of being connected to the first electrodes RME1 or the line connecting electrodes EP of other sub-pixels SPXn adjacent in the first direction DR1, and then the portions of the first insulating layer PAS1 where the separation openings are exposed may be etched to separate them from each other. The separation openings of the first insulating layer PAS1 may be disposed corresponding to the separation parts ROP1, ROP2 located between the first electrodes RME1 or between the first electrodes RME1 and the line connecting electrodes EP.

[0135] The contact holes CT1 and CT2 of the first insulating layer PAS1 may be arranged to overlap different electrodes RME in the sub-regions SA1 and SA2. For example, the contact holes CT1 and CT2 may include a first contact hole CT1 arranged to overlap the first electrode RME1 and a second contact hole CT2 arranged to overlap the second electrode RME2. The first contact hole CT1 and the second contact hole CT2 may be arranged in the sub-regions SA1 and SA2, respectively. The first contact hole CT1 arranged in the first sub-region SA1 may be arranged on the first electrode RME1 apart from the first separation part ROP1 arranged under the line connecting electrode EP. The first contact hole CT1 arranged in the second sub-region SA2 may be arranged on the first electrode RME1 of another sub-pixel SPXn apart from the second separation part ROP2. The second contact hole CT2 may be arranged on a portion of the electrode trunk RM_S of the second electrode RME2 that is arranged to protrude into the sub-regions SA1 and SA2.

[0136] The first contact hole CT1 and the second contact hole CT2 may penetrate the first insulating layer PAS1 to expose a part of the upper surface of the first electrode RME1 or the second electrode RME2 on the lower side thereof. The first contact hole CT1 and the second contact hole CT2 may further penetrate a part of another insulating layer disposed on the first insulating layer PAS1. The electrode RME exposed by each of the contact holes CT1 and CT2 may be in contact with the connecting electrode CNE.

[0137] The bank layer BNL may be disposed on the first insulating layer PAS1. The bank layer BNL may include portions extending in the first direction DR1 and the second direction DR2 and surround each subpixel SPXn. The bank layer BNL may surround and separate the light-emitting region EMA and subregions SA1, SA2 of each subpixel SPXn, and may surround the outermost portion of the display region DPA and separate the display region DPA from the non-display region NDA. The portion of the bank layer BNL extending in the first direction DR1 may separate the light-emitting region EMA and the subregions SA1, SA2, and the portion extending in the second direction DR2 may separate adjacent subpixels SPXn. The portion of the bank layer BNL extending in the second direction DR2 may be disposed on the second partition wall BP2.

[0138] The bank layer BNL may have a certain height, similar to the partition walls BP1 and BP2. In some embodiments, the bank layer BNL may have a height of an upper surface higher than the partition walls BP1 and BP2, and may have a thickness equal to or greater than that of the partition walls BP1 and BP2. The bank layer BNL may prevent ink from overflowing into the adjacent sub-pixel SPXn during an inkjet printing process in the manufacturing process of the display device 10. The bank layer BNL may include an organic insulating material such as polyimide, similar to the partition walls BP1 and BP2. However, without being limited thereto, the bank layer BNL may include a material different from that of the partition walls BP1 and BP2.

[0139] The light emitting element ED may be disposed in the light emitting region EMA. The light emitting element ED may be disposed on the first insulating layer PAS1 between the partition walls BP1, BP2. The light emitting element ED may be disposed such that one extending direction is parallel to the upper surface of the first substrate SUB. As described below, the light emitting element ED may include a plurality of semiconductor layers disposed along the one extending direction, and the plurality of semiconductor layers may be sequentially disposed along a direction parallel to the upper surface of the first substrate SUB. However, this is not limited thereto, and when the light emitting element ED has another structure, the plurality of semiconductor layers may be disposed in a direction perpendicular to the first substrate SUB.

[0140] The light emitting element ED arranged in each sub-pixel SPXn can emit light of different wavelength bands depending on the material of the semiconductor layer, but is not limited thereto, and the light emitting element ED arranged in each sub-pixel SPXn can include a semiconductor layer made of the same material and emit light of the same color.

[0141] The light emitting elements ED may be disposed on different electrodes RME between different partition walls BP1, BP2. The first light emitting element ED1 may be disposed between the first partition wall BP1 and the second partition wall BP2, and both ends may be disposed on the first electrode RME1 and the second electrode branch portion RM_B2 of the second electrode RME2. The second light emitting element ED2 may be disposed between the second partition wall BP2 and the first partition wall BP1, and both ends may be disposed on the first electrode RME1 and the first electrode branch portion RM_B1 of the second electrode RME2. The first light emitting element ED1 may be disposed on the right side of the first partition wall BP1 in the light emitting region EMA, and the second light emitting element ED2 may be disposed on the left side of the first partition wall BP1.

[0142] The light emitting element ED is in contact with the connecting electrode CNE and can be electrically connected to the electrode RME and the conductive layer below the via layer VIA, and can emit light in a specific wavelength band when an electrical signal is applied.

[0143] The second insulating layer PAS2 may be disposed on the light-emitting elements ED, the first insulating layer PAS1, and the bank layer BNL. The second insulating layer PAS2 includes a pattern portion extending in the first direction DR1 between the partition walls BP1, BP2 and disposed on the light-emitting elements ED. The pattern portion is disposed so as to partially surround the outer surface of the light-emitting element ED, and may not cover both sides or both ends of the light-emitting element ED. The pattern portion may form a linear or island pattern in each sub-pixel SPXn in a plan view. The pattern portion of the second insulating layer PAS2 may protect the light-emitting element ED and at the same time fix the light-emitting element ED in the manufacturing process of the display device 10. The second insulating layer PAS2 may also be disposed so as to fill a space between the light-emitting element ED and the second insulating layer PAS2 on the lower side thereof. A portion of the second insulating layer PAS2 may be disposed on the upper portion of the bank layer BNL and in the sub-region SA.

[0144] According to one embodiment, the second insulating layer PAS2 may include isolation openings and contact holes CT1, CT2 formed corresponding to the isolation portions ROP1, ROP2. The second insulating layer PAS2 is disposed over the entire surface of the first insulating layer PAS1, and may partially expose the underlying layer in the areas where the isolation openings and contact holes CT1, CT2 are formed. The explanation of the isolation openings and contact holes CT1, CT2 is the same as that described above for the first insulating layer PAS1.

[0145] The connecting electrode CNE may be disposed on the electrode RME and the partition walls BP1, BP2. The connecting electrode CNE may be divided into a connecting electrode of a first connecting electrode layer disposed between the second insulating layer PAS2 and the third insulating layer PAS3, and a connecting electrode of a second connecting electrode layer disposed on the third insulating layer PAS3. The third connecting electrode CNE3 may be a connecting electrode of the first connecting electrode layer, and the first connecting electrode CNE1 and the second connecting electrode CNE2 may be connecting electrodes of the second connecting electrode layer.

[0146] The first connecting electrode CNE1 may be disposed on the first electrode RME1 and the first partition wall BP1. The second connecting electrode CNE2 may be disposed on the second electrode RME2 and the second partition wall BP2. The third connecting electrode CNE3 may be disposed across the first electrode RME1, the second electrode RME2, the second partition wall BP2, and the first partition wall BP1. The planar arrangement of each connecting electrode CNE is the same as that described above with reference to FIG. 5.

[0147] The first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 are each disposed on the second insulating layer PAS2 and may be in contact with the light emitting element ED. The first connecting electrode CNE1 may be in contact with a first end of the first light emitting element ED1. The second connecting electrode CNE2 may be in contact with a second end of the second light emitting element ED2. The third connecting electrode CNE3 may have a first extension portion CN_E1 in contact with a second end of the first light emitting element ED1 and a second extension portion CN_E2 in contact with a first end of the second light emitting element ED2.

[0148] The first connecting electrode CNE1 and the second connecting electrode CNE2 are disposed across the light emitting region EMA and the sub-regions SA1 and SA2, and may be in direct contact with the electrodes RME1 and RME2 through contact holes CT1 and CT2 formed in the sub-regions SA1 and SA2, respectively. The first connecting electrode CNE1 may be in contact with the first electrode RME1 through a first contact hole CT1 penetrating the first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 in the sub-regions SA1 and SA2. The second connecting electrode CNE2 may be in contact with the second electrode RME2 through a second contact hole CT2 penetrating the first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 in the sub-regions SA1 and SA2. On the other hand, the third connecting electrode CNE3 may not be in contact with the electrode RME.

[0149] The first connecting electrode CNE1 is electrically connected to the first transistor T1 via a first electrode RME1 to receive a first power supply voltage, and the second connecting electrode CNE2 is electrically connected to the second voltage line VL2 via a second electrode RME2 to receive a second power supply voltage. The light emitting element ED can emit light by the power supply voltage received via the first connecting electrode CNE1 and the second connecting electrode CNE2.

[0150] The first connecting electrode CNE1 and the second connecting electrode CNE2 are first type connecting electrodes connected to the electrodes RME1 and RME2 directly connected to the third conductive layer, respectively, and the third connecting electrode CNE3 may be a second type connecting electrode not connected to the electrode RME. The third connecting electrode CNE3 is not connected to the electrode RME and contacts the light emitting element ED, and may form an electrical connecting circuit of the light emitting element ED together with the other connecting electrodes CNE.

[0151] However, the present invention is not limited thereto. In some embodiments, the display device 10 may have a portion of the connecting electrode CNE directly connected to the third conductive layer. For example, the first connecting electrode CNE1 and the second connecting electrode CNE2, which are the first type connecting electrodes, may each be directly connected to the third conductive layer and may not be electrically connected to the electrode RME. The second type connecting electrode may also not be electrically connected to the electrode RME and may only be connected to the light emitting element ED.

[0152] The connecting electrode CNE may include a conductive material, for example, ITO, IZO, ITZO, aluminum (Al), etc. For example, the connecting electrode CNE may include a transparent conductive material, and light emitted from the light emitting element ED may be transmitted through the connecting electrode CNE and emitted.

[0153] The third insulating layer PAS3 is disposed on the connecting electrode of the second connecting electrode layer and the second insulating layer PAS2. The third insulating layer PAS3 may be disposed entirely on the second insulating layer PAS2 to cover the third connecting electrode CNE3, and the first connecting electrode CNE1 and the second connecting electrode CNE2 may be disposed on the third insulating layer PAS3. The third insulating layer PAS3 may be disposed entirely on the via layer VIA except for the region where the third connecting electrode CNE3 is disposed. The third insulating layer PAS3 may insulate the connecting electrode of the first connecting electrode layer from the connecting electrode of the second connecting electrode layer so that they do not come into direct contact with each other.

[0154] According to an embodiment, the third insulating layer PAS3 may include a plurality of contact holes CT1, CT2. The third insulating layer PAS3 is disposed over the entire surface of the second insulating layer PAS2, and the layers below may be partially exposed in the portions where the plurality of contact holes CT1, CT2 are formed. The first contact hole CT1 and the second contact hole CT2 may penetrate the third insulating layer PAS3 in addition to the first insulating layer PAS1 and the second insulating layer PAS2. The contact holes CT1, CT2 may each expose a portion of the upper surface of the electrode RME below.

[0155] The above-mentioned first insulating layer PAS1, second insulating layer PAS2 and third insulating layer PAS3 may each include an inorganic insulating material or an organic insulating material. As an example, the first insulating layer PAS1, second insulating layer PAS2 and third insulating layer PAS3 may each include an inorganic insulating material, or the first insulating layer PAS1 and the third insulating layer PAS3 may include an inorganic insulating material and the second insulating layer PAS2 may include an organic insulating material. The first insulating layer PAS1, second insulating layer PAS2 and third insulating layer PAS3 may each, or at least one of them may be formed in a structure in which a plurality of insulating layers are alternately or repeatedly stacked. In an exemplary embodiment, the first insulating layer PAS1, second insulating layer PAS2 and third insulating layer PAS3 may each be formed of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiO x N y The first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 may be made of the same material, or may be made of materials that are partially the same and partially different from each other, or may be made of materials that are different from each other.

[0156] According to an embodiment, the display device 10 may further include a thermal control layer ("HCL" in FIG. 9), color control layers ("TPL", "WCL1", "WCL2" in FIG. 9) and color filter layers ("CFL1", "CFL2", "CFL3" in FIG. 9) arranged on the light-emitting element ED. Light emitted from the light-emitting element ED is emitted through the color control layers TPL, WCL1, WCL2 and the color filter layers CFL1, CFL2, CFL3, and even if the same type of light-emitting element ED is arranged in each sub-pixel SPXn, the color of the emitted light may be different for each sub-pixel SPXn. In addition, heat generated when the light-emitting element ED emits light may be absorbed by the thermal control layer HCL, and the thermal control layer HCL may prevent the heat from being transferred to the color control layers TPL, WCL1, WCL2.

[0157] 9 is a cross-sectional view of a color control layer and a thermal control layer disposed in one pixel of a display device according to an embodiment, and FIG 10 is a cross-sectional view of a first wavelength conversion layer and a thermal control layer of a first sub-pixel of FIG 9.

[0158] 9 and 10 are cross-sectional views showing the arrangement of the color control layers TPL, WCL1, WCL2, color filter layers CFL1, CFL2, CFL3, and thermal control layer HCL arranged in one pixel PX of the display device 10. Detailed arrangements and explanations of the partitions BP1, BP2, electrodes RME1, RME2, bank layer BNL, light emitting element ED, and connecting electrodes CNE1, CNE2 arranged in each subpixel SPXn in FIGs. 9 and 10 can be understood with reference to FIGs. 5 to 8.

[0159] 9 and 10, the display device 10 may include a light-emitting element ED disposed on a first substrate SUB, and a thermal control layer HCL, color control layers TPL, WCL1, WCL2, and color filter layers CFL1, CFL2, CFL3 disposed on the upper side thereof. The display device 10 may further include a plurality of layers disposed between and above the color control layers TPL, WCL1, WCL2 and the color filter layers CFL1, CFL2, CFL3.

[0160] An upper bank layer UBM, a thermal control layer HCL, color control layers TPL, WCL1, WCL2, color patterns CP1, CP2, CP3, and color filter layers CFL1, CFL2, CFL3 may be disposed on the third insulating layer PAS3. Between the color control layers TPL, WCL1, WCL2 and the color filter layers CFL1, CFL2, CFL3, capping layers CPL1, CPL2, low refractive index layers LRL, and planarization layers PNL may be disposed, and an overcoat layer OC may be disposed on the color filter layers CFL1, CFL2, CFL3.

[0161] Each subpixel SPXn of the display device 10 may include a plurality of light-transmitting regions (TA: TA1, TA2, TA3) in which color filter layers CFL1, CFL2, CFL3 are arranged and from which light is emitted, and light-shielding regions BA between the light-transmitting regions TA from which light is not emitted. The light-transmitting regions TA are arranged corresponding to a portion of the light-emitting region EMA of each subpixel SPXn, and the light-shielding regions BA may be regions other than the light-transmitting regions TA. For example, the light-shielding regions BA may surround each of the light-transmitting regions TA.

[0162] The upper bank layer UBM may be arranged so as to overlap the bank layer BNL on the third insulating layer PAS3. The upper bank layer UBM may be arranged in a grid pattern including portions extending in the first direction DR1 and the second direction DR2. The upper bank layer UBM may surround a portion in which the light emitting area EMA or the light emitting element ED is arranged. The upper bank layer UBM may form an area in which the color control layers TPL, WCL1, WCL2 are arranged.

[0163] The thermal control layer HCL may be disposed on the third insulating layer PAS3 and the first connecting electrode CNE1 and the second connecting electrode CNE2, which are the second connecting electrode layer. The thermal control layer HCL may be disposed on the third insulating layer PAS3, and may be disposed corresponding to an area partitioned by the bank layer BNL of each sub-pixel SPXn. For example, the thermal control layer HCL may be disposed in the light-emitting area EMA surrounded by the bank layer BNL, and may also be disposed in the sub-areas SA1 and SA2, although not shown in the drawing. The thermal control layers HCL disposed in different sub-pixels SPXn may be separated from each other by the bank layer BNL. However, without being limited thereto, the thermal control layers HCL may not be separated from each other and may be disposed as one layer over the entire surface of a plurality of sub-pixels SPXn or the display area DPA. A detailed description of this will be given later.

[0164] According to an embodiment, the thermal control layer HCL may include a resin layer PRS and phase change particles PCM dispersed in the resin layer PRS. The phase change particles PCM may include a material that changes phase by absorbing or releasing heat, and the thermal control layer HCL may absorb heat generated in the vicinity. In the display device 10, the thermal control layer HCL may be disposed on the third insulating layer PAS3 and disposed to cover the light emitting element ED, and may absorb heat generated in the light emitting element ED. The thermal control layer HCL may reduce the transfer of heat generated in the light emitting element ED to the color control layers TPL, WCL1, and WCL2 described below.

[0165] FIG. 11 is a schematic diagram illustrating phase change particles included in a thermal control layer of a display device according to an embodiment.

[0166] Referring to FIG. 11, the phase change particles PCM of the thermal control layer HCL may have a core-shell structure. The phase change particles PCM may include a core part C containing a phase change material and a first shell S1 surrounding the core part C. The core part C may include a material with a large amount of latent heat that can change phase according to the absorption and release of heat. For example, the core part C may include a material such as an alkane having 10 or more carbon atoms, polyethylene glycol (PEG), or a polyethylene glycol derivative, an aluminum-silicon alloy (Al-Si alloy), or an inorganic hydrate. In one embodiment, the core part C of the phase change particles PCM may include dodecane (C), which is an alkane having 12 carbon atoms. 12 H 26 ), and docosane (C 22 H 46 ) or an aluminum-silicon alloy (Al-Si alloy).

[0167] Dodecane (C 12 H 26 ) and Docosan (C 22 H 46 ) have latent heat capacities of approximately 210 kJ / kg and 230 kJ / kg, respectively, and docosane (C22 H 46 ), a phase change is possible at a temperature of about 44°C. Aluminum-silicon alloy (Al-Si alloy) has a latent heat of 180 kJ / kg and can undergo a phase change at a temperature of about 577°C. Although dodecane and docosane are given as examples of alkanes having 10 or more carbon atoms in core part C, the present invention is not limited thereto. Core part C can also include alkanes other than dodecane and docosane as long as they have a latent heat similar to that of dodecane and docosane and are capable of undergoing a phase change.

[0168] The core part C of the phase change particles PCM including such a material may change phase due to heat generated in the operating environment of the display device 10. Heat generated when the light emitting element ED emits light is absorbed by the phase change particles PCM of the thermal control layer HCL, and the heat can be prevented from spreading to the surroundings.

[0169] The first shell S1 of the phase change particle PCM may include a relatively hard material to accommodate the volume change caused by the phase change of the core C. For example, the first shell S1 may include polystyrene (PS), polymethylmethacrylate (PMMA), aluminum oxide (Al 2 O 3 The first shell S1 may include materials such as polymethyl methacrylate-silica (PMMA-silica) and the like. The first shell S1 includes a material that can maintain the shape of the phase change particle PCM even if the volume changes when the core C absorbs or releases heat to change phase, and can prevent the volatilization and outflow of the core C material.

[0170] FIG. 12 is a schematic diagram illustrating phase change particles included in a thermal control layer of a display device according to another embodiment.

[0171] Referring to FIG. 12, the phase change particle PCM may further include a second shell S2 disposed between the first shell S1 and the core portion C. The second shell S2 may be disposed to surround the core portion C, and the first shell S1 may be disposed to surround the second shell S2. The second shell S2 may include a thermally conductive material so that the core portion C can more easily absorb and release heat. For example, the second shell S2 may include a conductive polymer material such as graphite, carbon black, PEDOT-PSS, etc. As the phase change particle PCM further includes the second shell S2, the thermal control layer HCL may more easily control the heat generated in the light emitting element ED.

[0172] Heat generated when the light emitting element ED is driven may cause a decrease in brightness of the display device 10. If heat generated in the light emitting element ED is transferred to the surrounding light emitting element ED or the color control layers TPL, WCL1, and WCL2 described later, the light emitting element ED and the color control layers TPL, WCL1, and WCL2 deteriorate, causing a decrease in brightness. This may result in a decrease in the life of the display device 10. To prevent this, the display device 10 may include a thermal control layer HCL that covers the light emitting element ED and is disposed between the light emitting element ED and the color control layers TPL, WCL1, and WCL2. The thermal control layer HCL can absorb heat generated in the light emitting element ED to minimize the transfer of heat to other surrounding members. As most of the heat generated when the display device 10 is driven is absorbed by the thermal control layer HCL, deterioration of the light emitting element ED and the color control layers TPL, WCL1, and WCL2 can be prevented, and the life of the display device 10 can be increased.

[0173] According to an embodiment, the thermal control layer HCL may be formed by an inkjet printing process, and the phase change particles PCM of the thermal control layer HCL may be dispersed in the resin layer PRS to have a small size. The phase change particles PCM may have a sufficiently small diameter in consideration of the nozzle diameter of the inkjet printing device. According to an embodiment, the phase change particles PCM may have a diameter of 1 μm or less, or 0.5 μm or less, or 0.2 μm or less.

[0174] The resin layer PRS of the thermal control layer HCL may include an organic material having a viscosity such that the phase change particles PCM are dispersed and discharged through an inkjet printing device. The resin layer PRS may include a transparent material so that the light emitted from the light emitting element ED can be transmitted. In one embodiment, the resin layer PRS may include an epoxy resin, an acrylic resin, a cardo resin, an imide resin, or the like.

[0175] The color control layers TPL, WCL1, and WCL2 may be disposed directly on the heat control layer HCL and disposed within the area surrounded by the upper bank layer UBM. The color control layers TPL, WCL1, and WCL2 may be disposed so as to be in direct contact with the inner side of the upper bank layer UBM. The color control layers TPL, WCL1, and WCL2 may be disposed in the light-transmitting area TA surrounded by the upper bank layer UBM to form an island-like pattern in the display area DPA. FIG. 9 illustrates a case in which the color control layers TPL, WCL1, and WCL2 are disposed so as to fill the area surrounded by the bank layer BNL and the upper bank layer UBM, but is not limited thereto. The color control layers TPL, WCL1, and WCL2 may also be disposed so as to extend in one direction across a plurality of sub-pixels SPXn to form a linear pattern.

[0176] In an embodiment in which the light-emitting element ED of each subpixel SPXn emits blue light of the third color, the color control layers TPL, WCL1, WCL2 may include a wavelength conversion layer (WCL: WCL1, WCL2) and a transparent layer TPL. The wavelength conversion layers WCL1, WCL2 may include a first wavelength conversion layer WCL1 disposed in the first subpixel SPX1 and a second wavelength conversion layer WCL2 disposed in the second subpixel SPX2. The transparent layer TPL may be disposed in the third subpixel SPX3. The first wavelength conversion layer WCL1 may be disposed in the first transparent region TA1, and the second wavelength conversion layer WCL2 may be disposed in the second transparent region TA2. The transparent layer TPL may be disposed in the third transparent region TA3 of the third subpixel SPX3.

[0177] The first wavelength conversion layer WCL1 may include a first base resin BRS1 and a first wavelength conversion material WCP1 disposed in the first base resin BRS1. The second wavelength conversion layer WCL2 may include a second base resin BRS2 and a second wavelength conversion material WCP2 disposed in the second base resin BRS2. The wavelength conversion layers WCL1 and WCL2 may convert the wavelength of the third color blue light incident from the light emitting element ED and transmit the converted light. The wavelength conversion layers WCL1 and WCL2 may further include a scatterer SCP contained in each base resin, and the scatterer SCP may increase the wavelength conversion efficiency.

[0178] The transparent layer TPL may include a third base resin BRS3 and a scatterer SCP disposed in the third base resin BRS3. The transparent layer TPL may transmit the third color blue light incident from the light emitting element ED while maintaining the wavelength. The scatterer SCP of the transparent layer TPL may play a role in adjusting the emission path of the light emitted through the transparent layer TPL. The transparent layer TPL may not include a wavelength conversion material.

[0179] The scatterers SCP can be metal oxide particles or organic particles. The metal oxides include titanium oxide (TiO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3), barium sulfate (BaSO 4 ), zinc oxide (ZnO) or tin oxide (SnO 2 ) and the like can be exemplified as the organic particle material, and acrylic resins or urethane resins can be exemplified as the organic particle material.

[0180] The first to third base resins BRS1, BRS2, ​​and BRS3 may include a light-transmitting organic material. For example, the first to third base resins BRS1, BRS2, ​​and BRS3 may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first to third base resins BRS1, BRS2, ​​and BRS3 may all be made of the same material, but are not limited thereto.

[0181] The first wavelength conversion material WCP1 may convert the third color blue light into the first color red light, and the second wavelength conversion material WCP2 may convert the third color blue light into the second color green light. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 may be quantum dots, quantum rods, phosphors, etc. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or a combination thereof.

[0182] In some embodiments, the color control layers TPL, WCL1, and WCL2 may be formed by an inkjet printing process or a photoresist process. The color control layers TPL, WCL1, and WCL2 may be formed by spraying or applying the materials constituting the color control layers TPL, WCL1, and WCL2 in the area surrounded by the upper bank layer UBM, followed by a drying or exposure and development process. As an example, in an embodiment in which the color control layers TPL, WCL1, and WCL2 are formed by an inkjet printing process, the upper surfaces of the color control layers TPL, WCL1, and WCL2 may be curved in the drawings, and the edge portions adjacent to the upper bank layer UBM may be higher than the center portions. However, this is not limiting. In an embodiment in which the color control layers TPL, WCL1, and WCL2 are formed by a photoresist process, the upper surface of each of the color control layers TPL, WCL1, and WCL2 may be formed flat, and the edge portions adjacent to the upper bank layer UBM may be parallel to the upper surface of the upper bank layer UBM, or, unlike the drawing, the center portions of the color control layers TPL, WCL1, and WCL2 may be formed higher.

[0183] The first wavelength conversion layer WCL1 may be disposed in the first subpixel SPX1. The first wavelength conversion layer WCL1 may be disposed on the light emitting region EMA of the first subpixel SPX1, and the bank layer BNL and the upper bank layer UBM may be disposed in a region surrounding the first subpixel SPX1. The second wavelength conversion layer WCL2 may be disposed in the second subpixel SPX2. The second wavelength conversion layer WCL2 may be disposed in the light emitting region EMA of the second subpixel SPX2, and the bank layer BNL and the upper bank layer UBM may be disposed in a region surrounding the second subpixel SPX2.

[0184] The light-transmitting layer TPL may be disposed in the third subpixel SPX3. The light-transmitting layer TPL may be disposed in the light-emitting region EMA of the third subpixel SPX3, and the bank layer BNL and the upper bank layer UBM may be disposed in a region surrounding the third subpixel SPX3.

[0185] The light-emitting element ED arranged in each sub-pixel SPXn is arranged so as to overlap with the color control layers TPL, WCL1, WCL2 above it, and light emitted from the light-emitting element ED can be incident on the color control layers TPL, WCL1, WCL2.

[0186] For example, the light-emitting element ED of each subpixel SPXn may emit the same third color blue light, and the light emitted from each subpixel SPXn may be light of different colors. The light emitted from the light-emitting element ED arranged in the first subpixel SPX1 may be incident on the first wavelength conversion layer WCL1, the light emitted from the light-emitting element ED arranged in the second subpixel SPX2 may be incident on the second wavelength conversion layer WCL2, and the light emitted from the light-emitting element ED arranged in the third subpixel SPX3 may be incident on the transparent layer TPL. The light incident on the first wavelength conversion layer WCL1 is converted to red light, the light incident on the second wavelength conversion layer WCL2 is converted to green light, and the light incident on the transparent layer TPL may be transmitted as the same blue light without wavelength conversion. Although the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 each include a light-emitting element ED that emits light of the same color, they may emit light of different colors depending on the arrangement of the color control layers TPL, WCL1, and WCL2 arranged on the upper side thereof.

[0187] The thermal control layer HCL and the color control layers TPL, WCL1, and WCL2 may each include a resin layer PRS, or a base resin BRS1, BRS2, ​​or BRS3, and particles dispersed therein, such as phase transition particles PCM, or wavelength conversion materials WCP1 and WCP2, and a scatterer SCP. The thermal control layer HCL and the color control layers TPL, WCL1, and WCL2 may be similar in that they are disposed on the light-emitting element ED and include a resin layer PRS made of a transparent material, or a base resin BRS1, BRS2, ​​or BRS3. However, the thermal control layer HCL is a layer that controls the heat generated by the light-emitting element ED, and the color control layers TPL, WCL1, and WCL2 are layers that control the color of the light emitted from the light-emitting element ED, and there may be differences in their functions.

[0188] When the thermal control layer HCL covers the light-emitting element ED and contains enough phase change particles PCM to control the heat generated by the light-emitting element ED, the thickness and arrangement of the thermal control layer HCL may be modified in various ways. For example, in FIG. 9 and FIG. 10, the thermal control layer HCL is disposed within the area surrounded by the bank layer BNL, so that the height of the upper surface is the same as the height of the bank layer BNL and the top layer of the second insulating layer PAS2 and the third insulating layer PAS3. However, without being limited thereto, the thermal control layer HCL may have a larger thickness and the upper surface may be located above the bank layer BNL and the second insulating layer PAS2 and the third insulating layer PAS3. Alternatively, the height of the upper surface of the thermal control layer HCL may be lower than the height of the bank layer BNL and the top layer of the second insulating layer PAS2 and the third insulating layer PAS3.

[0189] On the other hand, the color control layers TPL, WCL1, and WCL2 may change the color coordinates or brightness of the light emitted from the light emitting element ED and converted or transmitted by the color control layers TPL, WCL1, and WCL2 depending on their thickness. The color control layers TPL, WCL1, and WCL2 of the display device 10 may have a minimum thickness for having sufficient conversion efficiency of the light emitted from the light emitting element ED depending on the materials of the wavelength conversion substances WCP1 and WCP2 and the scatterers SCP. According to an embodiment, the display device 10 may have a thickness of the color control layers TPL, WCL1, and WCL2 that is thicker than the thickness of the thermal control layer HCL. The upper bank layer UBM is disposed on the bank layer BNL and may have a thicker thickness. The color control layers TPL, WCL1, and WCL2 may have a thicker thickness than the thermal control layer HCL disposed in the area surrounded by the bank layer BNL, since they are disposed in the area surrounded by the upper bank layer UBM. In one embodiment, the thermal control layer HCL may have a thickness in the range of about 2 μm, and the color control layers TPL, WCL1, and WCL2 may have a thickness in the range of 8 μm to 10 μm. The thermal control layer HCL may be thicker or may be at least thinner than the color control layers TPL, WCL1, and WCL2. By adjusting the thickness of the thermal control layer HCL and the thickness of the color control layers TPL, WCL1, and WCL2, the display device 10 can effectively control the heat generated in the light emitting element ED and improve the conversion efficiency of the light emitted from the light emitting element ED.

[0190] Since the functions of the thermal control layer HCL and the color control layers TPL, WCL1, and WCL2 are different from each other, the functions of the resin layer PRS and the base resins BRS1, BRS2, ​​and BRS3 may also be different from each other. The resin layer PRS can be discharged through a nozzle so that the thermal control layer HCL is formed by an inkjet printing process, and can be made of various materials within a range of transparency if it has a viscosity that allows the phase transition particles PCM to be dispersed. On the other hand, the base resins BRS1, BRS2, ​​and BRS3 can be selected from materials that can be discharged through a nozzle, have a viscosity that allows the wavelength conversion materials WCP1 and WCP2 to be dispersed, and also take into consideration the conversion efficiency of light emitted from the light emitting element ED. The resin layer PRS and the base resins BRS1, BRS2, ​​and BRS3 may each include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin, and these materials may be the same or different from each other. This can be determined depending on the material of the phase change particles PCM of the thermal control layer HCL, the performance of the inkjet printing device, and the color coordinates of the light emitted from the light emitting element ED.

[0191] The first capping layer CPL1 may be disposed on the plurality of color control layers TPL, WCL1, WCL2 and the upper bank layer UBM. The first capping layer CPL1 may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color control layers TPL, WCL1, WCL2. The first capping layer CPL1 may include an inorganic insulating material.

[0192] The first capping layer CPL1 may be disposed so as to cover the color control layers TPL, WCL1, and WCL2 and may be disposed along the steps formed by these layers. The color control layers TPL, WCL1, and WCL2 may be disposed so as to fill the area surrounded by the upper bank layer UBM, and the first capping layer CPL1 may be disposed so as to extend from the upper surfaces of the color control layers TPL, WCL1, and WCL2 to the upper surface of the upper bank layer UBM.

[0193] The low refractive layer LRL may be disposed on the first capping layer CPL1. The low refractive layer LRL is an optical layer that recycles light that has passed through the color control layers TPL, WCL1, and WCL2, and can improve the light output efficiency and color purity of the display device 10. The low refractive layer LRL is made of an organic material having a low refractive index, and can compensate for steps formed by the color control layers TPL, WCL1, and WCL2 and the upper bank layer UBM.

[0194] The second capping layer CPL2 is disposed on the low refractive layer LRL and can prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the low refractive layer LRL. The second capping layer CPL2 may include an inorganic insulating material, similar to the first capping layer CPL1.

[0195] The planarization layer PNL may be disposed over the entire surface of the display area DPA and the non-display area NDA on the second capping layer CPL2. The planarization layer PNL may overlap the color control layers TPL, WCL1, and WCL2 in the display area DPA. The planarization layer PNL protects the capping layers CPL1 and CPL2 and the low refractive layer LRL as well as members disposed on the first substrate SUB, and can partially compensate for steps caused by these. In particular, the planarization layer PNL compensates for steps formed by the color control layers TPL, WCL1, and WCL2, the upper bank layer UBM, and the bank layer BNL on the lower side in the display area DPA, and the color filter layers CFL1, CFL2, and CFL3 disposed thereon may be formed on a flat surface.

[0196] The color filter layers CLF1, CLF2, and CFL3 may be disposed on the planarization layer PNL. Each of the color filter layers CFL1, CFL2, and CFL3 may be disposed in a light-transmitting region TA in the subpixel SPXn, and a portion of the color filter layers CFL1, CFL2, and CFL3 may extend to a light-shielding region BA. The color filter layers CFL1, CFL2, and CFL3 may overlap with other color filter layers CFL1, CFL2, and CFL3 or color patterns CP1, CP2, and CP3 in the light-shielding region BA. The portion of the color filter layers CFL1, CFL2, and CFL3 that do not overlap with other color filter layers CFL1, CFL2, and CFL3 is a light-transmitting region TA where light is emitted, and the region where the different color filter layers CFL1, CFL2, and CFL3 overlap or where the color patterns CP1, CP2, and CP3 are disposed may be a light-shielding region BA where light emission is blocked.

[0197] The color filter layers CFL1, CFL2, and CFL3 may include a first color filter layer CFL1 disposed in the first sub-pixel SPX1, a second color filter layer CFL2 disposed in the second sub-pixel SPX2, and a third color filter layer CFL3 disposed in the third sub-pixel SPX3. The color filter layers CFL1, CFL2, and CFL3 may be arranged in an island pattern corresponding to the light-transmitting regions TA or the light-emitting regions EMA. However, the present invention is not limited to this. The color filter layers CFL1, CFL2, and CFL3 may also be arranged across a plurality of light-transmitting regions TA or light-emitting regions EMA to form a linear pattern.

[0198] The color filter layers CFL1, CFL2, and CFL3 may include colorants such as dyes and pigments that absorb light in wavelength bands other than light in a specific wavelength band. The color filter layers CFL1, CFL2, and CFL3 can transmit only a portion of the light incident on the color filter layers CFL1, CFL2, and CFL3 in the sub-pixel SPXn. In each sub-pixel SPXn of the display device 10, only the light transmitted by the color filter layers CFL1, CFL2, and CFL3 is selectively displayed. In an exemplary embodiment, the first color filter layer CFL1 may be a red color filter layer, the second color filter layer CFL2 may be a green color filter layer, and the third color filter layer CFL3 may be a blue color filter layer. The light emitted from the light-emitting element ED may pass through the color control layers TPL, WCL1, and WCL2 and be emitted through the color filter layers CFL1, CFL2, and CFL3.

[0199] The color patterns CP1, CP2, CP3 may be disposed on the planarization layer PNL or the color filter layers CFL1, CFL2, CFL3. The color patterns CP1, CP2, CP3 may include the same material as the color filter layers CFL1, CFL2, CFL3, and may be disposed in the light-shielding area BA. In the light-shielding area BA, color filter layers CFL1, CFL2, CFL3 different from the color patterns CP1, CP2, CP3 are laminated and disposed, and light transmission can be blocked in the laminated area.

[0200] The first color pattern CP1 may include the same material as the first color filter layer CFL1 and may be disposed in the light-shielding region BA. The first color pattern CP1 may be disposed directly on the planarization layer PNL in the light-shielding region BA and may not be disposed in the light-shielding region BA adjacent to the first light-transmitting region TA1 of the first sub-pixel SPX1. The first color pattern CP1 may be disposed in a region between the second sub-pixel SPX2 and the third sub-pixel SPX3, or between the second light-transmitting region TA2 and the third light-transmitting region TA3. The first color filter layer CFL1 may be disposed to extend in the light-shielding region BA around the first sub-pixel SPX1.

[0201] The second color pattern CP2 may include the same material as the second color filter layer CFL2 and may be disposed in the light-shielding region BA. The second color pattern CP2 may be disposed directly on the first color pattern CP1 or the first color filter layer CFL1 on the planarization layer PNL in the light-shielding region BA, and may not be disposed in the light-shielding region BA adjacent to the second light-transmitting region TA2 of the second subpixel SPX2. The second color pattern CP2 may be disposed in a region between the third subpixel SPX3 and the first subpixel SPX1, or between the third light-transmitting region TA3 and the first light-transmitting region TA1. The second color filter layer CFL2 may be disposed to extend in the light-shielding region BA around the second subpixel SPX2.

[0202] Similarly, the third color pattern CP3 may be disposed in the light-shielding region BA, including the same material as the third color filter layer CFL3. The third color pattern CP3 may be disposed directly on the second color pattern CP2 or the second color filter layer CFL2 on the planarization layer PNL in the light-shielding region BA, and may not be disposed in the light-shielding region BA adjacent to the third light-transmitting region TA3 of the third sub-pixel SPX3. The third color pattern CP3 may be disposed in the region between the first sub-pixel SPX1 and the second sub-pixel SPX2, or between the first light-transmitting region TA1 and the second light-transmitting region TA2. The third color filter layer CFL3 may be disposed to extend in the light-shielding region BA around the third sub-pixel SPX3.

[0203] In the display device 10, the area overlapping the bank layer BNL and the upper bank layer UBM becomes a light-shielding area BA, and the first color pattern CP1, the second color pattern CP2, and the third color pattern CP3 may be arranged to overlap at least one of the color filter layers CFL1, CFL2, and CFL3 containing different color materials in the light-shielding area BA. For example, in the area between the different sub-pixels SPXn, the first color pattern CP1 may be arranged to overlap the second color filter layer CFL2 and the third color filter layer CFL3, the second color pattern CP2 may be arranged to overlap the first color filter layer CFL1 and the third color filter layer CFL3, and the third color pattern CP3 may be arranged to overlap the first color filter layer CFL1 and the second color filter layer CFL2. The light-shielding area BA can block the transmission of light by the color patterns CP1, CP2, and CP3 and the color filter layers CFL1, CFL2, and CFL3 containing different color materials overlapping each other.

[0204] The color patterns CP1, CP2, and CP3 have a structure in which they are laminated with the color filter layers CFL1, CFL2, and CFL3, and can prevent color mixing between adjacent regions by using materials containing different color materials. The color patterns CP1, CP2, and CP3 contain the same material as the color filter layers CFL1, CFL2, and CFL3, so that the external light or reflected light transmitted through the light-shielding region BA can have a specific color wavelength band. The sensitivity of the user's eyes to each hue varies depending on the hue of the light, and the user is less sensitive to light in the blue wavelength band than light in the green wavelength band and light in the red wavelength band. The display device 10 blocks the transmission of light by arranging the color patterns CP1, CP2, and CP3 in the light-shielding region BA, and at the same time, the user is less sensitive to reflected light, and can absorb a portion of the light flowing in from outside the display device 10, thereby reducing the reflected light caused by external light.

[0205] The overcoat layer OC may be disposed on the color filter layers CFL1, CFL2, and CFL3 and the color patterns CP1, CP2, and CP3. The overcoat layer OC may be disposed over the entire display area DPA, and a portion of the overcoat layer OC may also be disposed in the non-display area NDA. The overcoat layer OC contains an organic insulating material, and thus can protect the components disposed in the display area DPA from the outside.

[0206] The display device 10 according to one embodiment includes color control layers TPL, WCL1, WCL2 and color filter layers CFL1, CFL2, CFL3 arranged on the top of the light-emitting element ED, and can display light of different colors even if the same type of light-emitting element ED is arranged in each sub-pixel SPXn.

[0207] For example, the light-emitting element ED disposed in the first sub-pixel SPX1 emits blue light of a third color, and the light passes through the thermal control layer HCL and enters the first wavelength conversion layer WCL1. The resin layer PRS of the thermal control layer HCL and the first base resin BRS1 of the first wavelength conversion layer WCL1 are made of transparent materials, and a part of the light passes through the resin layer PRS and the first base resin BRS1 and enters the first capping layer CPL1 disposed thereon. However, at least a part of the light is entered into the scatterer SCP and the first wavelength conversion material WCP1 disposed in the first base resin BRS1, and the light is scattered and wavelength-converted to red light, which enters the first capping layer CPL1. The light that enters the first capping layer CPL1 passes through the low refractive index layer LRL, the second capping layer CPL2, and the planarization layer PNL and enters the first color filter layer CFL1, and the first color filter layer CFL1 can block the transmission of other light except red light. Therefore, red light can be emitted from the first sub-pixel SPX1.

[0208] Similarly, light emitted from the light-emitting element ED arranged in the second sub-pixel SPX2 can pass through the thermal control layer HCL, the second wavelength conversion layer WCL2, the first capping layer CPL1, the low refractive layer LRL, the second capping layer CPL2, the planarization layer PNL and the second color filter layer CFL2, and be emitted as green light.

[0209] The light-emitting element ED disposed in the third sub-pixel SPX3 emits a third color blue light, which passes through the thermal control layer HCL and enters the transparent layer TPL. The third base resin BRS3 of the transparent layer TPL is made of a transparent material, and a part of the light passes through the resin layer PRS and the third base resin BRS3 and enters the first capping layer CPL1 disposed thereon. The light that enters the first capping layer CPL1 passes through the low refractive layer LRL, the second capping layer CPL2, and the planarization layer PNL and enters the third color filter layer CFL3, which can block the transmission of light other than blue light. Therefore, blue light can be emitted from the third sub-pixel SPX3.

[0210] The display device 10 according to the embodiment includes a thermal control layer HCL disposed on the light emitting element ED, and can effectively control heat emitted from the light emitting element ED. The display device 10 can minimize deterioration caused by heat emitted from the light emitting element ED, and can improve the life span.

[0211] FIG. 13 is a schematic diagram of a light-emitting device according to one embodiment.

[0212] 13, the light emitting element ED may be a light emitting diode, and more specifically, the light emitting element ED may be an inorganic light emitting diode having a size of nanometer to micrometer and made of an inorganic material. When an electric field is formed in a specific direction between two electrodes facing each other, the light emitting element ED may be aligned in polarity between the two electrodes.

[0213] The light emitting device ED according to an embodiment may have a shape extending in one direction. The light emitting device ED may have a shape of a cylinder, a rod, a wire, a tube, etc. However, the shape of the light emitting device ED is not limited thereto, and may have various shapes such as a polygonal prism shape such as a regular cube, a rectangular cube, a hexagonal prism, etc., or may extend in one direction but have a shape with a partially inclined outer surface.

[0214] The light-emitting element ED may include a semiconductor layer doped with a dopant of any conductivity type (e.g., p-type or n-type). The semiconductor layer may emit light of a specific wavelength band when an electrical signal applied from an external power source is transmitted to the semiconductor layer. The light-emitting element ED may include a first semiconductor layer 31, a second semiconductor layer 32, a light-emitting layer 36, an electrode layer 37, and an insulating film 38.

[0215] The first semiconductor layer 31 may be an n-type semiconductor. The first semiconductor layer 31 may be an Al x Ga y In 1-x-y The first semiconductor layer 31 may include a semiconductor material having a chemical formula of 0≦x≦1, 0≦y≦1, 0≦x+y≦1. For example, the first semiconductor layer 31 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant doped in the first semiconductor layer 31 may be Si, Ge, Sn, Se, etc.

[0216] The second semiconductor layer 32 is disposed on the first semiconductor layer 31 with the light emitting layer 36 therebetween. The second semiconductor layer 32 may be a p-type semiconductor, and the second semiconductor layer 32 may be Al x Ga y In 1-x-y The second semiconductor layer 32 may include a semiconductor material having a chemical formula of 0≦x≦1, 0≦y≦1, 0≦x+y≦1. For example, the second semiconductor layer 32 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant doped in the second semiconductor layer 32 may be Mg, Zn, Ca, Ba, etc.

[0217] In addition, in the drawings, the first semiconductor layer 31 and the second semiconductor layer 32 are shown as being configured as one layer, but are not limited thereto. Depending on the material of the light emitting layer 36, the first semiconductor layer 31 and the second semiconductor layer 32 may further include more layers, for example, a clad layer or a tensile strain barrier reducing (TSBR) layer. For example, the light emitting element ED may further include another semiconductor layer disposed between the first semiconductor layer 31 and the light emitting layer 36, or between the second semiconductor layer 32 and the light emitting layer 36. The semiconductor layer disposed between the first semiconductor layer 31 and the light emitting layer 36 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, InN, and SLs (strained-layer superlattice) doped with an n-type dopant, and the semiconductor layer disposed between the second semiconductor layer 32 and the light emitting layer 36 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant.

[0218] The light emitting layer 36 is disposed between the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a material having a single or multiple quantum well structure. When the light emitting layer 36 includes a material having a multiple quantum well structure, the light emitting layer 36 may have a structure in which quantum layers and well layers are alternately stacked. The light emitting layer 36 may emit light by the combination of electron-hole pairs in response to an electrical signal applied through the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a material such as AlGaN, AlGaInN, or InGaN. In particular, when the light emitting layer 36 has a multiple quantum well structure in which quantum layers and well layers are alternately stacked, the quantum layers may include a material such as AlGaN or AlGaInN, and the well layers may include a material such as GaN or AlInN.

[0219] The light emitting layer 36 may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately laminated, and may include different Group 3 to Group 5 semiconductor materials depending on the wavelength band of the emitted light. The light emitted by the light emitting layer 36 is not limited to light in the blue wavelength band, and may also emit light in the red or green wavelength band depending on the case.

[0220] The electrode layer 37 may be an Ohmic connection electrode, but is not limited thereto, and may be a Schottky connection electrode. The light emitting device ED may include at least one electrode layer 37. The light emitting device ED may include one or more electrode layers 37, but is not limited thereto, and the electrode layer 37 may be omitted.

[0221] The electrode layer 37 can reduce the resistance between the light emitting element ED and the electrode or the connecting electrode when the light emitting element ED is electrically connected to the electrode or the connecting electrode in the display device 10. The electrode layer 37 can also include a conductive metal. For example, the electrode layer 37 can include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

[0222] The insulating film 38 is disposed so as to surround the outer surfaces of the plurality of semiconductor layers and electrode layers described above. For example, the insulating film 38 may be disposed so as to surround at least the outer surface of the light emitting layer 36, and both ends in the longitudinal direction of the light emitting element ED may be exposed. Also, the insulating film 38 may be formed so that the upper surface in cross section has a rounded shape in a region adjacent to at least one end of the light emitting element ED.

[0223] The insulating film 38 is made of a material having insulating properties, such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), Aluminum Nitride (AlN x), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO x In the drawings, the insulating film 38 is illustrated as being formed as a single layer, but is not limited thereto, and in some embodiments, the insulating film 38 may be formed as a multi-layer structure in which multiple layers are stacked.

[0224] The insulating film 38 can protect the semiconductor layer and the electrode layer of the light-emitting element ED. The insulating film 38 can prevent an electrical short circuit that may occur in the light-emitting layer 36 when the insulating film 38 is in direct contact with an electrode through which an electrical signal is transmitted to the light-emitting element ED. The insulating film 38 can also prevent a decrease in the luminous efficiency of the light-emitting element ED.

[0225] In addition, the outer surface of the insulating film 38 may be surface-treated. The light emitting elements ED may be aligned by being sprayed on the electrodes in a dispersed state in a certain ink. Here, in order to maintain the dispersed state of the light emitting elements ED in the ink without agglomerating with other adjacent light emitting elements ED, the surface of the insulating film 38 may be hydrophobically or hydrophilically treated.

[0226] Other embodiments of the display device 10 will be described below with reference to other drawings.

[0227] FIG. 14 is a cross-sectional view showing a wavelength conversion layer and a thermal control layer of one subpixel of a display device according to another embodiment.

[0228] 14, in the display device 10_1 according to an embodiment, the thermal control layer HCL_1 may further include a scatterer SCP. Even if the thermal control layer HCL_1 is disposed between the light emitting element ED and the color control layers TPL, WCL1, and WCL2, the display device 10_1 can minimize the output loss of the light emitted from the light emitting element ED because the thermal control layer HCL_1 includes the scatterer SCP.

[0229] As described above, the thermal control layer HCL_1 includes a resin layer PRS and phase transition particles PCM dispersed therein, and has a structural similarity to the color control layers TPL, WCL1, and WCL2. In consideration of this, the thermal control layer HCL_1 may further include a scatterer SCP that scatters light emitted from the light emitting element ED. The thermal control layer HCL_1 including the scatterer SCP can scatter the light emitted from the light emitting element ED and incident on the color control layers TPL, WCL1, and WCL2, and can provide the light emitted from the light emitting element ED to the color control layers TPL, WCL1, and WCL2 with uniform brightness.

[0230] FIG. 15 is a cross-sectional view showing a color control layer and a thermal control layer disposed in one pixel according to another embodiment.

[0231] 15, the display device 10_2 according to an embodiment has a larger thickness of the thermal control layer HCL_2. The upper surface of the thermal control layer HCL_2 may be located higher than the bank layer BNL and the uppermost surfaces of the second insulating layer PAS2 and the third insulating layer PAS3. A portion of the thermal control layer HCL_2 may be disposed in an area surrounded by the upper bank layer UBM, and a portion of the side surface may be in contact with the upper bank layer UBM. The upper surface of the thermal control layer HCL_2 may rise to the upper bank layer UBM.

[0232] In the manufacturing process of the display device 10_2, the thermal control layer HCL_2 may be formed by an inkjet printing process. As in the above-mentioned embodiment, when the thermal control layer HCL is printed before the upper bank layer UBM is formed, the upper surface of the thermal control layer HCL may have the same height as the bank layer BNL and the uppermost surfaces of the second insulating layer PAS2 and the third insulating layer PAS3. On the other hand, as in the present embodiment, when the thermal control layer HCL_2 is printed after the upper bank layer UBM is formed, the upper surface of the thermal control layer HCL_2 may be located higher than the bank layer BNL and the uppermost surfaces of the second insulating layer PAS2 and the third insulating layer PAS3. The color control layers TPL, WCL1, and WCL2 may be disposed directly on the thermal control layer HCL_2 within the area surrounded by the upper bank layer UBM. However, as described above, the thickness of the thermal control layer HCL_2 may be smaller than the thickness of the color control layers TPL, WCL1, and WCL2.

[0233] FIG. 16 is a cross-sectional view showing a color control layer and a thermal control layer disposed in one pixel according to another embodiment.

[0234] 16, in a display device 10_3 according to an embodiment, a thermal control layer HCL_3 may be disposed over a plurality of sub-pixels SPXn. The thermal control layer HCL_3 may be disposed over a plurality of sub-pixels SPXn beyond the bank layer BNL in addition to the region surrounded by the bank layer BNL. A portion of the thermal control layer HCL_3 may be disposed on the bank layer BNL, and the upper bank layer UBM and the color control layers TPL, WCL1, and WCL2 may be disposed on the thermal control layer HCL_3.

[0235] Different from the embodiment of FIG. 15, when the thermal control layer HCL_3 is printed before the formation of the upper bank layer UBM, and thus the thickness is larger, the thermal control layer HCL_3 can be formed to cover the bank layer BNL. The thermal control layer HCL_3 includes a resin layer PRS, and can also compensate for the lower step, and the upper bank layer UBM and the color control layers TPL, WCL1, and WCL2 can be disposed directly on the thermal control layer HCL_3, respectively. Different from the above-mentioned embodiment, the upper bank layer UBM overlaps the bank layer BNL, but the lower surface can contact the thermal control layer HCL_3.

[0236] FIG. 17 is a cross-sectional view showing a wavelength conversion layer and a thermal control layer of one subpixel of a display device according to another embodiment.

[0237] 17, in a display device 10_4 according to an embodiment, the thermal control layer HCL is omitted, and the color control layers TPL, WCL1, and WCL2 may include phase change particles PCM_4. The color control layers TPL, WCL1, and WCL2 may include phase change particles PCM_4 in addition to the wavelength conversion materials WCP1 and WCP2 or the scatterers SCP dispersed in the base resins BRS1, BRS2, ​​and BRS3. The color control layers TPL, WCL1, and WCL2 may further include phase change particles PCM_4 to convert the light emitted from the light emitting element ED and control the heat generated by the light emitting element ED.

[0238] Although the embodiment of the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiment is illustrative in all respects and not limiting.

Claims

1. a plurality of sub-pixels including a first electrode and a second electrode spaced apart from each other, and a light-emitting element disposed on the first electrode and the second electrode and electrically connected to the first electrode and the second electrode; a bank layer surrounding an area in which the light-emitting element of the sub-pixel is disposed; a thermal control layer disposed so as to cover the light emitting element and disposed in an area surrounded by the bank layer; an upper bank layer disposed on the bank layer; and a color control layer disposed on the thermal control layer and in an area surrounded by the upper bank layer; The display device, wherein the thermal control layer includes a resin layer, a core portion including a phase transition material, and a first shell surrounding the core portion, and the thermal control layer includes phase transition particles dispersed in the resin layer.

2. the core portion includes at least one of dodecane, docosane, and an aluminum-silicon alloy; 2. The display device of claim 1, wherein the first shell includes at least one of polystyrene, polymethylmethacrylate, aluminum oxide, and polymethylmethacrylate-silica.

3. the phase change particle further comprises a second shell surrounding the core and comprising a thermally conductive material; The display device of claim 2 , wherein the first shell surrounds the second shell.

4. The display device of claim 3, wherein the second shell includes at least one of graphite, carbon black, and a conductive polymer.

5. The display device of claim 1 , wherein the phase change particles have a diameter of 1 μm or less.

6. The display device according to claim 1 , wherein the resin layer of the thermal control layer includes any one of an epoxy resin, an acrylic resin, a cardo resin, and an imide resin.

7. The display device according to claim 1 , wherein the thermal control layer further comprises a scatterer.

8. The display device of claim 1 , wherein the color control layer has a thickness greater than the thermal control layer.

9. 9. The display device of claim 8, wherein the color control layer has a thickness in the range of 8 [mu]m to 10 [mu]m, and the thermal control layer has a thickness of about 2 [mu]m.

10. a first insulating layer disposed over the first electrode and the second electrode; a second insulating layer disposed on the light emitting element and the bank layer; and The display device according to claim 1 , further comprising a third insulating layer disposed on the second insulating layer and the bank layer, the bank layer being disposed on the first insulating layer.

11. The display device according to claim 10 , wherein the height of the upper surface of the thermal control layer is equal to or lower than the height of the upper surface of the third insulating layer disposed on the bank layer.

12. The display device according to claim 10 , wherein the height of the upper surface of the thermal control layer is higher than the height of the upper surface of the third insulating layer disposed on the bank layer.

13. The display device according to claim 12 , wherein a part of a side surface of the thermal control layer is in contact with the upper bank layer.

14. the thermal control layer is partially disposed on the bank layer; The display device of claim 1 , wherein the color control layer and the upper bank layer are disposed on the thermal control layer.

15. The color control layer is a first wavelength-converting layer disposed in the first sub-pixel and including first wavelength-converting particles; a second wavelength-converting layer disposed in the second sub-pixel and including second wavelength-converting particles; and a light-transmitting layer including a scatterer, the light-transmitting layer being disposed in a third sub-pixel; The display device according to claim 1 , wherein the thermal control layer is disposed between the first wavelength conversion layer, the second wavelength conversion layer, and the light-transmitting layer and the light-emitting element.

16. The display device of claim 1 , further comprising: a first connecting electrode in contact with the light emitting element and disposed on the first electrode; and a second connecting electrode in contact with the light emitting element and disposed on the second electrode.

17. a plurality of sub-pixels including a first electrode and a second electrode spaced apart from each other, and a light-emitting element disposed on the first electrode and the second electrode and electrically connected to the first electrode and the second electrode; a bank layer surrounding an area in which the light-emitting element of the sub-pixel is disposed; an upper bank layer disposed on the bank layer; and a color control layer disposed on the light emitting element and in a region surrounded by the upper bank layer; the color control layer includes a first wavelength conversion layer disposed in the first sub-pixel and including first wavelength conversion particles, a second wavelength conversion layer disposed in the second sub-pixel and including second wavelength conversion particles, and a light-transmitting layer disposed in the third sub-pixel and including a scatterer; The first wavelength conversion layer, the second wavelength conversion layer, and the light-transmitting layer each include a phase-transition particle including a core portion containing a phase-transition material and a first shell surrounding the core portion.

18. the core portion includes at least one of dodecane, docosane, and an aluminum-silicon alloy; 18. The display device of claim 17, wherein the first shell includes at least one of polystyrene, polymethylmethacrylate, aluminum oxide, and polymethylmethacrylate-silica.

19. the phase change particle further comprises a second shell surrounding the core and comprising a thermally conductive material; 20. The display of claim 18, wherein the first shell surrounds the second shell.

20. 20. The display device of claim 17, wherein the phase change particles have a diameter of 1 [mu]m or less.

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