Piezoelectric-on-insulator (POI) substrate and method for manufacturing a piezoelectric-on-insulator (POI) substrate
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-03-30
- Publication Date
- 2026-03-24
AI Technical Summary
The diffusion of metal elements, such as lithium, from the piezoelectric layer through the dielectric layer and trap structure to the interface with the support substrate during heat treatment reduces the performance quality of the trap structure, leading to increased side effects like signal attenuation and harmonic signal generation.
A piezoelectric on insulator (POI) substrate with a support substrate, a piezoelectric layer, a dielectric layer, and a trap structure is designed. The trap structure is composed of at least two trap layers separated by a dielectric intermediate layer, which effectively separates and reduces the accumulation of metallic contamination at the interface between the trap structure and the support substrate.
The separation of trap layers with a dielectric intermediate layer significantly reduces the concentration of metal elements at the interface, thereby minimizing side effects such as signal attenuation and harmonic signal generation, and maintaining high resistivity within the support substrate.
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Abstract
Description
[Technical field]
[0001] The present invention relates to a piezoelectric-on-insulator (POI) substrate comprising a support substrate, a trap structure, a dielectric layer, and a piezoelectric layer in this order, and to a method for manufacturing such a POI substrate.
[0002]
[0002] Such substrates are known in the prior art. Devices such as sensors or filters are fabricated in and / or on the piezoelectric layer.
[0003]
[0003] The trap structure makes it possible to reduce losses related to side effects at the interface between the support substrate and the dielectric layer. This is because the trap layer inserted between the support substrate and the dielectric layer serves to reduce the density of free carriers and prevent the fluctuation of the Fermi level. This makes it possible to make the resistivity in the support substrate higher and more constant, thereby reducing side effects such as signal attenuation, generation of harmonic signals, or direct coupling.
[0004] However, it has been found that metallic elements of the piezoelectric layer, such as lithium, can diffuse through the dielectric layer and the trapping structure to the interface with the support substrate during heat treatments or in conjunction with the manufacture of the POI substrate. The accumulation of these metallic elements reduces the performance quality of the trapping structure, thus adversely affecting the suppression of side effects.
[0005]
[0005] It is therefore an object of the present invention to reduce the deleterious effects of diffusion of metal elements through the structure of a POI substrate. Summary of the Invention
[0006] The object of the present invention is achieved by a Piezoelectric-on-insulator (POI) substrate comprising a support substrate, in particular a silicon-based substrate, a piezoelectric layer, in particular a layer of lithium tantalate (LTO) or lithium niobate (LNO), a dielectric layer, in particular a silicon oxide layer, sandwiched between the piezoelectric layer and the support substrate, and a trap structure sandwiched between the dielectric layer and the support substrate, characterized in that the trap structure comprises at least two trap layers, which are separated from each other by a dielectric intermediate layer. By separating the trap structure into at least two trap layers and providing a dielectric layer between the two trap layers, it becomes possible to separate a part of the contamination by metal elements at the interface between the trap layer and the intermediate layer, so that the cumulative level of metal elements at the interface between the trap structure and the support structure is reduced. Thus, side effects can be effectively reduced. The support substrate can preferably have a resistivity of 500 Ω.cm or more.
[0007] According to one embodiment, the trapping layer of the POI substrate can be based on polycrystalline silicon or amorphous silicon or porous silicon or based on silicon carbide (SiC). Such a layer effectively reduces side effects.
[0008] According to one embodiment, the dielectric intermediate layer of the POI substrate can be a layer of silicon oxide, in particular a layer of native silicon oxide, or a layer deposited by chemical vapor deposition (CVD), or a layer obtained by thermal oxidation. Silicon oxide is easy to fabricate and at the same time allows the accumulation of diffused metal elements to be observed at the interface of the intermediate layer of the trap structure.
[0009] According to one embodiment, the dielectric intermediate layer of the POI substrate can have a thickness of 5 nm or less, in particular 1 nm or less. Even such a thin layer is effective in reducing side effects.
[0010] According to one embodiment, at least two of the at least two trapping layers may have one or more different physical properties, particularly particle size, which may allow for better suppression of side effects.
[0011] According to one embodiment, each trapping layer of the POI substrate may have the same thickness. According to one alternative, at least one trapping layer of the POI substrate may have a different thickness than the other trapping layers, thereby optimizing the properties of the POI substrate.
[0012] According to one embodiment, the trap structure of the POI substrate can have a thickness of 5 μm or less, preferably 2 μm or less. Thus, even with a thinner trap structure than the prior art, a sufficient reduction in side effects can be obtained.
[0013]
[0013] The object of the present invention is also achieved by a method for manufacturing a piezoelectric-on-insulator (POI) substrate, comprising the steps of: providing a support substrate, in particular a silicon-based substrate; providing a substrate with a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO); forming a trap structure above the support substrate; forming a dielectric layer, in particular a silicon oxide layer, above the substrate with the piezoelectric layer and / or above the trap structure; and assembling the substrate with the piezoelectric layer with the support substrate such that the dielectric layer and the trap structure are sandwiched between the piezoelectric layer and the support substrate, characterized in that the step of forming the trap structure includes the steps of forming a first trap layer, forming a dielectric intermediate layer on the first trap layer, and forming a second trap layer on the dielectric intermediate layer. By this method, a substrate can be obtained that can effectively reduce the adverse effect of diffusion of metal elements into the support substrate.
[0014] According to one embodiment, the method for producing a piezoelectric substrate may further comprise the steps of forming a weakened zone in the piezoelectric layer in order to transfer a portion of the piezoelectric layer onto a support substrate, and fracturing along the weakened zone in order to separate the portion of the piezoelectric layer from the remaining portion of the substrate comprising the piezoelectric layer after the assembly step. This method allows industrial production of POI substrates according to the invention.
[0015] The invention and its advantages will be explained in more detail subsequently by means of preferred embodiments given as examples and with the aid of the following attached drawings in which reference numbers identify the features of the invention, in which: [Brief description of the drawings]
[0016] [Figure 1] 1 illustrates a schematic representation of a Piezoelectric-on-Insulator (POI) substrate according to a first embodiment of the present invention; [Diagram 2]
[0017] 2 illustrates diagrammatically a Piezoelectric-on-Insulator (POI) substrate according to a second embodiment of the present invention; [Diagram 3]
[0018] 2 illustrates diagrammatically a Piezoelectric-on-Insulator (POI) substrate according to a third embodiment of the present invention; [Figure 4]
[0019] 5A and 5B illustrate a method for manufacturing a Piezoelectric-on-Insulator (POI) substrate according to a fourth embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0017]
[0020] It should be noted that the described embodiments are merely possible configurations, and that individual features as described above may be provided independently of one another or may be omitted entirely during the implementation of the present invention.
[0018]
[0021] FIG. 1 illustrates a schematic diagram of a piezoelectric-on-insulator (POI) substrate 100 according to a first embodiment of the present invention.
[0019]
[0022] The piezoelectric-on-insulator substrate 100 comprises a supporting substrate 102. In this first embodiment, the supporting substrate 102 is a silicon-based substrate, in particular a single crystal silicon wafer. The supporting substrate preferably has a resistivity of 500 Ω.cm or higher.
[0020]
[0023] The trapping structure 104 is disposed above the supporting substrate 102. The trapping structure 104 may be in direct contact with the supporting substrate 102. The trapping structure 104 has a thickness of 5 μm or less, preferably 2 μm or less.
[0021]
[0024] According to the first embodiment, the trapping structure 104 comprises three layers: a first trapping layer 104a, a dielectric intermediate layer 104b and a second trapping layer 104c.
[0022]
[0025] The trapping layers 104a, 104c are based on polycrystalline or amorphous or porous silicon or on silicon carbide (SiC). Preferably, the trapping layers are layers deposited by low pressure chemical vapor deposition (LPCVD). In this embodiment, the thicknesses of the two trapping layers 104a, 104c are the same.
[0023]
[0026] The dielectric interlayer 104b may be a layer of silicon oxide, preferably a layer of native silicon oxide. According to an alternative, the dielectric interlayer may also be formed by chemical vapor deposition (CVD) or by thermal oxidation. The dielectric interlayer 104b preferably has a smaller thickness than the trapping layers 104a, 104b, in particular a thickness of 5 nm or less, in particular a thickness of 1 nm or less.
[0024]
[0027] The dielectric layer 106 is arranged above, in particular directly above, the trapping structure 104. The dielectric layer 106 is preferably a silicon oxide based layer. The dielectric layer 106 preferably has a thickness of 100 nm to 1 μm, in particular 200 nm to 700 nm. The dielectric layer 106 can be formed by CVD deposition or any other suitable deposition process.
[0025]
[0028] The piezoelectric layer 108 is disposed above, and in particular directly above, the dielectric layer 106. The piezoelectric layer is preferably a layer of lithium tantalate (LTO) or lithium niobate (LNO). The piezoelectric layer 108 typically has a thickness of 200 nm to 1 μm.
[0026]
[0029] According to an alternative, the two trapping layers 104a and 104c may have one or more different physical properties, such as grain size.
[0027]
[0030] By separating the trapping structure 104 into at least two trapping layers 104a, 104c and providing a dielectric intermediate layer 104b between the two trapping layers 104a, 104c, some of the contamination by metal elements can be separated at the interface between the trapping layers 104a, 104c and the intermediate layer 104b, thereby reducing the concentration of metal elements at the interface between the trapping structure 104 and the support structure 102, thus compensating for the reduced suppression of side effects.
[0028]
[0031] FIG. 2 illustrates a schematic diagram of a piezoelectric-on-insulator (POI) substrate 200 according to a second embodiment of the present invention.
[0029]
[0032] The piezoelectric-on-insulator substrate 200 comprises the support substrate 102, the dielectric layer 106 and the piezoelectric layer 108 of the first embodiment. A new description of these layers and the properties of these layers will be omitted, and reference is made to the above description of these layers related to the first embodiment.
[0030]
[0033] The only difference between the first and second embodiments is the use of a different trapping structure 204 .
[0031]
[0034] In the second embodiment, the trapping structure 204 comprises a total of five trapping layers 204a, 204c, 204e, 204g and 204i. An intermediate dielectric layer 204b, 204d, 204f, 204h is inserted between each two trapping layers.
[0032]
[0035] The trapping layers 204a, 204c, 204e, 204g, 204i are fabricated similarly to and have the same physical properties as the trapping layers 104a, 104c of the first embodiment, and in particular all have the same thickness, in particular all less than 0.2 μm.
[0033]
[0036] Similarly, the dielectric interlayers 204b, 204d, 204f, 204h are fabricated in a similar manner to the dielectric interlayer 104b of the first embodiment and have the same physical properties as this layer, and in particular all have the same thickness, in particular all have a thickness of a few tens of nanometers (a few Angstroms), in particular a thickness of 1 nanometer or less (10 Angstroms or less).
[0034]
[0037] By increasing the number of interfaces in the trapping structure 204, metal elements are captured at each interface, which further reduces the concentration of metal elements, particularly lithium, at the interface between the first trapping layer 204a and the support substrate 102. Therefore, the amount of metal elements that reach the interface with the support substrate 102 is less than in a structure with fewer interfaces.
[0035]
[0038] According to alternatives, more or less trapping layers and dielectric interlayers may be provided in the trapping structure depending on the concentration levels of the metallic elements that are deemed acceptable for a given application.
[0036]
[0039] FIG. 3 illustrates a piezoelectric-on-insulator (POI) substrate 300 according to a third embodiment of the present invention.
[0037]
[0040] The piezoelectric-on-insulator substrate 300 comprises the support substrate 102, the dielectric layer 106 and the piezoelectric layer 108 of the first embodiment. These layers and the properties of these layers will not be described again, but reference is made to the description thereof in the first embodiment.
[0038]
[0041] The only difference between the first and third embodiments is the use of a different trapping structure 304 .
[0039]
[0042] In this embodiment, the trapping structure 304 comprises several trapping layers 304a, 304c, 304e, 304g, 304i and 304k separated by dielectric intermediate layers 304b, 304d, 304f, 304h and 304j, as in the second embodiment.
[0040]
[0043] The dielectric intermediate layers 304b, 304d, 304f, 304h and 304j are fabricated as in the first or second embodiment and have the same thickness, for example a few tens of nanometers (a few angstroms), in particular less than or equal to 1 nanometer (less than or equal to 10 angstroms).
[0041]
[0044] On the other hand, several thin trapping layers 304c, 304e, 304g, 304i and 304k all have the same thickness, for example 0.1 μm or less, while trapping layer 304a is thicker, in particular having a thickness of 0.5 μm or more.
[0042]
[0045] Similar to the second embodiment, the concentration of metal elements, particularly lithium, at the interface between the first trapping layer 304a and the supporting substrate 102 can be reduced by increasing the interface in the trapping structure 304. The layer 304a at the interface with the supporting substrate 102 is thicker and therefore retains its trapping properties.
[0043]
[0046] According to alternatives, more or fewer trapping layers and dielectric interlayers may be provided in the trapping structure depending on the accumulated level of metallic elements that is deemed acceptable for a given application.
[0044]
[0047] [Figure 4] Figure 4 shows a schematic diagram of a method for manufacturing a piezoelectric on insulator (POI) substrate according to a fourth embodiment of the present invention, in order to obtain a POI substrate 100 according to the first embodiment described above in relation to Figure 1. The reference numbers already used in the description of the POI substrate 100 in Figure 1 are reused in the description of the method.
[0045]
[0048] The manufacturing method for a piezoelectric-on-insulator (POI) substrate 100 begins with step I) of providing a supporting substrate 102, in particular a silicon-based substrate, in particular a single crystal silicon wafer.
[0046]
[0049] According to this fourth embodiment of the invention, step II) forms a trapping structure 104 on the free surface 120 of the supporting substrate 102 .
[0047]
[0050] The formation of the trapping structure 104 begins with the formation of a first trapping layer 104a fabricated by low pressure chemical vapor deposition (LPCVD). According to alternatives, the formation can be carried out by thermal growth methods or physical vapor deposition (PVD).
[0048]
[0051] The trapping layer 104a formed on the support substrate 102 is a layer based on polycrystalline silicon, amorphous silicon or porous silicon or based on silicon carbide. The thickness of the trapping layer 104a is 2.5 μm or less, in particular 1 μm or less.
[0049]
[0052] Subsequently, a dielectric intermediate layer 104b is formed on the first trapping layer 104a. The dielectric intermediate layer 104b may be a layer of silicon oxide, preferably a layer of native silicon oxide. According to one alternative, the dielectric intermediate layer is formed by chemical vapor deposition (CVD) or by thermal oxidation. The dielectric intermediate layer 104b preferably has a smaller thickness than the first trapping layer 104a, in particular a thickness of less than 5 nm, in particular a thickness of less than 1 nm.
[0050]
[0053] To complete the formation of the trapping structure 104, a second trapping layer 104c is formed on the dielectric interlayer 104b in a similar manner to the first trapping layer 104a, specifically to the same thickness.
[0051]
[0054] According to an alternative, the two trapping layers 104a and 104c can be formed with one or more different physical properties, such as grain size. According to another alternative, the two trapping layers 104a and 104c can be based on different materials, among those named above. For example, layer 104a can be made of porous silicon and layer 104c can be made of polycrystalline silicon.
[0052]
[0055] During step III), a dielectric layer 106a is formed on the free surface 122 of the second trapping layer 104c. The dielectric layer 106a is preferably a silicon oxide layer formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). According to an alternative, the layer 106a is formed by oxidation of polycrystalline silicon.
[0053]
[0056] The thickness of the dielectric layer 106a is preferably 1 μm or less, and more preferably 700 nm or less.
[0054]
[0057] After deposition of the dielectric layer 106a, a heat treatment may be performed to densify the dielectric layer 106a.
[0055]
[0058] During step IV), a substrate 124 is provided with a piezoelectric layer 126, in particular a substrate 124 comprising lithium tantalate (LTO) or lithium niobate (LNO). The piezoelectric layer 124 is arranged above a base substrate 126 in this embodiment. In an alternative, the piezoelectric layer 126 is a bulk layer and forms the entire substrate 124.
[0056]
[0059] During step V), a second dielectric layer 106b, in particular a silicon oxide layer, is fabricated on the free surface 130 of the piezoelectric layer 126. This layer is fabricated in the same way as the dielectric layer 106a formed during step III). The thickness is chosen such that the sum of the thicknesses of the two dielectric layers 106a and 106b is between 100 nm and 1 μm, in particular between 200 nm and 700 nm.
[0057]
[0060] According to an alternative, one or more steps of surface treatment of the free surface 130 of the substrate 124 comprising the piezoelectric layer can be carried out before the formation of the dielectric layer 106b. For example, a surface activation treatment such as a plasma treatment and / or an ozone-based treatment can be carried out.
[0058]
[0061] During step VI), the substrate 124 obtained after step V) is assembled with the support substrate 102 obtained in assembly step III) to form an assembly 132 of support substrate-substrate with piezoelectric layer.
[0059]
[0062] The assembly is performed so that the dielectric layers 106a and 106b are in direct contact with each other, preferably by molecular adhesion.
[0060]
[0063] Once the two substrates are assembled, step VII) is performed to thin the assembly 132 in order to obtain a POI substrate 100 with a thinner piezoelectric layer 108, as shown in FIG.
[0061]
[0064] For example, the thinning step can be performed by milling or by forming and fracturing a weakened zone in the piezoelectric substrate 126 before assembly step VI) so as to define the boundary of the piezoelectric layer 108 to be transferred onto the support substrate 102. This step of forming a weakened zone is performed by implantation of atomic or ionic species into the piezoelectric layer 126. Atomic or ionic implantation can be performed such that the weakened zone is located inside the piezoelectric layer 126 and defines the boundary of the piezoelectric layer 108 to be transferred from the rest of the piezoelectric layer 126. Then, a step of fracturing the assembly 132 follows by supplying thermal and / or mechanical energy to the weakened zone of the piezoelectric layer 126 in order to obtain a piezoelectric-on-insulator (POI) substrate 100.
[0062]
[0065] According to an alternative, the bond between the support substrate 102 and the substrate 124 can also be made between the trapping structure 104 and the dielectric layer 106b, i.e. without performing step III), or between the dielectric layer 106a and the piezoelectric layer 126.
[0063]
[0066] Prior to fabricating one or more of the above-mentioned layers, one or more steps of cleaning, brushing or polishing the underlying surface may be performed to remove the presence of particles and dust.
[0064]
[0067] This method can also be applied to obtain the POI substrates 200 and 300 of the second and third embodiments of the invention described in relation to Figures 2 and 3, respectively.
Claims
1. Support substrate (102), particularly a silicon-based substrate, A piezoelectric layer (108), particularly a layer of lithium tantalate (LTO) or lithium niobate (LNO), A dielectric layer (106), particularly a silicon oxide layer, is sandwiched between the piezoelectric layer (108) and the support substrate (102). A trap structure (104) sandwiched between the dielectric layer (106) and the support substrate (102), A piezoelectric on-insulator (POI) substrate comprising, A piezoelectric on-insulator (POI) substrate characterized in that the trap structure (104) comprises at least two trap layers (104a, 104c), the trap layers (104a, 104c) are separated from each other by a dielectric intermediate layer (104b), and at least two of the at least two trap layers (104a, 104c) have different physical properties, particularly particle size.
2. The piezoelectric on-insulator (POI) substrate according to claim 1, wherein the trap layers (104a, 104c) are based on polycrystalline silicon and / or amorphous silicon and / or porous silicon and / or silicon carbide (SiC).
3. The piezoelectric on-insulator (POI) substrate according to claim 1 or 2, wherein the dielectric intermediate layer (104b) is a layer of silicon oxide, particularly a layer of native silicon oxide, or a layer deposited by chemical vapor deposition (CVD), or a layer obtained by thermal oxidation.
4. The piezoelectric on-insulator (POI) substrate according to claim 1 or 2, wherein the dielectric intermediate layer (104b) has a thickness of 5 nm or less, particularly 1 nm or less.
5. The piezoelectric on-insulator (POI) substrate according to claim 1 or 2, wherein each trap layer (104a, 104c) has the same thickness.
6. The piezoelectric on-insulator (POI) substrate according to claim 1 or 2, wherein at least one trap layer (304a) has a different thickness from the other trap layers (304c, 304e), and in particular, the trap layer (304a) provided directly on the support substrate is thicker than the other trap layers.
7. The piezoelectric on-insulator (POI) substrate according to claim 1 or 2, wherein the trap structure (104) has a thickness of 5 μm or less, preferably 2 μm or less.
8. The steps include providing a support substrate, particularly a silicon-based substrate, The steps include providing a substrate comprising a piezoelectric layer, particularly a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO), The steps include forming a trap structure above the support substrate, The steps include forming a dielectric layer, particularly a silicon oxide layer, above the substrate having a piezoelectric layer and / or above the trap structure, The steps include assembling the substrate having a piezoelectric layer with the support substrate such that the dielectric layer and the trap structure are sandwiched between the piezoelectric layer and the support substrate, A method for manufacturing a piezoelectric on-insulator (POI) substrate according to claim 1 or 2, comprising: The step of forming the trap structure is A method comprising the steps of forming a first trap layer, forming a dielectric intermediate layer on the first trap layer, and forming a second trap layer on the dielectric intermediate layer, wherein the two trap layers have different physical properties, particularly particle size.
9. The steps include forming a weakening zone inside the piezoelectric layer, A method for manufacturing a piezoelectric substrate according to claim 8, further comprising the step of crushing along the weakening zone after the assembly step in order to transfer a portion of the piezoelectric layer onto the support substrate, in order to separate the portion of the piezoelectric layer from the rest of the substrate having the piezoelectric layer.