Technique for processing data elements stored in an array storage - Patents.com

Abstract

An apparatus is provided that includes a processing circuit for performing an operation, an instruction decoder circuit for decoding instructions and controlling the processing circuit to perform an operation specified by the instruction, and an array storage including storage elements for storing data elements. The array storage is configured to store at least one two-dimensional array of data elements accessible to the processing circuit when performing the operation, each two-dimensional array of data elements including a plurality of vectors of data elements, each vector being one-dimensional. The instruction decoder circuit is configured to, in response to decoding a zero vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage, also decode a subsequent accumulate instruction configured to operate on the identified plurality of vectors of data elements, and to control the processing circuit to perform a non-accumulate version of the accumulate operation specified by the accumulate instruction to generate result data elements for storage in the identified plurality of vectors in the array storage.

Description

[Technical field]

[0001] The present technology relates to the field of data processing, and more particularly to processing data elements stored in array storage.

[0002] Some modern data processing systems may provide array storage for storing one or more two-dimensional arrays of data elements that may be accessed by processing circuitry of the data processing system when performing data processing operations. This may provide an efficient mechanism for performing a number of different types of operations, including, for example, cumulative sum functions, whose cumulative sum outputs may be maintained in a two-dimensional array of data elements.

[0003] However, in order to maximize the efficiency gains that can be realized from the use of such array storage, it would be beneficial to provide an efficient mechanism for freeing up array storage resources for use in connection with subsequent operations. Summary of the Invention

[0004] According to one exemplary configuration, an apparatus is provided comprising: a processing circuit for performing an operation; an instruction decoder circuit for decoding instructions and controlling the processing circuit to perform the operation specified by the instruction; and an array storage including storage elements for storing data elements, the array storage configured to store at least one two-dimensional array of data elements accessible to the processing circuit when performing the operation, each two-dimensional array of data elements including a plurality of vectors of data elements, each vector being one dimensional; and the instruction decoder circuit is configured to, in response to decoding a zero vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage, also decode a subsequent cumulative sum instruction configured to operate on the identified plurality of vectors of data elements, and to control the processing circuit to perform a non-cumulative sum variant of the cumulative sum operation specified by the cumulative sum instruction to generate result data elements for storage in the identified plurality of vectors in the array storage.

[0005] In another exemplary configuration, a method is provided for processing data elements in an array storage of a device, the method including: performing an operation using a processing circuit; decoding the instruction using an instruction decoder circuit to control the processing circuit to perform the operation specified by the instruction; providing storage elements in the array storage for storing the data elements, the array storage configured to store at least one two-dimensional array of data elements accessible to the processing circuit when performing the operation, each two-dimensional array of data elements including a plurality of vectors of data elements, each vector being one dimensional; and using the instruction decoder circuit to control the processing circuit to, in response to decoding a zero vector instruction that identifies a plurality of vectors of data elements in the given two-dimensional array of data elements in the array storage, also decode a subsequent cumulative sum instruction configured to operate on the identified plurality of vectors of data elements, perform a non-cumulative sum variant of the cumulative sum operation specified by the cumulative sum instruction, and generate result data elements for storage in the identified plurality of vectors in the array storage.

[0006] In a further exemplary arrangement, there is provided a computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program including: processing program logic for performing operations; instruction decode program logic for decoding instructions and controlling the processing program logic to perform operations specified by the instructions; and array storage emulation program logic for emulating an array storage including storage elements for storing data elements, the array storage configured to store at least one two dimensional array of data elements accessible to the processing program logic when performing the operations, each two dimensional array of data elements including a plurality of vectors of data elements, each vector being one dimensional; and the instruction decode program logic is configured to, in response to decoding a zero vector instruction that identifies a plurality of vectors of data elements of a given two dimensional array of data elements in the array storage, also decode a subsequent cumulative sum instruction configured to operate on the identified plurality of vectors of data elements, and to control the processing program logic to perform a non-cumulative sum variant of the cumulative sum operation specified by the cumulative sum instruction to generate result data elements for storage in the identified plurality of vectors in the array storage.

[0007] In another exemplary configuration, an apparatus is provided comprising: a processing circuit for performing an operation; an instruction decoder circuit for decoding instructions and controlling the processing circuit to perform the operation specified by the instruction; and an array storage including storage elements for storing data elements, the array storage configured to store at least one two-dimensional array of data elements accessible to the processing circuit when performing the operation, each two-dimensional array of data elements including a plurality of vectors of data elements, each vector being one dimensional; and the instruction decoder circuit configured to control the processing circuit to set storage elements of the array storage used to store data elements of the identified plurality of vectors to logical zero values ​​in response to decoding a zero vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage.

[0008] In a further exemplary configuration, a method is provided for processing data elements in an array storage of an apparatus, the method comprising: performing an operation using a processing circuit; decoding the instruction using an instruction decoder circuit to control the processing circuit to perform the operation specified by the instruction; and providing storage elements in the array storage for storing the data elements, the array storage configured to store at least one two-dimensional array of data elements accessible to the processing circuit when performing the operation, each two-dimensional array of data elements including a plurality of vectors of data elements, each vector being one dimensional, wherein in response to decoding a zero vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage, the instruction decoder circuit controls the processing circuit to set storage elements of the array storage used to store data elements of the identified plurality of vectors to logical zero values.

[0009] In a further exemplary arrangement, there is provided a computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program including: processing program logic for performing operations; instruction decode program logic for decoding instructions and controlling the processing program logic to perform operations specified by the instructions; and array storage emulation program logic for emulating an array storage including storage elements for storing data elements, the array storage being configured to store at least one two-dimensional array of data elements accessible to the processing program logic when performing the operations, each two-dimensional array of data elements including a plurality of vectors of data elements, each vector being one dimensional; and the instruction decode program logic is configured to control the processing program logic to set storage elements of the array storage used to store data elements of the identified plurality of vectors to logical zero values ​​in response to decoding a zero vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage. [Brief description of the drawings]

[0010] The present technology will now be further described, by way of example only, with reference to examples of the technology illustrated in the accompanying drawings. [Figure 1] FIG. 1 is a block diagram of an apparatus according to an exemplary implementation. [Diagram 2] FIG. 1 illustrates an example of architectural registers that may be provided within the apparatus, including vector registers for storing vector operands and array registers for storing 2D arrays of data elements, including an example of a physical implementation of the array registers. [Figure 3A] An example is given where a given 2D array of data elements can be either non-square or square. [Figure 3B] An example is given where a given 2D array of data elements can be either non-square or square. [Figure 4A]1 illustrates generally how access to a square 2D array in array storage may be performed according to one exemplary implementation. [Figure 4B] 1 illustrates generally how access to a square 2D array in array storage may be performed according to one exemplary implementation. [Figure 5A] 13 illustrates generally the fields that may be provided in a move and zero instruction, according to one exemplary implementation; [Figure 5B] 13 illustrates generally the sub-fields that may be used in one particular exemplary implementation to implement the vector identification field of the move and zero instructions. [Figure 6] 1 is a flow diagram illustrating how a move and zero command may be processed according to an example implementation. [Figure 7] 1 illustrates one exemplary instruction sequence that may operate on data elements provided within the array storage, the instruction sequence including several instances of the move and zero instructions described herein. [Figure 8] 1 illustrates diagrammatically a Finite Impulse Response (FIR) filtering operation that may be performed. [Figure 9A] FIG. 1 illustrates how array storage may be used when performing 2D image filtering operations, according to an exemplary implementation. [Figure 9B] FIG. 1 illustrates how array storage may be used when performing 2D image filtering operations, according to an exemplary implementation. [Figure 9C] FIG. 1 illustrates how array storage may be used when performing 2D image filtering operations, according to an exemplary implementation. [Figure 9D] FIG. 1 illustrates how array storage may be used when performing 2D image filtering operations, according to an exemplary implementation. [Figure 10]1 illustrates an alternative exemplary instruction sequence that may operate on data elements provided within the array storage, the instruction sequence including several instances of the move and zero instructions described herein. [Figure 11] 1 is a flow diagram illustrating how a zero vector instruction may be processed, according to an example implementation. [Figure 12] FIG. 10 is a schematic diagram illustrating fields that may be provided in a zero vector instruction, according to an exemplary implementation; [Figure 13] 11 is a flow diagram illustrating how a zero vector instruction may be processed according to an alternative exemplary implementation. [Figure 14] 1 illustrates a simulator implementation that may be used. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In one exemplary configuration, an apparatus is provided having a processing circuit for performing an operation and an instruction decoder circuit for decoding the instruction to control the processing circuit to perform an operation specified by the instruction. An array storage is also provided including storage elements for storing data elements. The array storage is configured to store at least one two-dimensional array of data elements accessible to the processing circuit when performing the operation, each two-dimensional array of data elements including a plurality of vectors of data elements, each vector being one-dimensional.

[0012] As mentioned above, the use of array storage can provide a very efficient mechanism for performing certain operations, for example, a cumulative sum operation. A cumulative sum operation can perform only a cumulative sum function, but alternatively can incorporate additional processing in addition to the cumulative sum function (purely by way of example, a cumulative sum operation can be of the form A=A+B *C). In order to take full advantage of the potential efficiency gains that can be realized, it may be necessary to have an efficient mechanism for moving data elements out of the array storage when they are no longer involved in computations performed using the array storage, and an efficient mechanism for freeing up associated storage elements of the array storage for use in connection with subsequent computations.

[0013] According to one exemplary implementation, move and zero instructions are provided that can enable significant improvements in the efficiency of such processes. In particular, in one exemplary implementation, the instruction decoder circuitry can be configured to control the processing circuitry to, in response to a move and zero instruction that identifies one or more vectors of data elements of a given two-dimensional array of data elements in the array storage, move the data elements of the one or more identified vectors from the array storage to a destination storage and set storage elements of the array storage that were used to store the data elements of the one or more identified vectors to a logical zero value.

[0014] Thus, in accordance with the above technique, a single instruction can be specified which, when executed, moves data elements in one or more identified vectors of data elements in a given two-dimensional array from array storage and also clears associated storage elements of the array storage that stored those data elements to logical zero values, thereby preparing them for use in subsequent computations.

[0015] This can result in significant performance improvements. In particular, the operations of moving data elements from array storage and preparing the associated storage elements for reuse do not perform useful computations by themselves and can therefore be considered overhead associated with the use of array storage. By enabling a single instruction to both move data elements and clear the associated storage elements to a logical zero value, this overhead can be significantly reduced.

[0016] In particular, in the prior known techniques, at least one move instruction needs to be executed to move the required data elements from the array storage to the specified destination storage, and then one or more additional move instructions are needed to move one or more vectors of logical zero values ​​from one or more source vector registers to the associated storage elements of the array storage. This therefore generates a sequence of dependent instructions that must be executed one by one. For example, if we only consider the simple case where a first move instruction is used to move one vector of data elements from the array storage, and then a second move instruction is used to move a vector of logical zero values ​​from the specified source vector register to the associated storage elements of the array storage, there are clearly two dependent move instructions that need to be executed one by one, and this instruction dependency is eliminated by using the new move and zero instruction.

[0017] It has further been found that the hardware cost associated with performing the combined move and zeroing operation may, in some implementations, be the same as the hardware cost associated with performing just a standard move operation to move the vector of data elements from the array storage, and thus the zeroing of the associated storage elements may be obtained effectively for no additional hardware overhead. It has further been found that the performance (speed of execution) of the combined move and zeroing operation is, in one exemplary implementation, the same as simply performing a single move operation.

[0018] Furthermore, use of the present technique avoids the need to store logical zero values ​​in vector registers that would otherwise need to be used as source operands for move instructions used to move those logical zero values ​​to array storage, thereby freeing up one or more vector registers in the vector register file.

[0019] Furthermore, it can be seen that performance is improved since a separate move instruction is not required to perform the zeroing function.

[0020] Such an approach has proven highly beneficial in many exemplary use cases of array storage. For example, array storage is often used to accumulate results generated when performing multiple iterations of an accumulating sum operation, and when the final accumulating sum results are generated, they are typically moved out of the array storage, for example, by being moved into one or more vector registers provided within the device. When the array storage is used in performing the accumulating sum operation, it is possible to reuse the storage elements that stored those final accumulating sum results for a new series of accumulating sum operations only if those storage elements are initially set to a logical zero value, and the use of move and zero instructions as described herein can allow this to be accomplished efficiently.

[0021] Thus, in one exemplary implementation, the processing circuitry may be configured to perform multiple iterations of the cumulative sum operation and maintain cumulative sum results generated when performing the cumulative sum operation using a given two-dimensional array of data elements, where after a given iteration of the cumulative sum operation, at least one given vector of data elements in the given two-dimensional array of data elements is configured to store the final cumulative sum result, while remaining vectors of data elements in the given two-dimensional array of data elements are configured to store intermediate cumulative sum results. In such an implementation, a move and zero instruction may be configured to identify the at least one given vector of data elements and may be executed after a given iteration of the cumulative sum operation to cause the processing circuitry to move the final cumulative sum result of the at least one given vector from the array storage to a destination storage and to clear storage elements of the array storage used to store the final cumulative sum result of the at least one given vector to free those storage elements for use in a subsequent cumulative sum operation.

[0022] It should be noted that the cumulative sum operation described above may simply perform a cumulative sum function (e.g., of the form A=A+B), but may more generally include some additional processing operations in addition to the cumulative sum function. Thus, the cumulative sum operation may include processing operations that are performed to generate a processing operation result value that is then accumulated with an existing data element value in an associated storage element of the array storage to create a new data element value that is stored in that associated storage element of the array storage. Purely by way of example, the cumulative sum operation described above may also include a multiply-accumulate-sum operation (e.g., A=A+B * C format).

[0023] There are various types of data processing operations that can utilize the cumulative sum function described above and for which the use of array storage provides an efficient implementation technique. In one particular exemplary use case, multiple iterations of the cumulative sum operation are processing operations used to perform a finite impulse response (FIR) filtering operation on an array of input data elements, and a given two-dimensional array of data elements in the array storage may be used to maintain an array of output data elements generated during the performance of the FIR filtering operation. The processing circuitry may be configured to process a single vector of input data elements during each iteration of the cumulative sum operation and generate output data elements for accumulating into multiple vectors of the array of output data elements.

[0024] The correspondence between input data elements and output data elements may vary depending on the implementation. For example, one vector of input data elements may be associated with multiple vectors of output data elements. In addition, these multiple vectors of output data elements may be arranged in either or both horizontal and vertical directions in the array storage (to support implementations in which vectors may be accessed both horizontally and vertically, the two-dimensional array of data elements is typically a two-dimensional square array of data elements). Furthermore, the sizes of the input data elements and the output data elements may differ.

[0025] Techniques such as those described above may utilize a cross product approach to use a square array of data elements to compute FIR filtering achieved by a sliding window technique. Such techniques typically result in some of the vectors of the square array of output data elements being determined before other vectors of output data elements, and thus the use of the move and zero instructions described above may enable those determined vectors of output data elements to be moved out of the array storage, and the associated storage elements freed up for use in conjunction with other vectors of output data elements.

[0026] The array of input data elements can take a variety of forms, but in one exemplary implementation can represent an array of pixel values, although the techniques described herein are equally applicable to other arrays of data elements that may not, for example, represent image data.

[0027] In some example implementations, the multiple vectors of output data elements generated by processing a row of input data elements may be referred to as multiple "rows" of output data elements. However, as noted above, it should be noted that the rows of output data elements accumulated in a given square 2D array of data elements of an output data element (such a square 2D array may also be referred to herein as a square subarray) may be stored in any desired orientation in the array storage. For example, a row may be stored as a horizontal vector in a square subarray or as a vertical vector in a square subarray, and thus the term "row" should not be construed herein as implying any particular orientation of data elements in the array storage.

[0028] In one exemplary configuration, the given two-dimensional array of data elements is a square two-dimensional array of data elements, the plurality of vectors forming the square two-dimensional array of data elements includes a first plurality of vectors arranged in a first array direction and a second plurality of vectors arranged in a second array direction orthogonal to the first array direction, and each instance of the move and zero instruction is configured to identify one or more vectors of data elements that all extend in the first array direction or that all extend in the second array direction. This thus provides great flexibility as to how the various vectors of data elements to be moved from the array storage are identified.

[0029] The one or more two-dimensional arrays of data elements stored in the array storage can take a variety of forms depending on the implementation. In one particular exemplary implementation, the processing circuitry is configured to perform processing operations on a square two-dimensional array of data elements, during which the processing circuitry is enabled to access vectors of data elements in both a first array direction and a second array direction.

[0030] In one exemplary implementation, the array storage may be configured to comprise a plurality of array vector registers extending in a first array direction. The processing circuitry may be configured to perform one or more cumulative sum operations, each cumulative sum operation configured to generate output data for accumulating within a group of the plurality of array vector registers of the array storage. Thus, in such an implementation, the array storage may be considered to comprise a plurality of separately addressable array vector registers extending in a single direction, and the aforementioned given two-dimensional array of data elements may be considered to comprise data elements stored within the group of the plurality of array vector registers referenced above.

[0031] In such an example implementation, once execution of the one or more cumulative sum operations results in final result data being present within one or more identified vectors identified by the move and zero instructions, a move and zero instruction may be executed to cause the processing circuitry to move data elements of the one or more identified vectors from the array storage to a destination storage and to set each array vector register in the group of multiple array vector registers used to store the data elements of the one or more identified vectors to a logical zero value.

[0032] In one particular exemplary implementation, when the processing circuitry completes execution of one or more cumulative sum operations, final result data resides in each array vector register in the group of the plurality of array vector registers. Execution of a move and zero instruction can then move the final result data from the group of the plurality of array vector registers to a destination storage and clear to zero each array vector register in the group of the plurality of array vector registers. This then allows the processing circuitry to reuse one or more array vector registers from the group of array vector registers for any desired subsequent processing operations (so that, for example, execution of a subsequent cumulative sum instruction using any or all of those array vector registers will result in a non-accumulating variant being executed due to the contents of the array vector registers being cleared to zero).

[0033] The destination storage specified for the move and zero instruction may take a variety of forms. In one exemplary implementation, the apparatus may further provide a vector register file comprising a plurality of vector registers, and the move and zero instruction may be configured to indicate one or more vector registers in the vector register file as the destination storage. There are various ways in which the move and zero instruction may be configured to identify the one or more vector registers. For example, in the case of a single vector register to which a single vector of data elements is moved from the array storage, the move and zero instruction may provide an identifier used to determine the single vector register. In the case of multiple vector registers to which multiple vectors of data elements are moved from the array storage, the multiple vector registers may be explicitly identified using separate identifier information for each of the vector registers, or alternatively, one vector register may be identified by the instruction and the other vector registers in the multiple vector registers are implicit. For example, the multiple vector registers may be a sequence of adjacent vector registers starting from an explicitly identified vector register, or the multiple vector registers may each be separated by a constant stride value.

[0034] However, in alternative implementations, if desired, the move and zero instructions may be configured to indicate as destination storage one or more locations in memory where the data elements of the one or more identified vectors should be stored, in which case the move and zero instructions may instead be referred to as store and zero instructions.

[0035] There are various ways in which the move and zero instruction may be configured to identify memory locations to which one or more vectors of data elements should be moved. For example, considering the single vector case where only a single vector of data elements is moved to memory, the move and zero instruction may be configured to identify a location in memory, and the vector of data elements is then written to consecutive memory addresses identified by that location (in this case the location may be, for example, the memory address of the first data element). If multiple vectors are moved, multiple separate locations in memory may be identified by the instruction, and each of the vectors of data elements is moved to a sequence of memory addresses identified by one of the specified locations. Alternatively, one location may be specified by the instruction, and the other locations may be implicit (e.g., the locations identify memory addresses at a fixed stride / offset from the identified location).

[0036] Depending on the array direction being accessed and the nature of the data elements held in that accessed vector within the array, there may be cases where the individual elements of a single vector are stored in separate memory locations. However, in situations where individual data elements within a single vector need to be stored in separate memory locations, the vector of data elements is typically first moved to a vector register before being transferred to memory in due course.

[0037] There are several ways in which one or more vectors of data elements to be moved may be identified by a move and zero instruction. In one exemplary implementation, the move and zero instruction may comprise a vector identification field that is used to identify one or more vectors of data elements of a given two-dimensional array of data elements in the array storage. For example, if a single vector of data elements is to be moved, an identifier sufficient to identify that single vector may be provided. When multiple vectors of data elements are to be moved, the vector identification field may be used to provide sufficient information to explicitly identify each of those multiple vectors, or alternatively, one vector of data elements may be explicitly identified, in which case other vectors, e.g., adjacent vectors, or regularly spaced vectors (often referred to as strided access), are implicit. In this latter case, a number may be provided by the vector identification field to identify the number of vectors to be moved.

[0038] In the above approach where access may be in either array direction, a vector identification field may also be used to provide sufficient information to identify the array direction being accessed. For example, in one implementation, the vector identification field may comprise a first subfield to identify a square two-dimensional array and a second subfield that provides one or more line identifiers used to identify one or more vectors and an array direction indication.

[0039] In one example implementation, the move and zero instruction may include a predicate field to identify predicate information used to identify which data elements of one or more identified vectors are to be moved from the array storage to the destination storage and to have their associated storage elements set to a logical zero value. This may provide further flexibility by allowing functionality to be limited to specific data elements within a particular vector.

[0040] In some implementations where predicates are used, the data element size may be allowed to vary, and in such cases the move and zero instruction may comprise a size field to identify the size of each data element in the one or more identified vectors. By allowing the instruction to provide this additional information, it is possible for the instruction to be used for a variety of different data element sizes being processed within the system, while allowing the move and zero operation to be performed on a subset of all data elements in the one or more identified vectors.

[0041] According to another technique described herein, an additional new form of instruction is provided that can also be used to zero vectors of data elements in an array storage and provide improved performance when performing an accumulative sum operation using such array storage. According to this technique, an apparatus is provided having a processing circuit for performing the operation, an instruction decoder circuit for decoding the instruction to control the processing circuit to perform the operation specified by the instruction, and an array storage comprising storage elements for storing the data elements. As in the previously described technique, the array storage is configured to store at least one two-dimensional array of data elements accessible to the processing circuit when performing the operation, each two-dimensional array of data elements including a plurality of vectors of data elements, each vector being one-dimensional. According to this additional technique, the instruction decoder circuit is configured to, in response to decoding a zero vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage, also decode a subsequent accumulative sum instruction configured to operate on the identified plurality of vectors of data elements, and to control the processing circuit to perform a non-accumulating variant of the accumulative sum operation specified by the accumulative sum instruction to generate result data elements for storage in the identified plurality of vectors in the array storage.

[0042] By using the above approach, a zero vector instruction, when decoded by an instruction decoder circuit, can be fused / merged with a subsequent accumulate sum instruction that specifies multiple vectors of the same data elements as specified by the zero vector instruction, effectively creating a non-accumulating variant of that accumulate sum instruction. While such an approach can be very beneficial since instruction encoding space is typically quite constrained, it has been found that while it may be desirable to provide several different accumulate sum instructions to perform accumulate sum operations on multiple vectors in the array storage, the amount of instruction encoding space consumed by providing non-accumulating variants of those instructions may make it highly undesirable to also attempt to provide those non-accumulating variants. By using the present technique, it is not necessary to provide non-accumulating variants of instructions, but instead they can be simulated by combining a zero vector instruction with a subsequent accumulate sum instruction to cause the processing circuit to execute the non-accumulating variants.

[0043] In one exemplary implementation, the array storage may comprise a plurality of array vector registers extending in a first array direction, and the identified plurality of vectors in the array storage are provided by a group of the plurality of array vector registers of the array storage. In such a configuration, a given two-dimensional array of data elements may comprise data elements stored in a group of the plurality of array vector registers. Furthermore, a subsequent accumulate sum instruction may specify a processing operation including an accumulate sum operation to be performed on the identified plurality of vectors of data elements (i.e., on the same group of the plurality of array vectors specified by the zero vector instruction), and the zero vector instruction may be used in combination with the subsequent accumulate sum instruction to enable execution by the processing circuit of a non-accumulating version of the processing operation.

[0044] In one example implementation, the zero vector instruction may comprise a vector identification field that is used to identify multiple vectors of data elements of a given two-dimensional array of data elements in the array storage.

[0045] Similar to the move and zero instructions described above, the zero vector instruction may optionally include a predicate field that identifies predicate information used to identify which storage elements in the plurality of identified vectors should be set to a logical zero value. Such an approach may, in effect, allow some data elements to undergo a non-accumulating variant of a subsequent accumulate sum instruction, while other data elements undergo a true accumulating variant. Also, optionally, the zero vector instruction may include a size field to identify the size of each data element in the plurality of identified vectors.

[0046] Specific example implementations will now be described with reference to the accompanying drawings.

[0047] 1 shows a schematic diagram of a data processing system 10 comprising a processor 20 coupled to a memory 30 storing data values ​​32 and program instructions 34. The processor 20 includes an instruction fetch unit 40 for fetching the program instructions 34 from the memory 30 and for providing the fetched program instructions to an instruction decoder circuit 50. The decoder circuit 50 decodes the fetched program instructions and generates control signals for controlling a processing circuit 60 to perform processing operations on data values ​​held in storage elements of a register storage 65 as specified by a decoded vector instruction. As shown in FIG. 1, the register storage 65 may be formed of a number of different blocks. For example, a scalar register file 70 may be provided that includes a number of scalar registers that can be specified by an instruction, and similarly a vector register file 80 may be provided that includes a number of vector registers that can be specified by an instruction.

[0048] As also shown in Figure 1, processor 20 has access to array storage 90. In the example shown in Figure 1, array storage 90 is provided as part of processor 20, although this is not a requirement. In various examples, array storage may be implemented as any one or more of the following: architecturally addressable registers, architecturally non-addressable registers, scratchpad memory, and cache.

[0049] The processing circuitry 60 may include both vector processing circuitry and scalar processing circuitry in one exemplary implementation. A general distinction between scalar and vector processing is as follows: Vector processing involves applying a single vector processing instruction to data elements of a data vector having multiple data elements at each position in the data vector. In accordance with the present technique, the processing circuitry may perform vector processing to perform operations on multiple vectors in a two-dimensional array (sometimes referred to as a subarray) of data elements stored in the array storage 90. Scalar processing effectively operates on single data elements rather than data vectors. Vector processing may be useful when processing operations are performed on many different instances of the data being processed. In a vector processing configuration, a single instruction may be applied to multiple data elements (of a data vector) simultaneously. This may improve the efficiency and throughput of data processing compared to scalar processing.

[0050] Processor 20 may be configured to process two-dimensional arrays of data elements stored in array storage 90. The two-dimensional arrays may, at least in some embodiments, be accessed as one-dimensional vectors of data elements in multiple directions. In one exemplary implementation, array storage 90 may be configured to store one or more two-dimensional arrays of data elements, where each two-dimensional array of data elements may form a square array portion of a larger or higher dimensional array of data elements in memory.

[0051] FIG. 2 illustrates an example of architectural registers 65 of processor 20 that may be provided in one exemplary implementation. The architectural registers (as defined in an instruction set architecture (ISA)) may include a set of scalar integer registers 100 that serve as general purpose registers for processing operations performed by scalar processing circuits in processing circuit 60. For example, a certain number of general purpose registers 100 may be provided, e.g., 31 registers X0-X30 in this example (the 32nd encoding of the scalar register field may not correspond to a register provided in the hardware because, for example, it may be assumed to indicate a value of 0 by default or may be used to indicate that it is a special purpose type register rather than a general purpose register). It may be possible to access scalar registers of different sizes mapped to the same physical storage. For example, register labels X0-X30 may refer to 64-bit registers, but the same registers may be accessed as 32-bit registers (e.g., accessed using the lower 32 bits of each 64-bit register provided in the hardware), in which case register labels W0-W30 may be used in assembler code to refer to the same registers.

[0052] Also, the architectural registers available for selection by program instructions in the ISA supported by the decoder 50 may include a fixed number of vector registers 105 (labeled Z0-Z31 in this example). Of course, it is not required to provide the number of scalar / vector registers shown in FIG. 2, and other examples may provide a different number of registers specifiable by program instructions. Each vector register may store a vector operand that includes a variable number of data elements, where each data element may represent an independent data value. In response to a vector processing (SIMD) instruction, the processing circuitry may perform vector operations on the vector operands stored in the registers to generate a result. For example, the vector processing may include lane-by-lane operations, where a corresponding operation is performed on each lane of elements in one or more operand vectors to generate a corresponding result of an element of a result vector. When performing vector or SIMD operations, each vector register may have a certain vector length VL, where vector length refers to the number of bits in a given vector register. The vector length VL used in the vector processing mode may be fixed or variable for a given hardware implementation. The ISA supported by processor 20 may support variable vector lengths, such that different processor implementations may choose to implement vector registers of different sizes, but the ISA may be vector length agnostic, such that instructions are designed such that code can function correctly regardless of the particular vector length implemented on a given CPU that executes the program.

[0053] Vector registers Z0-Z31 may also function as operand registers for storing vector operands that provide input to processing operations and cumulative sum operations performed by processing circuitry 60 on two-dimensional arrays of data elements stored in array storage 90. When vector registers are used to provide input to such operations, the vector registers have a vector length MVL, which may be the same as the vector length VL used for the vector operation, or may be a different vector length.

[0054] As shown in FIG. 2, the architectural registers are a fixed number N of registers forming the aforementioned array storage 90. A Array register 110, ZA0 to ZA(N A -1). Each array register can be considered as a set of register storage for storing a single 2D array of data elements, e.g., the results of processing and cumulative sum operations. However, processing and cumulative sum operations may not be the only operations for which array registers can be used. Array registers can also be used to store square arrays, such as when performing row / column-wise transposition of array structures in memory. When a program instruction refers to one of the array registers 110, it is referenced as a single entity using an array identifier ZAi, although some types of instructions (e.g., data transfer instructions) can also select a sub-portion of the array by defining an index value that selects a portion of the array (e.g., one horizontal / vertical group of elements).

[0055] In practice, the physical implementation of the register storage corresponding to the array register is a fixed number N R Array vector registers ZAR0 to ZAR(N RThe array vector registers ZAR forming the array register storage 110 may include a set of registers, such as vector registers Z0-Z31, which are used for vector input to SIMD and array operations. Each of the array vector registers ZAR may have a vector length MVL, and thus each array vector register ZAR may store a 1D vector of length MVL, which may be logically divided into a variable number of data elements. For example, if MVL is 512 bits, this may be, for example, a set of 64 8-bit elements, 32 16-bit elements, 16 32-bit elements, 8 64-bit elements, or 4 128-bit elements. It will be appreciated that not all of these options need to be supported in a given implementation. By supporting variable element sizes, this provides flexibility in computations involving data structures of different precision. To represent a 2D array of data, the array vector registers ZAR0-ZAR (N R The group of array register identifiers ZA0 to ZA(N A -1) can be logically thought of as a single entity that is assigned to a given one of the vector registers, and thus a 2D array is formed with elements spread out within a single vector register corresponding to one dimension of the array, and elements of the other dimension of the array striped across multiple vector registers.

[0056] It may be useful, though not required, to configure the array register ZA to store a square array of data in which the number of elements in the horizontal direction is equal to the number of elements in the vertical direction. By providing support for reading / writing the array register 110 in either the horizontal or vertical direction, this may help support on-the-fly transposition of the array, where the row / column dimensions of the array structure in memory may be switched when transferring the array structure between the array register 110 and the memory. By providing support for writing / reading data from the 2D array register in either the horizontal or vertical direction, this may allow data loaded from memory in one direction (e.g., row-by-row) to be written back to memory in the opposite direction (e.g., column-by-column) faster than is possible with some gather / scatter-load / store or permute operations to transfer data between memory and vector registers.

[0057] As mentioned above, a given 2D array of data elements may form a square array in some exemplary implementations, but this is not a requirement. Thus, as shown in FIG. 3A, in one exemplary implementation, a given 2D array of data elements 115 may form a non-square array. Alternatively, as shown in FIG. 3B, a given 2D array of data elements 120 may form a square array. In each of FIGS. 3A and 3B, individual square boxes represent data elements, and in some implementations, data element sizes may vary. In any example, a two-dimensional array of data elements may be specified in a variety of ways, but in one exemplary implementation, as shown in FIGS. 3A and 3B, a given 2D array of data elements may be specified by a sequence of array vector registers (ZARs).

[0058] As mentioned above, processing circuitry 60 is configured to access scalar registers 70, vector registers 80 and / or array storage 90 under control of instructions decoded by decoder circuitry 50. Further details of this latter arrangement will now be described with reference to Figure 4A, which merely provides one illustrative example of how the array storage may be accessed, particularly considering access to a square 2D array within the array storage.

[0059] In the embodiment shown, the square 2D array in array storage 90 is organized as an array 205 of n by n storage elements / locations 200, where n is an integer greater than 1. In this embodiment, n is 16, which means that the granularity of access to storage locations 200 is 1 / 16 of the total storage in either the horizontal or vertical array direction.

[0060] From the perspective of the processing circuitry, the array of n by n locations is accessible as n linear (one-dimensional) vectors in a first direction (e.g., horizontal as depicted) and n linear vectors in a second array direction (e.g., vertical as depicted). Thus, the n by n storage locations are organized, or at least accessible, from the perspective of the processing circuitry 60 as 2n linear vectors, each of n data elements.

[0061] The array of storage locations 200 is accessible by access circuits 210 , 220 , column select circuitry 230 and row select circuitry 240 under the control of control circuitry 250 in communication with at least processing circuitry 60 and optionally with decoder circuitry 50 .

[0062] With reference to FIG. 4B, the n linear vectors in a first direction (horizontal or "H" direction as depicted) are, for an exemplary square 2D array designated as "A1" (note that there may be more than one such 2D array provided within array storage 90, e.g., A0, A1, A2, etc., as described below), each of the 16 data elements 0 through F (in hexadecimal notation), which may be referenced as A1H0 through A1H15 in this example. The same underlying data stored in the 256 entries (16×16 entries) of array storage 90 A1 of FIG. 4B may instead be referenced in a second direction (vertical or "V" direction as depicted) as A1V0 through A1V15. Note, for example, that data element 260 is item F of A1H0, but is referenced as item 0 of A1V15. It should be noted that the use of "H" and "V" does not imply any spatial or physical layout requirements regarding the storage of the data elements that make up the array storage 90, nor does it relate to whether the 2D arrays within the array storage store row data or column data in any exemplary application.

[0063] As discussed above, the use of array storage 90 can significantly improve performance with respect to certain operations, e.g., cumulative sum operations, where multiple iterations of such cumulative sum operations may be performed on a given two-dimensional array of data elements in array storage 90, and the two-dimensional array of data elements is used to accumulate results when performing those cumulative sum operations. However, once these cumulative sum operations are completed, an efficient mechanism is desirable for moving the resulting vectors of data elements out of the array storage and preparing the associated storage elements in the array storage for use in a subsequent cumulative sum operation.

[0064] As discussed above, in one exemplary implementation, this is accomplished by using move and zero instructions that identify one or more vectors of data elements of a given two-dimensional array of data elements in array storage 90. Upon decoding such a move and zero instruction, processing circuitry 60 is controlled to move the data elements of the one or more identified vectors from the array storage to a destination storage (which may be, for example, one or more vector registers in vector register file 80) and set storage elements of the array storage used to store the data elements of the one or more identified vectors to logical zero values.

[0065] 5A illustrates diagrammatically the fields that may be provided in a move and zero instruction, according to one exemplary implementation. The opcode field 305 is used to identify the instruction as a move and zero instruction. In some exemplary implementations, there may be different variants of the move and zero instruction provided, and thus there may be two or more different opcodes that may identify the move and zero instruction. As one particular example, there may be one variant defined for the move and zero instruction when it is used to move an identified vector in the array storage to a target vector register in the vector register file 80, and a different variant may be provided when one or more vectors in the array storage are moved to memory (in this latter case, the instruction may be referred to as, for example, a store and zero instruction).

[0066] A vector identification field 310 is also provided to identify one or more vectors in the array storage that are to undergo a move operation. In some instances, only a single vector may be identified, while in other instances, multiple vectors may be identified by this field. In the latter case, the multiple vectors may all be identified independently in one exemplary implementation, while in another exemplary implementation, the multiple vectors may be inferred, for example, from an indication of the first vector and an indication of the number of vectors to be moved.

[0067] As shown in FIG. 5A, a destination storage identification field 315 is also provided in the move and zero instruction to identify the destination storage to which the vector should be moved. In one exemplary implementation, this field is used to identify one or more vector registers in the vector register file 80, and in examples where multiple such vector registers are identified, they may be identified in a manner similar to how multiple vectors are identified by the vector identification field (e.g., a first vector register may be identified and other vector registers are implicit based on knowledge of the number of vector registers required to form the destination storage). In an alternative implementation where one or more vectors in the array storage are moved to memory, the information provided in the destination storage identification field 315 may be configured to identify locations in memory where data elements of one or more vectors should be stored. This may include, for example, identifying one or more registers whose contents are used to identify the required locations in memory.

[0068] One or more optional additional fields 320 may be provided within the instruction 300, as desired. For example, a predicate field may be used to identify predicate information used to control which data elements within one or more identified vectors should undergo a move and zero operation. This provides flexibility by allowing an operation to be applied with respect to certain data elements but not with respect to other data elements. As another example, a data element size indication may be provided within the instruction, thereby allowing the instruction to be applied with respect to vectors whose data element sizes are not fixed.

[0069] In one exemplary implementation, the move and zero instructions may be configured to operate on array vector registers that extend in a first array direction, and in those implementations, it is not necessary to allow both horizontal and vertical directions to be encoded in the vector identification field 310. However, in examples where a 2D array in the array storage 90 may be accessed in either a horizontal or vertical direction (in one such implementation, the 2D array is a square array), the vector identification field may take the form shown in FIG. 5B. In particular, this vector identification field 310' may include a first subfield 312 used to identify a given square 2D array in the array storage 90 that is being accessed, and a second subfield formed from two portions 313 and 314. The first portion 313 provides one or more line identifiers for identifying one or more lines of data elements in the square 2D array, and the second portion 314 provides an array direction indication, thus enabling a determination as to whether the line of data elements identified by the line identifier extends in a horizontal or vertical direction. It will be appreciated that the combination of the first portion 313 and the second portion 314 allows one or more vectors within the square 2D array to be identified.

[0070] 6 is a flow diagram illustrating the operation of the move and zero instruction. If, in step 350, the decoder circuit 50 determines that a move and zero instruction has been encountered, then, in step 355, one or more vectors of data elements in the array storage are identified from the information provided in the vector identification field 310 of the move and zero instruction. Additionally, in step 360, the destination storage to be used is identified from the destination storage identification field 315 of the move and zero instruction. As previously mentioned, this step typically involves identifying one or more vector registers in the vector register file 80 as destinations for the data elements moved from the array storage, although alternatively, in some implementations, the identified destination storage may take the form of one or more locations in memory. In one exemplary implementation, steps 355 and 360 may be performed by the decoder circuit 50, although in alternative implementations, the processing circuit 60 may perform these determination steps based on information provided by the decoder circuit 50.

[0071] In step 365, the processing circuit 60 is used to move each identified vector of data elements to the destination storage and then set to zero the associated storage elements of the array storage, i.e., the storage elements that were used to store the data elements now being moved to the destination storage.

[0072] Figure 7 illustrates an exemplary instruction sequence that may operate on the array storage 90 in one exemplary implementation. As illustrated in the example of Figure 7, a series of data processing instructions (three instructions in this example) may be executed to perform processing operations and accumulated sum operations within a given 2D array provided in the array storage. During execution of these multiple instructions, results are accumulated within the given 2D array.

[0073] In this example, assume that when the third data processing instruction is completed, the first vertical vector in the given 2D array stores the final accumulated sum result, while the other vertical vectors in the given 2D array at this stage store only intermediate accumulated sum results. Assuming that the first vertical vector stores the final accumulated sum result, it would be useful to move those results out of the array storage to free up storage elements of that first vertical vector for use in subsequent processing operations and accumulated sum operations.

[0074] As shown in FIG. 7, this is accomplished by executing a move and zero instruction to identify vertical vector 1 and define the destination vector register to which the contents of that vertical vector should be moved, which in this example is register Z. i Execution of this instruction causes the final accumulated sum result in vertical vector 1 to be moved into the identified vector register and the associated storage elements in the given 2D array (i.e., the storage elements that implement vertical vector 1) to be cleared to a logical zero value. As a result of the execution of this single instruction, not only are the final accumulated sum results moved out of the array storage, but the underlying storage elements are also prepared and immediately available for reuse in subsequent processing operations and accumulated sum operations. In particular, by clearing their contents to zero, they can immediately begin to be designated as destinations for new accumulated sum results generated by subsequent instructions.

[0075] Thus, as shown in Figure 7, when a subsequent data processing instruction 4 is executed, it can accumulate into a 2D array and, if necessary, vertical vector 1 can be reused. When that data processing instruction is executed, vertical vector 2 is now assumed to hold the final accumulated sum result, and therefore the contents of vertical vector 2 in a given 2D array are transferred from the array storage to a destination vector register (register Z in this example). i+x) to vertical column 2. Again, execution of this instruction causes the contents of the identified vector to be moved out of the array storage and the corresponding storage elements to be cleared to logical zero values, thus freeing those storage elements for use in subsequent processing operations and the cumulative sum operation. Thus, as shown in Figure 7, subsequent iterations of the data processing instruction can be executed and vertical column 2 can be reused, if desired.

[0076] There are various types of operations that may be performed using a given 2D array in the array storage 90 to accumulate results, and not all of the vectors in that given 2D array necessarily hold the final accumulated sum result at the same time. In such situations, it may be useful to employ an approach, as illustrated by way of example in FIG. 7, to free up resources in the 2D array for reuse. One exemplary use case of such an approach is when performing 2D Finite Impulse Response (FIR) filtering using a sliding window approach. Such an approach is illustrated by way of example in FIG. 8, where an input image 400 is considered. In particular, an FIR filtering operation is applied to the input image to generate a corresponding output image 430, and each pixel 415, 420 in the output image 430 is generated as a result of a corresponding filtering operation 407, 412. For each of these filtering operations, multiple input pixels are considered, and filtering coefficients are applied with respect to these multiple input pixels to generate a value for the output pixel.

[0077] In the example shown in FIG. 8, it is assumed that each output pixel is generated by considering a 3×3 array of input pixels. Thus, a first 3×3 array of input pixels 405 is provided to a filter operation 407, which performs filtering using a corresponding array of filter coefficients to generate an output value for pixel 415. Similarly, a second 3×3 array of input pixels 410 is subjected to a filter operation 412, using a corresponding set of filter coefficients to generate a value for output pixel 420. It will be appreciated that array 410 is shifted one pixel position to the right relative to array 405, and as the above process is repeated, a sliding window of 3×3 pixels may be extracted to serve as an input to each filter operation. Upon reaching the end of a row, the process may return to the left side of the input image, but starting one row down in the image, and again proceeding from left to right in the image. It will thus be appreciated that in the arrangement shown in FIG. 8 there is effectively a sliding window moving first in the "horizontal" direction, which moves across the input image extracting a 3×3 array of input image pixels which are used in calculating each output image pixel.

[0078] Figures 9A-9D show how such a 2D image filtering operation can be performed efficiently using a square 2D array in array storage 90 by performing a cross-product accumulate sum operation on the data held in the 2D array. Note that in the example shown in Figures 9A-9D, the sliding window moves initially in a "vertical" direction, i.e., orthogonal to the direction shown in the example of Figure 8. Thus, the input image 440 shown in Figures 9A-9D can be thought of as lying transverse to its normal viewing direction.

[0079] As shown in Figures 9A-9D, one column (or portion of an image) of an input image 440 is processed at a time and undergoes a filtering operation using a vector of filter coefficients. Each block (see, e.g., block 465 in Figure 9A) in the vector of filter coefficients represents three filter coefficients from a 3x3 array of coefficients. The padding elements (see, e.g., element 467 in Figure 9A) correspond to zero or undefined values ​​and are merely an artifact of the implementation shown. Specifically, in the implementation shown, the instructions used can perform four multiplications and accumulated sums per result, but in the exemplary implementation shown, only three multiplications and accumulated sums need to be performed.

[0080] In the illustrated example, four sets of coefficients (e.g., see four blocks 468 in FIG. 9A taken from one row of four sets of 3×3 coefficients) are used as inputs to compute four output vectors for a provided input vector (one set of (3+1) coefficients is used in each of the four multiplication operations used to generate the four output vectors). In addition, the process illustrated in FIGS. 9A-9D uses only one column of three coefficients from each 3×3 array of coefficients per instruction, and therefore requires three instructions to generate a final accumulated sum result within any particular set of four vectors.

[0081] When the process is ongoing and in steady state, as described below with reference to Figures 9C and 9D, the process operates simultaneously on three sets of four output vectors (see, for example, the three sets of output vectors 475, 485, 495 shown in Figure 9C).

[0082] As shown in Figure 9A, when a first column 470 of the input image 440 is processed using vector of coefficients 460, this causes the accumulated sum results to be stored in four vectors 475. When a second column 480 of the input image 440 is processed using vector of coefficients 482, as shown in Figure 9B, this causes the accumulated sum results to be populated in both four vectors 475 and four vectors 485. When a third column 490 is then processed using vector of coefficients 492, as shown in Figure 9C, this causes the accumulated sum results to be populated in four vectors 475, four vectors 485, and four vectors 495. From the previous discussion of Figure 8, it will be appreciated that at this point, all pixels in the first three columns of the input image will have been processed, and therefore the contents of four horizontal vectors 475 represent the final accumulated sum results for the first group of columns of the output image. Thus, as shown in FIG. 9C , the contents of these four registers 475 can undergo the aforementioned move and zero instructions to move their contents to a destination storage, e.g., four vector registers in vector register file 80, and to clear the storage elements forming these four vectors 475 in 2D array 450 so that they are available for a subsequent cumulative sum operation.

[0083] Thus, as an example, as shown in Figure 9D, when the fourth column 500 of the input image 440 is processed using the vector of coefficients 460, this may cause the accumulated sum results to be populated into four vectors 485, four vectors 495, and four vectors 475 (which can now be reused because the storage elements in these vectors have been cleared to logical zero values ​​by the previous move and zero instruction). Also shown in Figure 9D, the four vectors 485 now store the final accumulated sum results representing the second group of columns of the output image (because at this point, each of the second, third, and fourth input columns have been processed). Thus, the data elements stored in those four horizontal vectors 485 may be moved from the array to vector registers of the vector register file, and the underlying storage elements are then cleared to allow for their reuse in a subsequent accumulated sum operation.

[0084] 9A-9D, while any vector that has undergone a move and zero command is immediately reused (as this can make programming easier), a cleared vector does not need to be immediately reused; instead, the process can continue to consume vectors below groups of vectors 475, 485, 495 as necessary, only to return to the beginning when the bottom of array 450 is reached.

[0085] In one exemplary implementation, a given square 2D array in array storage 90 may be accessed in either the horizontal or vertical direction. However, in some implementations, there are certain processing operations that can be performed using 2D arrays in array storage 90 where vectors are accessed in only one of the directions. Thus, by way of example, and referring back to FIG. 2 previously described, there may be some processing instructions that specifically identify array vector registers ZAR that extend through the array in a first array direction. These instructions may enable very efficient execution of certain processing operations and accumulated sum operations by specifying multiple ZAR registers on which the associated processing operations and accumulated sum operations are performed. However, when a series of these instructions are executed, although all of the identified array vector registers ZAR typically contain the final accumulated sum results, it is not possible to reuse these registers for subsequent processing operations and accumulated sum operations until these results are moved out of the array storage and the current contents of the storage elements that form these array vector registers are cleared to logical zero values.

[0086] FIG. 10 illustrates, in a simplified manner, how the aforementioned move and zero instructions can be used to significantly improve performance in such a situation. Specifically, as shown in FIG. 10, assume that three array vector registers ZAR2, ZAR3, and ZAR4 are initialized to zero, and then a series of data processing instructions of the above type are executed to perform processing operations and accumulated sum operations, with the accumulated sum results being maintained in the above three array vector registers. When the required series of data processing instructions is completed (in this example, it is assumed that two such data processing instructions are executed), all of the above three array vector registers store the final accumulated sum results. Thus, using the above-mentioned move and zero instructions, those three array vector registers can be designated as vectors whose data elements are to be moved to a destination storage, and also a storage to be used as the destination storage can be identified, in this example, it is assumed that three adjacent vector registers in the vector register file 80 are used. Thus, execution of the move and zero instructions moves all of the accumulated sum results from the array storage to the identified vector registers of the vector register file, and also causes the storage elements forming those three array vector registers to be cleared to a logical zero value. Thus, the process can then immediately proceed to execute a sequence of subsequent data processing instructions which are also accumulated in the same series of array vector registers ZAR2, ZAR3, and ZAR4, as shown in Figure 10. This provides a very efficient implementation.

[0087] According to another technique described herein, an additional new form of instruction (referred to herein as a zero vector instruction) is provided that zeros a vector of data elements in the array storage and can also be used to provide improved performance when using such array storage to perform a cumulative sum operation (compared to implementations that require the use of move instructions to pass zeros from one or more vector registers to a desired vector in the array storage and that require the reservation of one or more vector registers to hold those zero values). According to this additional technique, in response to decoding such a zero vector instruction (configured to identify a plurality of vectors of data elements in a given two-dimensional array of data elements in the array storage), the instruction decoder circuitry 50 is also configured to decode a subsequent cumulative sum instruction that is configured to operate on the identified plurality of vectors of data elements. The processing circuitry is then configured to set storage elements of the array storage used to store data elements of the identified plurality of vectors to logical zero values ​​and then perform the cumulative sum operation specified by the cumulative sum instruction to generate result data elements for storage in the identified plurality of vectors in the array storage.

[0088] By using the above approach, a zero vector instruction, when decoded by the instruction decoder circuit, can be merged with a subsequent accumulate sum instruction that specifies multiple vectors of the same data elements as specified by the zero vector instruction, effectively creating a non-accumulate variant of that accumulate sum instruction. This can be very beneficial since instruction encoding space is usually at a premium and it may not be possible to specify non-accumulate variants of the various accumulate sum instructions that may be defined to operate on multiple vectors of data elements in the array storage.

[0089] 11 is a flow diagram illustrating the processing of such a zero vector instruction according to one exemplary implementation. When the decoder circuit 50 encounters a zero vector instruction in step 520, in step 525, a plurality of vectors of data elements in the array storage are identified by reference to a vector identification field of the zero vector instruction. For example, a plurality of array vector registers ZAR may be identified in the vector identification field. Next, in step 530, the decoder circuit determines whether the next instruction to be decoded is an accumulate sum instruction operating on the same vector as that identified by the zero vector instruction.

[0090] If not, then in step 535 the processing circuitry is controlled to set the storage elements of the array storage used to store the data elements of the identified plurality of vectors determined in step 525 to a logical zero value, after which processing simply continues with the execution of the next instruction.

[0091] However, if, at step 530, it is determined that the next instruction is an accumulate sum instruction operating on the same vector as identified by the zero vector instruction, the decoder effectively fuses the two instructions and, at step 540, controls the processing circuitry to execute a non-accumulating variant of the accumulate sum operation specified by the accumulate sum instruction to generate a result for storage in each of the identified vectors (typically this includes both a processing operation and a subsequent accumulation). As previously mentioned, with such an approach, it is not necessary to specifically encode a non-accumulating variant of any accumulate sum instruction configured to operate on multiple vectors in the array storage, because such a non-accumulating variant can be effectively executed by the fusion procedure described above through the use of a zero vector instruction followed by the necessary accumulate sum instruction (thereby performing the processing operation defined by the accumulate sum instruction, but effectively negating the accumulate sum function).

[0092] 12 is a diagram that illustrates, in one exemplary implementation, the fields that may be provided within a zero vector instruction. In particular, the zero vector instruction 550 includes an opcode field 555 whose bits are used to identify that the instruction is in fact a zero vector instruction. In addition, a vector identification field 560 is provided that is used to identify multiple vectors within the array storage. The information within this field may generally take the form previously described when describing the vector identification field 310 of the move and zero instruction 300 of FIG. 5A, although in one exemplary implementation, the subsequent accumulate sum instruction is an instruction that is configured to operate on array vector registers that extend in a first array direction, and thus typically does not need to allow both horizontal and vertical directions to be encoded within the vector identification field 560.

[0093] If desired, a number of optional additional fields may be provided, such as a predicate information field and a data element size field as described above with reference to the move and zero instruction examples, as indicated by box 565.

[0094] 13 is a flow diagram illustrating the processing of a zero vector instruction according to another exemplary implementation. When the decoder circuit 50 encounters a zero vector instruction in step 570, a plurality of vectors of data elements in the array storage are identified in step 575 by reference to a vector identification field of the zero vector instruction. For example, a plurality of array vector registers ZAR may be identified in the vector identification field.

[0095] Then, in step 580, the processing circuitry is controlled to set the storage elements of the array storage used to store the data elements of the identified plurality of vectors determined in step 575 to a logical zero value, after which processing simply continues with the execution of the next instruction.

[0096] In this implementation, significant benefits can still be achieved if no fusion is performed to combine a zero vector instruction with a subsequent accumulate sum instruction. In particular, there is no need to execute multiple move instructions, each of which moves a vector of zeros from a vector register in the vector register file to an identified vector in the array storage. Moreover, such a zeroing function is easier and cheaper to build in hardware than having to execute a move vector (of zeros) function. Moreover, there is an additional savings, since there is no need to reserve one or more vector registers in the vector register file to hold logical zero values, which would be required if the above implementation based on the use of move instructions was adopted.

[0097] FIG. 14 illustrates a simulator implementation that may be used. Although the above examples implement the invention in terms of apparatus and methods for operating specific processing hardware that supports the technique, it is also possible to provide an instruction execution environment according to the examples described herein, which is implemented through the use of a computer program. Such computer programs are often referred to as simulators insofar as they provide a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 615, which optionally runs a host operating system 610 and supports the simulator program 605. In some configurations, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple different instruction execution environments may be provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such an approach may be justified in certain situations, such as when it is desired to run code native to another processor for compatibility or reuse reasons. For example, a simulator implementation may provide an instruction execution environment that has additional functionality not supported by the host processor hardware, or that is typically associated with a different hardware architecture. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0098] To the extent that examples have been described above with reference to particular hardware constructs or features, in a simulated implementation, equivalent functionality may be provided by suitable software constructs or features. For example, a particular circuit may be provided as computer program logic in a simulated implementation. Similarly, memory hardware such as registers or caches may be provided as software data structures in a simulated implementation. Also, the physical address space used to access memory 30 in hardware device 10 may be emulated as a simulated address space, which is mapped by simulator 605 to a virtual address space used by host operating system 610. In configurations where one or more of the hardware elements referred to in the preceding examples are present in host hardware (e.g., host processor 615), some simulated implementations may use the host hardware, if suitable.

[0099] The simulator program 605 may be stored in a computer-readable storage medium (which may be a non-transitory medium) and provides a virtual hardware interface (instruction execution environment) to the target code 600 (which may include applications, an operating system, and a hypervisor), the virtual hardware interface being the same as the hardware interface of the hardware architecture modeled by the simulator program 605. Thus, the program instructions of the target code 600 may be executed from within the instruction execution environment using the simulator program 605, so that a host computer 615 that does not actually have the hardware features of the device 10 discussed above can emulate these features. The simulator program may include processing program logic 620 that emulates the operation of the processing circuit 60, instruction decode program logic 625 that emulates the operation of the instruction decoder circuit 50, and array storage emulation program logic 622 that maintains data structures to emulate the array storage 90. Thus, the techniques described herein may be performed in software by the simulator program 605 in the example of FIG. 14.

[0100] In this application, the term "configured to..." is used to mean that an element of an apparatus has a configuration that is capable of performing a defined operation. In this context, "configuration" refers to a manner of arrangement or interconnection of hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that an apparatus element needs to be modified in any way to provide the defined operation.

[0101] Although illustrative examples have been described in detail herein with reference to the accompanying drawings, it will be understood that the invention is not limited to exact configurations thereof, and various changes, additions, and modifications may be made by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims. For example, various combinations of the features of the following dependent claims may be made with the features of the independent claims without departing from the scope of the invention.

Claims

1. It is a device, A processing circuit that performs calculations, An instruction decoder circuit that decodes an instruction and controls the processing circuit to execute the operation specified by the instruction, An array storage comprising a storage element for storing data elements, wherein the array storage is configured to store at least one two-dimensional array of data elements accessible to the processing circuit when performing the operation, and each two-dimensional array of data elements includes a plurality of vectors of data elements, each vector being one-dimensional, The device is configured such that the instruction decoder circuit, in response to decoding a zero-vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage, also decodes a subsequent cumulative sum instruction configured to perform an operation on the identified plurality of vectors of data elements, and controls the processing circuit to perform a non-cumulative sum variation of the cumulative sum operation specified by the cumulative sum instruction to generate a result data element for storage in the identified plurality of vectors in the array storage.

2. The array storage includes a plurality of array vector registers extending in a first array direction, and the identified plurality of vectors in the array storage are provided by a group of array vector registers of the array storage. The given two-dimensional array of data elements includes the data elements stored in the group of a plurality of array vector registers. The subsequent cumulative sum instruction specifies a processing operation which includes a cumulative sum operation to be performed on the identified vectors of data elements, The apparatus according to claim 1, wherein the zero vector instruction is used in combination with the subsequent cumulative sum instruction to enable the processing circuit to execute a non-cumulative sum variant of the processing operation.

3. The apparatus according to claim 1 or 2, wherein the zero vector instruction includes a vector identification field used to identify the plurality of vectors of the data elements of the given two-dimensional array in the array storage.

4. The apparatus according to claim 1 or 2, wherein the zero vector instruction includes a predicate field for identifying predicate information used to identify which storage element in the plurality of identified vectors should be set to a logical zero value.

5. The apparatus according to claim 4, wherein the zero vector instruction further includes a size field for identifying the size of each data element in the plurality of identified vectors.

6. A method for processing data elements in the array storage of a device, Performing calculations using a processing circuit, The instruction decoder circuit is used to decode the instruction and the processing circuit is controlled to execute the operation specified by the instruction, The array storage is configured to store at least one two-dimensional array of data elements accessible to the processing circuit when performing the calculation, and each two-dimensional array of data elements includes a plurality of vectors of data elements, each vector being one-dimensional, and the array storage is provided with a storage element for storing data elements. A method comprising using the instruction decoder circuit to decode a zero-vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage, a subsequent cumulative sum instruction configured to perform an operation on the identified plurality of vectors of data elements, a non-cumulative sum variation of the cumulative sum operation specified by the cumulative sum instruction, and to control the processing circuit to generate a result data element for storage in the identified plurality of vectors in the array storage.

7. A computer program that causes a host data processing device to perform processing in order to provide an instruction execution environment, The processing program logic that executes the calculation, Instruction decoding program logic that decodes an instruction and controls the processing program logic to execute the operation specified by the instruction, The system comprises array storage emulation program logic for emulating array storage which includes storage elements for storing data elements, wherein the array storage is configured to store at least one two-dimensional array of data elements accessible to the processing program logic when performing the operation, and each two-dimensional array of data elements includes a plurality of vectors of data elements, each vector being one-dimensional. A computer program wherein the instruction decoding program logic is configured to decode a zero-vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage, and to decode a subsequent cumulative sum instruction configured to perform an operation on the identified plurality of vectors of data elements, and to control the processing program logic to perform a non-cumulative sum variation of the cumulative sum operation specified by the cumulative sum instruction to generate a result data element for storage in the identified plurality of vectors in the array storage.

8. It is a device, A processing circuit that performs calculations, An instruction decoder circuit that decodes an instruction and controls the processing circuit to execute the operation specified by the instruction, The array storage comprises a storage element for storing data elements, wherein the array storage is configured to store at least one two-dimensional array of data elements accessible when the calculation is performed, and each two-dimensional array of data elements contains a plurality of vectors of data elements, each vector being one-dimensional. The apparatus wherein the instruction decoder circuit is configured to control the processing circuit to set the storage elements of the array storage used to store the identified data elements of the array storage to a logical zero value in response to decoding a zero-vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage.

9. A method for processing data elements in the array storage of a device, Performing calculations using a processing circuit, The instruction decoder circuit is used to decode the instruction and the processing circuit is controlled to execute the operation specified by the instruction, The array storage includes providing a storage element for storing data elements, wherein the array storage is configured to store at least one two-dimensional array of data elements accessible to the processing circuit when performing the operation, and each two-dimensional array of data elements includes a plurality of vectors of data elements, each vector being one-dimensional. A method comprising: the instruction decoder circuit, in response to decoding a zero-vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage, controls the processing circuit to set the storage elements of the array storage used to store the identified plurality of vectors of data elements to logical zero values.

10. A computer program that causes a host data processing device to perform processing in order to provide an instruction execution environment, The processing program logic that executes the calculation, Instruction decoding program logic that decodes an instruction and controls the processing program logic to execute the operation specified by the instruction, The system comprises array storage emulation program logic for emulating array storage which includes storage elements for storing data elements, wherein the array storage is configured to store at least one two-dimensional array of data elements accessible to the processing program logic when performing the operation, and each two-dimensional array of data elements includes a plurality of vectors of data elements, each vector being one-dimensional. A computer program wherein the instruction decoding program logic is configured to control the processing program logic to set the storage elements of the array storage used to store the identified data elements of the array storage to logical zero values ​​in response to decoding a zero-vector instruction that identifies a plurality of vectors of data elements of a given two-dimensional array of data elements in the array storage.

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