Operandless instruction system-based processor and computer including same

Abstract

Disclosed are an operandless instruction system-based processor and a computer including same. The operandless instruction system-based processor comprises: an instruction processing unit for processing instructions of a program, wherein the instructions are composed of operandless instructions without operands besides instructions for transmitting and receiving data; one or more function processing units for performing a plurality of functions for data processing; and a stack register for separating instruction processing by the instruction processing unit and data processing by the function processing units. Accordingly, the number of logic gates may be minimized and high efficiency may be maintained by using a simple instruction set that does not include operands.

Description

Operandless instruction scheme-based processor and computer including the same

[0001] The present invention relates to an operandless instruction system-based processor and a computer including the same, and more specifically, to an operandless instruction system-based processor composed of a minimum number of logic gates having a structure that maintains computational performance and a computer including the same.

[0002] Recent computer architectures show a trend of converging on massive matrix operations to solve AI problems. In particular, tensor operations are overwhelmingly increasing their importance. However, despite the significant rise in the proportion of tensor operations, applications cannot be built solely using them. Constructing a program requires various computational functions, and the overwhelming contribution of tensor operations is merely a result of this requirement.

[0003] A method of adding computational functions to memory within the Von Neumann computer architecture has been proposed as a navigation technique to maximize computer system performance in AI computation. While this approach is not considered highly effective in complex general scientific and engineering applications due to the increased complexity of algorithms, it is expected to yield significant performance improvements in the field of AI. Based on this, many companies and research institutes are attempting to add computational functions to the memory area.

[0004] Operations performed in the memory area are divided into in-memory operations (PIM) and near-memory operations (PNM); both are executed by a separate Arithmetic Logic Unit (ALU) connected to or included in memory, rather than by the central processor (CPU).

[0005] In this case, if the Arithmetic Logic Unit (ALU) of a standard central processor is utilized as is, the circuitry constituting the memory must be equipped with additional circuitry for the ALU, leading to a problem where memory complexity becomes excessively high. Therefore, an ALU with significantly reduced functionality is configured and applied. Consequently, the usability of the ALU within the PIM / PNM, which has limited functionality, is severely restricted. Although PIM / PNM is applied for various reasons to further expand the performance of computer systems, it is actually difficult to reap the benefits of performance improvement.

[0006] Generally, various methods are applied to improve processor performance. These include using complex instruction sets or employing multiple instruction pipelines or multiple arithmetic units. However, this excessively increases circuit complexity, leading to an increase in logic gates, power consumption, and heat generation. To address this, manufacturing technology has evolved in the direction of narrowing circuit linewidths; however, as linewidths become narrower than 10nm, this causes new heat and power issues due to leakage current in the insulation sections. In particular, for PIM processor cores located within memory, even though instructions are minimized by significantly compromising functionality, the heat generated by the processor core in addition to the heat from the memory poses a major problem in normalizing performance.

[0007] To address this, there is a need for new computer technology capable of achieving high efficiency and low power consumption by minimizing the number of logic gates while maintaining the maximum number of necessary instructions.

[0008] Accordingly, the technical problem of the present invention is based on this point, and the objective of the present invention is to provide a processor based on an operandless instruction system composed of a minimum number of logic gates, having a structure that maintains computational performance by using a simple set of instructions that does not include operands.

[0009] Another objective of the present invention is to provide an operandless instruction system-based computer comprising the processor described above.

[0010] To realize the objective of the present invention as described above, a processor based on an operandless instruction system according to one embodiment comprises: an instruction processing unit that processes program instructions, wherein the instruction consists of operandless instructions that have no operands other than instructions for sending and receiving data; one or more function processing units that perform a plurality of functions for data processing; and a stack register that separates instruction processing by the instruction processing unit and data processing by the function processing unit.

[0011] In one embodiment, the instruction processing unit may include: a program counter that stores the memory address of the currently executing instruction, controls the flow of the program, specifies the address of the next instruction to be executed, and increases the program counter value whenever an instruction is executed to point to the next instruction; an instruction loader that reads instructions from an external instruction memory; an instruction queue that stores instructions loaded by the instruction loader, supports continuous instruction processing, and allows for rapid access when instructions are needed; and an instruction processor connected to the program counter, the instruction queue, and the function processing unit, respectively.

[0012] In one embodiment, the program counter can track the address of the next instruction by incrementing the counter according to the contents of the instruction queue.

[0013] In one embodiment, the instruction queue is operated in byte units, and can store the instruction by including only 1 byte when the instruction has no operand, and 3 to 4 bytes when the instruction has an operand.

[0014] In one embodiment, the instruction processor may include an instruction fetcher that reads an instruction from the instruction queue and provides it to the function processing unit; an instruction decomposer that interprets the instruction and converts it into an executable form; and a function selector that activates a function module within the function processing unit.

[0015] In one embodiment, the instruction decomposer processes instructions without operands as 1 byte and can construct the entire instruction by including additional bytes for instructions with operands.

[0016] In one embodiment, the function processing unit may include a first function processing module corresponding to an arithmetic logic unit (ALU) having an operation function; and a second function processing module corresponding to a control device having a control function.

[0017] In one embodiment, the stack register may include an ALU register accessed by the first function processing module; and an FPU stack accessed by the stacker of the second function processing module.

[0018] In one embodiment, the FPU stack may include a register stack accessed by a stacker; and an operation-only register operated by an ALU.

[0019] In one embodiment, the operation-only register may include a first direct access register that stores a first operand which is input data; a second direct access register that stores a second operand which is input data; and a result storage register that stores the result of the operation.

[0020] In one embodiment, the first direct access register may be at the top of the register stack, and the second direct access register may be synchronized with or identical to the next higher register of the register stack.

[0021] In one embodiment, the result storage register can place the result value at the top of the register stack after the operation is completed.

[0022] To realize another objective of the present invention as described above, a computer based on an operandless instruction system according to one embodiment comprises: an instruction memory for storing instructions of a program; a data memory for storing data necessary during the execution of the program; and a processor for reading instructions of the program from the instruction memory and sending and receiving data from the data memory, wherein the processor comprises: an instruction processing unit for processing instructions of the program, wherein the instruction is composed of an operandless instruction having no operands other than instructions for sending and receiving data; one or more function processing units for performing a plurality of functions for data processing; and a stack register for separating instruction processing by the instruction processing unit and data processing by the function processing unit.

[0023] According to processors based on such an operandless instruction scheme and computers containing them, the number of logic gates can be minimized while maintaining high efficiency by using a simple set of instructions that do not include operands. Furthermore, reducing the number of logic gates can lower power consumption and heat generation. Additionally, since fewer logic gates are required, more processor cores can be integrated onto a semiconductor die of the same size, leading to expected performance improvements.

[0024] FIG. 1 is a block diagram illustrating a computer based on an operandless instruction system according to one embodiment of the present invention.

[0025] Figure 2 is a diagram illustrating the structure of the instruction processing unit shown in Figure 1.

[0026] Figure 3 is a diagram illustrating the structure of the functional processing unit shown in Figures 1 and 2.

[0027] Figure 4 is a diagram illustrating the structure of the stack register shown in Figure 3 in an exemplary manner.

[0028] Figure 5 is a diagram illustrating the FPU stack structure in an exemplary manner.

[0029] Figure 6 is a diagram illustrating an example of applying multiple functional processing units.

[0030] FIG. 7 is a diagram illustrating the application of a multi-dimensional and multidimensional functional processing unit.

[0031] Figures 8a and 8b are drawings to illustrate the form of detailed instructions.

[0032] Figure 9 is a diagram illustrating an instruction table.

[0033] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement the invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0034] Throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected" but also cases where they are "electrically connected" with other elements interposed between them. Furthermore, when a part is described as "including" a component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components, and it should be understood that this does not preclude the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0035] Terms such as “about,” “substantially,” etc., used throughout the specification, are used to mean at or near the stated value when inherent manufacturing and material tolerances are presented in the stated meaning, and are used to prevent unscrupulous infringers from unfairly exploiting the disclosure in which precise or absolute values ​​are mentioned to aid in understanding the invention. Terms such as “step” or “step of” used throughout the specification of the invention do not mean “step for”.

[0036] In this specification, the term "part" includes a unit realized by hardware, a unit realized by software, and a unit realized using both. Additionally, one unit may be realized using two or more pieces of hardware, and two or more units may be realized by one piece of hardware. Meanwhile, "part" is not limited to software or hardware, and "part" may be configured to reside in an addressable storage medium or configured to run on one or more processors. Accordingly, as an example, "part" includes components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and "parts" may be combined into a smaller number of components and "parts" or further separated into additional components and "parts." In addition, the components and '~parts' may be implemented to play one or more CPUs within the device or secure multimedia card.

[0037] Some of the operations or functions described herein as being performed by a terminal, device, or device may instead be performed by a server connected to said terminal, device, or device. Likewise, some of the operations or functions described as being performed by a server may also be performed by a terminal, device, or device connected to said server.

[0038] In this specification, some of the operations or functions described as mapping or matching with a terminal may be interpreted as meaning mapping or matching the terminal's unique number or personal identification information, which is the terminal's identifying data.

[0039] The present invention will be described in detail below with reference to the attached drawings.

[0040] General processors such as CISC (Complex Instruction Set Computer) or RISC (Reduced Instruction Set Computer) have been developed with a very complex structure comprising numerous registers, instruction processing units, and arithmetic units to improve performance. However, increasing the number of arithmetic units or instruction processing units does not result in proportional performance improvement. Performance improvement meets expectations only in very exceptional cases, and in a significant number of cases, the improvement is minimal compared to the increase in circuit complexity.

[0041] The present invention presents a method for configuring a processor with a minimum number of logic gates that implements identical functions and performance. A method for enhancing performance was devised by optimizing the number of semiconductors in the processor structure while maintaining computational performance. The present invention relates to a Non-Operand Instruction Set Computer (NOISC).

[0042] FIG. 1 is a block diagram illustrating a computer based on an operandless instruction system according to one embodiment of the present invention.

[0043] Referring to FIG. 1, a computer based on an operandless instruction system according to one embodiment of the present invention includes an instruction memory (100), a data memory (200), and a processor (300).

[0044] The instruction memory (100) stores instructions of a program, such as code to be executed by a processor (300). The instructions may include an operational code (opcode) indicating the type of operation and an operand specifying data to be processed or an address where the data is stored.

[0045] The data memory (200) stores information such as data required during program execution, such as variables, arrays, and objects.

[0046] The processor (300) includes an Instruction Processing Unit (IPU) (310), a Function Processing Unit (FPU) (320) connected to the Instruction Processing Unit (310), and a Stacked Register (SR) (330) connected to the Function Processing Unit (320), and reads program instructions from the instruction memory (100) and receives data from the data memory (200). The processor (300) uses an address when reading instructions from the instruction memory (100). The processor (300) uses an address when reading and writing data from the data memory (200), and memory access is performed according to the size and format of the data.

[0047] The instruction processing unit (310) processes program instructions and is responsible for the process of reading instructions from the instruction memory, interpreting them, and executing them. That is, since the instruction processing unit (310) utilizes the registers shared with the FPU stack in the ALU as registers of the arithmetic unit, the number of instructions is greatly reduced and operands are eliminated, allowing functions such as decoders to be simplified to an extreme degree. Consequently, even when integrated, the complexity of the structure is not high. Therefore, performance degradation can be avoided by resolving complexity.

[0048] The function processing unit (320) performs various functions for data processing, including various operation functions (arithmetic, logic, etc.) and receives data from data memory. That is, the function processing unit (320) includes control functions and an ALU, and by modularizing each function, it is easy to simplify and standardize, thereby allowing the structure to be extremely simplified. Furthermore, it is easy to expand the structure by adding modules. It consists of functions that perform operation functions, functions that receive data from data memory, and branch-related functions. Although the roles performed by each function are different, they operate equally in the instruction processing unit (310).

[0049] The function processing unit (320) has the effect of separating instruction processing by the instruction processing unit (310) and data processing by the function processing unit (320) via the stack register (330), thereby facilitating the advancement of the processor (300) through structuring, standardization, and simplification. Consistency can be ensured by accessing the FPU stack as a register in the ALU and the data stack in the control unit, and the overall structure becomes simpler accordingly.

[0050] The stack register (330) separates instruction processing by the instruction processing unit (310) and data processing by the function processing unit (320).

[0051] As described above, the instruction processing unit (310) can utilize registers connected to the ALU (arithmetic logic unit) to reduce complexity such as operands and minimize the number of instructions, thereby simplifying functions such as decoders. This reduces the complexity of the overall structure and prevents performance degradation.

[0052] In addition, the function processing unit (320) is modularized so that it can be easily standardized for each function and the structure can be easily expanded through additional modules. Each function performs a different role, but operates in the same way in cooperation with the instruction processing unit (310). Thanks to this modularization, the entire structure can be extremely simplified.

[0053] Additionally, the stack register (330) establishes a clear boundary between the instructions processed by the instruction processing unit (310) and the data processed by the function processing unit (320), thereby facilitating the structuring, standardization, and simplification of the processor. This improves the consistency and simplicity of the overall system.

[0054] FIG. 2 is a drawing for explaining the structure of the instruction processing unit (310) shown in FIG. 1.

[0055] Referring to FIGS. 1 and 2, the instruction processing unit (310) includes a program counter (PC) (312), an instruction loader (314), an instruction queue (IQ) (316), and an instruction processor (318).

[0056] The program counter (312) stores the memory address of the currently executing instruction. The program counter (312) controls the flow of the program and specifies the address of the next instruction to be executed. Whenever an instruction is executed, the program counter (312) increases its value to indicate the next instruction.

[0057] The instruction loader (314) reads an instruction from the instruction memory (100) and stores it in the instruction queue (316). This process is a step of preparing the instruction so that it can be used by the function processing unit (320).

[0058] The instruction queue (316) serves as a buffer for storing instructions loaded by the instruction loader (314). Instructions are processed in byte units, and when the contents of the queue are exhausted, the instruction processor (318) loads new instructions into the instruction queue (316). The instruction queue (316) supports continuous instruction processing and allows for quick access to instructions when they are needed.

[0059] The instruction processor (318) includes an instruction fetcher (318a), an instruction disassembler (318b), and a function selector (318c).

[0060] Specifically, the instruction fetcher (318a) reads instructions from the instruction queue (316) and provides them to the function processing unit (320). When the contents of the instruction queue (316) are exhausted, the instruction fetcher (318a) loads new instructions into the instruction queue (316) according to the address of the program counter (312). The instruction fetcher (318a) updates the address of the program counter (312) and readjusts the contents of the queue according to a change in control flow, such as a JMP instruction.

[0061] The instruction decomposer (318b) interprets the instruction and converts it into an executable form. The instruction decomposer (318b) processes instructions without operands as 1 byte and constructs the entire instruction by including additional bytes, for example, 3 to 4 bytes, for instructions with operands. The instruction decomposer (318b) extracts the instruction's control signal (Opcode) and function processing unit selector (Selector) from the first byte to provide clear processing information.

[0062] The function selector (318c) activates a function module within the function processing unit (320). That is, the function selector (318c) determines which function module to activate based on the control signal of the instruction. Depending on the type of instruction, it selects and executes an appropriate unit from among the multiple function processing units (320).

[0063] Thus, various functions such as integer operations, floating-point operations, vector operations, tensor operations, and branch processing can be performed efficiently.

[0064] When operating, since the instruction is composed of byte units, the instruction queue (316) is manipulated in byte units. When the most significant bit of the instruction (i.e., the bit indicating that it is an instruction without an operand) is set, the program counter (312) corresponding to one byte is incremented, and when the most significant bit of the instruction is not set, the instruction byte and the 4-byte instruction are added.

[0065] The instruction decomposer (318b) may correspond to an instruction decoder. The instruction decomposer (318b) receives an instruction and generates a control signal (Opcode) for the instruction in a simple separation form. Since the instruction basically has no operand, the instruction decoding process is simple and fast. The instruction decomposer (318b) simplifies the structure by incorporating the function of a decoder.

[0066] When the contents of the instruction queue (316) are exhausted, the instruction fetcher (318a) puts the instruction at the corresponding address into the instruction queue (316). When the contents of the program counter (312) are changed by the JMP function, etc., the instruction fetcher (318a) deletes the contents of the instruction queue (316) and loads the instruction at the address of the program counter (312) into the instruction queue (316).

[0067] In this embodiment, the instruction decomposer (318b) can select a unit to execute from among a plurality of function processing units (320). Thus, a plurality of function processing units (320) can be configured according to the type of instruction.

[0068] In this embodiment, the functional processing unit (320) can be configured by dividing it into multiple units according to the characteristics of the data being handled. Various expansions and modifications are easily made depending on the type of data processed by the functional processing unit (320). Separate functional processing units (320) can be configured for instructions that share a stack of a functional processing unit (320) of a specific structure, or simplified to configure a single functional processing unit (320). This greatly increases the functional expandability of the processor (300).

[0069] In this invention, the instruction set is simple, so a separate conversion from instructions to control signals (Opcodes) is unnecessary; thus, unlike the decoders of conventional computers, the instruction fetcher primarily performs the role of branching instructions. In other words, by utilizing this simplicity, the instruction fetcher performs a significant role of the control unit. Conventional computer architectures consist of an ALU that processes data and a control unit that manages the entire system; however, to improve performance, this invention divides the computer structure into an instruction processing unit and a function processing unit.

[0070] In this embodiment, the instruction processing unit (310) utilizes the register shared with the FPU stack in the ALU as the register of the arithmetic unit, so the number of instructions is greatly reduced and operands are eliminated, thereby allowing the functions of the instruction fetcher (318a) and decoder to be extremely simplified. Accordingly, the complexity of the structure is not high even when integrated. Therefore, performance degradation can be avoided by resolving complexity. A separate conversion function to an Opcode is not required in the instruction queue (316).

[0071] FIG. 3 is a drawing for explaining the structure of the functional processing unit (320) shown in FIG. 1 and FIG. 2.

[0072] Referring to FIGS. 1 to 3, the functional processing unit (320) includes a first functional processing module (322) corresponding to an arithmetic logic unit (ALU) having an operation function similar to a general computer, and a second functional processing module (324) corresponding to a control unit having a control function.

[0073] The function processing unit (320) utilizes a register having a stack structure instead of a general addressable register. Among all function units, the ALU-related function uses the top two stacks of the FPU stack (334). When an operation or function is completed, the result is placed in the next stack, and the top stack value is discarded. At this time, there is a separate register for storing intermediate operation results, and the separate register has a size that accommodates the result of a multiplication operation.

[0074] POP instructions or PUSH instructions that bring data from data memory (200) to the processor (300) have the address of the data in memory as an operand. To maximize convenience, an immediate value is also accepted as an operand.

[0075] Jump instructions (i.e., JMP and Jxx), which are branch instructions associated with CMP instructions, contain address information as an operand within the instruction. This is stored in a reference register and is used as the address of the instruction memory (100) when executed.

[0076] Control unit related functions also utilize the FPU stack (334), and functions related to branching or data delivery additionally utilize address data included in the instructions.

[0077] The stacker (324a) sends address information within the instruction to the data in the data memory (200) individually to the FPU stack (334), and the loader (324b) sends address information within the instruction to the FPU stack (334) in batches. Here, sending means supporting or performing a task or service.

[0078] The operation function unit corresponding to the ALU and the operating devices corresponding to the control unit, such as Jump and Push & Pop, are treated with the same operating mechanism.

[0079] The first function processing module (322) manipulates the ALU register (332), and the second function processing module (324) manipulates the FPU stack (334). That is, to perform a specific function or task, the first function processing module (322) performs processing such as reading, writing, and modifying data on the ALU register (332) using arithmetic logic operation instructions such as ADD, SUB, MUL, DIV, Shift, AND, etc., and the second function processing module (324) performs processing such as reading, writing, and modifying data on the FPU stack (334). Synchronizing these ALU registers (332) and FPU stack (334) simplifies the structure of the function processing unit (320).

[0080] In this embodiment, the FPU stack (334) and the return stack (placed in memory) are used separately. The FPU stack (334) stores data required for computation, and the return stack stores the return address when a function is called. The return stack stores information related to the execution state of the called function when the function is called, and is structured to use this information to return to the location where the function was called when the function terminates.

[0081] FIG. 4 is a diagram illustrating the structure of the stack register (330) illustrated in FIG. 3 as an example. In particular, a stacked register (330) for 32-bit integer processing is illustrated.

[0082] Referring to FIGS. 3 and 4, the stack register (330) includes an ALU register (332) accessed by the first function processing module (322) and an FPU stack (334) accessed by the stacker (324a) of the second function processing module (324).

[0083] The FPU stack (334) includes a register stack (334a) accessed by the stacker (324a) and an operation-only register (334b) operated by the ALU.

[0084] The register stack (334a) has a form that accommodates operands. The register stack (334a) has an appropriate depth as a first-in, first-out (FIFO) data device. The register stack (334a) may have a format such as a 32-bit or 64-bit floating-point number, 16, 32, or 64-bit integer as needed, and has an extended data format to process various data. The register stack (334a) operates with PUSH and POP instructions and receives data from the data memory (200). Additional functions may be added to the register stack (334a) as needed.

[0085] The operation-only register (334b) includes a first direct access register (Register 1, R1) that stores the first operand, which is the input data; a second direct access register (Register 2, R2) that stores the second operand, which is the input data; and a result storage register (Register 0, R0) that stores the result of the operation. Data transfer is performed through a stacker (324a), and the method involves the first direct access register (R1) being placed at the top of the register stack (334a) and the second direct access register (R2) being synchronized or identical with the next-highest level of the register stack (334a). The result storage register (R0) holds the result after the operation is completed and places that value at the top of the register stack (334a). At this time, the top of the register stack (334a) is pre-selected according to the characteristics of the operation.

[0086] Specifically, the result storage register (R0) stores the result value of the operation. That is, the result of the operation is finally stored in the result storage register (R0). The size of the result storage register (R0) is set to 64 bits, which is a size capable of accommodating 64 bits of the multiplication result or 32 bits of the addition result. After the result of the operation is stored in the result storage register (R0), the lower 32 bits are moved to an accessible area of ​​the stack. In this embodiment, the result storage register (R0) stores the execution result of an instruction executed by the processor and may include a 32-bit or 64-bit register, but the present invention is not limited thereto. In this embodiment, the result storage register (R0) may store integer data or floating-point data.

[0087] The first direct access register (R1) is the top register of the stack and is the register referenced by the operation instruction. Specifically, the value of the first direct access register (R1) is required when performing the operation, and since it is the top stack register (330), it is the value located at the very top of the current stack.

[0088] The second direct access register (R2) is the next higher register on the stack and is referenced in operation instructions together with the first direct access register (R1). Specifically, the second direct access register (R2) is located immediately below the first direct access register (R1), and when performing an operation, the values ​​of the first direct access register (R1) and the second direct access register (R2) are used to generate a result.

[0089] Accordingly, the result storage register (R0) serves as the final storage for storing the operation result, and the first direct access register (R1) and the second direct access register (R2) serve to provide the operands necessary to perform the operation. The first direct access register (R1) is the top register of the stack, and the second direct access register (R2) is the next-highest register located immediately below it.

[0090] It consists of a result storage register (R0) that stores result values ​​and a stack of n depths, the top of the stack is shared with the first direct access register (R1) and the next top of the stack is shared with the second direct access register (R2). The registers are accessible only within the FP of the operation function and exchange information with memory through the area of ​​the FPU stack (334).

[0091] The result of the result storage register (R0) is generated through the first direct access register (R1) and the second direct access register (R2) referenced by the operation instruction, and only the lower 32 bits of this result are moved to the area accessed by the stacker (324a). In the case of 32-bit multiplication, a 64-bit result is generated, and in the case of addition, a 33-bit result is generated. The size of the result storage register (R0) is 64 bits.

[0092] If the computation becomes complex and the size of the FPU stack (334) becomes insufficient, the entire FPU stack (334) may need to be backed up. However, if this is performed using a separate software program, significant performance degradation may occur. Increasing the size of the FPU stack (334) may increase the number of logic gates, so the depth of the stack must be minimized within an appropriate range. To minimize the depth of the stack, an instruction is required to move the entire FPU stack (334) into memory. An SBACKUP instruction can be established to move all the contents of the FPU stack (334) into memory, and an SRESTORE instruction can be established to move the contents of the FPU stack (334) stored in memory back to the FPU stack (334). This can overcome the limitations and performance degradation issues associated with the size of the stack.

[0093] Figure 5 is a diagram illustrating the FPU stack structure in an exemplary manner.

[0094] Referring to FIG. 5, the FPU stack (334) has a stack registers for dual access (Register Stack) structure for stack and direct access. The FPU stack (334) consists of stack-type registers and direct access registers.

[0095] The stack's T0 (top) and the first direct access register (R1) are synchronized, the stack's T1 (top-1) and the second direct access register (R2) are synchronized, and a result storage register (R0) for storing results is configured separately.

[0096] In terms of access in the FPU stack (334), there are two completely separate registers, but physically, the first direct access register (R1) and stack T0 are the same, and the second direct access register (R2) and stack T1 are the same.

[0097] There are various methods for synchronizing the first direct access register (R1) and stack T0, and the second direct access register (R2) and stack T1, such as operating the registers as dual ports and real-time mirroring.

[0098] Figure 6 is a diagram illustrating an example of applying multiple functional processing units (FPUs).

[0099] Referring to FIG. 6, a first functional group corresponding to a first dimension includes a plurality of functional processing units (412, 414, , 41X), and a second functional group corresponding to a second dimension includes a plurality of functional processing units (422, 424, , 41X). The first functional group and the second functional group operate a plurality of stack registers (432, 434, , 43X).

[0100] Meanwhile, for AI computations such as 4-bit, 8-bit, and 16-bit, it is also possible for a single Function Processing Unit (FPU) to manipulate multiple stacks. In this case, the structure of the existing NPU or PIM / PNM can be enhanced in functionality or simplified to facilitate performance expansion.

[0101] As such, by applying multiple Function Processing Units (FPUs), it is possible to configure a dedicated processor that performs various operations, such as advanced tensor operations required in the AI ​​domain, which is also very useful for vector operations and requires much fewer resources than existing methods.

[0102] Here, a tensor is a multidimensional array and is the basic unit of data representation in machine learning. For example, an image is represented as a 3-dimensional tensor (height, width, and color channels). AI models perform complex tensor operations, including matrix multiplication, convolution, and activation functions; however, multi-function processing units can process these operations simultaneously, thereby accelerating the learning speed.

[0103] Furthermore, vector operations process multiple data elements simultaneously, enabling parallel processing when there are multiple Functional Processing Units (FPUs). This is highly useful for vector dot products and vector transformations in AI algorithms. Additionally, by distributing computations through multiple FPUs, high performance can be maintained while consuming significantly fewer resources compared to traditional CPU-based methods, thereby increasing resource efficiency.

[0104] As described in FIG. 6, simple function grouping of function processing units by dimension, such as L1 FPU and L2 FPU, is possible, but FPU multiplexing of completely different dimensions is also possible, as shown in FIG. 7 below. Of course, a configuration utilizing the ALU in two dimensions in this way is possible in existing technology, but the complexity of the circuit configuration becomes excessively high, making it commercially unfeasible. In contrast, in the present invention, the chaining of FPUs and FPU stacks (334) and the multidimensional expansion of FPU functions are easy.

[0105] FIG. 7 is a diagram illustrating the application of a multi-dimensional functional processing unit (FPU).

[0106] Referring to Fig. 7, the structure of the FPU stack can be expanded to two dimensions to configure multiple FPUs with different functions. Functionality can be maximized by accessing the entire FPU stack group, such as FPU B.

[0107] Generally, to perform scalar processing and vector processing, two types of ALUs must be accompanied by two types of registers: general (scalar) registers and vector registers. In general operations, the general ALU operates general registers, while in vector operations, the vector ALU operates vector registers.

[0108] In contrast, in this embodiment, multiple sets of FPU stacks can be constructed and operated by a single FPU stack stacker, and it is possible to configure various FPUs to access them for various purposes. This makes vector processing easy to implement. In particular, by configuring separate instructions such as PUSH-PUSHV and POP-POPV that accommodate scalar data and vector data in a stacker (it is reasonable to view a stacker as a type of FPU), vector data and scalar data can be operated in a single FPU stack or a group of FPU stacks.

[0109] In addition to vector processing, Tensor processing capabilities can also be easily implemented, as shown in FPU B. Not only can the results computed in FPU Group A be summed in FPU Group B, but it is also easy to implement various functions. By expanding the capabilities of FPUs such as FPU Group B, ideal Tensor processing functions can be implemented, and furthermore, the possibility of easy optimization is opened up.

[0110] Below, the structure of the instruction set architecture (ISA) used in the present invention is described.

[0111] In this embodiment, the instructions are composed of operand-less instructions that have no operands other than those for sending and receiving data. Each instruction performs an operation based on the FPU stack and executes the operation using the top value of the stack. An operand corresponding to an address value is applied only when memory needs to be accessed, such as when data in data memory needs to be referenced. An instruction set is configured to enable seamless operation of the C language. The instructions required to implement the C language on general processors such as existing CISC or RISC are as follows.

[0112] Data Transfer Instructions

[0113] LOAD / LD: Loads data from memory into a register.

[0114] STORE / ST: Stores the data from the register into memory.

[0115] MOVE / MOV: Moves data from one register to another.

[0116] PUSH: Stores data on the stack.

[0117] POP: Reads data from the stack.

[0118] Arithmetic Instructions

[0119] ADD: Adds the values ​​of two registers.

[0120] SUB: Subtracts the values ​​of two registers.

[0121] MUL: Multiplies the values ​​of two registers.

[0122] DIV: Divides the values ​​of two registers.

[0123] INCREMENT / INC: Increases the value of the register by 1.

[0124] DECREMENT / DEC: Decreases the value of a register by 1.

[0125] NEGATE / NEG: Inverts the sign of the register value.

[0126] Logical Instructions

[0127] AND: Performs a bitwise logical AND operation between two registers.

[0128] OR: Performs a bitwise logical OR operation on two registers.

[0129] XOR: Performs a bitwise logical XOR operation on two registers.

[0130] NOT: Performs a bitwise logical NOT operation on the register.

[0131] SHIFT LEFT / SHL: Shifts the bits of the register to the left.

[0132] SHIFT RIGHT / SHR: Shifts the register bits to the right.

[0133] Control Flow Instructions

[0134] JUMP / JMP: Jumps unconditionally to a specific address.

[0135] JUMP IF ZERO / JZ: Jumps to a specific address if the register value is 0.

[0136] JUMP IF NOT ZERO / JNZ: Jumps to a specific address if the register value is not 0.

[0137] JUMP IF EQUAL / JE: Jumps to a specific address if the values ​​of two registers are the same.

[0138] JUMP IF NOT EQUAL / JNE: Jumps to a specific address if the values ​​of the two registers are different.

[0139] CALL: Calls a subroutine (function).

[0140] RETURN / RET: Returns from a subroutine (function).

[0141] LOOP: Repeats until the counter becomes 0.

[0142] Comparison Instructions

[0143] COMPARE / CMP: Compares the values ​​of two registers.

[0144] TEST: Tests a specific bit pattern.

[0145] System Instructions

[0146] NO OPERATION / NOP: Do not perform any work and proceed to the next instruction.

[0147] INTERRUPT / INT: Generates a software interrupt.

[0148] RETURN FROM INTERRUPT / RETI: Returns after interrupt processing.

[0149] HALT: Stops the processor.

[0150] Stack Instructions (Provides the ability to support Function Calls)

[0151] PUSH: Pushes data onto the stack.

[0152] POP: Pops data from the stack.

[0153] CALL: Saves the current address onto the stack, jumps to a specific address, and calls a subroutine.

[0154] RETURN / RET: Pops the previous address from the stack and jumps to that address to return from the subroutine.

[0155] Bit Manipulation Instructions

[0156] SET BIT / SETB: Sets a specific bit in a register or memory location.

[0157] CLEAR BIT / CLRB: Clears a specific bit at a register or memory location.

[0158] TOGGLE BIT / TGLB: Toggles a specific bit at a register or memory location.

[0159] Even if the processor of the present invention includes all functions, it can be processed in a single byte because the number of instructions is small. Since some instructions require operands, they have a structure as shown in the example below.

[0160] Operand-less instructions are as shown in Table 1 below. Table 1 shows 1-byte instructions.

[0161]

[0162] Referring to Table 1, the instruction without an operand is set to 1 byte, the lowest 6 bits of byte 0 are assigned an opcode, and the highest 2 bits of byte 0 are assigned an FPU.

[0163] Instructions with operands are shown in Table 2 below. Table 2 shows 5-byte instructions.

[0164]

[0165] Referring to Table 2, the instruction with operand is set to 5 bytes, and the address and 32-bit immediate value are assigned to the least significant byte 0 through 3. Additionally, the least significant 6 bits of the most significant byte 4 are assigned an opcode, and the most significant 2 bits of byte 4 are assigned an FPU.

[0166] Thus, the instruction consists of one byte. The 0 to 2 bits of the instruction are used as an identification area to select the function processing unit (310), and the remaining bits are used to correspond to the function.

[0167] <Example of Instruction Set Architecture>

[0168] The bit configuration of the instruction is as shown in Table 3 below.

[0169]

[0170] Referring to Table 3, this is an example of an instruction set when the function processing unit (310) is composed of four units: 'FPU00: operation without operand', 'FPU01: control without operand', 'FPU10: branch with operand', and 'FPU11: data receiving with operand'.

[0171] The instruction structure by function is as follows.

[0172] <Operation>

[0173] Arithmetic Instructions

[0174] ADD, SUB, INC, DEC, NEG, MUL, DIV, INV

[0175] (Logical Instructions)

[0176] AND, OR, XOR, NOT

[0177] Bit Manipulation Instructions

[0178] SHL, SHR

[0179] <Break>

[0180] JMP, JZ, JNZ, JE, JNE, JG, JGE, JL, JLE, CMP

[0181] Data Supply

[0182] PUSH, POP, CALL, RET

[0183] Control

[0184] NOP, HALT

[0185] This can be divided based on the presence or absence of an operand.

[0186] The instruction configurations for other instruction mechanisms are as follows.

[0187] Instruction without an offer

[0188] - When manipulating (computating) the FPU stack

[0189] ADD, SUB, INC, DEC, NEG, MUL, DIV, INV, AND, OR, XOR, NOT, SHL, SHR

[0190] - When manipulating other registers - Perform control functions

[0191] CMP, NOP, HALT, RET

[0192] Instructions with Offerland

[0193] - When moving data to the FPU stack

[0194] PUSH, POP, LOAD, RESTORE

[0195] - When jumping (when manipulating the program counter)

[0196] CALL, JMP, JZ, JNZ, JE, JNE, JL, JG, JLE, JGE

[0197] The above instructions are sufficient to implement the C language. A visual example of this is as follows.

[0198] FIGS. 8A and FIGS. 8B are drawings for illustrating the form of detailed instructions. In particular, FIG. 8A illustrates a 1-byte instruction for instruction processing without an operand, and FIG. 8B illustrates a 5-byte instruction for instruction processing with an operand.

[0199] Referring to FIG. 8a, a 1-byte instruction is stored in the first direct access register (R1) and the Register, respectively. That is, "00cccccc" is stored in the first direct access register (R1), and "01cccccc" is stored in the second direct access register (R2). Here, the OP codes and function codes of OP0 to OP4 are assigned to bits 2 to 7, the operation and control status code is assigned to bit 1, and the operand status code is assigned to bit 0.

[0200] The Opcode is passed to the corresponding instruction processing unit (310) among the four processing units. The program counter is incremented by 1.

[0201] Referring to FIG. 8a, 5 bytes of instructions are stored in the first direct access register (R1) and the second direct access register (R2), respectively. That is, "10cccccc" is stored in the top 1 byte of the first direct access register (R1), and "11cccccc" is stored in the top 1 byte of the second direct access register (R2). Additionally, an address value or immediate data is stored in the 3 bytes of each of the first direct access register (R1) and the second direct access register (R2).

[0202] Here, in the most significant byte of each of the first direct access register (R1) and the second direct access register (R2), the Opcodes and function codes of OP0 to OP4 are assigned to bits 2 to 7, the branch and control code is assigned to bit 1, and the operand code is assigned to bit 0.

[0203] The Opcode is passed to the corresponding instruction processing unit (310) among the four processing units. The program counter is incremented by 5.

[0204] An example of an instruction table can be constructed based on the contents described in Figures 8a and 8b.

[0205] Since it consists of 8 bits, it can have a total of 256 instructions, but in practice, it is expected that around 60 instructions will be sufficient. As shown in the example, if the most significant bits 1 to 3 are set as values ​​to designate (select) function processing units, multiple function processing units can be configured according to the function to obtain utility in terms of efficiency and performance.

[0206] Instructions from 0x00 to 00xff can be configured into four instruction sets corresponding to 0x00~0x3f, 0x40~0x7f, 0x80~0xbf, and 0xc0~0xff. Since each of these selects a separate function processing unit and calls a function (function, circuit) among them, a high degree of structuring can be achieved in the overall circuit configuration.

[0207] That is, the 256 numbers from 0x00 to 0xFF can be organized into the first instruction set of 0x00 to 0x3f, the second instruction set of 0x40 to 0x7f, the third instruction set of 0x80 to 0f, and the fourth instruction set of 0xc0 to 0xff. The instruction sets corresponding to each range may contain different functions or commands. For example, the first instruction set may contain basic instructions, the second instruction set may contain instructions of medium complexity, the third instruction set may contain advanced instructions, and the last, fourth instruction set may contain special instructions.

[0208] <Example of Instruction Table of the Present Invention>

[0209] If this is presented as a mechanism for accommodating the C language in the present invention, it can be composed of the following instruction set. The functions and instructions processed by the function processing unit correspond one-to-one. The instruction set can be exemplified as shown in FIG. 9 below.

[0210] Figure 9 is a diagram illustrating an instruction table.

[0211] A simplified decoder structure is formed to minimize the number of logic gates using the method shown in Fig. 9. In particular, since the number of instructions is small, instructions can be executed effectively even if the decoder is configured as a simple circuit. The role of the decoder is to automatically classify instructions according to their mechanism through the upper two bits. This is basically achievable by pursuing decoding simplification and is a mechanism different from that of existing processors.

[0212] Instructions have the following functions.

[0213] <Stack manipulation instructions>

[0214] Stack manipulation instructions perform the function of moving data from data memory to the FPU stack or operation data from the FPU stack to data memory.

[0215] PUSH [Addr]: Adds data from data memory to the FPU stack.

[0216] PUSHV [int4]: Adds 32-bit data to the FPU stack.

[0217] POP [Addr]: Moves data from the FPU stack to data memory and deletes it.

[0218] LOAD [Addr]: Loads data corresponding to a set of stack data in memory into the FPU stack.

[0219] RSTR [Addr]: Moves all data related to the FPU stack into memory as a set.

[0220] DUP: Copies the top value of the FPU stack and adds it back to the stack.

[0221] SWAP: Swaps the top two values ​​of the FPU stack.

[0222] CAS: Clears all values ​​on the FPU stack and initializes the stack pointer.

[0223] Instructions without operands, such as PPN (remove top value) and PSHN (insert null value), can be added.

[0224] <Arithmetic Operation Instructions>

[0225] All arithmetic instructions target only the stack within the ALU, but the mechanism of operation is the same as that of the registers in a conventional computer. On the ALU side, the registers are operated as fixed registers, such as the result storage register (R0), the first direct access register (R1), and the second direct access register (R2), and the exchange with memory is handled by stack operation instructions as a stack operation method.

[0226] In the ALU, operation functions such as 'ADD' operate based on the mechanism of conventional computers' 'ADD R0 R1 R2 ; R0 = R1 + R2'.

[0227] ADD: Adds the two most significant values ​​on the FPU stack, stores the result in the result register, discards the two most significant values, and inputs the value of the result register onto the stack. The pseudocode for the operation mechanism is as follows.

[0228] pop Register1; <top>

[0229] pop Register2; <top-1>

[0230] Register0 <- Register1 + Register2

[0231] push Register0; <top>

[0232] Although it produces an equivalent result of the operation described above, in practice, the ADD operation circuit adds the two upper values ​​(T0, T-1) of the stack and discards the highest value of the result at the next upper level (T-1).

[0233] SUB:(NEG + ADD) Changes the highest value on the FPU stack to half, adds the two highest values, deletes the two highest values, and inputs the value of the result register onto the stack. In other words, changes the next highest stack value to half and adds it to the highest value.

[0234] NEG: Changes the top value of the FPU stack to its half. In other words, it changes a negative number to a positive number or a positive number to a negative number.

[0235] INC: Increases the top value of the FPU stack by 1.

[0236] DEC: Decrease the top value of the FPU stack by 1.

[0237] MUL: Multiplies the two most significant values ​​on the FPU stack, stores the result in the result register, clears the two most significant values, and inputs the value from the result register onto the stack.

[0238] DIV:(INV + MUL) Changes the top value of the FPU stack to its reciprocal, multiplies the two top values, stores the result in the result register, deletes the two top values, and inputs the value of the result register onto the stack.

[0239] INV: Converts the top value of the FPU stack to its inverse. That is, changes the sign of the exponent part to the value obtained by dividing 1 by the value.

[0240] In practice, the ALU can be configured using only ADD and MUL.

[0241] Logical and Bitwise Operation Instructions

[0242] AND: Performs a bitwise AND operation on the two top values ​​of the FPU stack and stores the result in the stack.

[0243] OR: Performs a bitwise OR operation on the two top values ​​of the FPU stack and stores the result in the stack.

[0244] XOR: Performs a bitwise XOR operation on the two top values ​​of the FPU stack and stores the result in the stack.

[0245] NOT: Inverts the top value of the FPU stack bit by bit and stores the result on the stack.

[0246] SHL: Shift the next highest value in the FPU stack to the left by the highest value.

[0247] SHR: Shift the next highest value in the FPU stack to the right by the highest value.

[0248] Bitwise operations perform operations through all bits, while logical operations use only the lowest single bit of the data value.

[0249] Comparison and Conditional Branch Instructions

[0250] It requires an address value as an operand.

[0251] JMP [Addr]: Branch to [Addr].

[0252] JE [Addr]: Branch to [Addr] if the top value of the FPU stack is equal to the next-highest value.

[0253] JNE [Addr]: Branch to [Addr] if the top value of the FPU stack is not equal to the next-highest value.

[0254] JG [Addr]: Branch to [Addr] if the top value of the FPU stack is greater than the next-highest value.

[0255] JGE [Addr]: Branch to [Addr] if the top value of the FPU stack is greater than or equal to the next-highest value.

[0256] JL [Addr]: Branch to [Addr] if the top value of the FPU stack is smaller than the next-highest value.

[0257] JLE [Addr]: Branch to [Addr] if the top value of the FPU stack is less than or equal to the next-most value.

[0258] CALL [Addr]: Pushes the contents of the program counter onto the memory stack and branches to [Addr].

[0259] RTN: Pops from the memory stack and sets its contents to the program counter. In other words, it branches to the program counter.

[0260] System Control Instructions

[0261] NOP: Performs no work.

[0262] HALT:(Break) Resets the program counter and stops operation. Stops program execution. Keeps the processor in an idle state.

[0263] HLTA:(Exit) Resets the instruction memory area and stops operation.

[0264] PAUSE: Stops program execution until a restart signal is received.

[0265] Since the computer structure of the present invention differs significantly from existing computer technology, there are substantial derivative instructions in addition to the presented instructions.

[0266] <Derived Instruction>

[0267] JUMP <address>--> JMPD<immediate value>

[0268] PUSH <address>--> PSHV <immediate value>

[0269] POP <address>--> PPN

[0270] PUSH <address>--> PSP4 / PSP2 / PSP1 <address>

[0271] POP <address>--> POP4 / POP2 / POP1 <address>

[0272] To improve performance and functionality, various waveform instructions are added within a range that does not significantly increase circuit complexity.

[0273] The effects according to the present invention described above are summarized as follows.

[0274] (1) By configuring the registers used for operations within the ALU into a stack, operands can be eliminated in most instructions. Since most instructions, excluding branching and data transfer, do not have operands, short instructions of less than 1 byte can be constructed.

[0275] (2) Since there are no operands and the instructions are short, the control functions for processing them can be simplified. The execution speed is improved through the interpretation of simple instructions without operands, which increases processing speed. Since an instruction pipeline for instruction processing is unnecessary, the structure is simplified and implementation is easy.

[0276] (3) The instruction set can be restructured by reorganizing it according to instruction function or required resources. This allows for further simplification of the instruction processing unit. Simplification of the structure requires a smaller number of logic gates compared to processors in existing CISC and RISC architectures, and the number of logic gates is minimized. This is achieved through a simple instruction set and stack-based operations, which further simplifies the structure. A reduction in the number of logic gates reduces power consumption and heat generation. This increases power efficiency. Reduced heat generation extends the lifespan of the semiconductor, and heat management becomes easier, allowing for a significant extension of lifespan.

[0277] (4) The number of logic gates is reduced, allowing for a smaller chip size and enabling miniaturization. Furthermore, a larger number of processors can be integrated onto the same die. This can replace efforts to reduce the circuit width of semiconductors. Since this allows for the application of low-cost manufacturing technology, it can lead to a significant reduction in production costs. Moreover, since fewer transistors are required to achieve a unit of performance, a double reduction in production costs is possible.

[0278] (5) Compared to existing processors, the number of logic gates required to achieve any function and performance is extremely small, giving it an overwhelming advantage in constructing PIM or PNM. It is also advantageous for constructing collective operations such as vector operations or tensor operations. This opens up the possibility of advancing the structure of PIM / PNM.

[0279] (6) Since it requires fewer logic gates, the cross-sectional area of ​​the circuit configuration is smaller than that of conventional processor technology, even if the insulation is reinforced during the production process of fine linewidth semiconductors. This allows for the suppression of leakage current, making it possible to configure a revolutionary low-power processor.

[0280] (7) All functions, such as computation and control, can be appropriately modularized through standardization and simplification, allowing the entire processor configuration to be structured and optimized. By configuring processor cores and integrating multiple processors, it is advantageous in terms of cost compared to existing technologies.

[0281] (8) Stack-based processors make it easy to apply post-order notation to instructions. This means that the development of the compiler can be easy and efficient. It is optimized for this requirement.

[0282] Although the invention has been described above with reference to embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims.

[0283] <Explanation of Symbols>

[0284] 100 : Instruction memory 200 : Data memory

[0285] 300: Processor 310: Instruction Processing Unit

[0286] 312: Program Counter 314: Instruction Loader

[0287] 316 : Instruction Queue 318 : Instruction Processor

[0288] 318a: Instruction Fetcher 318b: Instruction Disassembler

[0289] 318c: Function selector 320: Function processing unit

[0290] 322: 1st Function Processing Module 324: 2nd Function Processing Module

[0291] 324a : Stacker 324b : Loader

[0292] 330: Stack Register 332: ALU Register

[0293] 334: FPU Stack 334a: Register Stack

[0294] 334b: Operation-only register< / address> < / address> < / address> < / address> < / address> < / address> < / address> < / top> < / top>

Claims

1. An instruction processing unit that processes program instructions, wherein the instructions consist of operandless instructions that have no operands other than instructions for sending and receiving data; One or more functional processing units that perform multiple functions for data processing; and An operandless instruction scheme-based processor characterized by including a stack register that separates instruction processing by the instruction processing unit and data processing by the function processing unit.

2. In paragraph 1, the instruction processing unit is, A program counter that stores the memory address of the currently executing instruction, controls the flow of the program, specifies the address of the next instruction to be executed, and increments the program counter value whenever an instruction is executed to point to the next instruction; An instruction loader that reads instructions from external instruction memory; An instruction queue that stores instructions loaded by the instruction loader, supports continuous instruction processing, and enables rapid access to instructions when needed; and An operandless instruction scheme-based processor characterized by including an instruction processor connected to the program counter, the instruction queue, and the function processing unit, respectively.

3. An operandless instruction scheme-based processor according to paragraph 2, wherein the program counter increments the counter according to the contents of the instruction queue to track the address of the next instruction.

4. An operandless instruction system-based processor according to claim 2, characterized in that the instruction queue is operated in byte units, and stores the instruction by including only 1 byte when the instruction has no operand, and 3 to 4 bytes when the instruction has an operand.

5. In paragraph 2, the instruction processor is, An instruction fetcher that reads instructions from the above instruction queue and provides them to the above function processing unit; An instruction decomposer that interprets instructions and converts them into an executable form; and An operandless instruction system-based processor characterized by including a function selector that operates a function module within the above-mentioned function processing unit.

6. An operandless instruction scheme-based processor according to claim 5, characterized in that the instruction decomposer processes instructions without operands as 1 byte and constructs the entire instruction by including additional bytes for instructions with operands.

7. In paragraph 1, the above-mentioned function processing unit is, A first function processing module corresponding to an arithmetic logic unit (ALU) having an operation function; and An operandless instruction system-based processor characterized by including a second function processing module corresponding to a control device having a control function.

8. In paragraph 7, the stack register is, An ALU register accessed by the first function processing module; and An operandless instruction scheme-based processor characterized by including an FPU stack accessed by a stacker of the second function processing module.

9. In paragraph 8, the above FPU stack is, The register stack accessed by the stacker; and An operandless instruction scheme-based processor characterized by including an operation-only register operated by an ALU.

10. In paragraph 9, the above-mentioned operation-only register is, A first direct access register that stores the first operand, which is input data; A second direct access register storing a second operand which is input data; and An operandless instruction scheme-based processor characterized by including a result storage register for storing the result of an operation.

11. An operandless instruction scheme-based processor according to claim 10, characterized in that the first direct access register is at the top of the register stack, and the second direct access register is synchronized or identical with the next higher level of the register stack.

12. An operandless instruction scheme-based processor according to claim 10, characterized in that the result storage register places the result value at the top of the register stack after the operation is completed.

13. Instruction memory for storing program instructions; A data memory for storing data required during the execution of the above program; and The system includes a processor that reads instructions of the program from the instruction memory and receives data from the data memory, wherein the processor, An instruction processing unit that processes instructions of the above program, wherein the instructions consist of operandless instructions that have no operands other than instructions for sending and receiving data; One or more functional processing units that perform multiple functions for data processing; and An operandless instruction system-based computer characterized by including a stack register that separates instruction processing by the instruction processing unit and data processing by the function processing unit.

14. In paragraph 13, the instruction processing unit is, A program counter that stores the memory address of the currently executing instruction, controls the flow of the program, specifies the address of the next instruction to be executed, and increments the program counter value whenever an instruction is executed to point to the next instruction; An instruction loader that reads instructions from the above instruction memory; An instruction queue that stores instructions loaded by the instruction loader, supports continuous instruction processing, and enables rapid access to instructions when needed; and An operandless instruction system-based computer characterized by including an instruction processor connected to the program counter, the instruction queue, and the function processing unit, respectively.

15. An operandless instruction system-based computer according to claim 14, wherein the program counter increments the counter according to the contents of the instruction queue to track the address of the next instruction.

16. An operandless instruction system-based computer according to claim 14, wherein the instruction queue is operated in byte units and stores the instruction by including only 1 byte when the instruction has no operand, and 3 to 4 bytes when the instruction has an operand.

17. In paragraph 14, the above instruction processor, An instruction fetcher that reads instructions from the above instruction queue and provides them to the above function processing unit; An instruction decomposer that interprets instructions and converts them into an executable form; and An operandless instruction system-based computer characterized by including a function selector that operates a function module within the above-mentioned function processing unit.

18. In Paragraph 13, the above-mentioned function processing unit is, A first function processing module corresponding to an arithmetic logic unit (ALU) having an operation function; and An operandless instruction system-based computer characterized by including a second function processing module corresponding to a control device having a control function.

19. In paragraph 18, the stack register is, An ALU register accessed by the first function processing module; and An operandless instruction system-based computer characterized by including an FPU stack accessed by a stacker of the second function processing module.

20. In paragraph 19, the above FPU stack is, The register stack accessed by the stacker; and An operandless instruction system-based computer characterized by including an operation-only register operated by an ALU.

Images