Upgrading method, device and equipment and computer readable storage medium

Abstract

The invention discloses an upgrading method, device and equipment and a computer readable storage medium, which are applied to the technical field of computers, and comprise the following steps: when a logic device mirror image is received, storing the logic device mirror image, and selecting a target processor core from a management controller with at least two or more processor cores; the storage address of the logic device mirror image is sent to a target processor core through inter-core communication, a cache disabling mechanism is started for memory areas corresponding to the target processor core and the logic device mirror image, and the upgrade task is configured to be the highest execution priority and set to be scheduling prohibition; and reading the logic device mirror image through the storage address by utilizing the target processor core, and burning the logic device mirror image to the logic device by simulating a JTAG protocol through GPIO (General Purpose Input / Output) to finish an upgrading task. According to the invention, the core pain point of high failure rate of simulation of JTAG upgrade by GPIO in the prior art is solved, and stable and efficient upgrade of the logic device mirror image is realized.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to an upgrade method, apparatus, device, and computer-readable storage medium. Background Technology

[0002] In server maintenance, logic device image upgrades need to be implemented through the management controller chip. There are two main methods: one is that the management controller uses GPIO (General-Purpose Input / Output) to simulate the JTAG (Joint Test Action Group, a standardized testing method for testing inter-chip interconnections on a circuit board) protocol to burn the image and trigger a system restart; the other is that the management controller uses its built-in JTAG-MASTER hardware module to complete the burning and restart. However, both methods have drawbacks: the GPIO simulation method is easily interrupted by other services, leading to discontinuous JTAG timing or even upgrade failure; the JTAG-MASTER hardware module, due to its fixed design, cannot fully adapt to the JTAG-SLAVE (JTAG slave device) of all logic device models, resulting in insufficient compatibility.

[0003] Therefore, how to balance the timing stability of logic device upgrades with the compatibility of multiple logic device models is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide an upgrade method, apparatus, device and computer-readable storage medium, which solves the problem that logic device upgrades in the prior art cannot simultaneously meet timing stability and compatibility requirements.

[0005] To address the aforementioned technical problems, this invention provides an upgrade method applied to a management controller having at least two or more processor cores, comprising: When a logic device image is received, the logic device image is stored, and a target processor core is selected from the management controller; The storage address of the logic device image is sent to the target processor core via inter-core communication, and a cache disabling mechanism is enabled for the memory region corresponding to the target processor core and the logic device image. At the same time, the upgrade task is configured with the highest execution priority and set to be disabled for scheduling. Using the target processor core, the logic device image is read through the storage address, and the logic device image is burned to the logic device through the Generalized Input / Output Simulation Joint Test Action Group Protocol to complete the upgrade task.

[0006] On the one hand, upon receiving a logic device image, the logic device image is stored, and a target processor core is selected from the management controller, including: The logic device image is received through in-band and out-of-band upgrade methods. When a complete logic device image is received, the complete logic device image is stored in a non-volatile memory medium. From the management controller having at least two or more processor cores, select one processor core as the target processor core.

[0007] On the one hand, after storing the logic device image upon receiving it and selecting the target processor core from the management controller, the method further includes: The image of the real-time operating system is migrated from non-volatile memory media to memory, and the memory attributes are marked as read-only. Using the target processor core, perform integrity verification on the image of the real-time operating system in the memory; If the verification passes, the target processor core executes the code of the real-time operating system, and the target processor core enters the real-time operating system running mode.

[0008] On the one hand, the storage address of the logic device image is sent to the target processor core via inter-core communication, and a cache disabling mechanism is enabled for the memory region corresponding to the target processor core and the logic device image. Simultaneously, the upgrade task is configured with the highest execution priority and set to be disabled for scheduling, including: Once the real-time operating system of the target processor core is running normally, the main processor core sends the storage address of the logic device mirrored in the non-volatile memory medium to the target processor core via inter-core communication; the main processor core can be any processor core other than the target processor core. When the target processor core receives the storage address, it marks the memory area corresponding to the target processor core and the logic device image as an uncached area, configures the upgrade task of the logic device as the highest execution priority and sets it to be disabled for scheduling.

[0009] On the one hand, after using the target processor core to read the logic device image through the memory address, and burning the logic device image to the logic device through the Joint Test Action Group Protocol (JTP) to complete the upgrade task, the process also includes: The target processor core sends upgrade progress information to the main processor core via inter-core communication, so that the main processor core can display the progress information.

[0010] On the one hand, after using the target processor core to read the logic device image through the memory address, and burning the logic device image to the logic device through the Joint Test Action Group Protocol (JTP) to complete the upgrade task, the process also includes: The real-time operating system of the target processor core is terminated, and the target processor core is added to the scheduling of the main processor core.

[0011] On the one hand, it also includes: All processor cores of the management controller have equal control over general-purpose input / output pins.

[0012] The present invention also provides an upgrade device for a management controller having at least two or more processor cores, comprising: The core determination module is used to store the logic device image when it receives the logic device image and select the target processor core from the management controller; The configuration module is used to send the storage address of the logic device image to the target processor core through inter-core communication, enable the cache disabling mechanism for the target processor core and the memory area corresponding to the logic device image, and configure the upgrade task to the highest execution priority and set it to be disabled for scheduling. The upgrade module is used to read the logic device image through the storage address using the target processor core, and burn the logic device image to the logic device through the General Input / Output Simulation Joint Test Action Group Protocol to complete the upgrade task.

[0013] The present invention also provides an upgrade device, comprising: Memory, used to store computer programs; A processor for implementing the upgrade method as described above when executing the computer program.

[0014] The present invention also provides a computer-readable storage medium storing computer-executable instructions, which, when loaded and executed by a processor, implement the upgrade method described above.

[0015] The present invention also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the upgrade method described above.

[0016] As can be seen from the above technical solution, the present invention, upon receiving a logic device image, stores the logic device image and selects a target processor core from the management controller; sends the storage address of the logic device image to the target processor core via inter-core communication, enables a cache disabling mechanism for the memory regions corresponding to the target processor core and the logic device image, and configures the upgrade task with the highest execution priority and sets it to be disabled for scheduling; using the target processor core, the logic device image is read through the storage address, and the logic device image is burned to the logic device through the Generalized Input / Output Simulation Joint Test Action Group Protocol, thus completing the upgrade task.

[0017] The beneficial effects of this invention are as follows: Through hardware-level core isolation, resource contention between upgrade tasks and the management controller's regular operations is fundamentally avoided. Combined with dedicated configurations for cache disabling and task scheduling, uncontrollable timing delays caused by processor caching are completely eliminated, preventing interruptions in the upgrade process and timing errors during burning. This effectively solves the core pain point of high failure rates in existing technologies for GPIO-simulated JTAG upgrades. Furthermore, firmware upgrades are implemented through a dedicated processor core, ensuring that the upgrade process does not occupy other core resources of the management controller and does not affect the normal operation of its regular services, achieving stable and efficient upgrades of logic device images. Based on a general multi-core management controller hardware architecture and standard GPIO and JTAG protocols, no customized modifications to the underlying hardware and communication protocols are required. It possesses excellent hardware and protocol compatibility and can adapt to different models of multi-core management controllers and conventional logic devices, demonstrating strong adaptability.

[0018] In addition, the present invention also provides an upgrade device, apparatus, and computer-readable storage medium, which also have the above-mentioned beneficial effects. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0020] Figure 1 A flowchart of an upgrade method provided in an embodiment of the present invention; Figure 2 An example architecture diagram provided for an embodiment of the present invention; Figure 3 A flowchart illustrating an upgrade method provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of an upgrade device provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of an upgrade device provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] The management controller is a control unit used to manage server hardware. It has its own complete and independent operating system. The management controller does not rely on any resources on the host side to operate. When the server is powered on, the logic devices distribute power to the motherboard. The management controller is powered on unconditionally. Once the management controller is powered on normally, it starts running. The management controller begins to monitor and control the status of some hardware resources on the server, and handles and reports abnormal statuses. However, as the server runs, it may be necessary to upgrade the logic code of the logic devices. In the server, the upgrade of the logic devices is performed through the management controller. The management controller uses GPIO pins to simulate JTAG timing and transfers the upgrade file to the logic devices, thereby completing the firmware upgrade of the logic devices.

[0023] The general method for upgrading current logic devices is as follows: (1) The management controller will use GPIO to simulate the JTAG protocol, burn the image file of the logic device to be upgraded to the logic device, and then trigger the restart of the entire system; (2) The management controller will use its own JTAG-MASTER module to burn the image file of the logic device to be upgraded to the logic device, and then trigger the restart of the entire system. Although the above upgrade method is feasible, it has many limitations. For example, when using GPIO simulation, the current upgrade process is easily interrupted by other services during the upgrade process, and the location and duration of the interruption are uncertain, resulting in discontinuous timing during the upgrade, which is intermittent. If a long interruption occurs, it will lead to the upgrade failure. The disadvantage of using the sub-band JTAG-MASTER module method is that the hardware JTAG-MASTER module cannot be fully compatible with the JTAG-SLAVE of all logic devices.

[0024] Therefore, this invention provides an upgrade method that can solve both compatibility issues and the timing discontinuity problems caused by using GPIO emulation. Please refer to [link / reference needed] for details. Figure 1 , Figure 1A flowchart illustrating an upgrade method provided in an embodiment of the present invention. The method may include: S101: When a logic device image is received, the logic device image is stored, and the target processor core is selected from the management controller.

[0025] In this embodiment, the execution entity is a management controller, which has at least two or more processor cores. (Refer to...) Figure 2 , Figure 2 This is an example architecture diagram provided for an embodiment of the present invention. In this embodiment, the management controller has two or more processor cores, which essentially performs hardware-level task isolation / high-priority scheduling to solve the problem of the upgrade process being interrupted by other services when GPIO simulates JTAG.

[0026] In this embodiment, the management controller can be a server operation and maintenance management controller or a BMC (Baseboard Management Controller). A BMC is an independent control module in a server responsible for hardware monitoring and management. It is typically embedded on the server motherboard and is an important component of the server management system. The logic device in this embodiment can be a programmable logic device or a CPLD (Complex Programmable Logic Device). A CPLD is a programmable integrated circuit capable of implementing various digital logic functions and is widely used in digital system design, communication, computers, industrial control, and many other fields. The core in this embodiment refers to the processor core, or it can be a CPU (Central Processing Unit) core. A CPU core is a unit in a computer's central processing unit that can execute program instructions. Specifically, when the BMC receives a CPLD image file, it stores the image file and then selects a dedicated CPU core from multiple CPU cores as the target processor core. In this embodiment, the BMC can have a single operating system or a dual operating system, and the CPU cores within the BMC can dynamically switch between operating systems.

[0027] Furthermore, all processor cores of the aforementioned management controller have equal control over the general purpose input / output (GPIO) pins. This means that the software architecture ensures that the control over the GPIO pins of the management controller is equal across all processor cores, allowing them to pull the GPIO pins high or low at any time.

[0028] S102: Send the storage address of the logic device image to the target processor core through inter-core communication, enable the cache disabling mechanism for the memory area corresponding to the target processor core and the logic device image, and configure the upgrade task to the highest execution priority and set it to be disabled for scheduling.

[0029] In this step, the inter-core communication mechanism within the management controller is first used to accurately transmit the memory address of the logic device image to be burned to the designated target processor core, providing a clear address basis for subsequent image reading. Then, the target processor core autonomously completes two key configurations: first, it enables a cache disabling mechanism for its own hardware cache and the memory region corresponding to the logic device image to eliminate uncontrollable timing delays caused by caching; second, it configures the logic device upgrade task as the highest execution priority in the system and sets it to a disabled scheduling state, ensuring that the upgrade task exclusively occupies the computing resources of the target processor core and avoids being preempted or interrupted by other tasks. From both hardware configuration and task scheduling perspectives, the timing stability and execution exclusivity of the upgrade process are guaranteed, laying the foundation for the accurate execution of subsequent image burning.

[0030] S103: Utilizes the target processor core, reads the logic device image through the storage address, and burns the logic device image to the logic device through the Generalized Input / Output Simulation Joint Test Action Group Protocol to complete the upgrade task.

[0031] In this step, a dedicated target processor core accurately reads the logic device image data from the corresponding memory region based on the received memory address. Then, this core simulates the Joint Test Action Group Protocol (JTAG protocol) via a general-purpose input / output interface (GPIO) to program the read logic device image data into the logic device to be upgraded. The entire process relies on the dedicated execution environment configured for the target processor core beforehand, ensuring precise timing and freedom from external task interference during the programming process, ultimately successfully completing the logic device image upgrade task. Using GPIO to simulate the JTAG protocol makes the code more universal, facilitates portability across different chip platforms, and ensures compatibility with multiple types of logic devices.

[0032] Furthermore, when the logic device image is received, storing the logic device image and selecting the target processor core from the management controller can specifically include: Step 11: Receive the logic device image through in-band and out-of-band upgrade methods. When a complete logic device image is received, store the complete logic device image in non-volatile memory medium. Specifically, before the formal upgrade, users can send the image of the logic device to be upgraded to the management controller via in-band or out-of-band upgrade methods. Once the management controller receives the complete logic device image, it will first store the image in non-volatile memory media (such as NOR flash, eMMC, etc.) to avoid data loss due to power failure caused by storing the image in volatile memory (such as SRAM, Static Random Access Memory), while ensuring the management controller can quickly access and read it. Out-of-band communication (such as the management controller's dedicated management network port, IPMI, or Intelligent Platform Management Interface) is independent communication without going through the server's main system. In-band communication (such as server PCIe, Serial Component Interconnect Express, or SATA) is forwarded through the main system, or it can be communication via network, USB, etc.

[0033] Step 12: Select one processor core as the target processor core from management controllers with at least two or more processor cores.

[0034] This embodiment does not limit the selection of the target processor core. Any core can be randomly selected. For example, the core with the largest number other than the main core (CPU0) in the management controller (such as dual-core CPU1 or quad-core CPU3) can be used as the target processor core. If the target processor core has a different operating system than the other cores, i.e., the management controller has a dual operating system, then before the upgrade begins, all cores of the management controller (including the main core and secondary cores) will run the Linux operating system, handling the management controller's routine business (e.g., server monitoring, fan speed control, network communication, etc.). At this time, core isolation has not yet been implemented, and it is the management controller's normal operating state. This utilizes the versatility of Linux to complete the basic preparations for image reception and multi-core scheduling without changing the original operating mode of the management controller. During the upgrade process, the currently running Linux operating system is taken offline, reducing the number of processors running the Linux operating system by one. The Linux operating system will no longer schedule this core, and its hardware resources (computation, bus, GPIO control) are completely released for subsequent upgrades. This achieves hardware-level task isolation, preventing Linux's regular business operations from preempting the upgrade kernel's resources and fundamentally solving the problem of the upgrade process being interrupted.

[0035] Furthermore, after storing the logic device image upon receipt and selecting the target processor core from the management controller, the above-mentioned steps may further include: Step 21: Migrate the image of the real-time operating system from the non-volatile memory medium to memory and mark the memory attributes as read-only.

[0036] In this step, the memory attribute is marked as read-only to prevent the RTOS (Real-Time Operating System) image from being tampered with or overwritten by the Linux system or other processes during subsequent operation, thus ensuring the integrity of the image. In this embodiment, the target processor core runs an RTOS system. RTOS is a hard real-time operating system, and its core goal is to ensure that tasks are completed within strict time constraints, that is, to make timely and predictable responses to external events. Compared with Linux (non-real-time, with process scheduling delays), RTOS has precise and controllable task execution time and no scheduling delays, which can perfectly match the stringent timing requirements of the JTAG protocol. This is also the key to solving the problem of unstable upgrade timing. This step builds an independent and secure memory environment for the secondary core (i.e., the target processor core) to run the RTOS, ensuring the integrity of the RTOS image.

[0037] Step 22: Use the target processor core to perform an integrity check on the image of the real-time operating system in memory.

[0038] In this step, the target processor core verifies the integrity of the memory image of the region storing the RTOS operating system (e.g., checksum, CRC) to prevent damage during image transfer / loading.

[0039] Step 23: If the verification passes, the target processor core executes the real-time operating system code, and the target processor core enters the real-time operating system running mode.

[0040] In this step, once the verification is successful, the target processor core begins executing the RTOS image's code and officially enters the RTOS running mode. At this point, the target processor core is completely taken over by the RTOS and has no scheduling overlap with the Linux operating system of other processor cores.

[0041] Furthermore, the aforementioned method sends the storage address of the logic device image to the target processor core via inter-core communication, enables a cache disabling mechanism for the memory regions corresponding to the target processor core and the logic device image, and configures the upgrade task with the highest execution priority and disables scheduling. Specifically, this may include: Step 31: After the real-time operating system of the target processor core is running normally, the main processor core sends the storage address of the logic device mirrored in the non-volatile memory medium to the target processor core through inter-core communication. The main processor core can be any processor core other than the target processor core.

[0042] In this step, after the real-time operating system on the target processor core has completed its normal startup, the main processor core in the management controller, excluding the target processor core, uses the inter-core communication method of the multi-core architecture to accurately transmit the storage address corresponding to the logic device image pre-stored in the non-volatile memory medium to the target processor core. This provides the target processor core with the key address location basis for subsequent reading of image data and execution of upgrade operations. At the same time, the main processor core can be any processor core other than the target processor core, adapting to the flexible deployment requirements of the multi-core architecture.

[0043] Step 32: After the target processor core receives the storage address, mark the memory area corresponding to the target processor core and the logic device image as an uncached area, configure the logic device upgrade task as the highest execution priority and set it to be disabled for scheduling.

[0044] In this step, after the target processor core receives the image storage address, it first marks the memory area corresponding to its own hardware and logic device image as non-cacheable, completely avoiding random timing delays caused by caching. At the same time, it configures the logic device upgrade task as the highest execution priority of the system and sets it to be disabled for scheduling. This ensures relatively stable timing because the code execution time is precisely controllable, ensuring that the core exclusively executes the upgrade operation. Timing guarantees for the upgrade process are provided from both hardware configuration and task scheduling perspectives, laying the foundation for accurate flashing in the future.

[0045] Furthermore, after utilizing the target processor core to read the logic device image through the storage address and burning the logic device image to the logic device via the Generalized Input / Output Synchronization Joint Test Action Group Protocol (GIP) to complete the upgrade task, the upgrade can further include: using inter-core communication, the target processor core sends the upgrade progress information to the main processor core, allowing the main processor core to display the progress information. In this embodiment, relying on the inter-core communication mechanism of the multi-core architecture, the target processor core performing the upgrade operation sends the real-time upgrade progress information of the logic device image back to the main processor core, which then displays this progress information externally, achieving visualized monitoring of the upgrade process and allowing users to intuitively grasp the upgrade progress status.

[0046] Furthermore, after utilizing the target processor core, reading the logic device image through the memory address, and burning the logic device image to the logic device via the Joint Test Action Group Protocol (JATP) to complete the upgrade task, the upgrade may further include: terminating the real-time operating system (RTOS) of the target processor core and adding the target processor core to the main processor core's scheduler. For example, after the upgrade is complete, the RTOS of the target processor core will terminate, and the target processor core will jump back to the Linux operating system's scheduler, increasing the number of processor cores running Linux by one.

[0047] Furthermore, it can also include: during the logic device image burning process, the target processor core monitors the communication link status of the Generalized Input / Output Simulation Joint Test Action Group protocol and the integrity of the burned data in real time. If an anomaly is detected, the burning process is immediately terminated, and an anomaly alarm message is sent to the main processor core via inter-core communication. Upon receiving the alarm message, the main processor core displays the anomaly and triggers a retry mechanism for image burning. This further enhances the automation and fault tolerance of logic device image upgrades. By monitoring the protocol link and data integrity in real time, various anomalies during the burning process can be quickly identified and the operation terminated in a timely manner, preventing damage to the logic device caused by continued burning due to anomalies. At the same time, the automatic triggering of the retry mechanism reduces the cost of manual intervention and significantly improves the success rate of upgrades under complex operating conditions. In addition, the anomaly alarm message is displayed externally through the main processor core, allowing users to quickly locate the cause of the anomaly, further improving the convenience and reliability of the upgrade operation and making the entire upgrade solution more adaptable to the actual application needs of industrial sites.

[0048] The upgrade method provided in this embodiment of the invention proceeds as follows: S101: When a logic device image is received, the logic device image is stored, and a target processor core is selected from the management controller; S102: The storage address of the logic device image is sent to the target processor core via inter-core communication, and a cache disabling mechanism is enabled for the memory regions corresponding to the target processor core and the logic device image. Simultaneously, the upgrade task is configured with the highest execution priority and is set to be disabled for scheduling; S103: Using the target processor core, the logic device image is read through the storage address, and the logic device image is burned to the logic device via the Generalized Input / Output Simulation Joint Test Action Group Protocol, thus completing the upgrade task. This method, through hardware-level core isolation, fundamentally avoids resource contention between upgrade tasks and the management controller's regular operations. Combined with dedicated configurations for cache disabling and task scheduling, it completely eliminates uncontrollable timing delays caused by processor caching, preventing upgrade process interruptions and burning timing errors. It effectively solves the core pain point of high failure rates in existing GPIO-simulated JTAG upgrades. Furthermore, by implementing firmware upgrades through a dedicated processor core, the upgrade process does not consume other core resources of the management controller and does not affect the normal operation of its regular services, achieving stable and efficient upgrades of logic device images. Based on a general multi-core management controller hardware architecture and standard GPIO and JTAG protocols, it requires no customized modifications to the underlying hardware and communication protocols, possesses excellent hardware and protocol compatibility, and can adapt to different models of multi-core management controllers and conventional logic devices, demonstrating strong adaptability. Furthermore, the target processor's core Linux services operate normally during the upgrade process, and the secondary core seamlessly reverts to Linux after the upgrade, with no loss of overall BMC functionality, balancing upgrade stability and business continuity. Moreover, inter-core communication enables information synchronization between Linux and the RTOS, allowing users to view the upgrade progress in real time and improving the user experience. Furthermore, the use of the RTOS instead of Linux as the runtime environment for the upgrade task, combined with a non-cached, highest-priority, and non-schedulable environment configuration, ensures precise and controllable timing of GPIO simulating JTAG with zero latency. Finally, leveraging the BMC's multi-core hardware foundation, dual-system core operation of Linux (main core, regular business) and RTOS (secondary core, upgrade task) is achieved, with hardware-level isolation fundamentally resolving resource contention issues.

[0049] For a clearer understanding of this invention, please refer to the following details. Figure 3 , Figure 3 A flowchart illustrating an upgrade method provided in an embodiment of the present invention may specifically include: The BMC's main core (running a Linux system) receives CPLD upgrade image files from in-band or out-of-band sources and stores them in non-volatile memory. A target core is selected from the BMC's multi-core CPUs and removed from the Linux system's scheduling list (offline), completely isolating it from the main system's workload and preventing the upgrade task from competing for resources with other services. A Real-Time Operating System (RTOS) is started on the offline target core, leveraging its hard real-time characteristics to provide a precise and controllable execution environment for subsequent CPLD upgrades. In the RTOS environment, its own cache and the cache of the image memory region are disabled, the upgrade task is set to the highest priority and its scheduling is locked, and then the image is read and burned into the CPLD chip via a Generalized Input / Output Simulation Joint Test Action Group Protocol. After the upgrade is complete, the target core exits the RTOS and reconnects to the Linux system, restoring its scheduling in the main system and returning the entire BMC multi-core architecture to its initial operational state.

[0050] The upgrade device provided in the embodiments of the present invention will be described below. The upgrade device described below and the upgrade method described above can be referred to in correspondence.

[0051] Please refer to the details. Figure 4 , Figure 4 A schematic diagram of an upgrade device provided in an embodiment of the present invention may include: The core determination module 100 is used to store the logic device image when it receives the logic device image and select the target processor core from the management controller; the management controller has at least two or more processor cores. The configuration module 200 is used to send the storage address of the logic device image to the target processor core through inter-core communication, enable the cache disabling mechanism for the target processor core and the memory area corresponding to the logic device image, and configure the upgrade task to the highest execution priority and set it to be disabled for scheduling. Upgrade module 300 is used to read the logic device image through the storage address using the target processor core, and burn the logic device image to the logic device through the Generalized Input / Output Simulation Joint Test Action Group Protocol to complete the upgrade task.

[0052] Based on the above embodiments, the core determination module 100 may include: The storage unit is used to receive the logic device image through in-band and out-of-band upgrade methods, and when a complete logic device image is received, to store the complete logic device image in a non-volatile memory medium. The selection unit is used to select one processor core as the target processor core from the management controller consisting of at least two or more processor cores.

[0053] Based on the above embodiments, the upgrading device may further include: The migration module is used to store the logic device image when it is received, and after selecting the target processor core from the management controller, migrate the image of the real-time operating system from the non-volatile memory medium to the memory and mark the memory attribute as read-only. The verification module is used to perform integrity verification on the image of the real-time operating system in the memory using the target processor core; The execution module is used to execute the code of the real-time operating system using the target processor core if the verification passes, and the target processor core enters the real-time operating system running mode.

[0054] Based on the above embodiments, the configuration module 200 may include: The sending unit is used to send the storage address of the logic device mirrored in the non-volatile memory medium to the target processor core through inter-core communication using the main processor core after the real-time operating system of the target processor core is running normally; the main processor core is any processor core other than the target processor core. The marking unit is used to mark the memory area corresponding to the target processor core and the logic device image as an uncached area after the target processor core receives the storage address, and to configure the upgrade task of the logic device as the highest execution priority and set it to be disabled for scheduling.

[0055] Based on the above embodiments, the upgrading device may further include: The display module is used to read the logic device image through the storage address using the target processor core, and burn the logic device image to the logic device through the Generalized Input / Output Simulation Joint Test Action Group Protocol. After completing the upgrade task, the target processor core sends the upgrade progress information to the main processor core through inter-core communication, so that the main processor core can display the progress information.

[0056] Based on the above embodiments, the upgrading device may further include: The module is used to read the logic device image through the storage address using the target processor core, burn the logic device image to the logic device through the General Input / Output Simulation Joint Test Action Group Protocol, complete the upgrade task, terminate the real-time operating system of the target processor core, and add the target processor core to the scheduling of the main processor core.

[0057] Based on the above embodiments, the upgrade device may further include: all processor cores of the management controller having equal control authority over general-purpose input / output pins.

[0058] It should be noted that the order of the modules and units in the aforementioned upgrade device can be changed without affecting the logic.

[0059] The upgrade device provided in this embodiment of the invention includes a core determination module 100, which, upon receiving a logic device image, stores the image and selects a target processor core from the management controller; the management controller has at least two or more processor cores; a configuration module 200, which sends the storage address of the logic device image to the target processor core via inter-core communication, enables a cache disabling mechanism for the memory region corresponding to the target processor core and the logic device image, and configures the upgrade task with the highest execution priority and sets it to be disabled for scheduling; and an upgrade module 300, which uses the target processor core to read the logic device image through the storage address and burns the logic device image to the logic device via the Generalized Input / Output Simulation Joint Test Action Group Protocol (GIP), thus completing the upgrade task. This device, through hardware-level core isolation, fundamentally avoids resource contention between upgrade tasks and the management controller's regular operations. Combined with dedicated configurations for cache disabling and task scheduling, it completely eliminates uncontrollable timing delays caused by processor caching, preventing upgrade process interruptions and programming timing errors. This effectively solves the core pain point of high failure rates in existing GPIO-simulated JTAG upgrades. Furthermore, firmware upgrades are implemented through a dedicated processor core, ensuring that the upgrade process does not consume other core resources of the management controller and does not affect the normal operation of its regular services, achieving stable and efficient upgrades of logic device images. Based on a general multi-core management controller hardware architecture and standard GPIO and JTAG protocols, no customized modifications to the underlying hardware and communication protocols are required. It possesses excellent hardware and protocol compatibility, adaptable to different models of multi-core management controllers and conventional logic devices, demonstrating strong adaptability.

[0060] Figure 5 This is a schematic diagram of the structure of an upgrade device provided in an embodiment of the present invention, such as... Figure 5 As shown, the upgrade equipment includes: Memory 60 is used to store computer programs; The processor 61 is used to implement the steps of the upgrade method as described in the above embodiments when executing a computer program.

[0061] The upgrade device provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.

[0062] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 61 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0063] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 60 is used to store at least the following computer program 601, which, after being loaded and executed by the processor 61, is capable of implementing the relevant steps of the upgrade method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, and the storage method may be temporary storage or permanent storage. The operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, data related to the upgrade method.

[0064] In some embodiments, the upgrade device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.

[0065] Those skilled in the art will understand that Figure 5 The structure shown does not constitute a limitation on the upgrade device and may include more or fewer components than illustrated.

[0066] It is understood that if the upgrade method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.

[0067] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the upgrade method described above.

[0068] The following describes a computer program product provided by an embodiment of this application. The computer program product described below can be referred to in conjunction with other embodiments described herein.

[0069] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the aforementioned disclosed upgrade method.

[0070] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0071] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0072] Finally, it should be noted that in this document, relationships such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0073] The above provides a detailed description of an upgraded method, apparatus, device, and computer-readable storage medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An upgrade method, characterized in that, Management controllers applied to devices with at least two or more processor cores, including: When a logic device image is received, the logic device image is stored, and a target processor core is selected from the management controller; The storage address of the logic device image is sent to the target processor core via inter-core communication, and a cache disabling mechanism is enabled for the memory region corresponding to the target processor core and the logic device image. At the same time, the upgrade task is configured with the highest execution priority and set to be disabled for scheduling. Using the target processor core, the logic device image is read through the storage address, and the logic device image is burned to the logic device through the Generalized Input / Output Simulation Joint Test Action Group Protocol to complete the upgrade task.

2. The upgrade method according to claim 1, characterized in that, Upon receiving a logic device image, the logic device image is stored, and a target processor core is selected from the management controller, including: The logic device image is received through in-band and out-of-band upgrade methods. When a complete logic device image is received, the complete logic device image is stored in a non-volatile memory medium. From the management controller having at least two or more processor cores, select one processor core as the target processor core.

3. The upgrade method according to claim 1, characterized in that, Upon receiving a logic device image, after storing the logic device image and selecting the target processor core from the management controller, the process further includes: The image of the real-time operating system is migrated from non-volatile memory media to memory, and the memory attributes are marked as read-only. Using the target processor core, perform integrity verification on the image of the real-time operating system in the memory; If the verification passes, the target processor core executes the code of the real-time operating system, and the target processor core enters the real-time operating system running mode.

4. The upgrade method according to claim 3, characterized in that, The storage address of the logic device image is sent to the target processor core via inter-core communication, and a cache disabling mechanism is enabled for the memory region corresponding to the target processor core and the logic device image. Simultaneously, the upgrade task is configured with the highest execution priority and is set to be disabled for scheduling, including: Once the real-time operating system of the target processor core is running normally, the main processor core sends the storage address of the logic device mirrored in the non-volatile memory medium to the target processor core via inter-core communication; the main processor core can be any processor core other than the target processor core. When the target processor core receives the storage address, it marks the memory area corresponding to the target processor core and the logic device image as an uncached area, configures the upgrade task of the logic device as the highest execution priority and sets it to be disabled for scheduling.

5. The upgrade method according to claim 4, characterized in that, After using the target processor core, reading the logic device image through the storage address, and burning the logic device image to the logic device via the Joint Test Action Group Protocol (JATP) using General Input / Output Simulation, the upgrade task is further included in: The target processor core sends upgrade progress information to the main processor core via inter-core communication, so that the main processor core can display the progress information.

6. The upgrade method according to claim 4, characterized in that, After using the target processor core, reading the logic device image through the storage address, and burning the logic device image to the logic device via the Joint Test Action Group Protocol (JATP) using General Input / Output Simulation, the upgrade task is further included in: The real-time operating system of the target processor core is terminated, and the target processor core is added to the scheduling of the main processor core.

7. The upgrade method according to claim 1, characterized in that, Also includes: All processor cores of the management controller have equal control over general-purpose input / output pins.

8. An upgrading device, characterized in that, Management controllers applied to devices with at least two or more processor cores, including: The core determination module is used to store the logic device image when it receives the logic device image and select the target processor core from the management controller; The configuration module is used to send the storage address of the logic device image to the target processor core through inter-core communication, enable the cache disabling mechanism for the target processor core and the memory area corresponding to the logic device image, and configure the upgrade task to the highest execution priority and set it to be disabled for scheduling. The upgrade module is used to read the logic device image through the storage address using the target processor core, and burn the logic device image to the logic device through the General Input / Output Simulation Joint Test Action Group Protocol to complete the upgrade task.

9. An upgrade device, characterized in that, include: Memory, used to store computer programs; A processor for implementing the upgrade method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when loaded and executed by a processor, implement the upgrade method as described in any one of claims 1 to 7.

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