Cross-chip access method and device, medium, program product and multi-chip system

Abstract

The invention discloses a cross-chip access method and device, a medium, a program product and a multi-chip system. The method is applied to a first chip, the first chip is any one of cascaded multi-stage chips, and the method comprises the following steps: receiving a first access instruction of a previous-stage chip, the first access instruction comprising a first address; querying a first mapping table, and converting the first address into a second address in a second address interval of the first chip in response to the fact that the first address is located in a first address interval of the upper-level chip; the first mapping table comprises a mapping relation between the first address interval and the second address interval; based on a second mapping table, converting the second address into a third address in a memory address interval of a next-level chip; the second mapping table comprises a mapping relation between the second address interval and the memory address interval; and sending a second access instruction to the next-level chip, wherein the second access instruction comprises the third address.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a cross-chip access method, apparatus, medium, program product, and multi-chip system. Background Technology

[0002] With the explosive growth in computing power demand, placing multiple chips on a single board has become the main means of improving system computing density. Currently, cascading interconnect based on high-speed buses is the infrastructure for realizing inter-chip communication.

[0003] However, due to the physical topology of cascaded interconnection, each chip can only access the memory of the downstream chips directly connected to it, and cannot access the memory of remote chips across chips, which will severely limit the efficiency of multi-chip collaboration. Summary of the Invention

[0004] The purpose of this application is to provide a cross-chip access method, apparatus, medium, program product, and multi-chip system that enables any level of chip to access the memory of a remote chip without introducing additional equipment, and has high scalability and compatibility.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions: In a first aspect, embodiments of this application provide a cross-chip access method applied to a first chip, wherein the first chip is any chip in a cascaded multi-level chip system, the method comprising: Receive a first access instruction from the previous level chip, wherein the first access instruction includes a first address; The first mapping table is queried. In response to the first address being located within the first address range of the upper-level chip, the first address is converted to a second address within the second address range of the first chip. The first mapping table includes the mapping relationship between the first address range and the second address range. Based on the second mapping table, the second address is converted into a third address within the memory address range of the next-level chip; the second mapping table includes the mapping relationship between the second address range and the memory address range; A second access instruction is sent to the next-level chip, the second access instruction including the third address.

[0006] Secondly, embodiments of this application provide a multi-chip system, including: Cascaded multi-stage chips; Any chip in the multi-level chip system accesses the downstream chip using the cross-chip access method provided in the first aspect.

[0007] Thirdly, embodiments of this application provide a cross-chip access device applied to a first chip, wherein the first chip is any one of a cascaded multi-level chip, the device comprising: The receiving module is used to receive a first access instruction from the previous stage chip, wherein the first access instruction includes a first address; The first mapping module is used to query the first mapping table and, in response to the first address being located within the first address range of the upper-level chip, convert the first address into a second address within the second address range of the first chip; the first mapping table includes the mapping relationship between the first address range and the second address range. The second mapping module is used to convert the second address into a third address within the memory address range of the next-level chip based on the second mapping table; the second mapping table includes the mapping relationship between the second address range and the memory address range. The sending module is used to send a second access instruction to the next-level chip, the second access instruction including the third address.

[0008] Fourthly, embodiments of this application provide a chip including a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the cross-chip access method provided in the first aspect.

[0009] Fifthly, embodiments of this application provide a computer-readable storage medium that, when instructions in the storage medium are executed by a chip's processor, enables the chip to perform the steps of the cross-chip access method provided in the first aspect.

[0010] In a sixth aspect, embodiments of this application provide a computer program product, the computer program product including a non-transitory computer-readable storage medium storing a computer program operable to cause a chip to perform steps of the cross-chip access method provided in the first aspect.

[0011] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects: For any chip in a cascaded multi-level chip system, a cross-chip mapping mechanism is established by configuring a first mapping table and a second mapping table within that chip. The first mapping table establishes a mapping relationship between the chip's second address range and the first address range of the preceding chip, while the second mapping table establishes a mapping relationship between the second address range and the memory address range of the following chip. Furthermore, when any chip needs to access the memory of a non-directly connected target chip, it simply sends an access command to its next-level chip, carrying its own address within its first address range. This address is then mapped to the target chip's memory address range via the aforementioned mapping mechanism. The access command is then automatically forwarded to the target chip through the cascaded downstream chips, thus enabling access to the target chip's memory.

[0012] The entire access process is transparent to the next-level chip above the first chip, requiring no modification to the hardware or bus protocol of that chip, thus ensuring good compatibility. Secondly, it avoids multiple software copies or additional chip forwarding between multiple chip levels, significantly reducing latency and improving bandwidth utilization, while also reducing hardware overhead and system complexity. Furthermore, this access method can be naturally extended to more chip levels by simply mapping the memory address spaces of each chip to the address spaces of the next-level chip, thus exhibiting high scalability. This not only overcomes limitations in access scope but also better meets the high-performance requirements of future multi-chip collaboration. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of an example environment in which embodiments of this application can be implemented; Figure 2 A schematic diagram of a cascaded multi-chip structure provided for one embodiment; Figure 3 A flowchart illustrating a cross-chip access method provided in one embodiment; Figure 4 A schematic diagram of a cross-chip access process provided for one embodiment; Figure 5 A schematic diagram of a cross-chip access device provided in one embodiment; Figure 6 This is a schematic diagram of the structure of a chip provided in one embodiment. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] The term "comprising" and its variations as used in this document are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description. The term "in response to" indicates that the performed operation depends on a condition or state. When the dependent condition or state is met, one or more operations may be performed in real time or with a set delay. Unless otherwise specified, there is no restriction on the order in which multiple operations are performed.

[0016] It should be noted that the concepts of "first" and "second" mentioned in this document are used only to distinguish different devices, modules or units, and are not used to restrict the order of functions performed by these devices, modules or units or their interdependencies.

[0017] It should be noted that the terms "one" and "more" used in this document are illustrative rather than restrictive, and those skilled in the art should understand that they should be understood as "one or more" unless explicitly stated in the context.

[0018] The names of messages or information exchanged between multiple devices in this document are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0019] As mentioned earlier, due to the physical topology of cascaded interconnection, any chip at level 1 can only access the memory of the downstream chips directly connected to it, and cannot directly access the memory of remote chips across chips, which will severely restrict the efficiency of multi-chip collaboration.

[0020] In existing multi-chip interconnect technologies, the mainstream solutions for achieving cross-chip memory access mainly include the following: Option 1: Software-based copy mechanism. The upstream chip directly accesses the memory of the adjacent chip via the bus, and then the chip copies the data to the next-level chip via inter-chip communication. The drawbacks of this approach are: long data access paths, multiple copies, resulting in high latency and low bandwidth utilization, while also increasing software management complexity and significantly increasing system power consumption.

[0021] Option 2: Address mapping mechanism based on external switching chips or relay devices. This approach utilizes dedicated switching chips or bridging chips, such as PCIe switches, as a central hub to map the memory of downstream chips to the address space visible to upstream chips. However, this solution incurs significant hardware overhead, increasing system complexity. Furthermore, the introduction of switching chips or relay devices can become a performance bottleneck (e.g., forwarding latency, high power consumption). In large-scale computing tasks (such as training large models), the scalability of this architecture is limited, failing to meet the high-performance requirements of future multi-chip collaboration.

[0022] Option 3: Direct interconnection mechanism based on multiple ports. This method directly connects upstream chips to other chips by configuring multiple bus ports, eliminating intermediate forwarding links. However, in practical applications, this solution is limited by physical channel resources (such as the number of bus channels and wiring space), making it difficult to achieve high-bandwidth access when integrating multiple chips on a single board, and its scalability is also limited.

[0023] Therefore, embodiments of this application provide a cross-chip access method. In a cascaded multi-level chip system, any chip obtains the memory address range of its directly connected next-level chip, divides a second address range within its own address space, and establishes a mapping relationship between the second address range and the memory address range. Furthermore, a mapping relationship is also established between the second address range and a first address range visible to the previous-level chip. This allows the previous-level chip to initiate memory access to the next-level chip using addresses within the first address range.

[0024] During operation, when any chip receives an access instruction from the previous-level chip, it converts the address in the instruction into a destination address within the memory address range of the next-level chip using the aforementioned two-level mapping relationship. Then, based on this destination address, it forwards the access instruction to the next-level chip, thus completing transparent access to the memory of the next-level chip. This process requires no additional software copying or the introduction of additional switching chips or relay devices, achieving efficient, low-latency, high-bandwidth utilization, and scalable cross-chip memory access, thus solving the bottleneck problems of existing technologies.

[0025] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0026] Figure 1 The diagram illustrates an example environment in which embodiments of this application can be implemented, the example environment including cascaded multi-stage chips, such as... Figure 1 Chips 1 to N are in the chip.

[0027] These chips can be mounted on the same board. They can be connected in various ways. For example, in some cases, the first-level chips and the second-level chips are connected via a bus, such as chip 1 and chip 2 connected via a PCIe (Peripheral Component Interconnect Express) bus; from the second-level chips onwards, adjacent chips are connected via a chip-to-chip (C2C) channel, that is, adjacent chips from chip 2 to chip N are connected via a C2C channel.

[0028] The aforementioned multi-level chip system can include various chips with data processing capabilities, working collaboratively to achieve large-scale computing power scheduling. For example, in a high-performance computing board designed for the field of artificial intelligence, the multi-level chip system can include a host and at least two levels of GPUs (Graphics Processing Units), which are cascaded on the same printed circuit board. Specifically, the connection relationship can be as follows: a communication link is established between the host and the first-level GPU via a system bus, and cascaded communication between GPUs at each level is achieved through a C2C high-speed interconnect channel. Figure 2 As shown, the multi-level chip includes a host, GPU1 and GPU2. The host and GPU1 are connected via a PCIe bus, and GPU1 and GPU2 are connected via a C2C channel.

[0029] However, in the existing physical topology, any chip at any level can only access the memory of adjacent downstream chips through direct links, and cannot directly access the memory of distant chips across chips, resulting in severely compromised multi-chip collaboration efficiency. For example... Figure 2 In the multi-stage chip architecture shown, the host typically needs to access the memory of the second-stage or more cascaded GPUs. However, since there is no physical direct connection between the host and the second-stage GPU, cross-stage access is blocked at the hardware level. Relying on the mainstream solutions mentioned above inevitably leads to problems such as access latency, low bandwidth utilization, excessive system power consumption, and poor scalability. Especially as the cascading depth increases, these performance bottlenecks will amplify exponentially, severely restricting the efficiency of multi-chip collaboration.

[0030] Based on the example environment described above, this application provides a cross-chip access method. Please refer to... Figure 3 This is a flowchart illustrating a cross-chip access method according to one embodiment. The method can be applied to a first chip, which is any chip in a cascaded multi-level chip system. The method may include the following steps: S302 receives the first access instruction from the previous stage chip. The first access instruction includes the first address.

[0031] The first access instruction includes a first address. The first access instruction instructs that an access operation be performed on the first address. The access operation here may include, but is not limited to, at least one of a read operation and a write operation.

[0032] For example, the first access instruction may include a read instruction, which instructs the execution of a read operation on the first address, such as reading target data from the first address. The first access instruction may also include a write instruction, which instructs the execution of a write operation on the first address, such as writing specified data to the first address.

[0033] In some cases, the first access instruction can be initiated by the upstream chip itself. For example, with Figure 2 Taking the multi-level chip as an example, the first chip is GPU1, the next-level chip is the host, and the next-level chip is GPU2. When the host needs to access the memory of GPU2, it can initiate an access instruction. For GPU1, this access instruction is the first access instruction.

[0034] In other cases, the second access instruction can also be obtained by the upper-level chip based on an access instruction initiated by another chip. For example, with Figure 1 Taking the example environment shown, the first chip is chip 3, the next-level chip is chip 2, and the next-level chip is chip 4. When chip 1 needs to access the memory of chip 4, it can send an access command to chip 2. This access command is then forwarded by chip 2 to chip 3. For chip 3, the access command forwarded by chip 2 is the first access command.

[0035] S304, query the first mapping table, and in response to the first address being located within the first address range of the previous level chip, convert the first address to a second address within the second address range of the first chip.

[0036] The first chip is configured with a first mapping table. The first mapping table may include the mapping relationship between a first address range and a second address range. In some embodiments, the first mapping table may be an inbound mapping table of the first chip, which may be configured by the bus controller (such as a PCIe controller) of the first chip.

[0037] The first address range can be understood as the free, visible, or accessible address range in the address space of the next-level chip; that is, the first address range is visible or accessible to other accesses. The second address range can be understood as the address range in the address space of the first chip that points to the memory of the next-level chip.

[0038] Each chip has its own independent address space. The size of the address space is determined by the chip's address bus width or internal addressing mechanism. A chip's address space refers to the local logical address domain within a single computing unit, managed by its memory controller or IOMMU (Input-Output Memory Management Unit). It is the complete set of all addressable resources encoded by the chip. These addressable resources can include, but are not limited to, memory, MMIO (Memory-Mapped Input / Output), registers, etc. Different addressable resources within the chip are mapped to different address ranges within this address space.

[0039] In some embodiments, the first address interval may include a first base address (e.g., 0xB000_0000) and a first address range (i.e., the size of the first address interval, e.g., 256MB). Correspondingly, the second address interval may include a second base address (e.g., 0x4000_0000) and a second address range (i.e., the size of the second address interval, e.g., 256MB). In this case, the first address range and the second address range may be equal, and the mapping relationship between the first address interval and the second address interval may include the mapping relationship between the first base address and the second base address. Further, the second address can be obtained by: calculating the offset of the first address relative to the first base address; offsetting this offset at the second base address to obtain the second address.

[0040] In other embodiments, the first address range may include a first base address and a first upper limit, and the second address range may include a second base address and a second upper limit. The first upper limit can be understood as the maximum address of the first address range, and the second upper limit can be understood as the maximum address of the second address range. In this case, the mapping relationship between the first address range and the second address range may include the mapping relationship between the first base address and the second base address. Further, the second address can be obtained by: calculating the offset of the first address relative to the first base address; determining the address range of the first address range based on the first base address and the first upper limit; determining the address range of the second address range based on the second base address and the second upper limit; determining the correspondence between the first address range and the second address range in terms of offset based on these two address ranges; and then offsetting at the second base address based on this offset and this correspondence to obtain the second address.

[0041] S306, based on the second mapping table, converts the second address into a third address within the memory address range of the next-level chip.

[0042] The second mapping table includes the mapping relationship between the second address range and the memory address range of the next-level chip. The memory address range can be understood as the address range of the memory of the next-level chip. The memory address range can include the physical address range of the memory. Of course, in some embodiments, the memory address range can also include the address range (i.e., the virtual address range) in the address space of the next-level chip that corresponds to the physical address range of the memory.

[0043] In some embodiments, the second address range may include a second base address (e.g., 0xB000_0000) and a second address range (i.e., the size of the second address range, e.g., 256MB). Correspondingly, the memory address range may include the base address of memory (e.g., 0x0000_0000) and the address range of memory (i.e., the size of the memory address range, e.g., 256MB). In this case, the second address range and the memory address range may be equal, and the mapping relationship between the second address range and the memory address range may include the mapping relationship between the second base address and the base address of memory. Further, the third address can be obtained by: calculating the offset of the second address relative to the second base address; and offsetting this offset from the base address of memory to obtain the third address.

[0044] In other embodiments, the second address range may include a second base address and a second upper limit, and the memory address range may include the base address and the upper limit of memory. The second upper limit can be understood as the maximum address of the second address range, and the upper limit of memory can be understood as the maximum address of the memory address range. In this case, the mapping relationship between the second address range and the memory address range may include the mapping relationship between the second base address and the base address of memory. Further, the third address can be obtained by: calculating the offset of the second address relative to the second base address; determining the address range of the second address range based on the second base address and the second upper limit; determining the address range of the memory address range based on the base address and the upper limit of memory; determining the correspondence between the second address range and the memory address range in terms of offset based on these two address ranges; and then offsetting at the base address of memory based on this offset and this correspondence to obtain the third address.

[0045] S308 sends a second access instruction to the next-level chip, which includes a third address.

[0046] The second access instruction instructs an access operation to be performed on a third address, which is the same access operation as that instructed by the first access instruction. In some embodiments, the first address in the first access instruction can be replaced with the third address.

[0047] Because the second access instruction includes a third address, the next-level chip, upon receiving the second access instruction, can execute the access operation indicated by the second access instruction on the third address and return the operation result to the first chip, which then returns it to the previous-level chip. This enables the next-level chip of the first chip to access the memory of the next-level chip. The entire access process is transparent to the next-level chip of the first chip, requiring no modification to its driver or bus protocol.

[0048] The cross-chip access method provided in the above embodiments, for any chip in a cascaded multi-level chip system, only requires configuring a first mapping table and a second mapping table in that chip. The first mapping table establishes a mapping relationship between the chip's second address range and the first address range of the preceding chip, and the second mapping table establishes a mapping relationship between the second address range and the memory address range of the following chip, thus establishing a cross-chip mapping mechanism. Furthermore, when any chip needs to access the memory of a non-directly connected target chip, it only needs to send an access instruction to its next-level chip, carrying its own address within its first address range. This address can then be mapped to the memory address range of the target chip through the aforementioned mapping mechanism. The access instruction is then automatically forwarded to the target chip through the cascaded downstream chips, realizing access to the target chip's memory.

[0049] The entire access process is transparent to the next-level chip above the first chip, requiring no modification to the hardware or bus protocol of that chip, thus ensuring good compatibility. Secondly, it avoids multiple software copies or additional chip forwarding between multiple chip levels, significantly reducing latency and improving bandwidth utilization, while also reducing hardware overhead and system complexity. Furthermore, this access method can be naturally extended to more chip levels by simply mapping the memory address spaces of each chip to the address spaces of the next-level chip, thus exhibiting high scalability. This not only overcomes limitations in access scope but also better meets the high-performance requirements of future multi-chip collaboration.

[0050] In some embodiments, the first mapping table may include an Inbound mapping table, and the second mapping table may include an Outbound mapping table.

[0051] In this embodiment of the application, the mapping relationship in the second mapping table can be obtained in various ways.

[0052] In some embodiments, the above method may further include: obtaining the memory address range of the next-level chip; dividing the address space of the first chip into an address range that matches the memory address range of the next-level chip, as a second address range; and establishing a mapping relationship between the memory address range and the second address range in a second mapping table.

[0053] The matching here can be understood as the address range of the divided address interval being equal to the address range of the memory address interval. For example, if the address range of the memory address interval is 256MB, then a 256MB address interval is divided from the address space of the first chip as the second address interval.

[0054] After power-on, the first chip can access the next-level chip through a connection channel (such as a C2C channel) to obtain the memory address space of the next-level chip.

[0055] In the above method, the first chip establishes a mapping relationship between the second address range and the memory address range of the next-level chip and writes it into the second mapping table, so that the first chip can access the memory of the next-level chip in its internal logic, just like accessing its own local memory.

[0056] In some cases, the memory management unit of the first chip can partition an address range within its address space that matches the memory address range of the next-level chip, serving as a second address range. Correspondingly, this memory management unit can establish a mapping relationship between this memory address range and the second address range in a second mapping table. The memory management unit here can include, but is not limited to, at least one of the following: IOMMU (Input / Output Memory Management Unit) or MMU (Memory Management Unit).

[0057] It is understandable that since the access instructions received by the first chip are usually executed by its computing core, dividing the second address range and establishing the mapping relationship through the memory management unit of the first chip can not only ensure low-latency, high-bandwidth data transmission, but also make the computing core completely unaware that the second address range points to the memory of the next level chip. That is, the second address range is the address range of local memory for the computing core. In this way, when the computing core executes the access instruction, it is as if it is accessing local memory.

[0058] In other embodiments, relevant personnel may pre-establish and write the second mapping table based on the architecture of the multi-level chip, the address space of each level chip, and the memory address range.

[0059] The foregoing illustrates a partial implementation of obtaining the mapping relationships in the second mapping table. It should be understood that these mapping relationships can also be obtained in other ways, and this application embodiment does not limit this.

[0060] In this embodiment of the application, the mapping relationship in the first mapping table can be obtained in various ways.

[0061] In some embodiments, the above method may further include: writing the second address range into the first register of the first chip; obtaining the first address range from the first register, wherein the first address range is partitioned from the address space of the previous chip and written into the first register after the previous chip reads the second address range from the first register; and establishing a mapping relationship between the first address range and the second address range in the first mapping table.

[0062] The first register may include registers accessible to the next-level chip. By writing the second address range into the first register of the first chip, the second address range is exposed to the next-level chip.

[0063] For example, the first register may include a BAR (Base Address Register). The upstream chip reads the first register to obtain the second address range. The upstream chip finds a free address range within its own address space's visible address range and writes it into the first register as the first address range. The first chip reads the first address range from the first register and binds the first address range to the second address range in a first mapping table (such as an inbound mapping table), thus establishing a mapping relationship between the two. Therefore, the internal hardware logic of the first chip establishes a rule: "All instructions that come in from the bus interface and whose addresses are located within the first address range are automatically converted into internal instructions within the second address range."

[0064] As can be seen, by establishing the mapping relationship between the first address range and the second address range in the first mapping table in the above manner, the upper-level chip does not need to be directly connected to the lower-level chip of the first chip. It can also enable the access instructions for the first address range to be automatically forwarded to the first chip, and then reach the lower-level chip of the first chip through the first chip, so as to realize the direct access of the memory of the lower-level chip by the upper-level chip.

[0065] In some embodiments, the first chip may also divide an address range from its own address space and provide it to the next-level chip so as to bind it to the second address space of the next-level chip.

[0066] Specifically, the above-mentioned cross-chip access method may further include: reading the third address range of the next-level chip from the second register of the next-level chip; dividing the address space of the first chip into a fourth address range that matches the third address range based on the third address range; and writing the fourth address range into the second register.

[0067] For example, the second register may include BAR.

[0068] The third address range is obtained by the next-level chip based on the memory address range of the connected downstream chips. The fourth address range is used to establish the mapping relationship between the third address range and the next-level chip. In other words, for the next-level chip, the third address range is the second address range, and the fourth address range is the first address range. For ease of understanding, the following will use... Figure 1 Taking the example environment shown, assuming the first chip is chip 2, chip 2 can read an address range pointing to the memory of chip 4 from the BAR of chip 3. This address range is the third address range for chip 2, but the second address range for chip 3. Chip 2 also partitions an address range from its own address space and writes it into the BAR of chip 3. Chip 3 then establishes a mapping relationship between this address range and the address range written into the BAR. At this point, the address range partitioned from chip 2 is the fourth address range for chip 2, but the first address range for chip 3.

[0069] Through the above embodiments, a multi-level mapping mechanism is formed between multiple chips, enabling any chip to access downstream chips that are not directly connected to it across chips.

[0070] In other embodiments, relevant personnel may pre-establish and write the first mapping table based on the architecture of the multi-level chip, the address space of each level chip, and the first address range.

[0071] The foregoing illustrates a partial implementation of obtaining the mapping relationships in the first mapping table. It should be understood that these mapping relationships can also be obtained in other ways, and this application embodiment does not limit this.

[0072] In some embodiments, the mapping relationships in the second mapping table are configured through the memory management unit of the first chip. Accordingly, S306 may include: querying the second mapping table through the memory management unit, converting the second address to a third address based on the mapping relationships in the second mapping table, and sending a second access instruction to the connection controller of the first chip; and sending the second access instruction to the next-level chip through the connection controller.

[0073] The connection controller manages the connection relationships between the first chip and other chips. For example, the connection controller may include, but is not limited to, a PCIe controller, a C2C module, etc.

[0074] As can be seen, in the above embodiments, the first access instruction is intercepted by the memory management unit, and when the first address is within the first address range, the first access instruction is automatically forwarded to the next level chip after address translation. This makes the computing core completely unaware that the first address points to the memory of the next level chip. In other words, the first address is the address range of the local memory for the computing core, so that the first chip can access the memory of the next level chip in its internal logic as if it were accessing its own local memory.

[0075] In some embodiments, the first mapping table may further include the mapping relationship between the fifth address range of the previous chip and the sixth address range of the first chip, and the second mapping table may further include the mapping relationship between the sixth address range and the memory address range of the first chip.

[0076] For example, the fifth address range can be understood as a free address range in the address space of the next higher-level chip. The sixth address range can be understood as a free address range in the address space of the first chip. The mapping relationship between the fifth and sixth address ranges is established in a similar way to the mapping relationship between the first and second address ranges described above, and will not be repeated here.

[0077] The memory address range of the first chip can be understood as the address space of the first chip's memory. This memory address range may include the physical address range of the memory. Of course, in some embodiments, the memory address range may also include the address range (i.e., the virtual address range) in the address space of the first chip that corresponds to the physical address range of the memory. The method for establishing the mapping relationship between the sixth address range and the memory address range of the first chip is similar to the method for establishing the mapping relationship between the second address range and the memory address range of the next-level chip described above, and will not be repeated here.

[0078] Optionally, in S204 above, after querying the first mapping table, the process may further include: in response to the first address being located within the fifth address range, converting the first address to a fourth address within the sixth address range; based on the second mapping table, converting the fourth address to a fifth address within the memory address range of the first chip; and accessing the memory of the first chip based on the fifth address. This enables upstream chips (including directly connected and non-directly connected upstream chips) to access the memory of the first chip.

[0079] The specific method for converting the first address to the fourth address is similar to the method for converting the first address to the second address described above, and will not be repeated here.

[0080] The method for converting the fourth address to the fifth address is similar to the method for converting the second address to the third address described above, and will not be repeated here.

[0081] To facilitate understanding of the cross-chip access method provided in the embodiments of this application, the following will use... Figure 2 Taking the multi-level chip shown as an example, combined with Figure 4 This cross-chip access method is described in detail.

[0082] like Figure 4 As shown, the host, CPU1, and CPU2 are arranged on the same board. The host and GPU1 are connected via a PCIe bus, and GPU1 and GPU2 are connected via a C2C channel. After the board is powered on, GPU1 directly reads the memory address range of GPU2 (such as the physical address range of GPU2's memory) through the C2C channel, and allocates a free address range from its own address space as a second address range. A mapping relationship is then established between the second address range and the memory address of GPU2 in a second mapping table. In this way, GPU1 can logically access the memory of GPU2 as if it were accessing local memory.

[0083] Furthermore, GPU1 writes the second address range into its own BAR (Browser Address Range) to expose it to the host. The host reads GPU1's BAR, obtains the second address range, and finds a free address range in its own address space, writing it into GPU1's BAR as the first address range. GPU1 reads the first address range from the BAR and establishes a mapping relationship between the first and second address ranges in a first mapping table.

[0084] During operation, when the host needs to access GPU2's memory, it sends a first access instruction to GPU1 via the PCIe bus. The first access instruction includes a first address, which is located within a first address range. GPU1's internal logic first converts the first address to a second address within a second address range according to a first mapping table, and then converts the second address to a third address within GPU2's memory address range according to a second mapping table. Furthermore, it modifies the first address in the first access instruction to the third address to obtain a second access instruction, and sends the second access instruction to GPU2 via the C2C module.

[0085] The C2C module of GPU2 receives the second access instruction, executes the second access instruction through internal logic, and returns the execution result through GPU1, which is then forwarded to the host via GPU1.

[0086] This enables the host to access GPU2 memory across chips.

[0087] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0088] This application also provides a multi-chip system, which includes: cascaded multi-level chips; any chip in the multi-level chips accesses downstream chips according to the cross-chip access method provided in this application.

[0089] The downstream chips here can include chips that are directly connected or not directly connected.

[0090] In some embodiments, the multi-level chip includes a host and at least two cascaded GPUs, with the host connected to the first of the at least two GPUs.

[0091] In some embodiments, the host and the first-level GPU are connected via a bus, and adjacent GPUs in the at least two levels are connected via an inter-chip interconnect channel.

[0092] This application also provides a cross-chip access device. Figure 5 A schematic diagram of a cross-chip access device 500 provided in one embodiment is shown. The device can be applied to a first chip, which can be any chip in a cascaded multi-level chip. The device may include: a receiving module 510, a first mapping module 520, a second mapping module 530, and a sending module 540.

[0093] The receiving module 510 is used to receive a first access instruction from the previous stage chip, the first access instruction including a first address.

[0094] The first mapping module 520 is used to query the first mapping table, and in response to the first address being located within the first address range of the upper-level chip, converts the first address into a second address within the second address range of the first chip; the first mapping table includes the mapping relationship between the first address range and the second address range.

[0095] The second mapping module 530 is used to convert the second address into a third address within the memory address range of the next-level chip based on the second mapping table; the second mapping table includes the mapping relationship between the second address range and the memory address range.

[0096] The sending module 540 is used to send a second access instruction to the next-level chip, the second access instruction including the third address.

[0097] In some embodiments, the cross-chip access device may further include: The first acquisition module is used to acquire the memory address range of the next-level chip; The first partitioning module is used to partition an address range in the address space of the first chip that matches the memory address range, and use it as the second address range; The first establishment module is used to establish a mapping relationship between the memory address range and the second address range in the second mapping table.

[0098] In some embodiments, the first partitioning module is used to: instruct the memory management unit of the first chip to partition an address range in the address space of the first chip that matches the memory address range; The first establishment module is used to: establish a mapping relationship between the memory address range and the second address range in the second mapping table through the memory management unit.

[0099] In some embodiments, the cross-chip access device may further include: The first write module is used to write the second address range into the first register of the first chip; The second acquisition module is used to acquire the first address range from the first register. The first address range is the address space of the upper-level chip that is partitioned from the address space of the upper-level chip and written into the first register after the upper-level chip reads the second address range from the first register. The second establishment module is used to establish a mapping relationship between the first address range and the second address range in the first mapping table.

[0100] In some embodiments, the cross-chip access device may further include: The third acquisition module is used to read the third address range of the next-level chip from the second register of the next-level chip. The third address range is obtained by the next-level chip based on the memory address range of the connected downstream chip. The second partitioning module is used to partition a fourth address interval from the address space of the first chip based on the third address interval, which matches the third address interval. The second write module is used to write the fourth address range into the second register, wherein the fourth address range is used to establish a mapping relationship with the third address range.

[0101] In some embodiments, the mapping relationships in the second mapping table are configured through the memory management unit of the first chip; The second mapping module is used for: The memory management unit queries the second mapping table and converts the second address into the third address based on the mapping relationship in the second mapping table; The sending module is used for: The memory management unit sends the second access instruction to the connection controller of the first chip. The second access command is sent to the next-level chip via the connection controller.

[0102] In some embodiments, the first mapping table further includes a mapping relationship between the fifth address range of the previous-level chip and the sixth address range of the first chip, and the second mapping table further includes a mapping relationship between the sixth address range and the memory address range of the first chip; The cross-chip access device may further include: The third conversion module is used to convert the first address into a fourth address within the sixth address range in response to the first address being located within the fifth address range. The fourth conversion module is used to convert the fourth address into a fifth address within the memory address range of the first chip based on the second mapping table. An access module is used to access the memory of the first chip based on the fifth address.

[0103] Obviously, the cross-chip access device 500 provided in this application embodiment can be used as described above. Figure 3 The execution entity of the cross-chip access method shown can therefore implement the above-mentioned cross-chip access method in Figure 3 The functions implemented are the same, so they will not be explained again here.

[0104] Figure 6 This is a schematic diagram of a chip structure provided in one embodiment. Please refer to it. Figure 6 At the hardware level, the chip includes a processor, and optionally also includes an internal bus, network interface, and memory. The memory may include main memory, such as high-speed random-access memory (RAM), or non-volatile memory, such as at least one disk drive. Of course, the chip may also include other hardware required for other business operations.

[0105] The processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0106] Memory is used to store programs. Specifically, programs may include program code, which includes computer operation instructions. Memory may include main memory and non-volatile memory, and provides instructions and data to the processor.

[0107] The processor reads the corresponding computer program from non-volatile memory into main memory and then runs it, forming a cross-chip access mechanism at the logical level. The processor executes the program stored in memory and specifically performs the following operations: Receive a first access instruction from the previous level chip, wherein the first access instruction includes a first address; The first mapping table is queried. In response to the first address being located within the first address range of the upper-level chip, the first address is converted to a second address within the second address range of the first chip. The first mapping table includes the mapping relationship between the first address range and the second address range. Based on the second mapping table, the second address is converted into a third address within the memory address range of the next-level chip; the second mapping table includes the mapping relationship between the second address range and the memory address range; A second access instruction is sent to the next-level chip, the second access instruction including the third address.

[0108] The above is as stated in this application. Figure 3The method for cross-chip access device execution disclosed in the illustrated embodiments can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0109] The chip can also perform Figure 3 The method, and enables cross-chip access to devices in Figure 3 The functions of the embodiments shown are not described in detail here.

[0110] Of course, in addition to software implementation, the chip of this application does not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. In other words, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0111] This application also proposes a computer-readable storage medium that stores one or more programs, the programs including instructions that, when executed by a chip comprising multiple applications, enable the chip to perform execution. Figure 3 The method of the illustrated embodiment is specifically used to perform the following operations: Receive a first access instruction from the previous level chip, wherein the first access instruction includes a first address; The first mapping table is queried. In response to the first address being located within the first address range of the upper-level chip, the first address is converted to a second address within the second address range of the first chip. The first mapping table includes the mapping relationship between the first address range and the second address range. Based on the second mapping table, the second address is converted into a third address within the memory address range of the next-level chip; the second mapping table includes the mapping relationship between the second address range and the memory address range; A second access instruction is sent to the next-level chip, the second access instruction including the third address.

[0112] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a chip to perform the steps of the cross-chip access method provided in this application.

[0113] In summary, the above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

[0114] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0115] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0116] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0117] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

Claims

1. A cross-chip access method, characterized in that, Applied to a first chip, wherein the first chip is any chip in a cascaded multi-stage chip system, the method includes: Receive a first access instruction from the previous level chip, wherein the first access instruction includes a first address; The first mapping table is queried. In response to the first address being located within the first address range of the upper-level chip, the first address is converted to a second address within the second address range of the first chip. The first mapping table includes the mapping relationship between the first address range and the second address range. Based on the second mapping table, the second address is converted into a third address within the memory address range of the next-level chip; the second mapping table includes the mapping relationship between the second address range and the memory address range; A second access instruction is sent to the next-level chip, the second access instruction including the third address.

2. The method according to claim 1, characterized in that, The method further includes: Obtain the memory address range of the next-level chip; In the address space of the first chip, an address range that matches the memory address range is divided out as the second address range; Establish a mapping relationship between the memory address range and the second address range in the second mapping table.

3. The method according to claim 2, characterized in that, The step of dividing the address space of the first chip into an address range that matches the memory address range includes: The memory management unit of the first chip divides the address space of the first chip into an address range that matches the memory address range. Establishing the mapping relationship between the memory address range and the second address range in the second mapping table includes: The memory management unit establishes a mapping relationship between the memory address range and the second address range in the second mapping table.

4. The method according to claim 1, characterized in that, The method further includes: Write the second address range into the first register of the first chip; The first address range is obtained from the first register. The first address range is the address space of the upper-level chip that is partitioned from the address space of the upper-level chip and written into the first register after the upper-level chip reads the second address range from the first register. Establish a mapping relationship between the first address range and the second address range in the first mapping table.

5. The method according to claim 1, characterized in that, The method further includes: The third address range of the next-level chip is read from the second register of the next-level chip. The third address range is obtained by the next-level chip based on the memory address range of the connected downstream chip. Based on the third address range, a fourth address range matching the third address range is divided from the address space of the first chip; The fourth address range is written into the second register, and the fourth address range is used to establish a mapping relationship with the third address range.

6. The method according to claim 1, characterized in that, The mapping relationships in the second mapping table are obtained through the memory management unit of the first chip; The step of converting the second address into a third address within the memory address range of the next-level chip based on the second mapping table includes: The memory management unit queries the second mapping table and converts the second address into the third address based on the mapping relationship in the second mapping table; The step of sending a second access instruction to the next-level chip, wherein the second access instruction includes the third address, includes: The memory management unit sends the second access instruction to the connection controller of the first chip. The second access command is sent to the next-level chip via the connection controller.

7. The method according to claim 1, characterized in that, The first mapping table also includes the mapping relationship between the fifth address range of the previous level chip and the sixth address range of the first chip, and the second mapping table also includes the mapping relationship between the sixth address range and the memory address range of the first chip; Following the query of the first mapping table, the following is also included: In response to the first address being located within the fifth address range, the first address is converted to a fourth address within the sixth address range; Based on the second mapping table, the fourth address is converted into a fifth address within the memory address range of the first chip; Access the memory of the first chip based on the fifth address.

8. A multi-chip system, characterized in that, include: Cascaded multi-stage chips; Any chip in the multi-level chip system accesses downstream chips according to any one of claims 1 to 7 of the cross-chip access method.

9. The multi-chip system according to claim 8, characterized in that, The multi-level chip includes a host and at least two cascaded GPUs, with the host connected to the first GPU of the at least two GPUs.

10. The multi-chip system according to claim 9, characterized in that, The host is connected to the first-level GPU via a bus, and adjacent GPUs in the at least two-level GPUs are connected via an inter-chip interconnect channel.

11. A cross-chip access device, characterized in that, The device is applied to a first chip, which is any one of a cascaded multi-stage chip, and includes: The receiving module is used to receive a first access instruction from the previous stage chip, wherein the first access instruction includes a first address; The first mapping module is used to query the first mapping table and, in response to the first address being located within the first address range of the upper-level chip, convert the first address into a second address within the second address range of the first chip; the first mapping table includes the mapping relationship between the first address range and the second address range. The second mapping module is used to convert the second address into a third address within the memory address range of the next-level chip based on the second mapping table; the second mapping table includes the mapping relationship between the second address range and the memory address range. The sending module is used to send a second access instruction to the next-level chip, the second access instruction including the third address.

12. A chip, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the cross-chip access method as described in any one of claims 1 to 7.

13. A computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the chip's processor, the chip is able to perform the steps of the cross-chip access method as described in any one of claims 1 to 7.

14. A computer program product, characterized in that, The computer program product includes a non-transitory computer-readable storage medium storing a computer program operable to cause the chip to perform the steps of the cross-chip access method as described in any one of claims 1 to 7.

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